2 * Simulator of microcontrollers (jmp_inst.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
36 *____________________________________________________________________________
40 cl_avr::ijmp(t_mem code)
44 z= ram->get(ZH)*256 + ram->get(ZL);
45 PC= rom->validate_address((PC & ~0xffff) | z);
52 cl_avr::eijmp(t_mem code)
59 * Indirect Call to Subroutine
62 *____________________________________________________________________________
66 cl_avr::icall(t_mem code)
75 PC= (PC & ~0xffff) | (z & 0xffff);
83 cl_avr::eicall(t_mem code)
90 * Return from Subroutine
93 *____________________________________________________________________________
97 cl_avr::ret(t_mem code)
102 PC= rom->validate_address(a);
109 * Return from Interrupt
111 * 1001 0101 0XX1 1000
112 *____________________________________________________________________________
116 cl_avr::reti(t_mem code)
121 PC= rom->validate_address(a);
122 t_mem sreg= ram->read(SREG);
124 ram->write(SREG, sreg);
133 * 1100 kkkk kkkk kkkk
134 *____________________________________________________________________________
138 cl_avr::rjmp_k(t_mem code)
140 long k= code & 0xfff;
144 PC= rom->validate_address((signed)PC + (signed)k);
151 * Relative Call to Subroutine
153 * 1101 kkkk kkkk kkkk -1K<=k<=+1k
154 *____________________________________________________________________________
158 cl_avr::rcall_k(t_mem code)
166 PC= rom->validate_address((signed)PC + (signed)k);
174 * Compare Skip if Equal
175 * CPSE Rd,Rr 0<=d<=31, 0<=r<=31
176 * 0001 00rd dddd rrrr
177 *____________________________________________________________________________
181 cl_avr::cpse_Rd_Rr(t_mem code)
186 r= ((code&0x200)>>5)|(code&0xf);
187 if (ram->read(r) == ram->read(d))
189 t_mem next_code= rom->get(PC);
191 struct dis_entry *dt= dis_tbl();
192 while ((next_code & dt[i].mask) != dt[i].code &&
195 if (dt[i].mnemonic != NULL)
197 PC= rom->validate_address(PC + dt[i].length);
210 * 1001 010k kkkk 110k
211 * kkkk kkkk kkkk kkkk
212 *____________________________________________________________________________
216 cl_avr::jmp_k(t_mem code)
220 k= ((code&0x1f0)>>3)|(code&1);
222 PC= rom->validate_address(k);
229 * Long Call to a Subroutine
230 * CALL k 0<=k<=64k/4M
231 * 1001 010k kkkk 111k
232 * kkkk kkkk kkkk kkkk
233 *____________________________________________________________________________
237 cl_avr::call_k(t_mem code)
241 k= (((code&0x1f0)>>3)|(code&1))*0x10000;
244 PC= rom->validate_address(k);
251 * Branch if Bit in SREG is Set
252 * BRBS s,k 0<=s<=7, -64<=k<=+63
253 * 1111 00kk kkkk ksss
254 *____________________________________________________________________________
258 cl_avr::brbs_s_k(t_mem code)
264 t_mem sreg= ram->get(SREG);
270 PC= rom->validate_address((signed)PC+k);
278 * Branch if Bit in SREG is Cleared
279 * BRBC s,k 0<=s<=7, -64<=k<=+63
280 * 1111 01kk kkkk ksss
281 *____________________________________________________________________________
285 cl_avr::brbc_s_k(t_mem code)
291 t_mem sreg= ram->get(SREG);
297 PC= rom->validate_address((signed)PC+k);
305 * Skip if Bit in Register is Cleared
306 * SBRC Rr,b 0<=r<=31, 0<=b<=7
307 * 1111 110r rrrr Xbbb
308 *____________________________________________________________________________
312 cl_avr::sbrc_Rr_b(t_mem code)
314 t_addr r= (code&0x1f0)>>4;
317 if (!(ram->read(r) & mask))
319 t_mem next_code= rom->get(PC);
321 struct dis_entry *dt= dis_tbl();
322 while ((next_code & dt[i].mask) != dt[i].code &&
325 if (dt[i].mnemonic != NULL)
327 PC= rom->validate_address(PC + dt[i].length);
338 * Skip if Bit in Register is Set
339 * SBRS Rr,b 0<=r<=31, 0<=b<=7
340 * 1111 111r rrrr Xbbb
341 *____________________________________________________________________________
345 cl_avr::sbrs_Rr_b(t_mem code)
347 t_addr r= (code&0x1f0)>>4;
350 if (ram->read(r) & mask)
352 t_mem next_code= rom->get(PC);
354 struct dis_entry *dt= dis_tbl();
355 while ((next_code & dt[i].mask) != dt[i].code &&
358 if (dt[i].mnemonic != NULL)
360 PC= rom->validate_address(PC + dt[i].length);
371 * Skip if Bit in I/O Register is Clear
372 * SBIC P,b 0<=P<=31 0<=b<=7
373 * 1001 1001 pppp pbbb
374 *____________________________________________________________________________
378 cl_avr::sbic_P_b(t_mem code)
382 addr= ((code&0xf8)>>3)+0x20;
384 if (0 == (mask & ram->read(addr)))
387 int size= inst_length(code);
400 * Skip if Bit in I/O Register is Set
401 * SBIS P,b 0<=P<=31 0<=b<=7
402 * 1001 1011 pppp pbbb
403 *____________________________________________________________________________
407 cl_avr::sbis_P_b(t_mem code)
411 addr= ((code&0xf8)>>3)+0x20;
413 if (mask & ram->read(addr))
416 int size= inst_length(code);
428 /* End of avr.src/jump_inst.cc */