2 * Simulator of microcontrollers (glob.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
33 struct dis_entry disass_avr[]= {
34 { 0x0000, 0xffff, ' ', 1, "nop" },
35 { 0x9488, 0xffff, ' ', 1, "clc" },
36 { 0x94d8, 0xffff, ' ', 1, "clh" },
37 { 0x94f8, 0xffff, ' ', 1, "cli" },
38 { 0x94a8, 0xffff, ' ', 1, "cln" },
39 { 0x94c8, 0xffff, ' ', 1, "cls" },
40 { 0x94e8, 0xffff, ' ', 1, "clt" },
41 { 0x94b8, 0xffff, ' ', 1, "clv" },
42 { 0x9498, 0xffff, ' ', 1, "clz" },
43 { 0x9408, 0xffff, ' ', 1, "sec" },
44 { 0x9458, 0xffff, ' ', 1, "seh" },
45 { 0x9478, 0xffff, ' ', 1, "sei" },
46 { 0x9428, 0xffff, ' ', 1, "sen" },
47 { 0x9448, 0xffff, ' ', 1, "ses" },
48 { 0x9468, 0xffff, ' ', 1, "set" },
49 { 0x9438, 0xffff, ' ', 1, "sev" },
50 { 0x9418, 0xffff, ' ', 1, "sez" },
51 { 0x1c00, 0xfc00, ' ', 1, "adc %d,%r" },
52 { 0x0c00, 0xfc00, ' ', 1, "add %d,%r" },
53 { 0x9600, 0xff00, ' ', 1, "adiw %2,%6" },
54 { 0x2000, 0xfc00, ' ', 1, "and %d,%r" },
55 { 0x7000, 0xf000, ' ', 1, "andi %D,%K" },
56 { 0x9405, 0xfe0f, ' ', 1, "asr %d" },
57 { 0x9488, 0xff8f, ' ', 1, "bclr %s" },
58 { 0xf800, 0xfe08, ' ', 1, "bld %d,%b" },
59 { 0xf400, 0xfc07, ' ', 1, "brcc %k" },
60 { 0xf000, 0xfc07, ' ', 1, "brcs %k" },
61 { 0xf001, 0xfc07, ' ', 1, "breq %k" },
62 { 0xf404, 0xfc07, ' ', 1, "brge %k" },
63 { 0xf405, 0xfc07, ' ', 1, "brhc %k" },
64 { 0xf005, 0xfc07, ' ', 1, "brhs %k" },
65 { 0xf407, 0xfc07, ' ', 1, "brid %k" },
66 { 0xf007, 0xfc07, ' ', 1, "brie %k" },
67 { 0xf000, 0xfc07, ' ', 1, "brlo %k" },
68 { 0xf004, 0xfc07, ' ', 1, "brlt %k" },
69 { 0xf002, 0xfc07, ' ', 1, "brmi %k" },
70 { 0xf401, 0xfc07, ' ', 1, "brne %k" },
71 { 0xf402, 0xfc07, ' ', 1, "brpl %k" },
72 { 0xf400, 0xfc07, ' ', 1, "brsh %k" },
73 { 0xf406, 0xfc07, ' ', 1, "brtc %k" },
74 { 0xf006, 0xfc07, ' ', 1, "brts %k" },
75 { 0xf403, 0xfc07, ' ', 1, "brvc %k" },
76 { 0xf003, 0xfc07, ' ', 1, "brvs %k" },
77 { 0xf400, 0xfc00, ' ', 1, "brbc %b,%k" },
78 { 0xf000, 0xfc00, ' ', 1, "brbs %b,%k" },
79 { 0x9408, 0xff8f, ' ', 1, "bset %s" },
80 { 0xfa00, 0xfe00, ' ', 1, "bst %d,%b" },
81 { 0x940e, 0xfe0e, 'l', 2, "call %A" },
82 { 0x9800, 0xff00, ' ', 1, "cbi %P,%b" },
83 { 0x9400, 0xfe0f, ' ', 1, "com %d" },
84 { 0x1400, 0xfc00, ' ', 1, "cp %d,%r" },
85 { 0x0400, 0xfc00, ' ', 1, "cpc %d,%r" },
86 { 0x3000, 0xf000, ' ', 1, "cpi %D,%K" },
87 { 0x1000, 0xfc00, ' ', 1, "cpse %d,%r" },
88 { 0x940a, 0xfe0f, ' ', 1, "dec %d" },
89 { 0x2400, 0xfc00, ' ', 1, "eor %d,%r" },
90 { 0x9509, 0xff0f, ' ', 1, "icall" },
91 { 0x9409, 0xff0f, ' ', 1, "ijmp" },
92 { 0xb000, 0xf800, ' ', 1, "in %d,%p" },
93 { 0x9403, 0xfe0f, ' ', 1, "inc %d" },
94 { 0x940c, 0xfe0e, ' ', 2, "jmp %A" },
95 { 0x900c, 0xfe0f, ' ', 1, "ld %d,X" },
96 { 0x900d, 0xfe0f, ' ', 1, "ld %d,X+" },
97 { 0x900e, 0xfe0f, ' ', 1, "ld %d,-X" },
98 { 0x8008, 0xfe0f, ' ', 1, "ld %d,Y" },
99 { 0x9009, 0xfe0f, ' ', 1, "ld %d,Y+" },
100 { 0x900a, 0xfe0f, ' ', 1, "ld %d,-Y" },
101 { 0x8008, 0xd208, ' ', 1, "ldd %d,Y+%q" },
102 { 0x8000, 0xfe0f, ' ', 1, "ld %d,Z" },
103 { 0x9001, 0xfe0f, ' ', 1, "ld %d,Z+" },
104 { 0x9002, 0xfe0f, ' ', 1, "ld %d,-Z" },
105 { 0x8000, 0xd208, ' ', 1, "ldd %d,Z+%q" },
106 { 0xe000, 0xf000, ' ', 1, "ldi %D,%K" },
107 { 0x9000, 0xfe0f, ' ', 2, "lds %d,%R" },
108 { 0x95c8, 0xffff, ' ', 1, "lpm" },
109 { 0x95d8, 0xffff, ' ', 1, "elpm" }, // in some devices equal to lpm
110 { 0x9406, 0xfe0f, ' ', 1, "lsr %d" },
111 { 0x2c00, 0xfc00, ' ', 1, "mov %d,%r" },
112 { 0x9c00, 0xfc00, ' ', 1, "mul %d,%r" },
113 { 0x9401, 0xfe0f, ' ', 1, "neg %d" },
114 { 0x2800, 0xfc00, ' ', 1, "or %d,%r" },
115 { 0x6000, 0xf000, ' ', 1, "ori %d,%K" },
116 { 0xb800, 0xf800, ' ', 1, "out %p,%d" },
117 { 0x900f, 0xfe0f, ' ', 1, "pop %d" },
118 { 0x920f, 0xfe0f, ' ', 1, "push %d" },
119 { 0xd000, 0xf000, ' ', 1, "rcall %a" },
120 { 0x9508, 0xff9f, ' ', 1, "ret" },
121 { 0x9518, 0xff9f, ' ', 1, "reti" },
122 { 0xc000, 0xf000, ' ', 1, "rjmp %a" },
123 { 0x9407, 0xfe0f, ' ', 1, "ror %d" },
124 { 0x0800, 0xfc00, ' ', 1, "sbc %d,%r" },
125 { 0x4000, 0xf000, ' ', 1, "sbci %D,%K" },
126 { 0x9a00, 0xff00, ' ', 1, "sbi %P,%b" },
127 { 0x9900, 0xff00, ' ', 1, "sbic %P,%b" },
128 { 0x9b00, 0xff00, ' ', 1, "sbis %P,%b" },
129 { 0x9700, 0xff00, ' ', 1, "sbiw %2,%6" },
130 { 0x6000, 0xf000, ' ', 1, "sbr %D,%K" },
131 { 0xfc00, 0xfe00, ' ', 1, "sbrc %d,%b" },
132 { 0xfe00, 0xfe00, ' ', 1, "sbrs %d,%b" },
133 { 0xef0f, 0xff0f, ' ', 1, "ser %D" },
134 { 0x9588, 0xffef, ' ', 1, "sleep" },
135 { 0x920c, 0xfe0f, ' ', 1, "st X,%d" },
136 { 0x920d, 0xfe0f, ' ', 1, "st X+,%d" },
137 { 0x920e, 0xfe0f, ' ', 1, "st -X,%d" },
138 { 0x8208, 0xfe0f, ' ', 1, "st Y,%d" },
139 { 0x9209, 0xfe0f, ' ', 1, "st Y+,%d" },
140 { 0x920a, 0xfe0f, ' ', 1, "st -Y,%d" },
141 { 0x8208, 0xd208, ' ', 1, "std Y+%q,%d" },
142 { 0x8200, 0xfe0f, ' ', 1, "st Z,%d" },
143 { 0x9201, 0xfe0f, ' ', 1, "st Z+,%d" },
144 { 0x9202, 0xfe0f, ' ', 1, "st -Z,%d" },
145 { 0x8200, 0xd208, ' ', 1, "std Z+%q,%d" },
146 { 0x9200, 0xfe0f, ' ', 2, "sts %R,%d" },
147 { 0x1800, 0xfc00, ' ', 1, "sub %d,%r" },
148 { 0x5000, 0xf000, ' ', 1, "subi %D,%K" },
149 { 0x9402, 0xfe0f, ' ', 1, "swap %d" },
150 { 0x95a8, 0xffef, ' ', 1, "wdr" },
154 // Addresses are IRAM addresses!
155 struct name_entry sfr_tabl[]= {
156 { CPU_ALL_AVR, 0x001a, "XL"},
157 { CPU_ALL_AVR, 0x001a, "XL" },
158 { CPU_ALL_AVR, 0x001b, "XH" },
159 { CPU_ALL_AVR, 0x001c, "YL" },
160 { CPU_ALL_AVR, 0x001d, "YH" },
161 { CPU_ALL_AVR, 0x001e, "ZL" },
162 { CPU_ALL_AVR, 0x001f, "ZH" },
163 { CPU_ALL_AVR, 0x0024, "ADCL" },
164 { CPU_ALL_AVR, 0x0025, "ADCH" },
165 { CPU_ALL_AVR, 0x0026, "ADCSR" },
166 { CPU_ALL_AVR, 0x0027, "ADMUX" },
167 { CPU_ALL_AVR, 0x0028, "ACSR" },
168 { CPU_ALL_AVR, 0x0029, "UBRR" },
169 { CPU_ALL_AVR, 0x002A, "UCR" },
170 { CPU_ALL_AVR, 0x002B, "USR" },
171 { CPU_ALL_AVR, 0x002C, "UDR" },
172 { CPU_ALL_AVR, 0x002D, "SPCR" },
173 { CPU_ALL_AVR, 0x002E, "SPSR" },
174 { CPU_ALL_AVR, 0x002F, "SPDR" },
175 { CPU_ALL_AVR, 0x0030, "PIND" },
176 { CPU_ALL_AVR, 0x0031, "DDRD" },
177 { CPU_ALL_AVR, 0x0032, "PORTD" },
178 { CPU_ALL_AVR, 0x0033, "PINC" },
179 { CPU_ALL_AVR, 0x0034, "DDRC" },
180 { CPU_ALL_AVR, 0x0035, "PORTC" },
181 { CPU_ALL_AVR, 0x0036, "PINB" },
182 { CPU_ALL_AVR, 0x0037, "DDRB" },
183 { CPU_ALL_AVR, 0x0038, "PORTB" },
184 { CPU_ALL_AVR, 0x0039, "PINA" },
185 { CPU_ALL_AVR, 0x003A, "DDRA" },
186 { CPU_ALL_AVR, 0x003B, "PORTA" },
187 { CPU_ALL_AVR, 0x003C, "EECR" },
188 { CPU_ALL_AVR, 0x003D, "EEDR" },
189 { CPU_ALL_AVR, 0x003E, "EEARL" },
190 { CPU_ALL_AVR, 0x003E, "EEARH" },
191 { CPU_ALL_AVR, 0x0041, "WDTCR" },
192 { CPU_ALL_AVR, 0x0042, "ASSR" },
193 { CPU_ALL_AVR, 0x0043, "OCR2" },
194 { CPU_ALL_AVR, 0x0044, "TCNT2" },
195 { CPU_ALL_AVR, 0x0045, "TCCR2" },
196 { CPU_ALL_AVR, 0x0046, "ICR1L" },
197 { CPU_ALL_AVR, 0x0047, "ICR1H" },
198 { CPU_ALL_AVR, 0x0048, "OCR1BL" },
199 { CPU_ALL_AVR, 0x0049, "OCR1BH" },
200 { CPU_ALL_AVR, 0x004A, "OCR1AL" },
201 { CPU_ALL_AVR, 0x004B, "OCR1AH" },
202 { CPU_ALL_AVR, 0x004C, "TCNT1L" },
203 { CPU_ALL_AVR, 0x004D, "TCNT1H" },
204 { CPU_ALL_AVR, 0x004E, "TCCR1B" },
205 { CPU_ALL_AVR, 0x004F, "TCCR1A" },
206 { CPU_ALL_AVR, 0x0052, "TCNT0" },
207 { CPU_ALL_AVR, 0x0053, "TCCR0" },
208 { CPU_ALL_AVR, 0x0054, "MCUSR" },
209 { CPU_ALL_AVR, 0x0055, "MCUCR" },
210 { CPU_ALL_AVR, 0x0058, "TIFR" },
211 { CPU_ALL_AVR, 0x0059, "TIMSK" },
212 { CPU_ALL_AVR, 0x005A, "GIFR" },
213 { CPU_ALL_AVR, 0x005B, "GIMSK" },
214 { CPU_ALL_AVR, 0x005D, "SPL" },
215 { CPU_ALL_AVR, 0x005E, "SPH" },
216 { CPU_ALL_AVR, 0x005F, "SREG" },
221 /* End of avr.src/glob.cc */