2 * Simulator of microcontrollers (arith_inst.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
33 cl_avr::cpi_Rd_K(t_mem code)
40 cl_avr::sbci_Rd_K(t_mem code)
47 cl_avr::subi_Rd_K(t_mem code)
54 cl_avr::muls_Rd_Rr(t_mem code)
61 cl_avr::mulsu_Rd_Rr(t_mem code)
68 cl_avr::fmul_Rd_Rr(t_mem code)
75 cl_avr::fmuls_Rd_Rr(t_mem code)
82 cl_avr::fmulsu_Rd_Rr(t_mem code)
89 cl_avr::cpc_Rd_Rr(t_mem code)
96 cl_avr::sbc_Rd_Rr(t_mem code)
104 * ADD Rd,Rr 0<=d<=31, 0<=r<=31
105 * 0000 11rd dddd rrrr
106 *____________________________________________________________________________
110 cl_avr::add_Rd_Rr(t_mem code)
113 t_mem R, D, result, res;
116 r= ((code&0x200)>>5)|(code&0xf);
123 t_mem sreg= ram->get(SREG);
128 if (((D&R&~res)&0x80) ||
130 sreg|= (BIT_V|BIT_S);
132 sreg&= ~(BIT_V|BIT_S);
144 if ((R&0xf) + (D&0xf) > 15)
148 ram->set(SREG, sreg);
155 cl_avr::cp_Rd_Rr(t_mem code)
162 cl_avr::sub_Rd_Rr(t_mem code)
170 * ADC Rd,Rr 0<=d<=31, 0<=r<=31
171 * 0001 11rd dddd rrrr
172 *____________________________________________________________________________
176 cl_avr::adc_Rd_Rr(t_mem code)
179 t_mem R, D, result, res;
182 r= ((code&0x200)>>5)|(code&0xf);
185 t_mem sreg= ram->get(SREG);
186 result= D+R+((sreg&BIT_C)?1:0);
194 if (((D&R&~res)&0x80) ||
196 sreg|= (BIT_V|BIT_S);
198 sreg&= ~(BIT_V|BIT_S);
210 if ((R&0xf) + (D&0xf) > 15)
214 ram->set(SREG, sreg);
221 cl_avr::com_Rd(t_mem code)
228 cl_avr::neg_Rd(t_mem code)
237 * 1001 010d dddd 0011
238 *____________________________________________________________________________
242 cl_avr::inc_Rd(t_mem code)
247 t_mem data= ram->read(d)+1;
248 ram->write(d, &data);
250 t_mem sreg= ram->get(SREG);
269 sreg&= ~(BIT_N|BIT_V|BIT_S);
275 ram->set(SREG, sreg);
281 cl_avr::asr_Rd(t_mem code)
288 cl_avr::lsr_Rd(t_mem code)
295 cl_avr::ror_Rd(t_mem code)
302 cl_avr::dec_Rd(t_mem code)
309 cl_avr::mul_Rd_Rr(t_mem code)
316 * Add Immediate to Word
317 * ADIW Rdl,K dl={24,26,28,30}, 0<=K<=63
318 * 1001 0110 KK dd KKKK
319 *____________________________________________________________________________
323 cl_avr::adiw_Rdl_K(t_mem code)
326 t_mem D, K, result, res;
328 dl= 24+(2*((code&0x30)>>4));
329 K= ((code&0xc0)>>2)|(code&0xf);
330 D= ram->read(dl+1)*256 + ram->read(dl);
332 res= result & 0xffff;
333 t_mem resl= result&0xff, resh= (result>>8)&0xff;
334 ram->write(dl+1, &resh);
335 ram->write(dl, &resl);
337 t_mem sreg= ram->get(SREG);
343 sreg|= (BIT_V|BIT_S);
345 sreg&= ~(BIT_V|BIT_S);
357 ram->set(SREG, sreg);
364 /* End of avr.src/arith_inst.cc */