3 * Copyright 2008 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %feature("autodoc", "1"); // generate python docstrings
25 %include "exception.i"
26 %import "gnuradio.i" // the common stuff
30 #include <gnuradio_swig_bug_workaround.h>
31 #include "usrp2_source_16sc.h"
32 #include "usrp2_source_32fc.h"
33 #include "usrp2_sink_16sc.h"
34 #include "usrp2_sink_32fc.h"
37 %include <usrp2/tune_result.h>
39 %template(uint32_t_vector) std::vector<uint32_t>;
41 // ----------------------------------------------------------------
43 class usrp2_base : public gr_sync_block
46 usrp2_base() throw (std::runtime_error);
51 std::string mac_addr() const;
52 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
53 bool fpga_master_clock_freq(long *freq);
55 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
56 bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
59 // ----------------------------------------------------------------
61 class usrp2_source_base : public usrp2_base
64 usrp2_source_base() throw (std::runtime_error);
69 bool set_gain(double gain);
70 %rename(_real_set_center_freq) set_center_freq;
71 bool set_center_freq(double frequency, usrp2::tune_result *r);
72 bool set_decim(int decimation_factor);
73 bool set_scale_iq(int scale_i, int scale_q);
75 %rename(_real_adc_rate) adc_rate;
76 bool adc_rate(long *rate);
79 double gain_db_per_step();
82 %rename(_real_daughterboard_id) daughterboard_id;
83 bool daughterboard_id(int *dbid);
84 unsigned int overruns();
85 unsigned int missing();
88 // ----------------------------------------------------------------
90 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
92 usrp2_source_32fc_sptr
93 usrp2_make_source_32fc(const std::string ifc="eth0",
94 const std::string mac="")
95 throw (std::runtime_error);
97 class usrp2_source_32fc : public usrp2_source_base
100 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
103 ~usrp2_source_32fc();
106 // ----------------------------------------------------------------
108 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
110 usrp2_source_16sc_sptr
111 usrp2_make_source_16sc(const std::string ifc="eth0",
112 const std::string mac="")
113 throw (std::runtime_error);
115 class usrp2_source_16sc : public usrp2_source_base
118 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
121 ~usrp2_source_16sc();
124 // ----------------------------------------------------------------
126 class usrp2_sink_base : public usrp2_base
129 usrp2_sink_base() throw (std::runtime_error);
134 bool set_gain(double gain);
135 %rename(_real_set_center_freq) set_center_freq;
136 bool set_center_freq(double frequency, usrp2::tune_result *r);
137 bool set_interp(int interp_factor);
138 bool set_scale_iq(int scale_i, int scale_q);
140 %rename(_real_dac_rate) dac_rate;
141 bool dac_rate(long *rate);
144 double gain_db_per_step();
147 %rename(_real_daughterboard_id) daughterboard_id;
148 bool daughterboard_id(int *dbid);
151 // ----------------------------------------------------------------
153 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
156 usrp2_make_sink_32fc(const std::string ifc="eth0",
157 const std::string mac="")
158 throw (std::runtime_error);
160 class usrp2_sink_32fc : public usrp2_sink_base
163 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
169 // ----------------------------------------------------------------
171 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
174 usrp2_make_sink_16sc(const std::string ifc="eth0",
175 const std::string mac="")
176 throw (std::runtime_error);
178 class usrp2_sink_16sc : public usrp2_sink_base
181 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
187 // ----------------------------------------------------------------
189 // some utility functions to allow Python to deal with pointers
191 long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
192 long deref_long_ptr(long *l) { return *l; }
193 void free_long_ptr(long *l) { free(l); }
194 int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
195 int deref_int_ptr(int *l) { return *l; }
196 void free_int_ptr(int *l) { free(l); }
199 long *make_long_ptr();
200 long deref_long_ptr(long *l);
201 void free_long_ptr(long *l);
203 int deref_int_ptr(int *l);
204 void free_int_ptr(int *l);
206 // create a more pythonic interface
209 def __set_center_freq(self, freq):
211 r = self._real_set_center_freq(freq, tr)
217 def __fpga_master_clock_freq(self):
219 r = self._real_fpga_master_clock_freq(f)
221 result = deref_long_ptr(f)
227 def __adc_rate(self):
228 rate = make_long_ptr();
229 r = self._real_adc_rate(rate)
231 result = deref_long_ptr(rate)
237 def __dac_rate(self):
238 rate = make_long_ptr();
239 r = self._real_dac_rate(rate)
241 result = deref_long_ptr(rate)
247 def __gain_range(self):
248 return [self.gain_min(),
250 self.gain_db_per_step()]
252 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
253 # but it's not really useful. We let an index error happen here
254 # to identify code using it.
255 def __freq_range(self):
256 return [self.freq_min(),
259 def __daughterboard_id(self):
260 dbid = make_int_ptr();
261 r = self._real_daughterboard_id(dbid)
263 result = deref_int_ptr(dbid)
269 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
270 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
271 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
272 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
274 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
275 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
276 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
277 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
279 usrp2_source_32fc_sptr.adc_rate = __adc_rate
280 usrp2_source_16sc_sptr.adc_rate = __adc_rate
281 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
282 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
284 usrp2_source_32fc_sptr.gain_range = __gain_range
285 usrp2_source_16sc_sptr.gain_range = __gain_range
286 usrp2_sink_32fc_sptr.gain_range = __gain_range
287 usrp2_sink_16sc_sptr.gain_range = __gain_range
289 usrp2_source_32fc_sptr.freq_range = __freq_range
290 usrp2_source_16sc_sptr.freq_range = __freq_range
291 usrp2_sink_32fc_sptr.freq_range = __freq_range
292 usrp2_sink_16sc_sptr.freq_range = __freq_range
294 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
295 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
296 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
297 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id