3 * Copyright 2008 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %feature("autodoc", "1"); // generate python docstrings
25 %include "exception.i"
26 %import "gnuradio.i" // the common stuff
29 #include <gnuradio_swig_bug_workaround.h>
30 #include "usrp2_source_16sc.h"
31 #include "usrp2_source_32fc.h"
32 #include "usrp2_sink_16sc.h"
33 #include "usrp2_sink_32fc.h"
36 %include <usrp2/tune_result.h>
38 // ----------------------------------------------------------------
40 class usrp2_base : public gr_sync_block
43 usrp2_base() throw (std::runtime_error);
48 std::string mac_addr() const;
49 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
50 bool fpga_master_clock_freq(long *freq);
54 // ----------------------------------------------------------------
56 class usrp2_source_base : public usrp2_base
59 usrp2_source_base() throw (std::runtime_error);
64 bool set_gain(double gain);
65 %rename(_real_set_center_freq) set_center_freq;
66 bool set_center_freq(double frequency, usrp2::tune_result *r);
67 bool set_decim(int decimation_factor);
68 bool set_scale_iq(int scale_i, int scale_q);
70 %rename(_real_adc_rate) adc_rate;
71 bool adc_rate(long *rate);
74 double gain_db_per_step();
77 %rename(_real_daughterboard_id) daughterboard_id;
78 bool daughterboard_id(int *dbid);
79 unsigned int overruns();
80 unsigned int missing();
83 // ----------------------------------------------------------------
85 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
87 usrp2_source_32fc_sptr
88 usrp2_make_source_32fc(const std::string ifc="eth0",
89 const std::string mac="")
90 throw (std::runtime_error);
92 class usrp2_source_32fc : public usrp2_source_base
95 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
101 // ----------------------------------------------------------------
103 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
105 usrp2_source_16sc_sptr
106 usrp2_make_source_16sc(const std::string ifc="eth0",
107 const std::string mac="")
108 throw (std::runtime_error);
110 class usrp2_source_16sc : public usrp2_source_base
113 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
116 ~usrp2_source_16sc();
119 // ----------------------------------------------------------------
121 class usrp2_sink_base : public usrp2_base
124 usrp2_sink_base() throw (std::runtime_error);
129 bool set_gain(double gain);
130 %rename(_real_set_center_freq) set_center_freq;
131 bool set_center_freq(double frequency, usrp2::tune_result *r);
132 bool set_interp(int interp_factor);
133 bool set_scale_iq(int scale_i, int scale_q);
135 %rename(_real_dac_rate) dac_rate;
136 bool dac_rate(long *rate);
139 double gain_db_per_step();
142 %rename(_real_daughterboard_id) daughterboard_id;
143 bool daughterboard_id(int *dbid);
146 // ----------------------------------------------------------------
148 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
151 usrp2_make_sink_32fc(const std::string ifc="eth0",
152 const std::string mac="")
153 throw (std::runtime_error);
155 class usrp2_sink_32fc : public usrp2_sink_base
158 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
164 // ----------------------------------------------------------------
166 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
169 usrp2_make_sink_16sc(const std::string ifc="eth0",
170 const std::string mac="")
171 throw (std::runtime_error);
173 class usrp2_sink_16sc : public usrp2_sink_base
176 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
182 // ----------------------------------------------------------------
184 // some utility functions to allow Python to deal with pointers
186 long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
187 long deref_long_ptr(long *l) { return *l; }
188 void free_long_ptr(long *l) { free(l); }
189 int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
190 int deref_int_ptr(int *l) { return *l; }
191 void free_int_ptr(int *l) { free(l); }
194 long *make_long_ptr();
195 long deref_long_ptr(long *l);
196 void free_long_ptr(long *l);
198 int deref_int_ptr(int *l);
199 void free_int_ptr(int *l);
201 // create a more pythonic interface
204 def __set_center_freq(self, freq):
206 r = self._real_set_center_freq(freq, tr)
212 def __fpga_master_clock_freq(self):
214 r = self._real_fpga_master_clock_freq(f)
216 result = deref_long_ptr(f)
222 def __adc_rate(self):
223 rate = make_long_ptr();
224 r = self._real_adc_rate(rate)
226 result = deref_long_ptr(rate)
232 def __dac_rate(self):
233 rate = make_long_ptr();
234 r = self._real_dac_rate(rate)
236 result = deref_long_ptr(rate)
242 def __gain_range(self):
243 return [self.gain_min(),
245 self.gain_db_per_step()]
247 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
248 # but it's not really useful. We let an index error happen here
249 # to identify code using it.
250 def __freq_range(self):
251 return [self.freq_min(),
254 def __daughterboard_id(self):
255 dbid = make_int_ptr();
256 r = self._real_daughterboard_id(dbid)
258 result = deref_int_ptr(dbid)
264 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
265 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
266 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
267 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
269 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
270 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
271 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
272 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
274 usrp2_source_32fc_sptr.adc_rate = __adc_rate
275 usrp2_source_16sc_sptr.adc_rate = __adc_rate
276 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
277 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
279 usrp2_source_32fc_sptr.gain_range = __gain_range
280 usrp2_source_16sc_sptr.gain_range = __gain_range
281 usrp2_sink_32fc_sptr.gain_range = __gain_range
282 usrp2_sink_16sc_sptr.gain_range = __gain_range
284 usrp2_source_32fc_sptr.freq_range = __freq_range
285 usrp2_source_16sc_sptr.freq_range = __freq_range
286 usrp2_sink_32fc_sptr.freq_range = __freq_range
287 usrp2_sink_16sc_sptr.freq_range = __freq_range
289 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
290 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
291 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
292 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id