3 * Copyright 2008 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %feature("autodoc", "1"); // generate python docstrings
25 %include "exception.i"
26 %import "gnuradio.i" // the common stuff
30 #include <gnuradio_swig_bug_workaround.h>
31 #include "usrp2_source_16sc.h"
32 #include "usrp2_source_32fc.h"
33 #include "usrp2_sink_16sc.h"
34 #include "usrp2_sink_32fc.h"
37 %include <usrp2/tune_result.h>
39 %template(uint32_t_vector) std::vector<uint32_t>;
41 // ----------------------------------------------------------------
43 class usrp2_base : public gr_sync_block
46 usrp2_base() throw (std::runtime_error);
51 std::string mac_addr() const;
52 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
53 bool fpga_master_clock_freq(long *freq);
55 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
58 // ----------------------------------------------------------------
60 class usrp2_source_base : public usrp2_base
63 usrp2_source_base() throw (std::runtime_error);
68 bool set_gain(double gain);
69 %rename(_real_set_center_freq) set_center_freq;
70 bool set_center_freq(double frequency, usrp2::tune_result *r);
71 bool set_decim(int decimation_factor);
72 bool set_scale_iq(int scale_i, int scale_q);
74 %rename(_real_adc_rate) adc_rate;
75 bool adc_rate(long *rate);
78 double gain_db_per_step();
81 %rename(_real_daughterboard_id) daughterboard_id;
82 bool daughterboard_id(int *dbid);
83 unsigned int overruns();
84 unsigned int missing();
87 // ----------------------------------------------------------------
89 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
91 usrp2_source_32fc_sptr
92 usrp2_make_source_32fc(const std::string ifc="eth0",
93 const std::string mac="")
94 throw (std::runtime_error);
96 class usrp2_source_32fc : public usrp2_source_base
99 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
102 ~usrp2_source_32fc();
105 // ----------------------------------------------------------------
107 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
109 usrp2_source_16sc_sptr
110 usrp2_make_source_16sc(const std::string ifc="eth0",
111 const std::string mac="")
112 throw (std::runtime_error);
114 class usrp2_source_16sc : public usrp2_source_base
117 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
120 ~usrp2_source_16sc();
123 // ----------------------------------------------------------------
125 class usrp2_sink_base : public usrp2_base
128 usrp2_sink_base() throw (std::runtime_error);
133 bool set_gain(double gain);
134 %rename(_real_set_center_freq) set_center_freq;
135 bool set_center_freq(double frequency, usrp2::tune_result *r);
136 bool set_interp(int interp_factor);
137 bool set_scale_iq(int scale_i, int scale_q);
139 %rename(_real_dac_rate) dac_rate;
140 bool dac_rate(long *rate);
143 double gain_db_per_step();
146 %rename(_real_daughterboard_id) daughterboard_id;
147 bool daughterboard_id(int *dbid);
150 // ----------------------------------------------------------------
152 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
155 usrp2_make_sink_32fc(const std::string ifc="eth0",
156 const std::string mac="")
157 throw (std::runtime_error);
159 class usrp2_sink_32fc : public usrp2_sink_base
162 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
168 // ----------------------------------------------------------------
170 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
173 usrp2_make_sink_16sc(const std::string ifc="eth0",
174 const std::string mac="")
175 throw (std::runtime_error);
177 class usrp2_sink_16sc : public usrp2_sink_base
180 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
186 // ----------------------------------------------------------------
188 // some utility functions to allow Python to deal with pointers
190 long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
191 long deref_long_ptr(long *l) { return *l; }
192 void free_long_ptr(long *l) { free(l); }
193 int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
194 int deref_int_ptr(int *l) { return *l; }
195 void free_int_ptr(int *l) { free(l); }
198 long *make_long_ptr();
199 long deref_long_ptr(long *l);
200 void free_long_ptr(long *l);
202 int deref_int_ptr(int *l);
203 void free_int_ptr(int *l);
205 // create a more pythonic interface
208 def __set_center_freq(self, freq):
210 r = self._real_set_center_freq(freq, tr)
216 def __fpga_master_clock_freq(self):
218 r = self._real_fpga_master_clock_freq(f)
220 result = deref_long_ptr(f)
226 def __adc_rate(self):
227 rate = make_long_ptr();
228 r = self._real_adc_rate(rate)
230 result = deref_long_ptr(rate)
236 def __dac_rate(self):
237 rate = make_long_ptr();
238 r = self._real_dac_rate(rate)
240 result = deref_long_ptr(rate)
246 def __gain_range(self):
247 return [self.gain_min(),
249 self.gain_db_per_step()]
251 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
252 # but it's not really useful. We let an index error happen here
253 # to identify code using it.
254 def __freq_range(self):
255 return [self.freq_min(),
258 def __daughterboard_id(self):
259 dbid = make_int_ptr();
260 r = self._real_daughterboard_id(dbid)
262 result = deref_int_ptr(dbid)
268 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
269 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
270 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
271 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
273 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
274 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
275 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
276 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
278 usrp2_source_32fc_sptr.adc_rate = __adc_rate
279 usrp2_source_16sc_sptr.adc_rate = __adc_rate
280 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
281 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
283 usrp2_source_32fc_sptr.gain_range = __gain_range
284 usrp2_source_16sc_sptr.gain_range = __gain_range
285 usrp2_sink_32fc_sptr.gain_range = __gain_range
286 usrp2_sink_16sc_sptr.gain_range = __gain_range
288 usrp2_source_32fc_sptr.freq_range = __freq_range
289 usrp2_source_16sc_sptr.freq_range = __freq_range
290 usrp2_sink_32fc_sptr.freq_range = __freq_range
291 usrp2_sink_16sc_sptr.freq_range = __freq_range
293 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
294 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
295 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
296 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id