3 * Copyright 2008 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %feature("autodoc", "1"); // generate python docstrings
25 %include "exception.i"
26 %import "gnuradio.i" // the common stuff
29 #include <gnuradio_swig_bug_workaround.h>
30 #include "usrp2_source_16sc.h"
31 #include "usrp2_source_32fc.h"
32 #include "usrp2_sink_16sc.h"
33 #include "usrp2_sink_32fc.h"
36 %include <usrp2/tune_result.h>
38 // ----------------------------------------------------------------
40 class usrp2_base : public gr_sync_block
43 usrp2_base() throw (std::runtime_error);
48 std::string mac_addr() const;
49 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
50 bool fpga_master_clock_freq(long *freq);
53 // ----------------------------------------------------------------
55 class usrp2_source_base : public usrp2_base
58 usrp2_source_base() throw (std::runtime_error);
63 bool set_gain(double gain);
64 %rename(_real_set_center_freq) set_center_freq;
65 bool set_center_freq(double frequency, usrp2::tune_result *r);
66 bool set_decim(int decimation_factor);
67 bool set_scale_iq(int scale_i, int scale_q);
69 %rename(_real_adc_rate) adc_rate;
70 bool adc_rate(long *rate);
73 double gain_db_per_step();
76 %rename(_real_daughterboard_id) daughterboard_id;
77 bool daughterboard_id(int *dbid);
78 unsigned int overruns();
79 unsigned int missing();
82 // ----------------------------------------------------------------
84 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
86 usrp2_source_32fc_sptr
87 usrp2_make_source_32fc(const std::string ifc="eth0",
88 const std::string mac="")
89 throw (std::runtime_error);
91 class usrp2_source_32fc : public usrp2_source_base
94 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
100 // ----------------------------------------------------------------
102 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
104 usrp2_source_16sc_sptr
105 usrp2_make_source_16sc(const std::string ifc="eth0",
106 const std::string mac="")
107 throw (std::runtime_error);
109 class usrp2_source_16sc : public usrp2_source_base
112 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
115 ~usrp2_source_16sc();
118 // ----------------------------------------------------------------
120 class usrp2_sink_base : public usrp2_base
123 usrp2_sink_base() throw (std::runtime_error);
128 bool set_gain(double gain);
129 %rename(_real_set_center_freq) set_center_freq;
130 bool set_center_freq(double frequency, usrp2::tune_result *r);
131 bool set_interp(int interp_factor);
132 bool set_scale_iq(int scale_i, int scale_q);
134 %rename(_real_dac_rate) dac_rate;
135 bool dac_rate(long *rate);
138 double gain_db_per_step();
141 %rename(_real_daughterboard_id) daughterboard_id;
142 bool daughterboard_id(int *dbid);
145 // ----------------------------------------------------------------
147 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
150 usrp2_make_sink_32fc(const std::string ifc="eth0",
151 const std::string mac="")
152 throw (std::runtime_error);
154 class usrp2_sink_32fc : public usrp2_sink_base
157 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
163 // ----------------------------------------------------------------
165 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
168 usrp2_make_sink_16sc(const std::string ifc="eth0",
169 const std::string mac="")
170 throw (std::runtime_error);
172 class usrp2_sink_16sc : public usrp2_sink_base
175 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
181 // ----------------------------------------------------------------
183 // some utility functions to allow Python to deal with pointers
185 long *make_long_ptr() { return (long *)malloc(sizeof(long)); }
186 long deref_long_ptr(long *l) { return *l; }
187 void free_long_ptr(long *l) { free(l); }
188 int *make_int_ptr() { return (int *)malloc(sizeof(int)); }
189 int deref_int_ptr(int *l) { return *l; }
190 void free_int_ptr(int *l) { free(l); }
193 long *make_long_ptr();
194 long deref_long_ptr(long *l);
195 void free_long_ptr(long *l);
197 int deref_int_ptr(int *l);
198 void free_int_ptr(int *l);
200 // create a more pythonic interface
203 def __set_center_freq(self, freq):
205 r = self._real_set_center_freq(freq, tr)
211 def __fpga_master_clock_freq(self):
213 r = self._real_fpga_master_clock_freq(f)
215 result = deref_long_ptr(f)
221 def __adc_rate(self):
222 rate = make_long_ptr();
223 r = self._real_adc_rate(rate)
225 result = deref_long_ptr(rate)
231 def __dac_rate(self):
232 rate = make_long_ptr();
233 r = self._real_dac_rate(rate)
235 result = deref_long_ptr(rate)
241 def __gain_range(self):
242 return [self.gain_min(),
244 self.gain_db_per_step()]
246 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
247 # but it's not really useful. We let an index error happen here
248 # to identify code using it.
249 def __freq_range(self):
250 return [self.freq_min(),
253 def __daughterboard_id(self):
254 dbid = make_int_ptr();
255 r = self._real_daughterboard_id(dbid)
257 result = deref_int_ptr(dbid)
263 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
264 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
265 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
266 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
268 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
269 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
270 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
271 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
273 usrp2_source_32fc_sptr.adc_rate = __adc_rate
274 usrp2_source_16sc_sptr.adc_rate = __adc_rate
275 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
276 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
278 usrp2_source_32fc_sptr.gain_range = __gain_range
279 usrp2_source_16sc_sptr.gain_range = __gain_range
280 usrp2_sink_32fc_sptr.gain_range = __gain_range
281 usrp2_sink_16sc_sptr.gain_range = __gain_range
283 usrp2_source_32fc_sptr.freq_range = __freq_range
284 usrp2_source_16sc_sptr.freq_range = __freq_range
285 usrp2_sink_32fc_sptr.freq_range = __freq_range
286 usrp2_sink_16sc_sptr.freq_range = __freq_range
288 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
289 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
290 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
291 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id