3 * Copyright 2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %include "gnuradio.i" // the common stuff
27 #include "usrp2_source_16sc.h"
28 #include "usrp2_source_32fc.h"
29 #include "usrp2_sink_16sc.h"
30 #include "usrp2_sink_32fc.h"
33 %include <usrp2/tune_result.h>
35 %template(uint32_t_vector) std::vector<uint32_t>;
37 // ----------------------------------------------------------------
39 class usrp2_base : public gr_sync_block
42 usrp2_base() throw (std::runtime_error);
47 std::string mac_addr() const;
48 std::string interface_name() const;
49 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
50 bool fpga_master_clock_freq(long *freq);
52 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
53 bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
56 // ----------------------------------------------------------------
58 class usrp2_source_base : public usrp2_base
61 usrp2_source_base() throw (std::runtime_error);
66 bool set_gain(double gain);
67 %rename(_real_set_center_freq) set_center_freq;
68 bool set_lo_offset(double frequency);
69 bool set_center_freq(double frequency, usrp2::tune_result *r);
70 bool set_decim(int decimation_factor);
71 bool set_scale_iq(int scale_i, int scale_q);
73 %rename(_real_adc_rate) adc_rate;
74 bool adc_rate(long *rate);
77 double gain_db_per_step();
80 %rename(_real_daughterboard_id) daughterboard_id;
81 bool daughterboard_id(int *dbid);
82 unsigned int overruns();
83 unsigned int missing();
84 bool set_gpio_ddr(uint16_t value, uint16_t mask);
85 bool set_gpio_sels(std::string sels);
86 bool write_gpio(uint16_t value, uint16_t mask);
87 %rename(_real_read_gpio) read_gpio;
88 bool read_gpio(uint16_t *value);
89 bool enable_gpio_streaming(int enable);
92 // ----------------------------------------------------------------
94 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
96 usrp2_source_32fc_sptr
97 usrp2_make_source_32fc(const std::string ifc="eth0",
98 const std::string mac="")
99 throw (std::runtime_error);
101 class usrp2_source_32fc : public usrp2_source_base
104 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
107 ~usrp2_source_32fc();
110 // ----------------------------------------------------------------
112 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
114 usrp2_source_16sc_sptr
115 usrp2_make_source_16sc(const std::string ifc="eth0",
116 const std::string mac="")
117 throw (std::runtime_error);
119 class usrp2_source_16sc : public usrp2_source_base
122 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
125 ~usrp2_source_16sc();
128 // ----------------------------------------------------------------
130 class usrp2_sink_base : public usrp2_base
133 usrp2_sink_base() throw (std::runtime_error);
138 bool set_gain(double gain);
139 %rename(_real_set_center_freq) set_center_freq;
140 bool set_lo_offset(double frequency);
141 bool set_center_freq(double frequency, usrp2::tune_result *r);
142 bool set_interp(int interp_factor);
143 bool set_scale_iq(int scale_i, int scale_q);
145 %rename(_real_default_tx_scale_iq) default_scale_iq;
146 void default_scale_iq(int interp, int *scale_i, int *scale_q);
147 %rename(_real_dac_rate) dac_rate;
148 bool dac_rate(long *rate);
151 double gain_db_per_step();
154 %rename(_real_daughterboard_id) daughterboard_id;
155 bool daughterboard_id(int *dbid);
156 bool set_gpio_ddr(uint16_t value, uint16_t mask);
157 bool set_gpio_sels(std::string sels);
158 bool write_gpio(uint16_t value, uint16_t mask);
159 %rename(_real_read_gpio) read_gpio;
160 bool read_gpio(uint16_t *value);
163 // ----------------------------------------------------------------
165 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
168 usrp2_make_sink_32fc(const std::string ifc="eth0",
169 const std::string mac="")
170 throw (std::runtime_error);
172 class usrp2_sink_32fc : public usrp2_sink_base
175 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
181 // ----------------------------------------------------------------
183 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
186 usrp2_make_sink_16sc(const std::string ifc="eth0",
187 const std::string mac="")
188 throw (std::runtime_error);
190 class usrp2_sink_16sc : public usrp2_sink_base
193 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
199 // ----------------------------------------------------------------
201 // some utility functions to allow Python to deal with pointers
203 long *make_long_ptr() { return new long; }
204 long deref_long_ptr(long *l) { return *l; }
205 void free_long_ptr(long *l) { delete l; }
206 int *make_int_ptr() { return new int; }
207 int deref_int_ptr(int *l) { return *l; }
208 void free_int_ptr(int *l) { delete l; }
209 uint16_t *make_uint16_ptr() { return new uint16_t; }
210 int deref_uint16_ptr(uint16_t *l) { return *l; }
211 void free_uint16_ptr(uint16_t *l) { delete l; }
214 long *make_long_ptr();
215 long deref_long_ptr(long *l);
216 void free_long_ptr(long *l);
218 int deref_int_ptr(int *l);
219 void free_int_ptr(int *l);
220 uint16_t *make_uint16_ptr();
221 int deref_uint16_ptr(uint16_t *l);
222 void free_uint16_ptr(uint16_t *l);
224 // create a more pythonic interface
227 def __set_center_freq(self, freq):
229 r = self._real_set_center_freq(freq, tr)
235 def __fpga_master_clock_freq(self):
237 r = self._real_fpga_master_clock_freq(f)
239 result = deref_long_ptr(f)
245 def __adc_rate(self):
246 rate = make_long_ptr();
247 r = self._real_adc_rate(rate)
249 result = deref_long_ptr(rate)
255 def __dac_rate(self):
256 rate = make_long_ptr();
257 r = self._real_dac_rate(rate)
259 result = deref_long_ptr(rate)
265 def __gain_range(self):
266 return [self.gain_min(),
268 self.gain_db_per_step()]
270 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
271 # but it's not really useful. We let an index error happen here
272 # to identify code using it.
273 def __freq_range(self):
274 return [self.freq_min(),
277 def __daughterboard_id(self):
278 dbid = make_int_ptr()
279 r = self._real_daughterboard_id(dbid)
281 result = deref_int_ptr(dbid)
287 def __default_tx_scale_iq(self, interp):
288 scale_i = make_int_ptr()
289 scale_q = make_int_ptr()
290 self._real_default_tx_scale_iq(interp, scale_i, scale_q)
291 return (deref_int_ptr(scale_i), deref_int_ptr(scale_q))
293 def __read_gpio(self):
294 value = make_uint16_ptr()
295 r = self._real_read_gpio(value)
297 result = deref_uint16_ptr(value)
300 free_uint16_ptr(value)
304 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
305 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
306 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
307 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
309 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
310 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
311 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
312 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
314 usrp2_source_32fc_sptr.adc_rate = __adc_rate
315 usrp2_source_16sc_sptr.adc_rate = __adc_rate
316 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
317 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
319 usrp2_source_32fc_sptr.gain_range = __gain_range
320 usrp2_source_16sc_sptr.gain_range = __gain_range
321 usrp2_sink_32fc_sptr.gain_range = __gain_range
322 usrp2_sink_16sc_sptr.gain_range = __gain_range
324 usrp2_source_32fc_sptr.freq_range = __freq_range
325 usrp2_source_16sc_sptr.freq_range = __freq_range
326 usrp2_sink_32fc_sptr.freq_range = __freq_range
327 usrp2_sink_16sc_sptr.freq_range = __freq_range
329 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
330 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
331 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
332 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id
334 usrp2_sink_32fc_sptr.default_scale_iq = __default_tx_scale_iq
335 usrp2_sink_16sc_sptr.default_scale_iq = __default_tx_scale_iq
337 usrp2_source_32fc_sptr.read_gpio = __read_gpio
338 usrp2_source_16sc_sptr.read_gpio = __read_gpio
339 usrp2_sink_32fc_sptr.read_gpio = __read_gpio
340 usrp2_sink_16sc_sptr.read_gpio = __read_gpio