3 * Copyright 2008,2009 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 3, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 %include "gnuradio.i" // the common stuff
27 #include "usrp2_source_16sc.h"
28 #include "usrp2_source_32fc.h"
29 #include "usrp2_sink_16sc.h"
30 #include "usrp2_sink_32fc.h"
33 %include <usrp2/tune_result.h>
34 %include <usrp2/mimo_config.h>
36 %template(uint32_t_vector) std::vector<uint32_t>;
38 // ----------------------------------------------------------------
40 class usrp2_base : public gr_sync_block
43 usrp2_base() throw (std::runtime_error);
48 std::string mac_addr() const;
49 std::string interface_name() const;
50 %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq;
51 bool fpga_master_clock_freq(long *freq);
52 bool config_mimo(int flags);
54 bool sync_every_pps(bool enable);
55 std::vector<uint32_t> peek32(uint32_t addr, uint32_t words);
56 bool poke32(uint32_t addr, const std::vector<uint32_t> &data);
59 // ----------------------------------------------------------------
61 class usrp2_source_base : public usrp2_base
64 usrp2_source_base() throw (std::runtime_error);
69 bool set_gain(double gain);
70 %rename(_real_set_center_freq) set_center_freq;
71 bool set_lo_offset(double frequency);
72 bool set_center_freq(double frequency, usrp2::tune_result *r);
73 bool set_decim(int decimation_factor);
74 bool set_scale_iq(int scale_i, int scale_q);
76 %rename(_real_adc_rate) adc_rate;
77 bool adc_rate(long *rate);
80 double gain_db_per_step();
83 %rename(_real_daughterboard_id) daughterboard_id;
84 bool daughterboard_id(int *dbid);
85 unsigned int overruns();
86 unsigned int missing();
87 bool set_gpio_ddr(uint16_t value, uint16_t mask);
88 bool set_gpio_sels(std::string sels);
89 bool write_gpio(uint16_t value, uint16_t mask);
90 %rename(_real_read_gpio) read_gpio;
91 bool read_gpio(uint16_t *value);
92 bool enable_gpio_streaming(int enable);
95 // ----------------------------------------------------------------
97 GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc)
99 usrp2_source_32fc_sptr
100 usrp2_make_source_32fc(const std::string ifc="eth0",
101 const std::string mac="")
102 throw (std::runtime_error);
104 class usrp2_source_32fc : public usrp2_source_base
107 usrp2_source_32fc(const std::string &ifc, const std::string &mac);
110 ~usrp2_source_32fc();
113 // ----------------------------------------------------------------
115 GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc)
117 usrp2_source_16sc_sptr
118 usrp2_make_source_16sc(const std::string ifc="eth0",
119 const std::string mac="")
120 throw (std::runtime_error);
122 class usrp2_source_16sc : public usrp2_source_base
125 usrp2_source_16sc(const std::string &ifc, const std::string &mac);
128 ~usrp2_source_16sc();
131 // ----------------------------------------------------------------
133 class usrp2_sink_base : public usrp2_base
136 usrp2_sink_base() throw (std::runtime_error);
141 bool set_gain(double gain);
142 %rename(_real_set_center_freq) set_center_freq;
143 bool set_lo_offset(double frequency);
144 bool set_center_freq(double frequency, usrp2::tune_result *r);
145 bool set_interp(int interp_factor);
146 bool set_scale_iq(int scale_i, int scale_q);
148 %rename(_real_default_tx_scale_iq) default_scale_iq;
149 void default_scale_iq(int interp, int *scale_i, int *scale_q);
150 %rename(_real_dac_rate) dac_rate;
151 bool dac_rate(long *rate);
154 double gain_db_per_step();
157 %rename(_real_daughterboard_id) daughterboard_id;
158 bool daughterboard_id(int *dbid);
159 bool set_gpio_ddr(uint16_t value, uint16_t mask);
160 bool set_gpio_sels(std::string sels);
161 bool write_gpio(uint16_t value, uint16_t mask);
162 %rename(_real_read_gpio) read_gpio;
163 bool read_gpio(uint16_t *value);
166 // ----------------------------------------------------------------
168 GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc)
171 usrp2_make_sink_32fc(const std::string ifc="eth0",
172 const std::string mac="")
173 throw (std::runtime_error);
175 class usrp2_sink_32fc : public usrp2_sink_base
178 usrp2_sink_32fc(const std::string &ifc, const std::string &mac);
184 // ----------------------------------------------------------------
186 GR_SWIG_BLOCK_MAGIC(usrp2,sink_16sc)
189 usrp2_make_sink_16sc(const std::string ifc="eth0",
190 const std::string mac="")
191 throw (std::runtime_error);
193 class usrp2_sink_16sc : public usrp2_sink_base
196 usrp2_sink_16sc(const std::string &ifc, const std::string &mac);
202 // ----------------------------------------------------------------
204 // some utility functions to allow Python to deal with pointers
206 long *make_long_ptr() { return new long; }
207 long deref_long_ptr(long *l) { return *l; }
208 void free_long_ptr(long *l) { delete l; }
209 int *make_int_ptr() { return new int; }
210 int deref_int_ptr(int *l) { return *l; }
211 void free_int_ptr(int *l) { delete l; }
212 uint16_t *make_uint16_ptr() { return new uint16_t; }
213 int deref_uint16_ptr(uint16_t *l) { return *l; }
214 void free_uint16_ptr(uint16_t *l) { delete l; }
217 long *make_long_ptr();
218 long deref_long_ptr(long *l);
219 void free_long_ptr(long *l);
221 int deref_int_ptr(int *l);
222 void free_int_ptr(int *l);
223 uint16_t *make_uint16_ptr();
224 int deref_uint16_ptr(uint16_t *l);
225 void free_uint16_ptr(uint16_t *l);
227 // create a more pythonic interface
230 def __set_center_freq(self, freq):
232 r = self._real_set_center_freq(freq, tr)
238 def __fpga_master_clock_freq(self):
240 r = self._real_fpga_master_clock_freq(f)
242 result = deref_long_ptr(f)
248 def __adc_rate(self):
249 rate = make_long_ptr();
250 r = self._real_adc_rate(rate)
252 result = deref_long_ptr(rate)
258 def __dac_rate(self):
259 rate = make_long_ptr();
260 r = self._real_dac_rate(rate)
262 result = deref_long_ptr(rate)
268 def __gain_range(self):
269 return [self.gain_min(),
271 self.gain_db_per_step()]
273 # NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'),
274 # but it's not really useful. We let an index error happen here
275 # to identify code using it.
276 def __freq_range(self):
277 return [self.freq_min(),
280 def __daughterboard_id(self):
281 dbid = make_int_ptr()
282 r = self._real_daughterboard_id(dbid)
284 result = deref_int_ptr(dbid)
290 def __default_tx_scale_iq(self, interp):
291 scale_i = make_int_ptr()
292 scale_q = make_int_ptr()
293 self._real_default_tx_scale_iq(interp, scale_i, scale_q)
294 return (deref_int_ptr(scale_i), deref_int_ptr(scale_q))
296 def __read_gpio(self):
297 value = make_uint16_ptr()
298 r = self._real_read_gpio(value)
300 result = deref_uint16_ptr(value)
303 free_uint16_ptr(value)
307 usrp2_source_32fc_sptr.set_center_freq = __set_center_freq
308 usrp2_source_16sc_sptr.set_center_freq = __set_center_freq
309 usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq
310 usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq
312 usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
313 usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
314 usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
315 usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq
317 usrp2_source_32fc_sptr.adc_rate = __adc_rate
318 usrp2_source_16sc_sptr.adc_rate = __adc_rate
319 usrp2_sink_32fc_sptr.dac_rate = __dac_rate
320 usrp2_sink_16sc_sptr.dac_rate = __dac_rate
322 usrp2_source_32fc_sptr.gain_range = __gain_range
323 usrp2_source_16sc_sptr.gain_range = __gain_range
324 usrp2_sink_32fc_sptr.gain_range = __gain_range
325 usrp2_sink_16sc_sptr.gain_range = __gain_range
327 usrp2_source_32fc_sptr.freq_range = __freq_range
328 usrp2_source_16sc_sptr.freq_range = __freq_range
329 usrp2_sink_32fc_sptr.freq_range = __freq_range
330 usrp2_sink_16sc_sptr.freq_range = __freq_range
332 usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id
333 usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id
334 usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id
335 usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id
337 usrp2_sink_32fc_sptr.default_scale_iq = __default_tx_scale_iq
338 usrp2_sink_16sc_sptr.default_scale_iq = __default_tx_scale_iq
340 usrp2_source_32fc_sptr.read_gpio = __read_gpio
341 usrp2_source_16sc_sptr.read_gpio = __read_gpio
342 usrp2_sink_32fc_sptr.read_gpio = __read_gpio
343 usrp2_sink_16sc_sptr.read_gpio = __read_gpio