2 # Copyright 2005 Free Software Foundation, Inc.
4 # This file is part of GNU Radio
6 # GNU Radio is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 3, or (at your option)
11 # GNU Radio is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License
17 # along with GNU Radio; see the file COPYING. If not, write to
18 # the Free Software Foundation, Inc., 51 Franklin Street,
19 # Boston, MA 02110-1301, USA.
22 from gnuradio import usrp1
27 import db_instantiator
28 from usrp_fpga_regs import *
30 #debug_using_gui = True # Must be set to True or False
31 debug_using_gui = False # Must be set to True or False
34 import flexrf_debug_gui
36 # d'board i/o pin defs
37 # Tx and Rx have shared defs, but different i/o regs
39 POWER_UP = (1 << 7) # enables power supply
40 RX_TXN = (1 << 6) # Tx only: T/R antenna switch for TX/RX port
41 RX2_RX1N = (1 << 6) # Rx only: antenna switch between RX2 and TX/RX port
42 ENABLE = (1 << 5) # enables mixer
45 PLL_LOCK_DETECT = (1 << 2)
49 SPI_ENABLE_TX_A = usrp1.SPI_ENABLE_TX_A
50 SPI_ENABLE_TX_B = usrp1.SPI_ENABLE_TX_B
51 SPI_ENABLE_RX_A = usrp1.SPI_ENABLE_RX_A
52 SPI_ENABLE_RX_B = usrp1.SPI_ENABLE_RX_B
54 class flexrf_base(db_base.db_base):
56 Abstract base class for all flexrf boards.
58 Derive board specific subclasses from db_flexrf_base_{tx,rx}
60 def __init__(self, usrp, which):
62 @param usrp: instance of usrp.source_c
63 @param which: which side: 0 or 1 corresponding to side A or B respectively
66 # sets _u _which _tx and _slot
67 db_base.db_base.__init__(self, usrp, which)
70 self.spi_format = usrp1.SPI_FMT_MSB | usrp1.SPI_FMT_HDR_0
72 self._u._write_oe(self._which, 0, 0xffff) # turn off all outputs
73 self._enable_refclk(False) # disable refclk
75 g = self.gain_range() # initialize gain
76 self.set_gain(float(g[0]+g[1]) / 2)
78 self.set_auto_tr(False)
81 title = "FlexRF Debug Rx"
83 title = "FlexRF Debug Tx"
84 self.gui = flexrf_debug_gui.flexrf_debug_gui(self, title)
89 #print "flexrf_base.__del__"
90 self._u.write_io(self._which, self.power_off, POWER_UP) # turn off power to board
91 self._enable_refclk(False) # turn off refclk
92 self.set_auto_tr(False)
94 def _write_all(self, R, control, N):
96 Write R counter latch, control latch and N counter latch to VCO.
98 Adds 10ms delay between writing control and N if this is first call.
99 This is the required power-up sequence.
101 @param $: 24-bit R counter latch
103 @param control: 24-bit control latch
105 @param N: 24-bit N counter latch
109 self._write_control( control)
115 def _write_control(self, control):
116 self._write_it((control & ~0x3) | 0)
118 def _write_R(self, R):
119 self._write_it((R & ~0x3) | 1)
121 def _write_N(self, N):
122 self._write_it((N & ~0x3) | 2)
124 def _write_it(self, v):
125 s = ''.join((chr((v >> 16) & 0xff),
126 chr((v >> 8) & 0xff),
128 self._u._write_spi(0, self.spi_enable, self.spi_format, s)
130 def _lock_detect(self):
132 @returns: the value of the VCO/PLL lock detect bit.
135 if self._u.read_io(self._which) & PLL_LOCK_DETECT:
137 else: # Give it a second chance
138 if self._u.read_io(self._which) & PLL_LOCK_DETECT:
143 def _compute_regs(self, freq):
145 Determine values of R, control, and N registers, along with actual freq.
147 @param freq: target frequency in Hz
149 @returns: (R, control, N, actual_freq)
150 @rtype: tuple(int, int, int, float)
152 Override this in derived classes.
154 raise NotImplementedError
156 def _refclk_freq(self):
157 # return float(self._u.fpga_master_clock_freq())/self._refclk_divisor()
158 return 64e6/self._refclk_divisor()
160 def set_freq(self, freq):
162 @returns (ok, actual_baseband_freq) where:
163 ok is True or False and indicates success or failure,
164 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
167 # Offsetting the LO helps get the Tx carrier leakage out of the way.
168 # This also ensures that on Rx, we're not getting hosed by the
169 # FPGA's DC removal loop's time constant. We were seeing a
170 # problem when running with discontinuous transmission.
171 # Offsetting the LO made the problem go away.
172 freq += self.lo_offset
174 R, control, N, actual_freq = self._compute_regs(freq)
177 self._write_all(R, control, N)
178 return (self._lock_detect(), actual_freq)
180 def gain_range(self):
182 Return range of gain that can be set by this d'board.
184 @returns (min_gain, max_gain, step_size)
185 Where gains are expressed in decibels (your mileage may vary)
187 return (self._u.pga_min(), self._u.pga_max(), self._u.pga_db_per_step())
189 def set_gain(self, gain):
193 @param gain: gain in decibels
196 return self._set_pga(gain)
198 def _set_pga(self, pga_gain):
199 if(self._which == 0):
200 self._u.set_pga (0, pga_gain)
201 self._u.set_pga (1, pga_gain)
203 self._u.set_pga (2, pga_gain)
204 self._u.set_pga (3, pga_gain)
206 def is_quadrature(self):
208 Return True if this board requires both I & Q analog channels.
210 This bit of info is useful when setting up the USRP Rx mux register.
214 # ----------------------------------------------------------------
216 class flexrf_base_tx(flexrf_base):
217 def __init__(self, usrp, which):
219 @param usrp: instance of usrp.sink_c
220 @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
222 flexrf_base.__init__(self, usrp, which)
223 self.spi_enable = (SPI_ENABLE_TX_A, SPI_ENABLE_TX_B)[which]
225 # power up the transmit side, but don't enable the mixer
226 self._u._write_oe(self._which,(POWER_UP|RX_TXN|ENABLE), 0xffff)
227 self._u.write_io(self._which, (self.power_on|RX_TXN), (POWER_UP|RX_TXN|ENABLE))
228 self.lo_offset = 4e6 # FIXME may want to be a function of d'board
231 #print "flexrf_base_tx.__del__"
232 # Power down and leave the T/R switch in the R position
233 self._u.write_io(self._which, (self.power_off|RX_TXN), (POWER_UP|RX_TXN|ENABLE))
234 flexrf_base.__del__(self)
236 def set_auto_tr(self, on):
238 self.set_atr_mask (RX_TXN | ENABLE)
239 self.set_atr_txval(0 | ENABLE)
240 self.set_atr_rxval(RX_TXN | 0)
242 self.set_atr_mask (0)
243 self.set_atr_txval(0)
244 self.set_atr_rxval(0)
246 def set_enable(self, on):
248 Enable transmitter if on is True
250 mask = RX_TXN | ENABLE
255 self._u.write_io(self._which, v, mask)
257 def gain_range(self):
259 Return range of gain that can be set by this d'board.
261 @returns (min_gain, max_gain, step_size)
262 Where gains are expressed in decibels (your mileage may vary)
264 Flex Tx boards require that the PGA be maxed out to properly bias their circuitry.
266 g = self._u.pga_max()
269 def set_gain(self, gain):
273 @param gain: gain in decibels
276 return self._set_pga(self._u.pga_max())
279 class flexrf_base_rx(flexrf_base):
280 def __init__(self, usrp, which):
282 @param usrp: instance of usrp.source_c
283 @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
285 flexrf_base.__init__(self, usrp, which)
286 self.spi_enable = (SPI_ENABLE_RX_A, SPI_ENABLE_RX_B)[which]
288 self._u._write_oe(self._which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff)
289 self._u.write_io(self._which, (self.power_on|RX2_RX1N|ENABLE), (POWER_UP|RX2_RX1N|ENABLE))
291 # set up for RX on TX/RX port
292 self.select_rx_antenna('TX/RX')
294 self.bypass_adc_buffers(True)
296 self.lo_offset = -4e6 # FIXME may want to be a function of d'board
299 # print "flexrf_base_rx.__del__"
301 self._u.write_io(self._which, self.power_off, (POWER_UP|ENABLE))
302 flexrf_base.__del__(self)
304 def set_auto_tr(self, on):
306 self.set_atr_mask (ENABLE)
307 self.set_atr_txval( 0)
308 self.set_atr_rxval(ENABLE)
310 self.set_atr_mask (0)
311 self.set_atr_txval(0)
312 self.set_atr_rxval(0)
314 def select_rx_antenna(self, which_antenna):
316 Specify which antenna port to use for reception.
317 @param which_antenna: either 'TX/RX' or 'RX2'
319 if which_antenna in (0, 'TX/RX'):
320 self._u.write_io(self._which, 0, RX2_RX1N)
321 elif which_antenna in (1, 'RX2'):
322 self._u.write_io(self._which, RX2_RX1N, RX2_RX1N)
324 raise ValueError, "which_antenna must be either 'TX/RX' or 'RX2'"
326 def set_gain(self, gain):
330 @param gain: gain in decibels
333 maxgain = self.gain_range()[1] - self._u.pga_max()
335 pga_gain = gain-maxgain
336 assert pga_gain <= self._u.pga_max()
344 dac_value = (agc_gain*(V_maxgain-V_mingain)/maxgain + V_mingain)*4096/V_fullscale
345 assert dac_value>=0 and dac_value<4096
346 return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
347 self._set_pga(int(pga_gain))
350 # ----------------------------------------------------------------
352 class _AD4360_common(object):
354 # R-Register Common Values
355 self.R_RSV = 0 # bits 23,22
356 self.BSC = 3 # bits 21,20 Div by 8 to be safe
357 self.TEST = 0 # bit 19
358 self.LDP = 1 # bit 18
359 self.ABP = 0 # bit 17,16 3ns
361 # N-Register Common Values
362 self.N_RSV = 0 # bit 7
364 # Control Register Common Values
365 self.PD = 0 # bits 21,20 Normal operation
366 self.PL = 0 # bits 13,12 11mA
367 self.MTLD = 1 # bit 11 enabled
368 self.CPG = 0 # bit 10 CP setting 1
369 self.CP3S = 0 # bit 9 Normal
370 self.PDP = 1 # bit 8 Positive
371 self.MUXOUT = 1 # bits 7:5 Digital Lock Detect
372 self.CR = 0 # bit 4 Normal
373 self.PC = 1 # bits 3,2 Core power 10mA
375 def _compute_regs(self, freq):
377 Determine values of R, control, and N registers, along with actual freq.
379 @param freq: target frequency in Hz
381 @returns: (R, control, N, actual_freq)
382 @rtype: tuple(int, int, int, float)
385 # Band-specific N-Register Values
386 phdet_freq = self._refclk_freq()/self.R_DIV
387 desired_n = round(freq*self.freq_mult/phdet_freq)
388 actual_freq = desired_n * phdet_freq
389 B = math.floor(desired_n/self._prescaler())
390 A = desired_n - self._prescaler()*B
391 self.B_DIV = int(B) # bits 20:8
392 self.A_DIV = int(A) # bit 6:2
393 #assert self.B_DIV >= self.A_DIV
394 if self.B_DIV < self.A_DIV:
396 R = (self.R_RSV<<22) | (self.BSC<<20) | (self.TEST<<19) | (self.LDP<<18) \
397 | (self.ABP<<16) | (self.R_DIV<<2)
399 control = (self.P<<22) | (self.PD<<20) | (self.CP2<<17) | (self.CP1<<14) | (self.PL<<12) \
400 | (self.MTLD<<11) | (self.CPG<<10) | (self.CP3S<<9) | (self.PDP<<8) | \
401 (self.MUXOUT<<5) | (self.CR<<4) | (self.PC<<2)
403 N = (self.DIVSEL<<23) | (self.DIV2<<22) | (self.CPGAIN<<21) | (self.B_DIV<<8) | \
404 (self.N_RSV<<7) | (self.A_DIV<<2)
406 return (R,control,N,actual_freq/self.freq_mult)
408 def _refclk_divisor(self):
410 Return value to stick in REFCLK_DIVISOR register
414 def _prescaler(self):
422 #----------------------------------------------------------------------
423 class _2400_common(_AD4360_common):
425 _AD4360_common.__init__(self)
427 # Band-specific R-Register Values
428 self.R_DIV = 16 # bits 15:2
430 # Band-specific C-Register values
431 self.P = 1 # bits 23,22 Div by 16/17
432 self.CP2 = 7 # bits 19:17
433 self.CP1 = 7 # bits 16:14
435 # Band specifc N-Register Values
436 self.DIVSEL = 0 # bit 23
437 self.DIV2 = 0 # bit 22
438 self.CPGAIN = 0 # bit 21
441 def freq_range(self): # FIXME
442 return (2300e6, 2700e6, 4e6)
444 #----------------------------------------------------------------------
445 class _1200_common(_AD4360_common):
447 _AD4360_common.__init__(self)
449 # Band-specific R-Register Values
450 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
452 # Band-specific C-Register values
453 self.P = 1 # bits 23,22 Div by 16/17
454 self.CP2 = 7 # bits 19:17 1.25 mA
455 self.CP1 = 7 # bits 16:14 1.25 mA
457 # Band specifc N-Register Values
458 self.DIVSEL = 0 # bit 23
459 self.DIV2 = 1 # bit 22
460 self.CPGAIN = 0 # bit 21
463 def freq_range(self): # FIXME
464 return (1150e6, 1350e6, 4e6)
466 #-------------------------------------------------------------------------
467 class _1800_common(_AD4360_common):
469 _AD4360_common.__init__(self)
471 # Band-specific R-Register Values
472 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
474 # Band-specific C-Register values
475 self.P = 1 # bits 23,22 Div by 16/17
476 self.CP2 = 7 # bits 19:17 1.25 mA
477 self.CP1 = 7 # bits 16:14 1.25 mA
479 # Band specifc N-Register Values
480 self.DIVSEL = 0 # bit 23
481 self.DIV2 = 0 # bit 22
483 self.CPGAIN = 0 # bit 21
485 def freq_range(self): # FIXME
486 return (1600e6, 2000e6, 4e6)
488 #-------------------------------------------------------------------------
489 class _900_common(_AD4360_common):
491 _AD4360_common.__init__(self)
493 # Band-specific R-Register Values
494 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
496 # Band-specific C-Register values
497 self.P = 1 # bits 23,22 Div by 16/17
498 self.CP2 = 7 # bits 19:17 1.25 mA
499 self.CP1 = 7 # bits 16:14 1.25 mA
501 # Band specifc N-Register Values
502 self.DIVSEL = 0 # bit 23
503 self.DIV2 = 1 # bit 22
505 self.CPGAIN = 0 # bit 21
507 def freq_range(self): # FIXME
508 return (800e6, 1000e6, 4e6)
510 #-------------------------------------------------------------------------
511 class _400_common(_AD4360_common):
513 _AD4360_common.__init__(self)
515 # Band-specific R-Register Values
516 self.R_DIV = 16 # bits 15:2
518 # Band-specific C-Register values
519 self.P = 0 # bits 23,22 Div by 8/9
520 self.CP2 = 7 # bits 19:17 1.25 mA
521 self.CP1 = 7 # bits 16:14 1.25 mA
523 # Band specifc N-Register Values These are different for TX/RX
524 self.DIVSEL = 0 # bit 23
526 self.DIV2 = 1 # bit 22
528 self.DIV2 = 0 # bit 22 # RX side has built-in DIV2 in AD8348
531 self.CPGAIN = 0 # bit 21
533 def freq_range(self):
534 #return (350e6, 465e6, 1e6) # FIXME prototype
535 return (400e6, 500e6, 1e6) # final version
538 #------------------------------------------------------------
539 class db_flexrf_2400_tx(_2400_common, flexrf_base_tx):
540 def __init__(self, usrp, which):
541 self.power_on = ~POWER_UP
542 self.power_off = ~POWER_UP # powering it off kills the serial bus
543 flexrf_base_tx.__init__(self, usrp, which)
544 _2400_common.__init__(self)
546 class db_flexrf_2400_rx(_2400_common, flexrf_base_rx):
547 def __init__(self, usrp, which):
548 self.power_on = ~POWER_UP
549 self.power_off = ~POWER_UP # Powering it off kills the serial bus
550 flexrf_base_rx.__init__(self, usrp, which)
551 _2400_common.__init__(self)
553 def gain_range(self):
555 Return range of gain that can be set by this d'board.
557 @returns (min_gain, max_gain, step_size)
558 Where gains are expressed in decibels (your mileage may vary)
560 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
562 def i_and_q_swapped(self):
565 class db_flexrf_1200_tx(_1200_common, flexrf_base_tx):
566 def __init__(self, usrp, which):
567 self.power_on = ~POWER_UP
568 self.power_off = ~POWER_UP # powering it off kills the serial bus
569 flexrf_base_tx.__init__(self, usrp, which)
570 _1200_common.__init__(self)
572 class db_flexrf_1200_rx(_1200_common, flexrf_base_rx):
573 def __init__(self, usrp, which):
574 self.power_on = ~POWER_UP
575 self.power_off = ~POWER_UP # powering it off kills the serial bus
576 flexrf_base_rx.__init__(self, usrp, which)
577 _1200_common.__init__(self)
579 def gain_range(self):
581 Return range of gain that can be set by this d'board.
583 @returns (min_gain, max_gain, step_size)
584 Where gains are expressed in decibels (your mileage may vary)
586 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
588 def i_and_q_swapped(self):
591 class db_flexrf_1800_tx(_1800_common, flexrf_base_tx):
592 def __init__(self, usrp, which):
593 self.power_on = ~POWER_UP
594 self.power_off = ~POWER_UP # powering it off kills the serial bus
595 flexrf_base_tx.__init__(self, usrp, which)
596 _1800_common.__init__(self)
598 class db_flexrf_1800_rx(_1800_common, flexrf_base_rx):
599 def __init__(self, usrp, which):
600 self.power_on = ~POWER_UP
601 self.power_off = ~POWER_UP # powering it off kills the serial bus
602 flexrf_base_rx.__init__(self, usrp, which)
603 _1800_common.__init__(self)
605 def gain_range(self):
607 Return range of gain that can be set by this d'board.
609 @returns (min_gain, max_gain, step_size)
610 Where gains are expressed in decibels (your mileage may vary)
612 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
614 def i_and_q_swapped(self):
617 class db_flexrf_900_tx(_900_common, flexrf_base_tx):
618 def __init__(self, usrp, which):
619 self.power_on = ~POWER_UP
620 self.power_off = ~POWER_UP # powering it off kills the serial bus
621 flexrf_base_tx.__init__(self, usrp, which)
622 _900_common.__init__(self)
624 class db_flexrf_900_rx(_900_common, flexrf_base_rx):
625 def __init__(self, usrp, which):
626 self.power_on = ~POWER_UP
627 self.power_off = ~POWER_UP # powering it off kills the serial bus
628 flexrf_base_rx.__init__(self, usrp, which)
629 _900_common.__init__(self)
631 def gain_range(self):
633 Return range of gain that can be set by this d'board.
635 @returns (min_gain, max_gain, step_size)
636 Where gains are expressed in decibels (your mileage may vary)
638 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
640 def i_and_q_swapped(self):
643 class db_flexrf_400_tx(_400_common, flexrf_base_tx):
644 def __init__(self, usrp, which):
645 self.power_on = POWER_UP
646 self.power_off = ~POWER_UP
647 flexrf_base_tx.__init__(self, usrp, which)
648 _400_common.__init__(self)
650 class db_flexrf_400_rx(_400_common, flexrf_base_rx):
651 def __init__(self, usrp, which):
652 self.power_on = POWER_UP
653 self.power_off = ~POWER_UP
654 flexrf_base_rx.__init__(self, usrp, which)
655 _400_common.__init__(self)
657 def gain_range(self):
659 Return range of gain that can be set by this d'board.
661 @returns (min_gain, max_gain, step_size)
662 Where gains are expressed in decibels (your mileage may vary)
664 return (self._u.pga_min(), self._u.pga_max() + 45, 0.035)
666 def i_and_q_swapped(self):
669 # hook these daughterboard classes into the auto-instantiation framework
671 db_instantiator.add(usrp_dbid.FLEX_2400_TX, lambda usrp, which : (db_flexrf_2400_tx(usrp, which),))
672 db_instantiator.add(usrp_dbid.FLEX_2400_RX, lambda usrp, which : (db_flexrf_2400_rx(usrp, which),))
673 db_instantiator.add(usrp_dbid.FLEX_1200_TX, lambda usrp, which : (db_flexrf_1200_tx(usrp, which),))
674 db_instantiator.add(usrp_dbid.FLEX_1200_RX, lambda usrp, which : (db_flexrf_1200_rx(usrp, which),))
675 db_instantiator.add(usrp_dbid.FLEX_1800_TX, lambda usrp, which : (db_flexrf_1800_tx(usrp, which),))
676 db_instantiator.add(usrp_dbid.FLEX_1800_RX, lambda usrp, which : (db_flexrf_1800_rx(usrp, which),))
677 db_instantiator.add(usrp_dbid.FLEX_900_TX, lambda usrp, which : (db_flexrf_900_tx(usrp, which),))
678 db_instantiator.add(usrp_dbid.FLEX_900_RX, lambda usrp, which : (db_flexrf_900_rx(usrp, which),))
679 db_instantiator.add(usrp_dbid.FLEX_400_TX, lambda usrp, which : (db_flexrf_400_tx(usrp, which),))
680 db_instantiator.add(usrp_dbid.FLEX_400_RX, lambda usrp, which : (db_flexrf_400_rx(usrp, which),))