2 # Copyright 2005,2007 Free Software Foundation, Inc.
4 # This file is part of GNU Radio
6 # GNU Radio is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 3, or (at your option)
11 # GNU Radio is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License
17 # along with GNU Radio; see the file COPYING. If not, write to
18 # the Free Software Foundation, Inc., 51 Franklin Street,
19 # Boston, MA 02110-1301, USA.
22 from gnuradio import usrp1
25 from usrpm import usrp_dbid
27 import db_instantiator
28 from usrpm.usrp_fpga_regs import *
30 #debug_using_gui = True # Must be set to True or False
31 debug_using_gui = False # Must be set to True or False
34 import flexrf_debug_gui
36 # d'board i/o pin defs
37 # Tx and Rx have shared defs, but different i/o regs
39 POWER_UP = (1 << 7) # enables power supply
40 RX_TXN = (1 << 6) # Tx only: T/R antenna switch for TX/RX port
41 RX2_RX1N = (1 << 6) # Rx only: antenna switch between RX2 and TX/RX port
42 ENABLE = (1 << 5) # enables mixer
45 PLL_LOCK_DETECT = (1 << 2)
49 SPI_ENABLE_TX_A = usrp1.SPI_ENABLE_TX_A
50 SPI_ENABLE_TX_B = usrp1.SPI_ENABLE_TX_B
51 SPI_ENABLE_RX_A = usrp1.SPI_ENABLE_RX_A
52 SPI_ENABLE_RX_B = usrp1.SPI_ENABLE_RX_B
54 class flexrf_base(db_base.db_base):
56 Abstract base class for all flexrf boards.
58 Derive board specific subclasses from db_flexrf_base_{tx,rx}
60 def __init__(self, usrp, which):
62 @param usrp: instance of usrp.source_c
63 @param which: which side: 0 or 1 corresponding to side A or B respectively
66 # sets _u _which _tx and _slot
67 db_base.db_base.__init__(self, usrp, which)
70 self.spi_format = usrp1.SPI_FMT_MSB | usrp1.SPI_FMT_HDR_0
72 self._u._write_oe(self._which, 0, 0xffff) # turn off all outputs
73 self._enable_refclk(False) # disable refclk
75 g = self.gain_range() # initialize gain
76 self.set_gain(float(g[0]+g[1]) / 2)
78 self.set_auto_tr(False)
81 title = "FlexRF Debug Rx"
83 title = "FlexRF Debug Tx"
84 self.gui = flexrf_debug_gui.flexrf_debug_gui(self, title)
89 #print "flexrf_base.__del__"
90 self._u.write_io(self._which, self.power_off, POWER_UP) # turn off power to board
91 self._enable_refclk(False) # turn off refclk
92 self.set_auto_tr(False)
94 def _write_all(self, R, control, N):
96 Write R counter latch, control latch and N counter latch to VCO.
98 Adds 10ms delay between writing control and N if this is first call.
99 This is the required power-up sequence.
101 @param $: 24-bit R counter latch
103 @param control: 24-bit control latch
105 @param N: 24-bit N counter latch
109 self._write_control( control)
115 def _write_control(self, control):
116 self._write_it((control & ~0x3) | 0)
118 def _write_R(self, R):
119 self._write_it((R & ~0x3) | 1)
121 def _write_N(self, N):
122 self._write_it((N & ~0x3) | 2)
124 def _write_it(self, v):
125 s = ''.join((chr((v >> 16) & 0xff),
126 chr((v >> 8) & 0xff),
128 self._u._write_spi(0, self.spi_enable, self.spi_format, s)
130 def _lock_detect(self):
132 @returns: the value of the VCO/PLL lock detect bit.
135 if self._u.read_io(self._which) & PLL_LOCK_DETECT:
137 else: # Give it a second chance
138 if self._u.read_io(self._which) & PLL_LOCK_DETECT:
143 def _compute_regs(self, freq):
145 Determine values of R, control, and N registers, along with actual freq.
147 @param freq: target frequency in Hz
149 @returns: (R, control, N, actual_freq)
150 @rtype: tuple(int, int, int, float)
152 Override this in derived classes.
154 raise NotImplementedError
156 def _refclk_freq(self):
157 # return float(self._u.fpga_master_clock_freq())/self._refclk_divisor()
158 return 64e6/self._refclk_divisor()
160 def set_freq(self, freq):
162 @returns (ok, actual_baseband_freq) where:
163 ok is True or False and indicates success or failure,
164 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
167 # Offsetting the LO helps get the Tx carrier leakage out of the way.
168 # This also ensures that on Rx, we're not getting hosed by the
169 # FPGA's DC removal loop's time constant. We were seeing a
170 # problem when running with discontinuous transmission.
171 # Offsetting the LO made the problem go away.
172 freq += self._lo_offset
174 R, control, N, actual_freq = self._compute_regs(freq)
177 self._write_all(R, control, N)
178 return (self._lock_detect(), actual_freq)
180 def gain_range(self):
182 Return range of gain that can be set by this d'board.
184 @returns (min_gain, max_gain, step_size)
185 Where gains are expressed in decibels (your mileage may vary)
187 return (self._u.pga_min(), self._u.pga_max(), self._u.pga_db_per_step())
189 def set_gain(self, gain):
193 @param gain: gain in decibels
196 return self._set_pga(gain)
198 def _set_pga(self, pga_gain):
199 if(self._which == 0):
200 self._u.set_pga (0, pga_gain)
201 self._u.set_pga (1, pga_gain)
203 self._u.set_pga (2, pga_gain)
204 self._u.set_pga (3, pga_gain)
206 def is_quadrature(self):
208 Return True if this board requires both I & Q analog channels.
210 This bit of info is useful when setting up the USRP Rx mux register.
214 def set_lo_offset(self, offset):
216 Set amount by which LO is offset from requested tuning frequency.
218 @param offset: offset in Hz
220 self._lo_offset = offset
224 Get amount by which LO is offset from requested tuning frequency.
226 @returns Offset in Hz
228 return self._lo_offset
230 # ----------------------------------------------------------------
232 class flexrf_base_tx(flexrf_base):
233 def __init__(self, usrp, which):
235 @param usrp: instance of usrp.sink_c
236 @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
238 flexrf_base.__init__(self, usrp, which)
239 self.spi_enable = (SPI_ENABLE_TX_A, SPI_ENABLE_TX_B)[which]
241 # power up the transmit side, but don't enable the mixer
242 self._u._write_oe(self._which,(POWER_UP|RX_TXN|ENABLE), 0xffff)
243 self._u.write_io(self._which, (self.power_on|RX_TXN), (POWER_UP|RX_TXN|ENABLE))
244 self.set_lo_offset(4e6)
247 #print "flexrf_base_tx.__del__"
248 # Power down and leave the T/R switch in the R position
249 self._u.write_io(self._which, (self.power_off|RX_TXN), (POWER_UP|RX_TXN|ENABLE))
250 flexrf_base.__del__(self)
252 def set_auto_tr(self, on):
254 self.set_atr_mask (RX_TXN | ENABLE)
255 self.set_atr_txval(0 | ENABLE)
256 self.set_atr_rxval(RX_TXN | 0)
258 self.set_atr_mask (0)
259 self.set_atr_txval(0)
260 self.set_atr_rxval(0)
262 def set_enable(self, on):
264 Enable transmitter if on is True
266 mask = RX_TXN | ENABLE
271 self._u.write_io(self._which, v, mask)
273 def gain_range(self):
275 Return range of gain that can be set by this d'board.
277 @returns (min_gain, max_gain, step_size)
278 Where gains are expressed in decibels (your mileage may vary)
280 Flex Tx boards require that the PGA be maxed out to properly bias their circuitry.
282 g = self._u.pga_max()
285 def set_gain(self, gain):
289 @param gain: gain in decibels
292 return self._set_pga(self._u.pga_max())
294 class flexrf_base_rx(flexrf_base):
295 def __init__(self, usrp, which):
297 @param usrp: instance of usrp.source_c
298 @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
300 flexrf_base.__init__(self, usrp, which)
301 self.spi_enable = (SPI_ENABLE_RX_A, SPI_ENABLE_RX_B)[which]
303 self._u._write_oe(self._which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff)
304 self._u.write_io(self._which, (self.power_on|RX2_RX1N|ENABLE), (POWER_UP|RX2_RX1N|ENABLE))
306 # set up for RX on TX/RX port
307 self.select_rx_antenna('TX/RX')
309 self.bypass_adc_buffers(True)
310 self.set_lo_offset(-4e6)
313 # print "flexrf_base_rx.__del__"
315 self._u.write_io(self._which, self.power_off, (POWER_UP|ENABLE))
316 flexrf_base.__del__(self)
318 def set_auto_tr(self, on):
320 self.set_atr_mask (ENABLE)
321 self.set_atr_txval( 0)
322 self.set_atr_rxval(ENABLE)
324 self.set_atr_mask (0)
325 self.set_atr_txval(0)
326 self.set_atr_rxval(0)
328 def select_rx_antenna(self, which_antenna):
330 Specify which antenna port to use for reception.
331 @param which_antenna: either 'TX/RX' or 'RX2'
333 if which_antenna in (0, 'TX/RX'):
334 self._u.write_io(self._which, 0, RX2_RX1N)
335 elif which_antenna in (1, 'RX2'):
336 self._u.write_io(self._which, RX2_RX1N, RX2_RX1N)
338 raise ValueError, "which_antenna must be either 'TX/RX' or 'RX2'"
340 def set_gain(self, gain):
344 @param gain: gain in decibels
347 maxgain = self.gain_range()[1] - self._u.pga_max()
349 pga_gain = gain-maxgain
350 assert pga_gain <= self._u.pga_max()
358 dac_value = (agc_gain*(V_maxgain-V_mingain)/maxgain + V_mingain)*4096/V_fullscale
359 assert dac_value>=0 and dac_value<4096
360 return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
361 self._set_pga(int(pga_gain))
363 # ----------------------------------------------------------------
365 class _AD4360_common(object):
367 # R-Register Common Values
368 self.R_RSV = 0 # bits 23,22
369 self.BSC = 3 # bits 21,20 Div by 8 to be safe
370 self.TEST = 0 # bit 19
371 self.LDP = 1 # bit 18
372 self.ABP = 0 # bit 17,16 3ns
374 # N-Register Common Values
375 self.N_RSV = 0 # bit 7
377 # Control Register Common Values
378 self.PD = 0 # bits 21,20 Normal operation
379 self.PL = 0 # bits 13,12 11mA
380 self.MTLD = 1 # bit 11 enabled
381 self.CPG = 0 # bit 10 CP setting 1
382 self.CP3S = 0 # bit 9 Normal
383 self.PDP = 1 # bit 8 Positive
384 self.MUXOUT = 1 # bits 7:5 Digital Lock Detect
385 self.CR = 0 # bit 4 Normal
386 self.PC = 1 # bits 3,2 Core power 10mA
388 def _compute_regs(self, freq):
390 Determine values of R, control, and N registers, along with actual freq.
392 @param freq: target frequency in Hz
394 @returns: (R, control, N, actual_freq)
395 @rtype: tuple(int, int, int, float)
398 # Band-specific N-Register Values
399 phdet_freq = self._refclk_freq()/self.R_DIV
400 desired_n = round(freq*self.freq_mult/phdet_freq)
401 actual_freq = desired_n * phdet_freq
402 B = math.floor(desired_n/self._prescaler())
403 A = desired_n - self._prescaler()*B
404 self.B_DIV = int(B) # bits 20:8
405 self.A_DIV = int(A) # bit 6:2
406 #assert self.B_DIV >= self.A_DIV
407 if self.B_DIV < self.A_DIV:
409 R = (self.R_RSV<<22) | (self.BSC<<20) | (self.TEST<<19) | (self.LDP<<18) \
410 | (self.ABP<<16) | (self.R_DIV<<2)
412 control = (self.P<<22) | (self.PD<<20) | (self.CP2<<17) | (self.CP1<<14) | (self.PL<<12) \
413 | (self.MTLD<<11) | (self.CPG<<10) | (self.CP3S<<9) | (self.PDP<<8) | \
414 (self.MUXOUT<<5) | (self.CR<<4) | (self.PC<<2)
416 N = (self.DIVSEL<<23) | (self.DIV2<<22) | (self.CPGAIN<<21) | (self.B_DIV<<8) | \
417 (self.N_RSV<<7) | (self.A_DIV<<2)
419 return (R,control,N,actual_freq/self.freq_mult)
421 def _refclk_divisor(self):
423 Return value to stick in REFCLK_DIVISOR register
427 def _prescaler(self):
435 #----------------------------------------------------------------------
436 class _2400_common(_AD4360_common):
438 _AD4360_common.__init__(self)
440 # Band-specific R-Register Values
441 self.R_DIV = 16 # bits 15:2
443 # Band-specific C-Register values
444 self.P = 1 # bits 23,22 Div by 16/17
445 self.CP2 = 7 # bits 19:17
446 self.CP1 = 7 # bits 16:14
448 # Band specifc N-Register Values
449 self.DIVSEL = 0 # bit 23
450 self.DIV2 = 0 # bit 22
451 self.CPGAIN = 0 # bit 21
454 def freq_range(self): # FIXME
455 return (2300e6, 2700e6, 4e6)
457 #----------------------------------------------------------------------
458 class _1200_common(_AD4360_common):
460 _AD4360_common.__init__(self)
462 # Band-specific R-Register Values
463 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
465 # Band-specific C-Register values
466 self.P = 1 # bits 23,22 Div by 16/17
467 self.CP2 = 7 # bits 19:17 1.25 mA
468 self.CP1 = 7 # bits 16:14 1.25 mA
470 # Band specifc N-Register Values
471 self.DIVSEL = 0 # bit 23
472 self.DIV2 = 1 # bit 22
473 self.CPGAIN = 0 # bit 21
476 def freq_range(self): # FIXME
477 return (1150e6, 1350e6, 4e6)
479 #-------------------------------------------------------------------------
480 class _1800_common(_AD4360_common):
482 _AD4360_common.__init__(self)
484 # Band-specific R-Register Values
485 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
487 # Band-specific C-Register values
488 self.P = 1 # bits 23,22 Div by 16/17
489 self.CP2 = 7 # bits 19:17 1.25 mA
490 self.CP1 = 7 # bits 16:14 1.25 mA
492 # Band specifc N-Register Values
493 self.DIVSEL = 0 # bit 23
494 self.DIV2 = 0 # bit 22
496 self.CPGAIN = 0 # bit 21
498 def freq_range(self): # FIXME
499 return (1600e6, 2000e6, 4e6)
501 #-------------------------------------------------------------------------
502 class _900_common(_AD4360_common):
504 _AD4360_common.__init__(self)
506 # Band-specific R-Register Values
507 self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
509 # Band-specific C-Register values
510 self.P = 1 # bits 23,22 Div by 16/17
511 self.CP2 = 7 # bits 19:17 1.25 mA
512 self.CP1 = 7 # bits 16:14 1.25 mA
514 # Band specifc N-Register Values
515 self.DIVSEL = 0 # bit 23
516 self.DIV2 = 1 # bit 22
518 self.CPGAIN = 0 # bit 21
520 def freq_range(self): # FIXME
521 return (800e6, 1000e6, 4e6)
523 #-------------------------------------------------------------------------
524 class _400_common(_AD4360_common):
526 _AD4360_common.__init__(self)
528 # Band-specific R-Register Values
529 self.R_DIV = 16 # bits 15:2
531 # Band-specific C-Register values
532 self.P = 0 # bits 23,22 Div by 8/9
533 self.CP2 = 7 # bits 19:17 1.25 mA
534 self.CP1 = 7 # bits 16:14 1.25 mA
536 # Band specifc N-Register Values These are different for TX/RX
537 self.DIVSEL = 0 # bit 23
539 self.DIV2 = 1 # bit 22
541 self.DIV2 = 0 # bit 22 # RX side has built-in DIV2 in AD8348
544 self.CPGAIN = 0 # bit 21
546 def freq_range(self):
547 #return (350e6, 465e6, 1e6) # FIXME prototype
548 return (400e6, 500e6, 1e6) # final version
551 #------------------------------------------------------------
552 class db_flexrf_2400_tx(_2400_common, flexrf_base_tx):
553 def __init__(self, usrp, which):
554 self.power_on = ~POWER_UP
555 self.power_off = ~POWER_UP # powering it off kills the serial bus
556 flexrf_base_tx.__init__(self, usrp, which)
557 _2400_common.__init__(self)
559 class db_flexrf_2400_rx(_2400_common, flexrf_base_rx):
560 def __init__(self, usrp, which):
561 self.power_on = ~POWER_UP
562 self.power_off = ~POWER_UP # Powering it off kills the serial bus
563 flexrf_base_rx.__init__(self, usrp, which)
564 _2400_common.__init__(self)
566 def gain_range(self):
568 Return range of gain that can be set by this d'board.
570 @returns (min_gain, max_gain, step_size)
571 Where gains are expressed in decibels (your mileage may vary)
573 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
575 def i_and_q_swapped(self):
578 class db_flexrf_1200_tx(_1200_common, flexrf_base_tx):
579 def __init__(self, usrp, which):
580 self.power_on = ~POWER_UP
581 self.power_off = ~POWER_UP # powering it off kills the serial bus
582 flexrf_base_tx.__init__(self, usrp, which)
583 _1200_common.__init__(self)
585 class db_flexrf_1200_rx(_1200_common, flexrf_base_rx):
586 def __init__(self, usrp, which):
587 self.power_on = ~POWER_UP
588 self.power_off = ~POWER_UP # powering it off kills the serial bus
589 flexrf_base_rx.__init__(self, usrp, which)
590 _1200_common.__init__(self)
592 def gain_range(self):
594 Return range of gain that can be set by this d'board.
596 @returns (min_gain, max_gain, step_size)
597 Where gains are expressed in decibels (your mileage may vary)
599 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
601 def i_and_q_swapped(self):
604 class db_flexrf_1800_tx(_1800_common, flexrf_base_tx):
605 def __init__(self, usrp, which):
606 self.power_on = ~POWER_UP
607 self.power_off = ~POWER_UP # powering it off kills the serial bus
608 flexrf_base_tx.__init__(self, usrp, which)
609 _1800_common.__init__(self)
611 class db_flexrf_1800_rx(_1800_common, flexrf_base_rx):
612 def __init__(self, usrp, which):
613 self.power_on = ~POWER_UP
614 self.power_off = ~POWER_UP # powering it off kills the serial bus
615 flexrf_base_rx.__init__(self, usrp, which)
616 _1800_common.__init__(self)
618 def gain_range(self):
620 Return range of gain that can be set by this d'board.
622 @returns (min_gain, max_gain, step_size)
623 Where gains are expressed in decibels (your mileage may vary)
625 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
627 def i_and_q_swapped(self):
630 class db_flexrf_900_tx(_900_common, flexrf_base_tx):
631 def __init__(self, usrp, which):
632 self.power_on = ~POWER_UP
633 self.power_off = ~POWER_UP # powering it off kills the serial bus
634 flexrf_base_tx.__init__(self, usrp, which)
635 _900_common.__init__(self)
637 class db_flexrf_900_rx(_900_common, flexrf_base_rx):
638 def __init__(self, usrp, which):
639 self.power_on = ~POWER_UP
640 self.power_off = ~POWER_UP # powering it off kills the serial bus
641 flexrf_base_rx.__init__(self, usrp, which)
642 _900_common.__init__(self)
644 def gain_range(self):
646 Return range of gain that can be set by this d'board.
648 @returns (min_gain, max_gain, step_size)
649 Where gains are expressed in decibels (your mileage may vary)
651 return (self._u.pga_min(), self._u.pga_max() + 70, 0.05)
653 def i_and_q_swapped(self):
656 class db_flexrf_400_tx(_400_common, flexrf_base_tx):
657 def __init__(self, usrp, which):
658 self.power_on = POWER_UP
659 self.power_off = ~POWER_UP
660 flexrf_base_tx.__init__(self, usrp, which)
661 _400_common.__init__(self)
663 class db_flexrf_400_rx(_400_common, flexrf_base_rx):
664 def __init__(self, usrp, which):
665 self.power_on = POWER_UP
666 self.power_off = ~POWER_UP
667 flexrf_base_rx.__init__(self, usrp, which)
668 _400_common.__init__(self)
670 def gain_range(self):
672 Return range of gain that can be set by this d'board.
674 @returns (min_gain, max_gain, step_size)
675 Where gains are expressed in decibels (your mileage may vary)
677 return (self._u.pga_min(), self._u.pga_max() + 45, 0.035)
679 def i_and_q_swapped(self):
682 # hook these daughterboard classes into the auto-instantiation framework
684 db_instantiator.add(usrp_dbid.FLEX_2400_TX, lambda usrp, which : (db_flexrf_2400_tx(usrp, which),))
685 db_instantiator.add(usrp_dbid.FLEX_2400_RX, lambda usrp, which : (db_flexrf_2400_rx(usrp, which),))
686 db_instantiator.add(usrp_dbid.FLEX_1200_TX, lambda usrp, which : (db_flexrf_1200_tx(usrp, which),))
687 db_instantiator.add(usrp_dbid.FLEX_1200_RX, lambda usrp, which : (db_flexrf_1200_rx(usrp, which),))
688 db_instantiator.add(usrp_dbid.FLEX_1800_TX, lambda usrp, which : (db_flexrf_1800_tx(usrp, which),))
689 db_instantiator.add(usrp_dbid.FLEX_1800_RX, lambda usrp, which : (db_flexrf_1800_rx(usrp, which),))
690 db_instantiator.add(usrp_dbid.FLEX_900_TX, lambda usrp, which : (db_flexrf_900_tx(usrp, which),))
691 db_instantiator.add(usrp_dbid.FLEX_900_RX, lambda usrp, which : (db_flexrf_900_rx(usrp, which),))
692 db_instantiator.add(usrp_dbid.FLEX_400_TX, lambda usrp, which : (db_flexrf_400_tx(usrp, which),))
693 db_instantiator.add(usrp_dbid.FLEX_400_RX, lambda usrp, which : (db_flexrf_400_rx(usrp, which),))