2 # Copyright 2005 Free Software Foundation, Inc.
4 # This file is part of GNU Radio
6 # GNU Radio is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 3, or (at your option)
11 # GNU Radio is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License
17 # along with GNU Radio; see the file COPYING. If not, write to
18 # the Free Software Foundation, Inc., 51 Franklin Street,
19 # Boston, MA 02110-1301, USA.
25 import db_instantiator
27 def int_seq_to_str (seq):
28 """convert a sequence of integers into a string"""
29 return ''.join (map (chr, seq))
31 def str_to_int_seq (str):
32 """convert a string to a list of integers"""
35 class db_dbs_rx (db_base.db_base):
36 def __init__ (self, usrp, which):
38 Control DBS receiver based USRP daughterboard.
40 @param usrp: instance of usrp.source_c
41 @param which: which side: 0 or 1 corresponding to RX_A or RX_B respectively
45 db_base.db_base.__init__(self, usrp, which)
47 self._u._write_oe(self._which,0x0001,0x0001)
48 self.i2c_addr = (0x67, 0x65)[self._which]
49 # set basic parameters
65 # FIXME this should be in the core dboard class
66 self.refclk_divisor = 16
67 self._enable_refclk(True)
70 self.set_gain(float(g[0]+g[1]) / 2)
71 self.bypass_adc_buffers(True)
75 self._enable_refclk(False)
77 def _write_reg (self, regno, v):
78 """regno is in [0,5], v is value to write to register"""
79 assert (0 <= regno and regno <= 5)
80 self._u.write_i2c (self.i2c_addr, int_seq_to_str ((regno, v)))
82 def _write_regs (self, starting_regno, vals):
83 """starting_regno is in [0,5],
84 vals is a seq of integers to write to consecutive registers"""
85 self._u.write_i2c (self.i2c_addr,
86 int_seq_to_str ((starting_regno,) + tuple (vals)))
88 def _read_status (self):
89 """If successful, return list of two ints: [status_info, filter_DAC]"""
90 s = self._u.read_i2c (self.i2c_addr, 2)
93 return str_to_int_seq (s)
95 def _send_reg(self,regno):
96 assert (0 <= regno and regno <= 5)
98 self._write_reg(0,(self.div2<<7) + (self.n>>8))
100 self._write_reg(1,self.n & 255)
102 self._write_reg(2,self.osc + (self.cp<<3) + (self.r_int<<5))
104 self._write_reg(3,self.fdac)
106 self._write_reg(4,self.m + (self.dl<<5) + (self.ade<<6) + (self.adl<<7))
108 self._write_reg(5,self.gc2 + (self.diag<<5))
116 def _set_fdac(self,fdac):
117 assert fdac>=0 and fdac<128
121 def set_bw (self, bw):
122 #assert (bw>=4e6 and bw<=33e6)
123 assert (bw>=1e6 and bw<=33e6)
125 m_max = int(min(31,math.floor(self._refclk_freq()/1e6)))
126 elif bw >= 2e6: # Outside of Specs!
127 m_max = int(min(31,math.floor(self._refclk_freq()/.5e6)))
128 else: # Way outside of Specs!
129 m_max = int(min(31,math.floor(self._refclk_freq()/.25e6)))
131 m_min = int(math.ceil(self._refclk_freq()/2.5e6))
133 while m_test >= m_min:
134 fdac_test = int(round(((bw * m_test / self._refclk_freq())-4)/.145))
139 if (m_test>=m_min and fdac_test >=0):
141 self._set_fdac(fdac_test)
142 return (self.m,self.fdac,self._refclk_freq()/self.m*(4+0.145*self.fdac))
144 print "Failed to set bw"
147 def _set_dl(self,dl):
148 assert dl == 0 or dl == 1
152 def _set_gc2(self,gc2):
153 assert gc2<32 and gc2>=0
157 def _set_gc1(self,gc1):
158 assert gc1>=0 and gc1<4096
160 self._u.write_aux_dac(self._which,0,int(gc1))
162 def _set_pga(self, pga_gain):
163 assert pga_gain >=0 and pga_gain <=20
164 if(self._which == 0):
165 self._u.set_pga (0, pga_gain)
166 self._u.set_pga (1, pga_gain)
168 self._u.set_pga (2, pga_gain)
169 self._u.set_pga (3, pga_gain)
171 def gain_range(self):
174 def set_gain(self,gain):
175 if not (gain>=0 and gain<105):
176 raise ValueError, "gain out of range"
182 gc1 = int((-gain*1.85/56.0 + 2.6)*4096.0/3.3)
188 gc2 = int(round(31.0 * (1-gain/24.0)))
203 def _set_osc(self,osc):
204 assert osc>=0 and osc<8
208 def _set_cp(self,cp):
209 assert cp>=0 and cp<4
214 assert n>256 and n<32768
219 def _set_div2(self,div2):
220 assert div2 == 0 or div2 == 1
225 assert r>=0 and r<128
227 self.r_int = int(round(math.log10(r)/math.log10(2)) - 1)
230 # FIXME How do we handle ADE and ADL properly?
231 def _set_ade(self,ade):
232 assert ade == 0 or ade == 1
236 def freq_range(self):
237 return (500e6, 2.6e9, 1e6)
239 def _refclk_divisor(self):
241 Return value to stick in REFCLK_DIVISOR register
245 def set_freq(self, freq):
249 @param freq: target frequency in Hz
252 @returns (ok, actual_baseband_freq) where:
253 ok is True or False and indicates success or failure,
254 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
256 if not (freq>=500e6 and freq<=2.6e9):
266 rmin=max(2,self._refclk_freq()/2e6)
267 rmax=min(128,self._refclk_freq()/150e3)
274 n = round(freq/(self._refclk_freq()/r))
278 delta = abs(n*self._refclk_freq()/r - freq)
283 if delta < best_delta*0.9:
288 self._set_r(int(best_r))
290 self._set_n(int(round(best_n)))
294 elif vcofreq < 2711e6:
296 elif vcofreq < 3025e6:
298 elif vcofreq < 3341e6:
300 elif vcofreq < 3727e6:
302 elif vcofreq < 4143e6:
304 elif vcofreq < 4493e6:
313 while adc_val == 0 or adc_val == 7:
314 (byte1,byte2) = self._read_status()
327 if adc_val == 1 or adc_val == 2:
329 elif adc_val == 3 or adc_val == 4:
334 return (True, self.n * self._refclk_freq() / self.r)
336 def is_quadrature(self):
338 Return True if this board requires both I & Q analog channels.
340 This bit of info is useful when setting up the USRP Rx mux register.
344 # hook this daughterboard class into the auto-instantiation framework
345 db_instantiator.add(usrp_dbid.DBS_RX, lambda usrp, which : (db_dbs_rx(usrp, which),))