2 # Copyright 2005,2006,2007 Free Software Foundation, Inc.
4 # This file is part of GNU Radio
6 # GNU Radio is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 2, or (at your option)
11 # GNU Radio is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License
17 # along with GNU Radio; see the file COPYING. If not, write to
18 # the Free Software Foundation, Inc., 51 Franklin Street,
19 # Boston, MA 02110-1301, USA.
23 from usrpm import usrp_prims
24 from usrpm.usrp_fpga_regs import *
26 class db_base(object):
28 Abstract base class for all daughterboards.
30 This defines the required operations and interfaces for all d'boards.
32 def __init__(self, usrp, which):
34 Initialize daughterboard interface.
36 @param usrp: instance of usrp
37 @param which: which daughterboard side: A = 0, B = 1
41 if not (which in (0, 1)):
42 raise ValueError, "Invalid value of which: %s" % (which,)
44 self._u = weakref.proxy(usrp)
47 if hasattr(self._u, 'tx_freq'): # is this a tx or rx daughterboard?
49 self._slot = which * 2
52 self._slot = which * 2 + 1
54 self._refclk_reg = (FR_TX_A_REFCLK,FR_RX_A_REFCLK,FR_TX_B_REFCLK,FR_RX_B_REFCLK)[self._slot]
58 return self._u.daughterboard_id(self._which)
61 return usrp_prims.usrp_dbid_to_string(self.dbid())
63 def side_and_name(self):
64 return "AB"[self._which] + ': ' + self.name()
66 # Function to bypass ADC buffers. Any board which is DC-coupled should bypass the buffers
67 def bypass_adc_buffers(self,bypass):
69 raise RuntimeError, "TX Board has no adc buffers"
71 self._u.set_adc_buffer_bypass(0, bypass)
72 self._u.set_adc_buffer_bypass(1, bypass)
74 self._u.set_adc_buffer_bypass(2, bypass)
75 self._u.set_adc_buffer_bypass(3, bypass)
77 # ------------------------------------------------------------------------
78 # Reference Clock section
80 # Control whether a reference clock is sent to the daughterboards,
83 # Bit 7 -- 1 turns on refclk, 0 allows IO use
84 # Bits 6:0 Divider value
87 def _refclk_freq(self):
88 return self._u.fpga_master_clock_freq()/self._refclk_divisor()
90 def _enable_refclk(self,enable):
91 CLOCK_OUT = 1 # Clock is on lowest bit
93 REFCLK_DIVISOR_MASK = 0x7f
95 self._u._write_oe(self._which, CLOCK_OUT, CLOCK_OUT) # output enable
96 self._u._write_fpga_reg(self._refclk_reg,
97 ((self._refclk_divisor() & REFCLK_DIVISOR_MASK)
100 self._u._write_fpga_reg(self._refclk_reg, 0)
102 def _refclk_divisor(self):
104 Return value to stick in REFCLK_DIVISOR register
106 raise NotImplementedError
108 # ------------------------------------------------------------------------
109 # Automatic Transmit/Receive switching
111 # The presence or absence of data in the FPGA transmit fifo
112 # selects between two sets of values for each of the 4 banks of
113 # daughterboard i/o pins.
115 # Each daughterboard slot has 3 16-bit registers associated with it:
116 # FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
118 # FR_ATR_MASK_{0,1,2,3}:
120 # These registers determine which of the daugherboard i/o pins are
121 # affected by ATR switching. If a bit in the mask is set, the
122 # corresponding i/o bit is controlled by ATR, else it's output
123 # value comes from the normal i/o pin output register:
126 # FR_ATR_TXVAL_{0,1,2,3}:
127 # FR_ATR_RXVAL_{0,1,2,3}:
129 # If the Tx fifo contains data, then the bits from TXVAL that are
130 # selected by MASK are output. Otherwise, the bits from RXVAL that
131 # are selected by MASK are output.
133 def set_atr_mask(self, v):
137 return self._u._write_fpga_reg(FR_ATR_MASK_0 + 3 * self._slot, v)
139 def set_atr_txval(self, v):
141 Set Auto T/R register value to be used when transmitting.
143 return self._u._write_fpga_reg(FR_ATR_TXVAL_0 + 3 * self._slot, v)
145 def set_atr_rxval(self, v):
147 Set Auto T/R register value to be used when receiving.
149 return self._u._write_fpga_reg(FR_ATR_RXVAL_0 + 3 * self._slot, v)
151 def set_atr_tx_delay(self, v):
153 Set Auto T/R delay (in clock ticks) from when Tx fifo gets data to
156 return self._u._write_fpga_reg(FR_ATR_TX_DELAY, v)
158 def set_atr_rx_delay(self, v):
160 Set Auto T/R delay (in clock ticks) from when Tx fifo goes empty to
163 return self._u._write_fpga_reg(FR_ATR_RX_DELAY, v)
165 # derived classes should override the following methods
167 def freq_range(self):
169 Return range of frequencies in Hz that can be tuned by this d'board.
171 @returns (min_freq, max_freq, step_size)
174 raise NotImplementedError
176 def set_freq(self, target_freq):
180 @param freq: target RF frequency in Hz
183 @returns (ok, actual_baseband_freq) where:
184 ok is True or False and indicates success or failure,
185 actual_baseband_freq is the RF frequency that corresponds to DC in the IF.
187 raise NotImplementedError
189 def gain_range(self):
191 Return range of gain that can be set by this d'board.
193 @returns (min_gain, max_gain, step_size)
194 Where gains are expressed in decibels (your mileage may vary)
196 raise NotImplementedError
198 def set_gain(self, gain):
202 @param gain: gain in decibels
205 raise NotImplementedError
207 def is_quadrature(self):
209 Return True if this daughterboard does quadrature up or down conversion.
210 That is, return True if this board requires both I & Q analog channels.
212 This bit of info is useful when setting up the USRP Rx mux register.
214 raise NotImplementedError
216 def i_and_q_swapped(self):
218 Return True if this is a quadrature device and ADC 0 is Q.
222 def spectrum_inverted(self):
224 Return True if the dboard gives an inverted spectrum
228 def set_enable(self, on):
230 For tx daughterboards, this controls the transmitter enable.
234 def set_auto_tr(self,on):
236 Enable automatic Transmit/Receive switching (ATR).
238 Should be overridden in subclasses that care. This will typically
239 set the atr_mask, txval and rxval.