3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
6 // Copyright (C) 2007 Corgan Enterprises LLC
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 // Top level module for a full setup with DUCs and DDCs
25 // Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
26 // for debugging info. NB, This can kill the m'board and/or d'board if you
27 // have anything except basic d'boards installed.
29 // Uncomment the following to include optional circuitry
32 (output MYSTERY_SIGNAL,
43 input wire [11:0] rx_a_a,
44 input wire [11:0] rx_b_a,
45 input wire [11:0] rx_a_b,
46 input wire [11:0] rx_b_b,
48 output wire [13:0] tx_a,
49 output wire [13:0] tx_b,
56 input wire [2:0] usbctl,
57 output wire [1:0] usbrdy,
58 inout [15:0] usbdata, // NB Careful, inout
60 // These are the general purpose i/o's that go to the daughterboard slots
61 inout wire [15:0] io_tx_a,
62 inout wire [15:0] io_tx_b,
63 inout wire [15:0] io_rx_a,
64 inout wire [15:0] io_rx_b
66 wire [15:0] debugdata,debugctrl;
67 assign MYSTERY_SIGNAL = 1'b0;
71 // wire WR = usbctl[0];
76 assign usbrdy[0] = 1'b0; // have_space;
77 assign usbrdy[1] = have_pkt_rdy;
79 wire tx_underrun, rx_overrun;
80 wire clear_status = FX2_1;
81 assign FX2_2 = rx_overrun;
82 assign FX2_3 = 1'b0; // tx_underrun;
84 wire [15:0] usbdata_out;
86 wire [3:0] rx_numchan;
87 wire enable_tx, enable_rx;
88 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
90 // Tri-state bus macro
91 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
93 assign clk64 = master_clk;
96 wire tx_sample_strobe;
100 wire [6:0] serial_addr;
101 wire [31:0] serial_data;
103 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
106 wire [15:0] tx_i, tx_q;
109 dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
110 .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
111 .tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
113 assign tx_a = tx_dac[15:2];
115 // Wedge DAC #2 at zero
116 assign TXSYNC_B = 1'b0;
119 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
121 wire rx_sample_strobe, rx_strobe;
122 wire [15:0] rx_adc0_i, rx_adc0_q;
123 wire [15:0] rx_buf_i, rx_buf_q;
125 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
126 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
127 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
128 .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
129 .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
130 .ddc1_in_i(),.ddc1_in_q(),
131 .ddc2_in_i(),.ddc2_in_q(),
132 .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
135 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
136 .reset_regs(rx_dsp_reset),
137 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
138 .channels(rx_numchan),
139 .ch_0(rx_buf_i),.ch_1(rx_buf_q),
143 .rxclk(clk64),.rxstrobe(rx_strobe),
144 .clear_status(clear_status),
145 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
149 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
150 // Top level application
153 ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
154 .tx_rst_i(tx_dsp_reset),.tx_enable_i(enable_tx),.tx_strobe_i(tx_sample_strobe),
155 .tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
156 .rx_rst_i(rx_dsp_reset),.rx_enable_i(enable_rx),.rx_strobe_i(rx_sample_strobe),.rx_strobe_o(rx_strobe),
157 .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),.rx_imp_i_o(rx_buf_i),.rx_imp_q_o(rx_buf_q)
161 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
164 wire [31:0] capabilities;
165 assign capabilities[7] = 0; // `TX_CAP_HB;
166 assign capabilities[6:4] = 2; // `TX_CAP_NCHAN;
167 assign capabilities[3] = 0; // `RX_CAP_HB;
168 assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
171 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
172 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
173 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
174 .readback_0(),.readback_1(),.readback_2(capabilities),.readback_3(),
175 .readback_4(),.readback_5(),.readback_6(),.readback_7()
178 wire [15:0] reg_0,reg_1,reg_2,reg_3;
179 master_control master_control
180 ( .master_clk(clk64),.usbclk(usbclk),
181 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
182 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
183 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
184 .enable_tx(enable_tx),.enable_rx(enable_rx),
185 .interp_rate(),.decim_rate(),
186 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(),
187 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
189 .debug_0(),.debug_1(),
190 .debug_2(),.debug_3(),
191 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
194 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
195 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
196 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
197 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
199 endmodule // usrp_sounder