3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2007 Corgan Enterprises LLC
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 `include "../../../../usrp/firmware/include/fpga_regs_common.v"
23 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
25 module sounder(clk_i,saddr_i,sdata_i,s_strobe_i,tx_rst_i,tx_enable_i,tx_strobe_i,
26 tx_dac_i_o,tx_dac_q_o,
27 rx_rst_i,rx_enable_i,rx_strobe_i,rx_strobe_o,
28 rx_adc_i_i,rx_adc_q_i,rx_imp_i_o,rx_imp_q_o);
31 input clk_i; // Master clock @ 64 MHz
32 input [6:0] saddr_i; // Configuration bus address
33 input [31:0] sdata_i; // Configuration bus data
34 input s_strobe_i; // Configuration bus write
37 input tx_rst_i; // Independent subsystem reset
38 input tx_enable_i; // Turn on transmitter functionality
39 input tx_strobe_i; // Generate an transmitter output sample
40 output [15:0] tx_dac_i_o; // I channel transmitter output to DAC
41 output [15:0] tx_dac_q_o; // Q channel transmitter output to DAC
44 input rx_rst_i; // Independent subsystem reset
45 input rx_enable_i; // Turn on receiver functionality
46 input rx_strobe_i; // Indicates receive sample ready from ADC
47 output rx_strobe_o; // Indicates output samples ready for Rx FIFO
48 input [15:0] rx_adc_i_i; // I channel input from ADC
49 input [15:0] rx_adc_q_i; // Q channel input from ADC
50 output [15:0] rx_imp_i_o; // I channel impulse response to Rx FIFO
51 output [15:0] rx_imp_q_o; // Q channel impulse response to Rx FIFO
54 wire [4:0] degree; // LFSR register length
55 wire [15:0] mask; // LFSR parity mask
56 wire [15:0] len; // PN code sequence length
57 wire loopback; // Enable digital loopback
59 // Loopback implementation
60 wire [15:0] tx_i, tx_q, rx_i, rx_q; // Internal transmit and receive data bus
62 assign tx_dac_i_o = loopback ? 16'b0 : tx_i;
63 assign tx_dac_q_o = loopback ? 16'b0 : tx_q;
64 assign rx_i = loopback ? tx_i : rx_adc_i_i;
65 assign rx_q = loopback ? tx_q : rx_adc_q_i;
67 setting_reg #(`FR_USER_0) sr_lfsr_degree
68 ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(degree) );
70 setting_reg #(`FR_USER_1) sr_mode
71 ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
74 lfsr_constants constants(.degree_i(degree),.mask_o(mask),.len_o(len));
76 sounder_tx transmitter
77 ( .clk_i(clk_i),.rst_i(tx_rst_i),.ena_i(tx_enable_i),.strobe_i(tx_strobe_i),.mask_i(mask),
78 .tx_i_o(tx_i),.tx_q_o(tx_q) );
81 ( .clk_i(clk_i),.rst_i(rx_rst_i),.ena_i(rx_enable_i),
82 .rx_strobe_i(rx_strobe_i),.tx_strobe_i(tx_strobe_i),.mask_i(mask),.len_i(len),
83 .rx_in_i_i(rx_i),.rx_in_q_i(rx_q),.rx_i_o(rx_imp_i_o),.rx_q_o(rx_imp_q_o),
84 .rx_strobe_o(rx_strobe_o) );