3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2003,2004 Matt Ettus
6 // Copyright (C) 2007 Corgan Enterprises LLC
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 module usrp_radar_mono
24 (output MYSTERY_SIGNAL,
35 input wire [11:0] rx_a_a,
36 input wire [11:0] rx_b_a,
37 input wire [11:0] rx_a_b,
38 input wire [11:0] rx_b_b,
40 output wire [13:0] tx_a,
41 output wire [13:0] tx_b,
48 input wire [2:0] usbctl,
49 output wire [1:0] usbrdy,
50 inout [15:0] usbdata, // NB Careful, inout
52 // These are the general purpose i/o's that go to the daughterboard slots
53 inout wire [15:0] io_tx_a,
54 inout wire [15:0] io_tx_b,
55 inout wire [15:0] io_rx_a,
56 inout wire [15:0] io_rx_b
58 wire [15:0] debugdata,debugctrl;
59 assign MYSTERY_SIGNAL = 1'b0;
63 // wire WR = usbctl[0];
68 assign usbrdy[0] = 1'b0; // have_space;
69 assign usbrdy[1] = have_pkt_rdy;
71 wire tx_underrun, rx_overrun;
72 wire clear_status = FX2_1;
73 assign FX2_2 = rx_overrun;
74 assign FX2_3 = 1'b0; // tx_underrun;
76 wire [15:0] usbdata_out;
78 wire [3:0] rx_numchan;
79 wire enable_tx, enable_rx;
80 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
82 // Tri-state bus macro
83 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
85 assign clk64 = master_clk;
88 wire tx_sample_strobe;
92 wire [6:0] serial_addr;
93 wire [31:0] serial_data;
95 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
99 wire [13:0] tx_i, tx_q;
103 dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
104 .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
105 .tx_data_o(tx_dac),.tx_sync_o(tx_sync));
107 // Route transmitted signal to side A or side B
108 assign tx_a = tx_side ? 14'b0 : tx_dac;
109 assign tx_b = tx_side ? tx_dac : 14'b0;
110 assign TXSYNC_A = tx_side ? 1'b0 : tx_sync;
111 assign TXSYNC_B = tx_side ? tx_sync : 1'b0;
113 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
116 wire [15:0] rx_adc0_i, rx_adc0_q;
117 wire [15:0] rx_buf_i, rx_buf_q;
119 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
120 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
121 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
122 .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
123 .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
124 .ddc1_in_i(),.ddc1_in_q(),
125 .ddc2_in_i(),.ddc2_in_q(),
126 .ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
129 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
130 .reset_regs(rx_dsp_reset),
131 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
132 .channels(rx_numchan),
133 .ch_0(rx_buf_i),.ch_1(rx_buf_q),
137 .rxclk(clk64),.rxstrobe(rx_strobe),
138 .clear_status(clear_status),
139 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
143 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
144 // Top level application
145 radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
146 .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
147 .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
148 .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.io_tx_ena_o(io_tx_ena)
151 // Route TX enable out to RFX transmit mixer enable
152 assign io_tx_a[5] = tx_side ? 1'bz : io_tx_ena;
153 assign io_tx_b[5] = tx_side ? io_tx_ena : 1'bz;
155 // Route opposite of TX enable out to RFX receive mixer
156 //assign io_rx_a[5] = tx_side ? 1'bz : ~io_tx_ena;
157 //assign io_rx_b[5] = tx_side ? ~io_tx_ena : 1'bz;
158 assign io_rx_a[5] = 1'b1;
159 assign io_rx_b[5] = 1'b1;
162 // Route TX enable out to RX/TX switch
163 assign io_tx_a[6] = tx_side ? 1'bz : ~io_tx_ena;
164 assign io_tx_b[6] = tx_side ? ~io_tx_ena : 1'bz;
166 // Enable common RX/TX antenna
167 assign io_rx_a[6] = tx_side ? 1'bz : 1'b0;
168 assign io_rx_b[6] = tx_side ? 1'b0 : 1'bz;
170 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
173 wire [31:0] capabilities;
174 assign capabilities[7] = 0; // `TX_CAP_HB;
175 assign capabilities[6:4] = 1; // `TX_CAP_NCHAN;
176 assign capabilities[3] = 0; // `RX_CAP_HB;
177 assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
180 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
181 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
182 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
183 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
184 .readback_4(),.readback_5(),.readback_6(),.readback_7()
187 wire [15:0] reg_0,reg_1,reg_2,reg_3;
188 master_control master_control
189 ( .master_clk(clk64),.usbclk(usbclk),
190 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
191 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
192 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
193 .enable_tx(enable_tx),.enable_rx(enable_rx),
194 .interp_rate(),.decim_rate(),
195 .tx_sample_strobe(),.strobe_interp(),
196 .rx_sample_strobe(),.strobe_decim(),
198 .debug_0(),.debug_1(),
199 .debug_2(),.debug_3(),
200 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
202 wire [1:0] dummy_io = 2'bz;
205 (.io_0({io_tx_a[15:7],dummy_io,io_tx_a[4:0]}), // Don't connect pins used above
206 .io_1({io_rx_a[15:7],dummy_io,io_rx_a[4:0]}),
207 .io_2({io_tx_b[15:7],dummy_io,io_tx_b[4:0]}),
208 .io_3({io_rx_b[15:7],dummy_io,io_rx_b[4:0]}),
209 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
210 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
211 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
213 endmodule // usrp_radar_mono