3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2007 Corgan Enterprises LLC
7 // This program is free software; you can redistribute it and/or modify
8 // it under the terms of the GNU General Public License as published by
9 // the Free Software Foundation; either version 2 of the License, or
10 // (at your option) any later version.
12 // This program is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 // GNU General Public License for more details.
17 // You should have received a copy of the GNU General Public License
18 // along with this program; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 `include "../lib/radar_config.vh"
24 module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
25 tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
26 ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
29 input clk_i; // Master clock @ 64 MHz
30 input [6:0] saddr_i; // Configuration bus address
31 input [31:0] sdata_i; // Configuration bus data
32 input s_strobe_i; // Configuration bus write
34 // Control and configuration outputs
42 output [31:0] fstart_o;
43 output [31:0] fincr_o;
44 output [15:0] pulse_num_o;
47 // Internal configuration
58 // Configuration from host
60 setting_reg #(`FR_RADAR_MODE) sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
62 assign reset_o = mode[0];
63 assign tx_side_o = mode[1];
64 assign lp_ena = mode[2];
65 assign md_ena = mode[3];
66 assign dr_ena = mode[4];
67 assign chirps = mode[6:5];
68 assign dbg_o = mode[7];
70 setting_reg #(`FR_RADAR_TON) sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
73 setting_reg #(`FR_RADAR_TSW) sr_tsw(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
76 setting_reg #(`FR_RADAR_TLOOK) sr_tlook(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
79 setting_reg #(`FR_RADAR_TIDLE) sr_tidle(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
82 setting_reg #(`FR_RADAR_AMPL) sr_ampl(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
85 setting_reg #(`FR_RADAR_FSTART) sr_fstart(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
88 setting_reg #(`FR_RADAR_FINCR) sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
91 setting_reg #(`FR_RADAR_ATRDEL) sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
94 // Pulse state machine
97 `define ST_LOOK 4'b0100
98 `define ST_IDLE 4'b1000
102 reg [15:0] pulse_num_o;
104 always @(posedge clk_i)
109 pulse_num_o <= 16'b0;
114 if (count == {16'b0,t_on})
118 pulse_num_o <= pulse_num_o + 16'b1;
121 count <= count + 32'b1;
124 if (count == {16'b0,t_sw})
130 count <= count + 32'b1;
133 if (count == {16'b0,t_look})
139 count <= count + 32'b1;
148 count <= count + 32'b1;
150 default: // Invalid state, reset state machine
157 assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
158 assign tx_ctrl_o = (state == `ST_ON);
159 assign rx_ctrl_o = (state == `ST_LOOK);
161 // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
162 atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
163 .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
164 .atr_tx_o(io_tx_ena_o));
166 endmodule // radar_control