3 * Copyright 2008 Free Software Foundation, Inc.
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23 #ifndef INCLUDED_MSDD_SOURCE_BASE_H
24 #define INCLUDED_MSDD_SOURCE_BASE_H
25 #include <gr_sync_block.h>
29 * \brief abstract interface to MSDD 6000 Softronics module Rx path (Rev 1)
32 class msdd_source_base : public gr_sync_block {
34 enum msdd_command_type_t {
40 enum msdd_fft_window_type_t {
47 enum msdd_fft_mode_t {
53 enum msdd_decimation_t {
65 enum msdd_fft_points_t {
80 std::auto_ptr<Impl> pimpl;
84 msdd_source_base (const std::string &name,
85 gr_io_signature_sptr output_signature,
89 unsigned short port_src
90 ) throw (std::runtime_error);
93 * \brief return number of msdd input bytes required to produce noutput items.
95 virtual int ninput_bytes_reqd_for_noutput_items (int noutput_items) = 0;
98 * \brief number of bytes in a low-level sample
100 unsigned int sizeof_basic_sample() const;
102 virtual void copy_from_msdd_buffer (gr_vector_void_star &output_items,
104 int output_items_available,
105 int &output_items_produced,
106 const void *msdd_buffer,
107 int msdd_buffer_length,
108 int &bytes_read) = 0;
110 int readsock(int sockfd, unsigned char* buf, int nbytes);
112 void write_request_packet(unsigned int number_samples);
113 void* make_request_packet(unsigned int& size, unsigned int number_samples);
115 unsigned long set_fft_size (int channel, unsigned long fft_size);
118 //! magic value used on alternate register read interfaces
119 static const int READ_FAILED = -99999;
121 ~msdd_source_base ();
123 int work (int noutput_items,
124 gr_vector_const_void_star &input_items,
125 gr_vector_void_star &output_items);
131 * \brief open a socket specified by the port and ip address info
133 * Opens a socket, binds to the address, and waits for a connection
134 * over UDP. If any of these fail, the fuction retuns the error and exits.
139 * \brief Close current socket.
141 * Shuts down read/write on the socket
146 * \brief Set decimator rate. \p rate must be EVEN and in [8, 256].
148 * The final complex sample rate across the USB is
149 * adc_freq () / decim_rate ()
151 bool set_decim_rate (unsigned int rate);
152 //bool set_nchannels (int nchan);
153 //bool set_mux (int mux);
156 * \brief set the center frequency of the digital down converter.
158 * \p channel must be 0. \p freq is the center frequency in Hz.
159 * It must be in the range [-FIXME, FIXME]. The frequency specified is
160 * quantized. Use rx_freq to retrieve the actual value used.
162 bool set_rx_freq (int channel, double freq);
167 bool set_opp_mode (int channel, msdd_command_type_t mode);
171 // * \brief set fpga special modes
173 // bool set_fpga_mode (int mode);
175 void set_verbose (bool verbose);
178 // * \brief Set the digital down converter phase register.
180 // * \param channel which ddc channel [0, 3]
181 // * \param phase 32-bit integer phase value.
183 // bool set_ddc_phase(int channel, int phase);
186 * \brief Set Programmable Gain Amplifier (PGA)
188 * \param which which A/D [0,3]
189 * \param gain_in_db gain value (linear in dB)
191 * gain is rounded to closest setting supported by hardware.
193 * \returns true iff sucessful.
195 * \sa pga_min(), pga_max(), pga_db_per_step()
197 bool set_pga (int which, double gain_in_db);
200 * \brief Return programmable gain amplifier gain setting in dB.
202 * \param which which A/D [0,3]
204 double pga (int which) const;
207 * \brief Return minimum legal PGA setting in dB.
209 double pga_min () const;
212 * \brief Return maximum legal PGA setting in dB.
214 double pga_max () const;
217 * \brief Return hardware step size of PGA (linear in dB).
219 double pga_db_per_step () const;
223 // long converter_rate() const;
225 unsigned int decim_rate () const;
226 // int nchannels () const;
228 double rx_freq (int channel) const;
229 unsigned int fft_points() const;
230 int noverruns () const;
233 * \brief return the msdd's serial number.
235 * \returns non-zero length string iff successful.
237 std::string serial_number();
240 // * \brief Enable/disable automatic DC offset removal control loop in FPGA
242 // * \param bits which control loops to enable
243 // * \param mask which \p bits to pay attention to
245 // * If the corresponding bit is set, enable the automatic DC
246 // * offset correction control loop.
249 // * The 4 low bits are significant:
257 // * By default the control loop is enabled on all ADC's.
259 // bool set_dc_offset_cl_enable(int bits, int mask);
262 * \brief Specify Rx data format.
264 * \param format format specifier
266 * Rx data format control register
269 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
270 * +-----------------------------------------+-+-+---------+-------+
271 * | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
272 * +-----------------------------------------+-+-+---------+-------+
274 * SHIFT specifies arithmetic right shift [0, 15]
275 * WIDTH specifies bit-width of I & Q samples across the USB [1, 16] (not all valid)
276 * Q if set deliver both I & Q, else just I
277 * B if set bypass half-band filter.
279 * Right now the acceptable values are:
285 * More valid combos to come.
287 * Default value is 0x00000300 16-bits, 0 shift, deliver both I & Q.
289 // bool set_format(unsigned int format);
292 * \brief return current format
294 // unsigned int format () const;
296 // static unsigned int make_format(int width=16, int shift=0,
297 // bool want_q=true, bool bypass_halfband=false);
298 // static int format_width(unsigned int format);
299 // static int format_shift(unsigned int format);
300 // static bool format_want_q(unsigned int format);
301 // static bool format_bypass_halfband(unsigned int format);
303 bool set_desired_packet_size (int which, unsigned long packet_size);
305 unsigned long desired_packet_size (int which) const;
308 #endif /* INCLUDED_MSDD_SOURCE_BASE_H */