3 // USRP - Universal Software Radio Peripheral
5 // Copyright (C) 2005,2006 Matt Ettus
6 // Copyright (C) 2008 Corgan Enterprises LLC
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
23 `include "../../../../usrp/firmware/include/fpga_regs_common.v"
24 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
27 ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
28 input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
29 input wire [15:0] io_0_force_output, input wire [15:0] io_2_force_output,
30 input wire [15:0] io_1_force_input, input wire [15:0] io_3_force_input,
31 input clock, input rx_reset, input tx_reset,
32 input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
34 reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
36 bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe | io_0_force_output),.reg_val(reg_0));
37 bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe & (~io_1_force_input)),.reg_val(reg_1));
38 bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe | io_2_force_output),.reg_val(reg_2));
39 bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe & (~io_3_force_input)),.reg_val(reg_3));
41 // Upper 16 bits are mask for lower 16
42 always @(posedge clock)
46 <= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
48 <= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
50 <= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
52 <= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
53 endcase // case(serial_addr)