1 Quick start multi-usrp:
3 Unpack, build and install usrp, gnuradio-core and gr-usrp
4 Versions need to be more recent then 2.7cvs/svn 11 may 2006
6 Make sure usrp/fpga/rbf/rev2/multi*.rbf is installed in /usr/local/share/usrp/rev2/
7 Make sure usrp/fpga/rbf/rev4/multi*.rbf is installed in /usr/local/share/usrp/rev4/
8 (If in doubt, copy manually)
10 build and install gr-wxgui gr-audio-xxx and so on.
12 unpack gnuradio-examples.
14 There is a gnuradio-examples/python/multi_usrp directory which contains examples
17 Put at least a basic RX or dbsrx board in RXA of the master and RXA of the slave board.
18 Make sure that the usrps have a serial or unique identifier programmed in their eeprom.
19 (All new rev 4.1 boards have this)
20 You can do without a serial but then you never know which usrp is the master and which is the slave.
24 Now connect the 64MHz clocks between the boards with a short sma coax cable.
25 (See the wiki on how to enable clock-out and clock-in
26 http://comsec.com/wiki?USRPClockingNotes )
28 You need one board with a clock out and one board with a clock in.
30 You can choose any of the two boards as master or slave, this is not dependant on which board has the clock-out or in.
31 In my experiments I had fewer problems when the board that has the clock-in will be the master board.
33 You can use a standard 16-pole flatcable to connect tvrx, basic-rx or dbsrx boards.
34 Of this 16pin flatcable only two pins are used (io15 and ground)
35 For all new daughterboards which use up a lot of io pins you have to use a cable with fewer connections.
36 The savest is using a 2pin headercable connected to io15,gnd (a cable like the ones used to connect frontpanel leds to the mainboard of a PC)
38 If using basic rx board:
39 Connect a 16-pole flatcable from J25 on basicrx/dbs_rx in rxa of the master usrp to J25 on basicrx/dbsrx in RXA of the slave usrp
40 Don't twist the cable (Make sure the pin1 marker (red line on the flatcable) is on the same side of the connector (at io-8 on the master and at io8 on the slave.))
41 For basic_rx this means the marker should be on the side of the dboard with the sma connectors.
42 For dbs_rx this means the marker should be on the side of the dboard with the two little chips.
43 In other words, don't twist the cable, you will burn your board if you do.
45 You can also connect a flatcable with multiple connectors from master-J25 to slave1-J25 to slave2-J25 to ...
46 You will however have to think of something to create a common 64Mhz clock for more then two usrps.
48 For all other daughterboards, connect a 2wire cable from masterRXA J25 io15,gnd to slaveRXA J25 io15,gnd
51 So now the hardware is setup, software is setup. Lets do some tests.
53 Connect power to both usrps.
54 unpack the gnuradio_examples somewhere (cvs version later then 11 may 2006)
55 go to the gnuradio-examples/python/multi_usrp folder.
58 ./multi_usrp_oscope.py -x 12345678
60 It should tell you that usrp 12345678 is not found and tell you which serials are available.
62 Now run ./multi_usrp_oscope.py -x actualserialnum
63 You should now get an oscope with two channels, one is from the master and one is from the slave
64 It will which show the I-signal from channel 0 of the master usrp and I-signal from channel 0 of the slave usrp.
65 (For testing connect the same signal source to the inputs of both boards)
66 The signals should be aligned.
67 If you click the sync button, it will resync the master and slave (should never be needed)
70 ./multi_usrp_oscope.py --help
71 To see all available options.
74 Now you are ready to do phase-locked aligned signal processing.
76 You can also capture to file with:
77 ./multi_usrp_rx_cfile.py
79 run ./multi_usrp_rx_cfile.py --help to see all available options.
83 Here follows a description of the detail blocks used in usrp_multi.py
87 With this code you can connect two or more usrps (with a locked clock) and get synchronised samples.
88 You must connect a (flat)cable between a dboard on the master in RXA and a dboard on the slave in RXA.
89 You then put one usrp in master mode, put the other in slave mode.
91 The easiest thing to see how this works is just looking at the code in
93 multi_usrp_rx_cfile.py
95 Use the usrp_multi block which is installed by gr-usrp.
96 instantiate in the following way:
98 self.multi=usrp_multi.multi_source_align( fg=self, master_serialno=options.master_serialno, decim=options.decim, nchan=options.nchan )
100 nchan should be 2 or 4.
102 You determine which is the master by master_serialno (this is a text string a hexadecimal number).
103 If you enter a serial number which is not found it will print the serial numbers which are available.
104 If you give no serial number (master_serialno=None), the code will pick a Master for you.
106 You can get a reference to the master and the slave usrp in the following way:
108 self.um=self.multi.get_master_usrp()
109 self.us=self.multi.get_slave_usrp()
111 You only need these references for setting freqs/gains or getting info about daughterboards.
112 Don't use the output directly but use the aligned output from multi.get_master_source_c() and multi.get_slave_source_c()
114 You get references to the aligned output samples in the following way:
115 aligned_master_source_c=self.multi.get_master_source_c()
116 aligned_slave_source_c=self.multi.get_slave_source_c()
118 These blocks have multiple outputs.
119 output 0 is the sample counter (high bits in I, low bits in Q)
120 You normally don't need the samplecounters so you can ignore output 0
122 output 1 is the first aligend output channel (if you enable 2 or 4 channels)
123 output 2 is the second output channel (only if you enable 4 channels)
125 so the usefull 4 channels are:
126 self.aligned_master_chan1=(self.multi.get_master_source_c(),1)
127 self.aligned_master_chan2=(self.multi.get_master_source_c(),2)
128 self.aligned_slave_chan1=(self.multi.get_slave_source_c(),1)
129 self.aligned_slave_chan2=(self.multi.get_slave_source_c(),2)
131 The two samplecounters are:
132 self.aligned_master_samplecounter=(self.multi.get_master_source_c(),0)
133 self.aligned_slave_samplecounter=(self.multi.get_slave_source_c(),0)
135 You can set the gain or tune the frequency for all 4 receive daughetrboards at once:
136 self.multi.set_gain_all_rx(options.gain)
137 result,r1,r2,r3,r4 = self.multi.tune_all_rx(options.freq)
139 This will only work reliably when you have all the same daughterboards.
140 Otherwise set all freqs and gains individually.
142 You must call self.multi.sync() at least once AFTER the flowgraph has started running.
143 (This will synchronise the streams of the two usrps)
145 This work was funded by Toby Oliver at Sensus Analytics / Path Intelligence.
146 Many Thanks for making this possible.
148 It was written by Martin Dudok van Heel at Olifantasia.
152 Here follows a brief of the new blocks and (changes)functionality written for multi-usrp support.
154 You can also look at the generated documentation in
155 /usr/local/share/doc/gnuradio-core-X.X
156 /usr/local/share/doc/usrp-X.X
157 (Make sure to build and install the documentation, go to the doc directory of the sourcetree and issue make doc; make install)
162 multi_usrp/multi_usrp_oscope.py
163 multi_usrp/multi_usrp_rx_cfile.py
167 gr.align_on_samplenumbers_ss (int nchan,int align_interval)
169 align several complex short (interleaved short) input channels with corresponding unsigned 32 bit sample_counters (provided as interleaved 16 bit values)
172 nchan number of complex_short input channels (including the 32 bit counting channel)
173 align_interval interval at which the samples are aligned, ignored for now.
175 Pay attention on how you connect this block It expects a minimum of 2 usrp_source_s with nchan number of channels and as mode usrp_prims.bmFR_MODE_RX_COUNTING_32BIT enabled. This means that the first complex_short channel is an interleaved 32 bit counter. The samples are aligned by dropping samples untill the samplenumbers match.
178 gnuradio-core/src/lib/general/gr_align_on_samplenumbers_ss.cc
179 gnuradio-core/src/lib/general/gr_align_on_samplenumbers_ss.h
180 gnuradio-core/src/lib/general/gr_align_on_samplenumbers_ss.i
184 added _write_fpga_reg_masked
186 new usrp_multi block which can instantiate two linked usrps as master and slave and alignes their output.
187 It has a sync() function which should be called AFTER the flowgraph has started running.
189 \brief Call this on a master usrp to sync master and slave by outputing a sync pulse on rx_a_io[15].
190 The 32 bit samplecounter of master and slave will be reset to zero and all phase and buffer related things in the usrps are reset.
191 Call this only after the flowgraph has been started, otherwise there will be no effect since everything is kept in reset state as long as the flowgraph is not running.
192 \returns true if successfull.
198 src/usrp1_source_base.cc
199 src/usrp1_source_base.h
204 new constant bmFR_MODE_RX_COUNTING_32BIT (could also be added as extra mode like FPGA_MODE_COUNTING_32BIT)
205 Use this for the mode parameter when creating a usrp when you want to use the master/slave setup or if you want to use the 32 bit counter for other things, like testing with gr.check_counting_s(True)
207 added register FR_RX_MASTER_SLAVE
208 added bitno and bitmaskes:
209 bmFR_MODE_RX_COUNTING_32BIT
212 bitnoFR_RX_SYNC_MASTER
213 bitnoFR_RX_SYNC_SLAVE
215 bitnoFR_RX_SYNC_INPUT_IOPIN 15
216 bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
217 bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
218 bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
220 added _write_fpga_reg_masked()
221 added new toplevel folder usrp_multi
222 added usrp_multi.v and master_control_multi.v
223 added new MULTI_ON and COUNTER_32BIT_ON defines
224 If these are turned off usrp_multi.v will behave exactly as usrp_std.v
226 added setting_reg_masked.v
227 changed reset behaviour of phase_acc.v and rx_buffer.v
229 changed generate_regs.py to handle bm and bitno defines
233 firmware/include/fpga_regs_standard.v
234 firmware/include/fpga_regs_common.h
235 firmware/include/generate_regs.py
236 firmware/include/fpga_regs_standard.h
237 host/lib/usrp_basic.h
238 host/lib/usrp_basic.cc
239 host/lib/usrp_standard.h
241 fpga/toplevel/usrp_std/usrp_std.v
242 fpga/toplevel/usrp_multi/usrp_multi.esf
243 fpga/toplevel/usrp_multi/usrp_multi.vh
244 fpga/toplevel/usrp_multi/usrp_std.vh
245 fpga/toplevel/usrp_multi/usrp_multi_config_2rxhb_0tx.vh
246 fpga/toplevel/usrp_multi/usrp_multi_config_2rxhb_2tx.vh
247 fpga/toplevel/usrp_multi/usrp_multi.v
248 fpga/toplevel/usrp_multi/usrp_multi.qpf
249 fpga/toplevel/usrp_multi/usrp_multi.psf
250 fpga/toplevel/usrp_multi/usrp_multi_config_2rx_0tx.vh
251 fpga/toplevel/usrp_multi/usrp_multi.qsf
252 fpga/toplevel/usrp_multi/usrp_multi_config_4rx_0tx.vh
253 fpga/toplevel/usrp_multi/usrp_multi.csf
254 fpga/toplevel/usrp_multi/.cvsignore
255 fpga/sdr_lib/rx_buffer.v
256 fpga/sdr_lib/master_control_multi.v
257 fpga/sdr_lib/phase_acc.v
258 fpga/sdr_lib/setting_reg_masked.v