2 * Copyright (C) 2011 Peter Zotov <whitequark@whitequark.org>
3 * Use of this source code is governed by a BSD-style
4 * license that can be found in the LICENSE file.
14 #include <sys/types.h>
18 #include <sys/socket.h>
19 #include <netinet/in.h>
20 #include <arpa/inet.h>
23 #include <stlink-common.h>
24 #include <uglylogging.h>
26 #include "gdb-remote.h"
27 #include "gdb-server.h"
29 #define FLASH_BASE 0x08000000
31 //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize
32 #define FLASH_PAGE (sl->flash_pgsz)
34 stlink_t *connected_stlink = NULL;
36 static const char hex[] = "0123456789abcdef";
38 static const char* current_memory_map = NULL;
40 typedef struct _st_state_t {
41 // things from command line, bleh
50 int serve(stlink_t *sl, st_state_t *st);
51 char* make_memory_map(stlink_t *sl);
53 static void cleanup(int signal __attribute__((unused))) {
54 if (connected_stlink) {
55 /* Switch back to mass storage mode before closing. */
56 stlink_run(connected_stlink);
57 stlink_exit_debug_mode(connected_stlink);
58 stlink_close(connected_stlink);
66 int parse_options(int argc, char** argv, st_state_t *st) {
67 static struct option long_options[] = {
68 {"help", no_argument, NULL, 'h'},
69 {"verbose", optional_argument, NULL, 'v'},
70 {"stlink_version", required_argument, NULL, 's'},
71 {"stlinkv1", no_argument, NULL, '1'},
72 {"listen_port", required_argument, NULL, 'p'},
73 {"multi", optional_argument, NULL, 'm'},
74 {"no-reset", optional_argument, NULL, 'n'},
77 const char * help_str = "%s - usage:\n\n"
78 " -h, --help\t\tPrint this help\n"
79 " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n"
80 " -v, --verbose\t\tSpecify generally verbose logging\n"
81 " -s X, --stlink_version=X\n"
82 "\t\t\tChoose what version of stlink to use, (defaults to 2)\n"
83 " -1, --stlinkv1\tForce stlink version 1\n"
84 " -p 4242, --listen_port=1234\n"
85 "\t\t\tSet the gdb server listen port. "
86 "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n"
88 "\t\t\tSet gdb server to extended mode.\n"
89 "\t\t\tst-util will continue listening for connections after disconnect.\n"
91 "\t\t\tDo not reset board on connection.\n"
93 "The STLINKv2 device to use can be specified in the environment\n"
94 "variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.\n"
102 while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) {
105 printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n");
106 printf("option %s", long_options[option_index].name);
108 printf(" with arg %s", optarg);
113 printf(help_str, argv[0]);
118 st->logging_level = atoi(optarg);
120 st->logging_level = DEFAULT_LOGGING_LEVEL;
124 st->stlink_version = 1;
127 sscanf(optarg, "%i", &q);
128 if (q < 0 || q > 2) {
129 fprintf(stderr, "stlink version %d unknown!\n", q);
132 st->stlink_version = q;
135 sscanf(optarg, "%i", &q);
137 fprintf(stderr, "Can't use a negative port to listen on: %d\n", q);
152 printf("non-option ARGV-elements: ");
153 while (optind < argc)
154 printf("%s ", argv[optind++]);
161 int main(int argc, char** argv) {
167 memset(&state, 0, sizeof(state));
169 state.stlink_version = 2;
170 state.logging_level = DEFAULT_LOGGING_LEVEL;
171 state.listen_port = DEFAULT_GDB_LISTEN_PORT;
172 state.reset = 1; /* By default, reset board */
173 parse_options(argc, argv, &state);
174 switch (state.stlink_version) {
176 sl = stlink_open_usb(state.logging_level, 0);
177 if(sl == NULL) return 1;
180 sl = stlink_v1_open(state.logging_level, 0);
181 if(sl == NULL) return 1;
185 connected_stlink = sl;
186 signal(SIGINT, &cleanup);
187 signal(SIGTERM, &cleanup);
193 ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id);
195 voltage = stlink_target_voltage(sl);
197 ILOG("Target voltage is %d mV.\n", voltage);
202 current_memory_map = make_memory_map(sl);
206 if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) {
212 if (serve(sl, &state)) {
213 sleep (1); // don't go bezurk if serve returns with error
218 } while (state.persistent);
225 /* Switch back to mass storage mode before closing. */
226 stlink_exit_debug_mode(sl);
232 static const char* const target_description_F4 =
233 "<?xml version=\"1.0\"?>"
234 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
235 "<target version=\"1.0\">"
236 " <architecture>arm</architecture>"
237 " <feature name=\"org.gnu.gdb.arm.m-profile\">"
238 " <reg name=\"r0\" bitsize=\"32\"/>"
239 " <reg name=\"r1\" bitsize=\"32\"/>"
240 " <reg name=\"r2\" bitsize=\"32\"/>"
241 " <reg name=\"r3\" bitsize=\"32\"/>"
242 " <reg name=\"r4\" bitsize=\"32\"/>"
243 " <reg name=\"r5\" bitsize=\"32\"/>"
244 " <reg name=\"r6\" bitsize=\"32\"/>"
245 " <reg name=\"r7\" bitsize=\"32\"/>"
246 " <reg name=\"r8\" bitsize=\"32\"/>"
247 " <reg name=\"r9\" bitsize=\"32\"/>"
248 " <reg name=\"r10\" bitsize=\"32\"/>"
249 " <reg name=\"r11\" bitsize=\"32\"/>"
250 " <reg name=\"r12\" bitsize=\"32\"/>"
251 " <reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
252 " <reg name=\"lr\" bitsize=\"32\"/>"
253 " <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
254 " <reg name=\"xpsr\" bitsize=\"32\" regnum=\"25\"/>"
255 " <reg name=\"msp\" bitsize=\"32\" regnum=\"26\" type=\"data_ptr\" group=\"general\" />"
256 " <reg name=\"psp\" bitsize=\"32\" regnum=\"27\" type=\"data_ptr\" group=\"general\" />"
257 " <reg name=\"control\" bitsize=\"8\" regnum=\"28\" type=\"int\" group=\"general\" />"
258 " <reg name=\"faultmask\" bitsize=\"8\" regnum=\"29\" type=\"int\" group=\"general\" />"
259 " <reg name=\"basepri\" bitsize=\"8\" regnum=\"30\" type=\"int\" group=\"general\" />"
260 " <reg name=\"primask\" bitsize=\"8\" regnum=\"31\" type=\"int\" group=\"general\" />"
261 " <reg name=\"s0\" bitsize=\"32\" regnum=\"32\" type=\"float\" group=\"float\" />"
262 " <reg name=\"s1\" bitsize=\"32\" type=\"float\" group=\"float\" />"
263 " <reg name=\"s2\" bitsize=\"32\" type=\"float\" group=\"float\" />"
264 " <reg name=\"s3\" bitsize=\"32\" type=\"float\" group=\"float\" />"
265 " <reg name=\"s4\" bitsize=\"32\" type=\"float\" group=\"float\" />"
266 " <reg name=\"s5\" bitsize=\"32\" type=\"float\" group=\"float\" />"
267 " <reg name=\"s6\" bitsize=\"32\" type=\"float\" group=\"float\" />"
268 " <reg name=\"s7\" bitsize=\"32\" type=\"float\" group=\"float\" />"
269 " <reg name=\"s8\" bitsize=\"32\" type=\"float\" group=\"float\" />"
270 " <reg name=\"s9\" bitsize=\"32\" type=\"float\" group=\"float\" />"
271 " <reg name=\"s10\" bitsize=\"32\" type=\"float\" group=\"float\" />"
272 " <reg name=\"s11\" bitsize=\"32\" type=\"float\" group=\"float\" />"
273 " <reg name=\"s12\" bitsize=\"32\" type=\"float\" group=\"float\" />"
274 " <reg name=\"s13\" bitsize=\"32\" type=\"float\" group=\"float\" />"
275 " <reg name=\"s14\" bitsize=\"32\" type=\"float\" group=\"float\" />"
276 " <reg name=\"s15\" bitsize=\"32\" type=\"float\" group=\"float\" />"
277 " <reg name=\"s16\" bitsize=\"32\" type=\"float\" group=\"float\" />"
278 " <reg name=\"s17\" bitsize=\"32\" type=\"float\" group=\"float\" />"
279 " <reg name=\"s18\" bitsize=\"32\" type=\"float\" group=\"float\" />"
280 " <reg name=\"s19\" bitsize=\"32\" type=\"float\" group=\"float\" />"
281 " <reg name=\"s20\" bitsize=\"32\" type=\"float\" group=\"float\" />"
282 " <reg name=\"s21\" bitsize=\"32\" type=\"float\" group=\"float\" />"
283 " <reg name=\"s22\" bitsize=\"32\" type=\"float\" group=\"float\" />"
284 " <reg name=\"s23\" bitsize=\"32\" type=\"float\" group=\"float\" />"
285 " <reg name=\"s24\" bitsize=\"32\" type=\"float\" group=\"float\" />"
286 " <reg name=\"s25\" bitsize=\"32\" type=\"float\" group=\"float\" />"
287 " <reg name=\"s26\" bitsize=\"32\" type=\"float\" group=\"float\" />"
288 " <reg name=\"s27\" bitsize=\"32\" type=\"float\" group=\"float\" />"
289 " <reg name=\"s28\" bitsize=\"32\" type=\"float\" group=\"float\" />"
290 " <reg name=\"s29\" bitsize=\"32\" type=\"float\" group=\"float\" />"
291 " <reg name=\"s30\" bitsize=\"32\" type=\"float\" group=\"float\" />"
292 " <reg name=\"s31\" bitsize=\"32\" type=\"float\" group=\"float\" />"
293 " <reg name=\"fpscr\" bitsize=\"32\" type=\"int\" group=\"float\" />"
297 static const char* const memory_map_template_F4 =
298 "<?xml version=\"1.0\"?>"
299 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
300 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
302 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
303 " <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
304 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x20000\"/>" // sram
305 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
306 " <property name=\"blocksize\">0x4000</property>" //16kB
308 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
309 " <property name=\"blocksize\">0x10000</property>" //64kB
311 " <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
312 " <property name=\"blocksize\">0x20000</property>" //128kB
314 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
315 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
316 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
317 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
318 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
321 static const char* const memory_map_template_F4_HD =
322 "<?xml version=\"1.0\"?>"
323 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
324 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
326 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
327 " <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
328 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x40000\"/>" // sram
329 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x10000000\"/>" // fmc bank 1 (nor/psram/sram)
330 " <memory type=\"ram\" start=\"0x70000000\" length=\"0x20000000\"/>" // fmc bank 2 & 3 (nand flash)
331 " <memory type=\"ram\" start=\"0x90000000\" length=\"0x10000000\"/>" // fmc bank 4 (pc card)
332 " <memory type=\"ram\" start=\"0xC0000000\" length=\"0x20000000\"/>" // fmc sdram bank 1 & 2
333 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
334 " <property name=\"blocksize\">0x4000</property>" //16kB
336 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
337 " <property name=\"blocksize\">0x10000</property>" //64kB
339 " <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
340 " <property name=\"blocksize\">0x20000</property>" //128kB
342 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
343 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
344 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
345 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
348 static const char* const memory_map_template_F2 =
349 "<?xml version=\"1.0\"?>"
350 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
351 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
353 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>" // code = sram, bootrom or flash; flash is bigger
354 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x%zx\"/>" // sram
355 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
356 " <property name=\"blocksize\">0x4000</property>" //16kB
358 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
359 " <property name=\"blocksize\">0x10000</property>" //64kB
361 " <memory type=\"flash\" start=\"0x08020000\" length=\"0x%zx\">" //Sectors 5..
362 " <property name=\"blocksize\">0x20000</property>" //128kB
364 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
365 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
366 " <memory type=\"rom\" start=\"0x%08x\" length=\"0x%zx\"/>" // bootrom
367 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
370 static const char* const memory_map_template =
371 "<?xml version=\"1.0\"?>"
372 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
373 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
375 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>" // code = sram, bootrom or flash; flash is bigger
376 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x%zx\"/>" // sram 8k
377 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x%zx\">"
378 " <property name=\"blocksize\">0x%zx</property>"
380 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
381 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
382 " <memory type=\"rom\" start=\"0x%08x\" length=\"0x%zx\"/>" // bootrom
383 " <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
386 static const char* const memory_map_template_F7 =
387 "<?xml version=\"1.0\"?>"
388 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
389 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
391 " <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
392 " <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
393 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // sram
394 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
395 " <property name=\"blocksize\">0x8000</property>" // 32kB
397 " <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
398 " <property name=\"blocksize\">0x20000</property>" // 128kB
400 " <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
401 " <property name=\"blocksize\">0x40000</property>" // 128kB
403 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
404 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
405 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
406 " <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
407 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
410 char* make_memory_map(stlink_t *sl) {
411 /* This will be freed in serve() */
412 char* map = malloc(4096);
415 if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
416 strcpy(map, memory_map_template_F4);
417 } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
418 strcpy(map, memory_map_template_F7);
419 } else if(sl->chip_id==STM32_CHIPID_F4_HD) {
420 strcpy(map, memory_map_template_F4_HD);
421 } else if(sl->chip_id==STM32_CHIPID_F2) {
422 snprintf(map, 4096, memory_map_template_F2,
425 sl->flash_size - 0x20000,
426 sl->sys_base, sl->sys_size);
428 snprintf(map, 4096, memory_map_template,
431 sl->flash_size, sl->flash_pgsz,
432 sl->sys_base, sl->sys_size);
439 * DWT_COMP0 0xE0001020
440 * DWT_MASK0 0xE0001024
441 * DWT_FUNCTION0 0xE0001028
442 * DWT_COMP1 0xE0001030
443 * DWT_MASK1 0xE0001034
444 * DWT_FUNCTION1 0xE0001038
445 * DWT_COMP2 0xE0001040
446 * DWT_MASK2 0xE0001044
447 * DWT_FUNCTION2 0xE0001048
448 * DWT_COMP3 0xE0001050
449 * DWT_MASK3 0xE0001054
450 * DWT_FUNCTION3 0xE0001058
453 #define DATA_WATCH_NUM 4
455 enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 };
457 struct code_hw_watchpoint {
463 struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
465 static void init_data_watchpoints(stlink_t *sl) {
466 DLOG("init watchpoints\n");
468 // set trcena in debug command to turn on dwt unit
469 stlink_write_debug32(sl, 0xE000EDFC,
470 stlink_read_debug32(sl, 0xE000EDFC) | (1<<24));
472 // make sure all watchpoints are cleared
473 for(int i = 0; i < DATA_WATCH_NUM; i++) {
474 data_watches[i].fun = WATCHDISABLED;
475 stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
479 static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
480 stm32_addr_t addr, unsigned int len) {
485 // find a free watchpoint
495 if((mask != (uint32_t)-1) && (mask < 16)) {
496 for(i = 0; i < DATA_WATCH_NUM; i++) {
497 // is this an empty slot ?
498 if(data_watches[i].fun == WATCHDISABLED) {
499 DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
501 data_watches[i].fun = wf;
502 data_watches[i].addr = addr;
503 data_watches[i].mask = mask;
505 // insert comparator address
506 stlink_write_debug32(sl, 0xE0001020 + i * 16, addr);
509 stlink_write_debug32(sl, 0xE0001024 + i * 16, mask);
512 stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
514 // just to make sure the matched bit is clear !
515 stlink_read_debug32(sl, 0xE0001028 + i * 16);
521 DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len);
525 static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
529 for(i = 0 ; i < DATA_WATCH_NUM; i++) {
530 if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) {
531 DLOG("delete watchpoint %d addr %x\n", i, addr);
533 data_watches[i].fun = WATCHDISABLED;
534 stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
540 DLOG("failure: delete watchpoint addr %x\n", addr);
545 #define CODE_BREAK_NUM 6
546 #define CODE_LIT_NUM 2
547 #define CODE_BREAK_LOW 0x01
548 #define CODE_BREAK_HIGH 0x02
550 struct code_hw_breakpoint {
555 struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM];
557 static void init_code_breakpoints(stlink_t *sl) {
558 memset(sl->q_buf, 0, 4);
559 stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
560 unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
561 if (((val & 3) != 1) ||
562 ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) ||
563 (((val >> 8) & 0xf) != CODE_LIT_NUM)){
564 ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val,
565 ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1);
569 for(int i = 0; i < CODE_BREAK_NUM; i++) {
570 code_breaks[i].type = 0;
571 stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
575 static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
576 stm32_addr_t fpb_addr = addr & ~0x3;
577 int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
580 ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
585 for(int i = 0; i < CODE_BREAK_NUM; i++) {
586 if(fpb_addr == code_breaks[i].addr ||
587 (set && code_breaks[i].type == 0)) {
594 if(set) return -1; // Free slot not found
595 else return 0; // Breakpoint is already removed
598 struct code_hw_breakpoint* brk = &code_breaks[id];
600 brk->addr = fpb_addr;
602 if(set) brk->type |= type;
603 else brk->type &= ~type;
606 DLOG("clearing hw break %d\n", id);
608 stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
610 uint32_t mask = (brk->addr) | 1 | (brk->type << 30);
612 DLOG("setting hw break %d at %08x (%d)\n",
613 id, brk->addr, brk->type);
617 stlink_write_debug32(sl, 0xe0002008 + id * 4, mask);
629 struct flash_block* next;
632 static struct flash_block* flash_root;
634 static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) {
636 if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) {
637 ELOG("flash_add_block: incorrect bounds\n");
641 stlink_calculate_pagesize(sl, addr);
642 if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) {
643 ELOG("flash_add_block: unaligned block\n");
647 struct flash_block* new = malloc(sizeof(struct flash_block));
648 new->next = flash_root;
651 new->length = length;
652 new->data = calloc(length, 1);
659 static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) {
660 unsigned int fit_blocks = 0, fit_length = 0;
662 for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
663 /* Block: ------X------Y--------
667 * Block intersects with data, if:
671 unsigned X = fb->addr, Y = fb->addr + fb->length;
672 unsigned a = addr, b = addr + length;
674 // from start of the block
675 unsigned start = (a > X ? a : X) - X;
676 unsigned end = (b > Y ? Y : b) - X;
678 memcpy(fb->data + start, data, end - start);
681 fit_length += end - start;
685 if(fit_blocks == 0) {
686 ELOG("Unfit data block %08x -> %04x\n", addr, length);
690 if(fit_length != length) {
691 WLOG("data block %08x -> %04x truncated to %04x\n",
692 addr, length, fit_length);
693 WLOG("(this is not an error, just a GDB glitch)\n");
699 static int flash_go(stlink_t *sl) {
702 // Some kinds of clock settings do not allow writing to flash.
705 for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
706 DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
708 unsigned length = fb->length;
709 for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) {
712 stlink_calculate_pagesize(sl, page);
714 DLOG("flash_do: page %08x\n", page);
716 if(stlink_write_flash(sl, page, fb->data + (page - fb->addr),
717 length > FLASH_PAGE ? FLASH_PAGE : length) < 0)
727 for(struct flash_block* fb = flash_root, *next; fb; fb = next) {
738 int serve(stlink_t *sl, st_state_t *st) {
739 int sock = socket(AF_INET, SOCK_STREAM, 0);
745 unsigned int val = 1;
746 setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
748 struct sockaddr_in serv_addr;
749 memset(&serv_addr,0,sizeof(struct sockaddr_in));
750 serv_addr.sin_family = AF_INET;
751 serv_addr.sin_addr.s_addr = INADDR_ANY;
752 serv_addr.sin_port = htons(st->listen_port);
754 if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) {
759 if(listen(sock, 5) < 0) {
764 ILOG("Listening at *:%d...\n", st->listen_port);
766 int client = accept(sock, NULL, NULL);
767 //signal (SIGINT, SIG_DFL);
775 stlink_force_debug(sl);
779 init_code_breakpoints(sl);
780 init_data_watchpoints(sl);
782 ILOG("GDB connected.\n");
785 * To allow resetting the chip from GDB it is required to
786 * emulate attaching and detaching to target.
788 unsigned int attached = 1;
793 int status = gdb_recv_packet(client, &packet);
795 ELOG("cannot recv: %d\n", status);
797 win32_close_socket(sock);
802 DLOG("recv: %s\n", packet);
809 if(packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') {
814 char *separator = strstr(packet, ":"), *params = "";
815 if(separator == NULL) {
816 separator = packet + strlen(packet);
818 params = separator + 1;
821 unsigned queryNameLength = (separator - &packet[1]);
822 char* queryName = calloc(queryNameLength + 1, 1);
823 strncpy(queryName, &packet[1], queryNameLength);
825 DLOG("query: %s;%s\n", queryName, params);
827 if(!strcmp(queryName, "Supported")) {
828 if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) {
829 reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
832 reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
834 } else if(!strcmp(queryName, "Xfer")) {
835 char *type, *op, *__s_addr, *s_length;
837 char *annex __attribute__((unused));
839 type = strsep(&tok, ":");
840 op = strsep(&tok, ":");
841 annex = strsep(&tok, ":");
842 __s_addr = strsep(&tok, ",");
845 unsigned addr = strtoul(__s_addr, NULL, 16),
846 length = strtoul(s_length, NULL, 16);
848 DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n",
849 type, op, annex, addr, length);
851 const char* data = NULL;
853 if(!strcmp(type, "memory-map") && !strcmp(op, "read"))
854 data = current_memory_map;
856 if(!strcmp(type, "features") && !strcmp(op, "read"))
857 data = target_description_F4;
860 unsigned data_length = strlen(data);
861 if(addr + length > data_length)
862 length = data_length - addr;
867 reply = calloc(length + 2, 1);
869 strncpy(&reply[1], data, length);
872 } else if(!strncmp(queryName, "Rcmd,",4)) {
873 // Rcmd uses the wrong separator
874 char *separator = strstr(packet, ","), *params = "";
875 if(separator == NULL) {
876 separator = packet + strlen(packet);
878 params = separator + 1;
882 if (!strncmp(params,"726573756d65",12)) {// resume
883 DLOG("Rcmd: resume\n");
886 reply = strdup("OK");
887 } else if (!strncmp(params,"68616c74",8)) { //halt
888 reply = strdup("OK");
890 stlink_force_debug(sl);
892 DLOG("Rcmd: halt\n");
893 } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset
894 reply = strdup("OK");
896 stlink_jtag_reset(sl, 0);
897 stlink_jtag_reset(sl, 1);
898 stlink_force_debug(sl);
900 DLOG("Rcmd: jtag_reset\n");
901 } else if (!strncmp(params,"7265736574",10)) { //reset
902 reply = strdup("OK");
904 stlink_force_debug(sl);
906 init_code_breakpoints(sl);
907 init_data_watchpoints(sl);
909 DLOG("Rcmd: reset\n");
911 DLOG("Rcmd: %s\n", params);
926 char *cmdName = strtok_r(packet, ":;", ¶ms);
928 cmdName++; // vCommand -> Command
930 if(!strcmp(cmdName, "FlashErase")) {
931 char *__s_addr, *s_length;
934 __s_addr = strsep(&tok, ",");
937 unsigned addr = strtoul(__s_addr, NULL, 16),
938 length = strtoul(s_length, NULL, 16);
940 DLOG("FlashErase: addr:%08x,len:%04x\n",
943 if(flash_add_block(addr, length, sl) < 0) {
944 reply = strdup("E00");
946 reply = strdup("OK");
948 } else if(!strcmp(cmdName, "FlashWrite")) {
949 char *__s_addr, *data;
952 __s_addr = strsep(&tok, ":");
955 unsigned addr = strtoul(__s_addr, NULL, 16);
956 unsigned data_length = status - (data - packet);
958 // Length of decoded data cannot be more than
959 // encoded, as escapes are removed.
960 // Additional byte is reserved for alignment fix.
961 uint8_t *decoded = calloc(data_length + 1, 1);
962 unsigned dec_index = 0;
963 for(unsigned int i = 0; i < data_length; i++) {
964 if(data[i] == 0x7d) {
966 decoded[dec_index++] = data[i] ^ 0x20;
968 decoded[dec_index++] = data[i];
973 if(dec_index % 2 != 0)
976 DLOG("binary packet %d -> %d\n", data_length, dec_index);
978 if(flash_populate(addr, decoded, dec_index) < 0) {
979 reply = strdup("E00");
981 reply = strdup("OK");
983 } else if(!strcmp(cmdName, "FlashDone")) {
984 if(flash_go(sl) < 0) {
985 reply = strdup("E00");
987 reply = strdup("OK");
989 } else if(!strcmp(cmdName, "Kill")) {
992 reply = strdup("OK");
1005 int status = gdb_check_for_interrupt(client);
1007 ELOG("cannot check for int: %d\n", status);
1009 win32_close_socket(sock);
1015 stlink_force_debug(sl);
1020 if(sl->core_stat == STLINK_CORE_HALTED) {
1027 reply = strdup("S05"); // TRAP
1033 reply = strdup("S05"); // TRAP
1038 reply = strdup("S05"); // TRAP
1040 /* Stub shall reply OK if not attached. */
1041 reply = strdup("OK");
1046 stlink_read_all_regs(sl, ®p);
1048 reply = calloc(8 * 16 + 1, 1);
1049 for(int i = 0; i < 16; i++)
1050 sprintf(&reply[i * 8], "%08x", htonl(regp.r[i]));
1055 unsigned id = strtoul(&packet[1], NULL, 16);
1056 unsigned myreg = 0xDEADDEAD;
1059 stlink_read_reg(sl, id, ®p);
1060 myreg = htonl(regp.r[id]);
1061 } else if(id == 0x19) {
1062 stlink_read_reg(sl, 16, ®p);
1063 myreg = htonl(regp.xpsr);
1064 } else if(id == 0x1A) {
1065 stlink_read_reg(sl, 17, ®p);
1066 myreg = htonl(regp.main_sp);
1067 } else if(id == 0x1B) {
1068 stlink_read_reg(sl, 18, ®p);
1069 myreg = htonl(regp.process_sp);
1070 } else if(id == 0x1C) {
1071 stlink_read_unsupported_reg(sl, id, ®p);
1072 myreg = htonl(regp.control);
1073 } else if(id == 0x1D) {
1074 stlink_read_unsupported_reg(sl, id, ®p);
1075 myreg = htonl(regp.faultmask);
1076 } else if(id == 0x1E) {
1077 stlink_read_unsupported_reg(sl, id, ®p);
1078 myreg = htonl(regp.basepri);
1079 } else if(id == 0x1F) {
1080 stlink_read_unsupported_reg(sl, id, ®p);
1081 myreg = htonl(regp.primask);
1082 } else if(id >= 0x20 && id < 0x40) {
1083 stlink_read_unsupported_reg(sl, id, ®p);
1084 myreg = htonl(regp.s[id-0x20]);
1085 } else if(id == 0x40) {
1086 stlink_read_unsupported_reg(sl, id, ®p);
1087 myreg = htonl(regp.fpscr);
1089 reply = strdup("E00");
1092 reply = calloc(8 + 1, 1);
1093 sprintf(reply, "%08x", myreg);
1099 char* s_reg = &packet[1];
1100 char* s_value = strstr(&packet[1], "=") + 1;
1102 unsigned reg = strtoul(s_reg, NULL, 16);
1103 unsigned value = strtoul(s_value, NULL, 16);
1106 stlink_write_reg(sl, ntohl(value), reg);
1107 } else if(reg == 0x19) {
1108 stlink_write_reg(sl, ntohl(value), 16);
1109 } else if(reg == 0x1A) {
1110 stlink_write_reg(sl, ntohl(value), 17);
1111 } else if(reg == 0x1B) {
1112 stlink_write_reg(sl, ntohl(value), 18);
1113 } else if(reg == 0x1C) {
1114 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1115 } else if(reg == 0x1D) {
1116 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1117 } else if(reg == 0x1E) {
1118 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1119 } else if(reg == 0x1F) {
1120 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1121 } else if(reg >= 0x20 && reg < 0x40) {
1122 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1123 } else if(reg == 0x40) {
1124 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1126 reply = strdup("E00");
1130 reply = strdup("OK");
1137 for(int i = 0; i < 16; i++) {
1139 strncpy(str, &packet[1 + i * 8], 8);
1140 uint32_t reg = strtoul(str, NULL, 16);
1141 stlink_write_reg(sl, ntohl(reg), i);
1144 reply = strdup("OK");
1148 char* s_start = &packet[1];
1149 char* s_count = strstr(&packet[1], ",") + 1;
1151 stm32_addr_t start = strtoul(s_start, NULL, 16);
1152 unsigned count = strtoul(s_count, NULL, 16);
1154 unsigned adj_start = start % 4;
1155 unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4;
1157 stlink_read_mem32(sl, start - adj_start, count_rnd);
1159 reply = calloc(count * 2 + 1, 1);
1160 for(unsigned int i = 0; i < count; i++) {
1161 reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4];
1162 reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf];
1169 char* s_start = &packet[1];
1170 char* s_count = strstr(&packet[1], ",") + 1;
1171 char* hexdata = strstr(packet, ":") + 1;
1173 stm32_addr_t start = strtoul(s_start, NULL, 16);
1174 unsigned count = strtoul(s_count, NULL, 16);
1177 unsigned align_count = 4 - start % 4;
1178 if (align_count > count) align_count = count;
1179 for(unsigned int i = 0; i < align_count; i ++) {
1180 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1181 uint8_t byte = strtoul(hex, NULL, 16);
1182 sl->q_buf[i] = byte;
1184 stlink_write_mem8(sl, start, align_count);
1185 start += align_count;
1186 count -= align_count;
1187 hexdata += 2*align_count;
1190 if(count - count % 4) {
1191 unsigned aligned_count = count - count % 4;
1193 for(unsigned int i = 0; i < aligned_count; i ++) {
1194 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1195 uint8_t byte = strtoul(hex, NULL, 16);
1196 sl->q_buf[i] = byte;
1198 stlink_write_mem32(sl, start, aligned_count);
1199 count -= aligned_count;
1200 start += aligned_count;
1201 hexdata += 2*aligned_count;
1205 for(unsigned int i = 0; i < count; i ++) {
1206 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1207 uint8_t byte = strtoul(hex, NULL, 16);
1208 sl->q_buf[i] = byte;
1210 stlink_write_mem8(sl, start, count);
1212 reply = strdup("OK");
1218 stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
1219 stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
1221 switch (packet[1]) {
1223 if(update_code_breakpoint(sl, addr, 1) < 0) {
1224 reply = strdup("E00");
1226 reply = strdup("OK");
1230 case '2': // insert write watchpoint
1231 case '3': // insert read watchpoint
1232 case '4': { // insert access watchpoint
1234 if(packet[1] == '2') {
1236 } else if(packet[1] == '3') {
1242 if(add_data_watchpoint(sl, wf, addr, len) < 0) {
1243 reply = strdup("E00");
1245 reply = strdup("OK");
1257 stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
1258 //stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
1260 switch (packet[1]) {
1261 case '1': // remove breakpoint
1262 update_code_breakpoint(sl, addr, 0);
1263 reply = strdup("OK");
1266 case '2' : // remove write watchpoint
1267 case '3' : // remove read watchpoint
1268 case '4' : // remove access watchpoint
1269 if(delete_data_watchpoint(sl, addr) < 0) {
1270 reply = strdup("E00");
1272 reply = strdup("OK");
1284 * Enter extended mode which allows restarting.
1285 * We do support that always.
1289 * Also, set to persistent mode
1290 * to allow GDB disconnect.
1294 reply = strdup("OK");
1300 /* Reset the core. */
1303 init_code_breakpoints(sl);
1304 init_data_watchpoints(sl);
1308 reply = strdup("OK");
1318 DLOG("send: %s\n", reply);
1320 int result = gdb_send_packet(client, reply);
1322 ELOG("cannot send: %d\n", result);
1326 win32_close_socket(sock);
1338 win32_close_socket(sock);