2 * Copyright (C) 2011 Peter Zotov <whitequark@whitequark.org>
3 * Use of this source code is governed by a BSD-style
4 * license that can be found in the LICENSE file.
14 #include <sys/types.h>
18 #include <sys/socket.h>
19 #include <netinet/in.h>
20 #include <arpa/inet.h>
23 #include <stlink-common.h>
24 #include <uglylogging.h>
26 #include "gdb-remote.h"
27 #include "gdb-server.h"
29 #define FLASH_BASE 0x08000000
31 //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize
32 #define FLASH_PAGE (sl->flash_pgsz)
34 stlink_t *connected_stlink = NULL;
36 static const char hex[] = "0123456789abcdef";
38 static const char* current_memory_map = NULL;
40 typedef struct _st_state_t {
41 // things from command line, bleh
50 int serve(stlink_t *sl, st_state_t *st);
51 char* make_memory_map(stlink_t *sl);
52 static void init_cache (stlink_t *sl);
54 static void cleanup(int signal __attribute__((unused))) {
55 if (connected_stlink) {
56 /* Switch back to mass storage mode before closing. */
57 stlink_run(connected_stlink);
58 stlink_exit_debug_mode(connected_stlink);
59 stlink_close(connected_stlink);
67 int parse_options(int argc, char** argv, st_state_t *st) {
68 static struct option long_options[] = {
69 {"help", no_argument, NULL, 'h'},
70 {"verbose", optional_argument, NULL, 'v'},
71 {"stlink_version", required_argument, NULL, 's'},
72 {"stlinkv1", no_argument, NULL, '1'},
73 {"listen_port", required_argument, NULL, 'p'},
74 {"multi", optional_argument, NULL, 'm'},
75 {"no-reset", optional_argument, NULL, 'n'},
78 const char * help_str = "%s - usage:\n\n"
79 " -h, --help\t\tPrint this help\n"
80 " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n"
81 " -v, --verbose\t\tSpecify generally verbose logging\n"
82 " -s X, --stlink_version=X\n"
83 "\t\t\tChoose what version of stlink to use, (defaults to 2)\n"
84 " -1, --stlinkv1\tForce stlink version 1\n"
85 " -p 4242, --listen_port=1234\n"
86 "\t\t\tSet the gdb server listen port. "
87 "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n"
89 "\t\t\tSet gdb server to extended mode.\n"
90 "\t\t\tst-util will continue listening for connections after disconnect.\n"
92 "\t\t\tDo not reset board on connection.\n"
94 "The STLINKv2 device to use can be specified in the environment\n"
95 "variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.\n"
100 int option_index = 0;
103 while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) {
106 printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n");
107 printf("option %s", long_options[option_index].name);
109 printf(" with arg %s", optarg);
114 printf(help_str, argv[0]);
119 st->logging_level = atoi(optarg);
121 st->logging_level = DEFAULT_LOGGING_LEVEL;
125 st->stlink_version = 1;
128 sscanf(optarg, "%i", &q);
129 if (q < 0 || q > 2) {
130 fprintf(stderr, "stlink version %d unknown!\n", q);
133 st->stlink_version = q;
136 sscanf(optarg, "%i", &q);
138 fprintf(stderr, "Can't use a negative port to listen on: %d\n", q);
153 printf("non-option ARGV-elements: ");
154 while (optind < argc)
155 printf("%s ", argv[optind++]);
162 int main(int argc, char** argv) {
168 memset(&state, 0, sizeof(state));
170 state.stlink_version = 2;
171 state.logging_level = DEFAULT_LOGGING_LEVEL;
172 state.listen_port = DEFAULT_GDB_LISTEN_PORT;
173 state.reset = 1; /* By default, reset board */
174 parse_options(argc, argv, &state);
175 switch (state.stlink_version) {
177 sl = stlink_open_usb(state.logging_level, 0, NULL);
178 if(sl == NULL) return 1;
181 sl = stlink_v1_open(state.logging_level, 0);
182 if(sl == NULL) return 1;
186 connected_stlink = sl;
187 signal(SIGINT, &cleanup);
188 signal(SIGTERM, &cleanup);
194 ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id);
196 voltage = stlink_target_voltage(sl);
198 ILOG("Target voltage is %d mV.\n", voltage);
203 current_memory_map = make_memory_map(sl);
207 if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) {
215 if (serve(sl, &state)) {
216 sleep (1); // don't go bezurk if serve returns with error
221 } while (state.persistent);
228 /* Switch back to mass storage mode before closing. */
229 stlink_exit_debug_mode(sl);
235 static const char* const target_description_F4 =
236 "<?xml version=\"1.0\"?>"
237 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
238 "<target version=\"1.0\">"
239 " <architecture>arm</architecture>"
240 " <feature name=\"org.gnu.gdb.arm.m-profile\">"
241 " <reg name=\"r0\" bitsize=\"32\"/>"
242 " <reg name=\"r1\" bitsize=\"32\"/>"
243 " <reg name=\"r2\" bitsize=\"32\"/>"
244 " <reg name=\"r3\" bitsize=\"32\"/>"
245 " <reg name=\"r4\" bitsize=\"32\"/>"
246 " <reg name=\"r5\" bitsize=\"32\"/>"
247 " <reg name=\"r6\" bitsize=\"32\"/>"
248 " <reg name=\"r7\" bitsize=\"32\"/>"
249 " <reg name=\"r8\" bitsize=\"32\"/>"
250 " <reg name=\"r9\" bitsize=\"32\"/>"
251 " <reg name=\"r10\" bitsize=\"32\"/>"
252 " <reg name=\"r11\" bitsize=\"32\"/>"
253 " <reg name=\"r12\" bitsize=\"32\"/>"
254 " <reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
255 " <reg name=\"lr\" bitsize=\"32\"/>"
256 " <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
257 " <reg name=\"xpsr\" bitsize=\"32\" regnum=\"25\"/>"
258 " <reg name=\"msp\" bitsize=\"32\" regnum=\"26\" type=\"data_ptr\" group=\"general\" />"
259 " <reg name=\"psp\" bitsize=\"32\" regnum=\"27\" type=\"data_ptr\" group=\"general\" />"
260 " <reg name=\"control\" bitsize=\"8\" regnum=\"28\" type=\"int\" group=\"general\" />"
261 " <reg name=\"faultmask\" bitsize=\"8\" regnum=\"29\" type=\"int\" group=\"general\" />"
262 " <reg name=\"basepri\" bitsize=\"8\" regnum=\"30\" type=\"int\" group=\"general\" />"
263 " <reg name=\"primask\" bitsize=\"8\" regnum=\"31\" type=\"int\" group=\"general\" />"
264 " <reg name=\"s0\" bitsize=\"32\" regnum=\"32\" type=\"float\" group=\"float\" />"
265 " <reg name=\"s1\" bitsize=\"32\" type=\"float\" group=\"float\" />"
266 " <reg name=\"s2\" bitsize=\"32\" type=\"float\" group=\"float\" />"
267 " <reg name=\"s3\" bitsize=\"32\" type=\"float\" group=\"float\" />"
268 " <reg name=\"s4\" bitsize=\"32\" type=\"float\" group=\"float\" />"
269 " <reg name=\"s5\" bitsize=\"32\" type=\"float\" group=\"float\" />"
270 " <reg name=\"s6\" bitsize=\"32\" type=\"float\" group=\"float\" />"
271 " <reg name=\"s7\" bitsize=\"32\" type=\"float\" group=\"float\" />"
272 " <reg name=\"s8\" bitsize=\"32\" type=\"float\" group=\"float\" />"
273 " <reg name=\"s9\" bitsize=\"32\" type=\"float\" group=\"float\" />"
274 " <reg name=\"s10\" bitsize=\"32\" type=\"float\" group=\"float\" />"
275 " <reg name=\"s11\" bitsize=\"32\" type=\"float\" group=\"float\" />"
276 " <reg name=\"s12\" bitsize=\"32\" type=\"float\" group=\"float\" />"
277 " <reg name=\"s13\" bitsize=\"32\" type=\"float\" group=\"float\" />"
278 " <reg name=\"s14\" bitsize=\"32\" type=\"float\" group=\"float\" />"
279 " <reg name=\"s15\" bitsize=\"32\" type=\"float\" group=\"float\" />"
280 " <reg name=\"s16\" bitsize=\"32\" type=\"float\" group=\"float\" />"
281 " <reg name=\"s17\" bitsize=\"32\" type=\"float\" group=\"float\" />"
282 " <reg name=\"s18\" bitsize=\"32\" type=\"float\" group=\"float\" />"
283 " <reg name=\"s19\" bitsize=\"32\" type=\"float\" group=\"float\" />"
284 " <reg name=\"s20\" bitsize=\"32\" type=\"float\" group=\"float\" />"
285 " <reg name=\"s21\" bitsize=\"32\" type=\"float\" group=\"float\" />"
286 " <reg name=\"s22\" bitsize=\"32\" type=\"float\" group=\"float\" />"
287 " <reg name=\"s23\" bitsize=\"32\" type=\"float\" group=\"float\" />"
288 " <reg name=\"s24\" bitsize=\"32\" type=\"float\" group=\"float\" />"
289 " <reg name=\"s25\" bitsize=\"32\" type=\"float\" group=\"float\" />"
290 " <reg name=\"s26\" bitsize=\"32\" type=\"float\" group=\"float\" />"
291 " <reg name=\"s27\" bitsize=\"32\" type=\"float\" group=\"float\" />"
292 " <reg name=\"s28\" bitsize=\"32\" type=\"float\" group=\"float\" />"
293 " <reg name=\"s29\" bitsize=\"32\" type=\"float\" group=\"float\" />"
294 " <reg name=\"s30\" bitsize=\"32\" type=\"float\" group=\"float\" />"
295 " <reg name=\"s31\" bitsize=\"32\" type=\"float\" group=\"float\" />"
296 " <reg name=\"fpscr\" bitsize=\"32\" type=\"int\" group=\"float\" />"
300 static const char* const memory_map_template_F4 =
301 "<?xml version=\"1.0\"?>"
302 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
303 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
305 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
306 " <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
307 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x20000\"/>" // sram
308 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
309 " <property name=\"blocksize\">0x4000</property>" //16kB
311 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
312 " <property name=\"blocksize\">0x10000</property>" //64kB
314 " <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
315 " <property name=\"blocksize\">0x20000</property>" //128kB
317 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
318 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
319 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
320 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
321 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
324 static const char* const memory_map_template_F4_HD =
325 "<?xml version=\"1.0\"?>"
326 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
327 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
329 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
330 " <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
331 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x40000\"/>" // sram
332 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x10000000\"/>" // fmc bank 1 (nor/psram/sram)
333 " <memory type=\"ram\" start=\"0x70000000\" length=\"0x20000000\"/>" // fmc bank 2 & 3 (nand flash)
334 " <memory type=\"ram\" start=\"0x90000000\" length=\"0x10000000\"/>" // fmc bank 4 (pc card)
335 " <memory type=\"ram\" start=\"0xC0000000\" length=\"0x20000000\"/>" // fmc sdram bank 1 & 2
336 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
337 " <property name=\"blocksize\">0x4000</property>" //16kB
339 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
340 " <property name=\"blocksize\">0x10000</property>" //64kB
342 " <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
343 " <property name=\"blocksize\">0x20000</property>" //128kB
345 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
346 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
347 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
348 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
351 static const char* const memory_map_template_F2 =
352 "<?xml version=\"1.0\"?>"
353 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
354 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
356 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>" // code = sram, bootrom or flash; flash is bigger
357 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x%zx\"/>" // sram
358 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
359 " <property name=\"blocksize\">0x4000</property>" //16kB
361 " <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
362 " <property name=\"blocksize\">0x10000</property>" //64kB
364 " <memory type=\"flash\" start=\"0x08020000\" length=\"0x%zx\">" //Sectors 5..
365 " <property name=\"blocksize\">0x20000</property>" //128kB
367 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
368 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
369 " <memory type=\"rom\" start=\"0x%08x\" length=\"0x%zx\"/>" // bootrom
370 " <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
373 static const char* const memory_map_template =
374 "<?xml version=\"1.0\"?>"
375 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
376 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
378 " <memory type=\"rom\" start=\"0x00000000\" length=\"0x%zx\"/>" // code = sram, bootrom or flash; flash is bigger
379 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x%zx\"/>" // sram 8k
380 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x%zx\">"
381 " <property name=\"blocksize\">0x%zx</property>"
383 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
384 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
385 " <memory type=\"rom\" start=\"0x%08x\" length=\"0x%zx\"/>" // bootrom
386 " <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
389 static const char* const memory_map_template_F7 =
390 "<?xml version=\"1.0\"?>"
391 "<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
392 " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
394 " <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
395 " <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
396 " <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // sram
397 " <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
398 " <property name=\"blocksize\">0x8000</property>" // 32kB
400 " <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
401 " <property name=\"blocksize\">0x20000</property>" // 128kB
403 " <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
404 " <property name=\"blocksize\">0x40000</property>" // 128kB
406 " <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
407 " <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
408 " <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
409 " <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
410 " <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
413 char* make_memory_map(stlink_t *sl) {
414 /* This will be freed in serve() */
415 char* map = malloc(4096);
418 if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
419 strcpy(map, memory_map_template_F4);
420 } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
421 strcpy(map, memory_map_template_F7);
422 } else if(sl->chip_id==STM32_CHIPID_F4_HD) {
423 strcpy(map, memory_map_template_F4_HD);
424 } else if(sl->chip_id==STM32_CHIPID_F2) {
425 snprintf(map, 4096, memory_map_template_F2,
428 sl->flash_size - 0x20000,
429 sl->sys_base, sl->sys_size);
431 snprintf(map, 4096, memory_map_template,
434 sl->flash_size, sl->flash_pgsz,
435 sl->sys_base, sl->sys_size);
442 * DWT_COMP0 0xE0001020
443 * DWT_MASK0 0xE0001024
444 * DWT_FUNCTION0 0xE0001028
445 * DWT_COMP1 0xE0001030
446 * DWT_MASK1 0xE0001034
447 * DWT_FUNCTION1 0xE0001038
448 * DWT_COMP2 0xE0001040
449 * DWT_MASK2 0xE0001044
450 * DWT_FUNCTION2 0xE0001048
451 * DWT_COMP3 0xE0001050
452 * DWT_MASK3 0xE0001054
453 * DWT_FUNCTION3 0xE0001058
456 #define DATA_WATCH_NUM 4
458 enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 };
460 struct code_hw_watchpoint {
466 struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
468 static void init_data_watchpoints(stlink_t *sl) {
469 DLOG("init watchpoints\n");
471 // set trcena in debug command to turn on dwt unit
472 stlink_write_debug32(sl, 0xE000EDFC,
473 stlink_read_debug32(sl, 0xE000EDFC) | (1<<24));
475 // make sure all watchpoints are cleared
476 for(int i = 0; i < DATA_WATCH_NUM; i++) {
477 data_watches[i].fun = WATCHDISABLED;
478 stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
482 static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
483 stm32_addr_t addr, unsigned int len) {
488 // find a free watchpoint
498 if((mask != (uint32_t)-1) && (mask < 16)) {
499 for(i = 0; i < DATA_WATCH_NUM; i++) {
500 // is this an empty slot ?
501 if(data_watches[i].fun == WATCHDISABLED) {
502 DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
504 data_watches[i].fun = wf;
505 data_watches[i].addr = addr;
506 data_watches[i].mask = mask;
508 // insert comparator address
509 stlink_write_debug32(sl, 0xE0001020 + i * 16, addr);
512 stlink_write_debug32(sl, 0xE0001024 + i * 16, mask);
515 stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
517 // just to make sure the matched bit is clear !
518 stlink_read_debug32(sl, 0xE0001028 + i * 16);
524 DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len);
528 static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
532 for(i = 0 ; i < DATA_WATCH_NUM; i++) {
533 if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) {
534 DLOG("delete watchpoint %d addr %x\n", i, addr);
536 data_watches[i].fun = WATCHDISABLED;
537 stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
543 DLOG("failure: delete watchpoint addr %x\n", addr);
550 #define CODE_BREAK_NUM_MAX 15
551 #define CODE_BREAK_LOW 0x01
552 #define CODE_BREAK_HIGH 0x02
554 struct code_hw_breakpoint {
559 struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
561 static void init_code_breakpoints(stlink_t *sl) {
562 memset(sl->q_buf, 0, 4);
563 stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
564 unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
565 code_break_num = ((val >> 4) & 0xf);
566 code_lit_num = ((val >> 8) & 0xf);
568 ILOG("Found %i hw breakpoint registers\n", code_break_num);
570 for(int i = 0; i < code_break_num; i++) {
571 code_breaks[i].type = 0;
572 stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0);
576 static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
577 stm32_addr_t fpb_addr;
579 int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
582 ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
586 if (sl->chip_id==STM32_CHIPID_F7) {
589 fpb_addr = addr & ~0x3;
593 for(int i = 0; i < code_break_num; i++) {
594 if(fpb_addr == code_breaks[i].addr ||
595 (set && code_breaks[i].type == 0)) {
602 if(set) return -1; // Free slot not found
603 else return 0; // Breakpoint is already removed
606 struct code_hw_breakpoint* brk = &code_breaks[id];
608 brk->addr = fpb_addr;
610 if (sl->chip_id==STM32_CHIPID_F7) {
611 if(set) brk->type = type;
614 mask = (brk->addr) | 1;
616 if(set) brk->type |= type;
617 else brk->type &= ~type;
619 mask = (brk->addr) | 1 | (brk->type << 30);
623 DLOG("clearing hw break %d\n", id);
625 stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
627 DLOG("setting hw break %d at %08x (%d)\n",
628 id, brk->addr, brk->type);
632 stlink_write_debug32(sl, 0xe0002008 + id * 4, mask);
644 struct flash_block* next;
647 static struct flash_block* flash_root;
649 static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) {
651 if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) {
652 ELOG("flash_add_block: incorrect bounds\n");
656 stlink_calculate_pagesize(sl, addr);
657 if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) {
658 ELOG("flash_add_block: unaligned block\n");
662 struct flash_block* new = malloc(sizeof(struct flash_block));
663 new->next = flash_root;
666 new->length = length;
667 new->data = calloc(length, 1);
674 static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) {
675 unsigned int fit_blocks = 0, fit_length = 0;
677 for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
678 /* Block: ------X------Y--------
682 * Block intersects with data, if:
686 unsigned X = fb->addr, Y = fb->addr + fb->length;
687 unsigned a = addr, b = addr + length;
689 // from start of the block
690 unsigned start = (a > X ? a : X) - X;
691 unsigned end = (b > Y ? Y : b) - X;
693 memcpy(fb->data + start, data, end - start);
696 fit_length += end - start;
700 if(fit_blocks == 0) {
701 ELOG("Unfit data block %08x -> %04x\n", addr, length);
705 if(fit_length != length) {
706 WLOG("data block %08x -> %04x truncated to %04x\n",
707 addr, length, fit_length);
708 WLOG("(this is not an error, just a GDB glitch)\n");
714 static int flash_go(stlink_t *sl) {
717 // Some kinds of clock settings do not allow writing to flash.
719 stlink_force_debug(sl);
721 for(struct flash_block* fb = flash_root; fb; fb = fb->next) {
722 DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
724 for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) {
725 unsigned length = fb->length - (page - fb->addr);
728 stlink_calculate_pagesize(sl, page);
730 DLOG("flash_do: page %08x\n", page);
731 unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length;
732 if(stlink_write_flash(sl, page, fb->data + (page - fb->addr),
745 for(struct flash_block* fb = flash_root, *next; fb; fb = next) {
756 #define CLIDR 0xE000ED78
757 #define CTR 0xE000ED7C
758 #define CCSIDR 0xE000ED80
759 #define CSSELR 0xE000ED84
760 #define CCR 0xE000ED14
761 #define CCR_DC (1 << 16)
762 #define CCR_IC (1 << 17)
763 #define DCCSW 0xE000EF6C
764 #define ICIALLU 0xE000EF50
766 struct cache_level_desc
770 unsigned int log2_nways;
776 /* Minimal line size in bytes. */
777 unsigned int dminline;
778 unsigned int iminline;
780 /* Last level of unification (uniprocessor). */
783 struct cache_level_desc icache[7];
784 struct cache_level_desc dcache[7];
787 static struct cache_desc_t cache_desc;
789 /* Return the smallest R so that V <= (1 << R). Not performance critical. */
790 static unsigned ceil_log2(unsigned v)
793 for (res = 0; (1 << res) < v; res++)
798 static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc)
801 unsigned int log2_nsets;
802 ccsidr = stlink_read_debug32(sl, CCSIDR);
803 desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
804 desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
805 desc->log2_nways = ceil_log2 (desc->nways);
806 log2_nsets = ceil_log2 (desc->nsets);
807 desc->width = 4 + (ccsidr & 7) + log2_nsets;
808 ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n",
809 ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width);
812 static void init_cache (stlink_t *sl) {
818 /* Assume only F7 has a cache. */
819 if(sl->chip_id!=STM32_CHIPID_F7)
822 clidr = stlink_read_debug32(sl, CLIDR);
823 ccr = stlink_read_debug32(sl, CCR);
824 ctr = stlink_read_debug32(sl, CTR);
825 cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
826 cache_desc.iminline = 4 << (ctr & 0x0f);
827 cache_desc.louu = (clidr >> 27) & 7;
829 ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n",
830 clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off");
831 ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n",
832 (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7);
833 ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr,
834 cache_desc.dminline, cache_desc.iminline);
835 for(i = 0; i < 7; i++)
837 unsigned int ct = (clidr >> (3 * i)) & 0x07;
839 cache_desc.dcache[i].width = 0;
840 cache_desc.icache[i].width = 0;
842 if(ct == 2 || ct == 3 || ct == 4)
845 stlink_write_debug32(sl, CSSELR, i << 1);
846 ILOG("D-Cache L%d: ", i);
847 read_cache_level_desc(sl, &cache_desc.dcache[i]);
850 if(ct == 1 || ct == 3)
853 stlink_write_debug32(sl, CSSELR, (i << 1) | 1);
854 ILOG("I-Cache L%d: ", i);
855 read_cache_level_desc(sl, &cache_desc.icache[i]);
860 static void cache_flush(stlink_t *sl, unsigned ccr) {
864 for (level = cache_desc.louu - 1; level >= 0; level--)
866 struct cache_level_desc *desc = &cache_desc.dcache[level];
868 unsigned max_addr = 1 << desc->width;
869 unsigned way_sh = 32 - desc->log2_nways;
871 /* D-cache clean by set-ways. */
872 for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline)
876 for (way = 0; way < desc->nways; way++)
877 stlink_write_debug32(sl, DCCSW, addr | (way << way_sh));
881 /* Invalidate all I-cache to oPU. */
883 stlink_write_debug32(sl, ICIALLU, 0);
886 static int cache_modified;
888 static void cache_change(stm32_addr_t start, unsigned count)
896 static void cache_sync(stlink_t *sl)
900 if(sl->chip_id!=STM32_CHIPID_F7)
906 ccr = stlink_read_debug32(sl, CCR);
907 if (ccr & (CCR_IC | CCR_DC))
908 cache_flush(sl, ccr);
911 int serve(stlink_t *sl, st_state_t *st) {
912 int sock = socket(AF_INET, SOCK_STREAM, 0);
918 unsigned int val = 1;
919 setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
921 struct sockaddr_in serv_addr;
922 memset(&serv_addr,0,sizeof(struct sockaddr_in));
923 serv_addr.sin_family = AF_INET;
924 serv_addr.sin_addr.s_addr = INADDR_ANY;
925 serv_addr.sin_port = htons(st->listen_port);
927 if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) {
932 if(listen(sock, 5) < 0) {
937 ILOG("Listening at *:%d...\n", st->listen_port);
939 int client = accept(sock, NULL, NULL);
940 //signal (SIGINT, SIG_DFL);
948 stlink_force_debug(sl);
952 init_code_breakpoints(sl);
953 init_data_watchpoints(sl);
955 ILOG("GDB connected.\n");
958 * To allow resetting the chip from GDB it is required to
959 * emulate attaching and detaching to target.
961 unsigned int attached = 1;
966 int status = gdb_recv_packet(client, &packet);
968 ELOG("cannot recv: %d\n", status);
970 win32_close_socket(sock);
975 DLOG("recv: %s\n", packet);
982 if(packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') {
987 char *separator = strstr(packet, ":"), *params = "";
988 if(separator == NULL) {
989 separator = packet + strlen(packet);
991 params = separator + 1;
994 unsigned queryNameLength = (separator - &packet[1]);
995 char* queryName = calloc(queryNameLength + 1, 1);
996 strncpy(queryName, &packet[1], queryNameLength);
998 DLOG("query: %s;%s\n", queryName, params);
1000 if(!strcmp(queryName, "Supported")) {
1001 if(sl->chip_id==STM32_CHIPID_F4
1002 || sl->chip_id==STM32_CHIPID_F4_HD
1003 || sl->chip_id==STM32_CHIPID_F7) {
1004 reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
1007 reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
1009 } else if(!strcmp(queryName, "Xfer")) {
1010 char *type, *op, *__s_addr, *s_length;
1012 char *annex __attribute__((unused));
1014 type = strsep(&tok, ":");
1015 op = strsep(&tok, ":");
1016 annex = strsep(&tok, ":");
1017 __s_addr = strsep(&tok, ",");
1020 unsigned addr = strtoul(__s_addr, NULL, 16),
1021 length = strtoul(s_length, NULL, 16);
1023 DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n",
1024 type, op, annex, addr, length);
1026 const char* data = NULL;
1028 if(!strcmp(type, "memory-map") && !strcmp(op, "read"))
1029 data = current_memory_map;
1031 if(!strcmp(type, "features") && !strcmp(op, "read"))
1032 data = target_description_F4;
1035 unsigned data_length = strlen(data);
1036 if(addr + length > data_length)
1037 length = data_length - addr;
1040 reply = strdup("l");
1042 reply = calloc(length + 2, 1);
1044 strncpy(&reply[1], data, length);
1047 } else if(!strncmp(queryName, "Rcmd,",4)) {
1048 // Rcmd uses the wrong separator
1049 char *separator = strstr(packet, ","), *params = "";
1050 if(separator == NULL) {
1051 separator = packet + strlen(packet);
1053 params = separator + 1;
1057 if (!strncmp(params,"726573756d65",12)) {// resume
1058 DLOG("Rcmd: resume\n");
1062 reply = strdup("OK");
1063 } else if (!strncmp(params,"68616c74",8)) { //halt
1064 reply = strdup("OK");
1066 stlink_force_debug(sl);
1068 DLOG("Rcmd: halt\n");
1069 } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset
1070 reply = strdup("OK");
1072 stlink_jtag_reset(sl, 0);
1073 stlink_jtag_reset(sl, 1);
1074 stlink_force_debug(sl);
1076 DLOG("Rcmd: jtag_reset\n");
1077 } else if (!strncmp(params,"7265736574",10)) { //reset
1078 reply = strdup("OK");
1080 stlink_force_debug(sl);
1082 init_code_breakpoints(sl);
1083 init_data_watchpoints(sl);
1085 DLOG("Rcmd: reset\n");
1087 DLOG("Rcmd: %s\n", params);
1101 char *params = NULL;
1102 char *cmdName = strtok_r(packet, ":;", ¶ms);
1104 cmdName++; // vCommand -> Command
1106 if(!strcmp(cmdName, "FlashErase")) {
1107 char *__s_addr, *s_length;
1110 __s_addr = strsep(&tok, ",");
1113 unsigned addr = strtoul(__s_addr, NULL, 16),
1114 length = strtoul(s_length, NULL, 16);
1116 DLOG("FlashErase: addr:%08x,len:%04x\n",
1119 if(flash_add_block(addr, length, sl) < 0) {
1120 reply = strdup("E00");
1122 reply = strdup("OK");
1124 } else if(!strcmp(cmdName, "FlashWrite")) {
1125 char *__s_addr, *data;
1128 __s_addr = strsep(&tok, ":");
1131 unsigned addr = strtoul(__s_addr, NULL, 16);
1132 unsigned data_length = status - (data - packet);
1134 // Length of decoded data cannot be more than
1135 // encoded, as escapes are removed.
1136 // Additional byte is reserved for alignment fix.
1137 uint8_t *decoded = calloc(data_length + 1, 1);
1138 unsigned dec_index = 0;
1139 for(unsigned int i = 0; i < data_length; i++) {
1140 if(data[i] == 0x7d) {
1142 decoded[dec_index++] = data[i] ^ 0x20;
1144 decoded[dec_index++] = data[i];
1149 if(dec_index % 2 != 0)
1152 DLOG("binary packet %d -> %d\n", data_length, dec_index);
1154 if(flash_populate(addr, decoded, dec_index) < 0) {
1155 reply = strdup("E00");
1157 reply = strdup("OK");
1159 } else if(!strcmp(cmdName, "FlashDone")) {
1160 if(flash_go(sl) < 0) {
1161 reply = strdup("E00");
1163 reply = strdup("OK");
1165 } else if(!strcmp(cmdName, "Kill")) {
1168 reply = strdup("OK");
1182 int status = gdb_check_for_interrupt(client);
1184 ELOG("cannot check for int: %d\n", status);
1186 win32_close_socket(sock);
1192 stlink_force_debug(sl);
1197 if(sl->core_stat == STLINK_CORE_HALTED) {
1204 reply = strdup("S05"); // TRAP
1211 reply = strdup("S05"); // TRAP
1216 reply = strdup("S05"); // TRAP
1218 /* Stub shall reply OK if not attached. */
1219 reply = strdup("OK");
1224 stlink_read_all_regs(sl, ®p);
1226 reply = calloc(8 * 16 + 1, 1);
1227 for(int i = 0; i < 16; i++)
1228 sprintf(&reply[i * 8], "%08x", htonl(regp.r[i]));
1233 unsigned id = strtoul(&packet[1], NULL, 16);
1234 unsigned myreg = 0xDEADDEAD;
1237 stlink_read_reg(sl, id, ®p);
1238 myreg = htonl(regp.r[id]);
1239 } else if(id == 0x19) {
1240 stlink_read_reg(sl, 16, ®p);
1241 myreg = htonl(regp.xpsr);
1242 } else if(id == 0x1A) {
1243 stlink_read_reg(sl, 17, ®p);
1244 myreg = htonl(regp.main_sp);
1245 } else if(id == 0x1B) {
1246 stlink_read_reg(sl, 18, ®p);
1247 myreg = htonl(regp.process_sp);
1248 } else if(id == 0x1C) {
1249 stlink_read_unsupported_reg(sl, id, ®p);
1250 myreg = htonl(regp.control);
1251 } else if(id == 0x1D) {
1252 stlink_read_unsupported_reg(sl, id, ®p);
1253 myreg = htonl(regp.faultmask);
1254 } else if(id == 0x1E) {
1255 stlink_read_unsupported_reg(sl, id, ®p);
1256 myreg = htonl(regp.basepri);
1257 } else if(id == 0x1F) {
1258 stlink_read_unsupported_reg(sl, id, ®p);
1259 myreg = htonl(regp.primask);
1260 } else if(id >= 0x20 && id < 0x40) {
1261 stlink_read_unsupported_reg(sl, id, ®p);
1262 myreg = htonl(regp.s[id-0x20]);
1263 } else if(id == 0x40) {
1264 stlink_read_unsupported_reg(sl, id, ®p);
1265 myreg = htonl(regp.fpscr);
1267 reply = strdup("E00");
1270 reply = calloc(8 + 1, 1);
1271 sprintf(reply, "%08x", myreg);
1277 char* s_reg = &packet[1];
1278 char* s_value = strstr(&packet[1], "=") + 1;
1280 unsigned reg = strtoul(s_reg, NULL, 16);
1281 unsigned value = strtoul(s_value, NULL, 16);
1284 stlink_write_reg(sl, ntohl(value), reg);
1285 } else if(reg == 0x19) {
1286 stlink_write_reg(sl, ntohl(value), 16);
1287 } else if(reg == 0x1A) {
1288 stlink_write_reg(sl, ntohl(value), 17);
1289 } else if(reg == 0x1B) {
1290 stlink_write_reg(sl, ntohl(value), 18);
1291 } else if(reg == 0x1C) {
1292 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1293 } else if(reg == 0x1D) {
1294 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1295 } else if(reg == 0x1E) {
1296 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1297 } else if(reg == 0x1F) {
1298 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1299 } else if(reg >= 0x20 && reg < 0x40) {
1300 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1301 } else if(reg == 0x40) {
1302 stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
1304 reply = strdup("E00");
1308 reply = strdup("OK");
1315 for(int i = 0; i < 16; i++) {
1317 strncpy(str, &packet[1 + i * 8], 8);
1318 uint32_t reg = strtoul(str, NULL, 16);
1319 stlink_write_reg(sl, ntohl(reg), i);
1322 reply = strdup("OK");
1326 char* s_start = &packet[1];
1327 char* s_count = strstr(&packet[1], ",") + 1;
1329 stm32_addr_t start = strtoul(s_start, NULL, 16);
1330 unsigned count = strtoul(s_count, NULL, 16);
1332 unsigned adj_start = start % 4;
1333 unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4;
1335 stlink_read_mem32(sl, start - adj_start, count_rnd);
1337 reply = calloc(count * 2 + 1, 1);
1338 for(unsigned int i = 0; i < count; i++) {
1339 reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4];
1340 reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf];
1347 char* s_start = &packet[1];
1348 char* s_count = strstr(&packet[1], ",") + 1;
1349 char* hexdata = strstr(packet, ":") + 1;
1351 stm32_addr_t start = strtoul(s_start, NULL, 16);
1352 unsigned count = strtoul(s_count, NULL, 16);
1355 unsigned align_count = 4 - start % 4;
1356 if (align_count > count) align_count = count;
1357 for(unsigned int i = 0; i < align_count; i ++) {
1358 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1359 uint8_t byte = strtoul(hex, NULL, 16);
1360 sl->q_buf[i] = byte;
1362 stlink_write_mem8(sl, start, align_count);
1363 cache_change(start, align_count);
1364 start += align_count;
1365 count -= align_count;
1366 hexdata += 2*align_count;
1369 if(count - count % 4) {
1370 unsigned aligned_count = count - count % 4;
1372 for(unsigned int i = 0; i < aligned_count; i ++) {
1373 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1374 uint8_t byte = strtoul(hex, NULL, 16);
1375 sl->q_buf[i] = byte;
1377 stlink_write_mem32(sl, start, aligned_count);
1378 cache_change(start, aligned_count);
1379 count -= aligned_count;
1380 start += aligned_count;
1381 hexdata += 2*aligned_count;
1385 for(unsigned int i = 0; i < count; i ++) {
1386 char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
1387 uint8_t byte = strtoul(hex, NULL, 16);
1388 sl->q_buf[i] = byte;
1390 stlink_write_mem8(sl, start, count);
1391 cache_change(start, count);
1393 reply = strdup("OK");
1399 stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
1400 stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
1402 switch (packet[1]) {
1404 if(update_code_breakpoint(sl, addr, 1) < 0) {
1405 reply = strdup("E00");
1407 reply = strdup("OK");
1411 case '2': // insert write watchpoint
1412 case '3': // insert read watchpoint
1413 case '4': { // insert access watchpoint
1415 if(packet[1] == '2') {
1417 } else if(packet[1] == '3') {
1423 if(add_data_watchpoint(sl, wf, addr, len) < 0) {
1424 reply = strdup("E00");
1426 reply = strdup("OK");
1438 stm32_addr_t addr = strtoul(&packet[3], &endptr, 16);
1439 //stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
1441 switch (packet[1]) {
1442 case '1': // remove breakpoint
1443 update_code_breakpoint(sl, addr, 0);
1444 reply = strdup("OK");
1447 case '2' : // remove write watchpoint
1448 case '3' : // remove read watchpoint
1449 case '4' : // remove access watchpoint
1450 if(delete_data_watchpoint(sl, addr) < 0) {
1451 reply = strdup("E00");
1453 reply = strdup("OK");
1465 * Enter extended mode which allows restarting.
1466 * We do support that always.
1470 * Also, set to persistent mode
1471 * to allow GDB disconnect.
1475 reply = strdup("OK");
1481 /* Reset the core. */
1484 init_code_breakpoints(sl);
1485 init_data_watchpoints(sl);
1489 reply = strdup("OK");
1499 DLOG("send: %s\n", reply);
1501 int result = gdb_send_packet(client, reply);
1503 ELOG("cannot send: %d\n", result);
1507 win32_close_socket(sock);
1519 win32_close_socket(sock);