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   1 /* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */
   2
   3 write:
   4         ldr     r4, STM32_FLASH_BASE
   5         mov     r5, #1            /*  FLASH_CR_PG, FLASH_SR_BUSY */
   6         mov     r6, #4            /*  PGERR  */
   7 write_half_word:
   8         ldr     r3, [r4, #16]     /*  FLASH->CR   */
   9         orr     r3, r5
  10         str     r3, [r4, #16]     /*  FLASH->CR |= FLASH_CR_PG */
  11         ldrh    r3, [r0]          /*  r3 = *sram */
  12         strh    r3, [r1]          /*  *flash = r3 */
  13 busy:
  14         ldr     r3, [r4, #12]     /*  FLASH->SR  */
  15         tst     r3, r5            /*  FLASH_SR_BUSY  */
  16         beq     busy
  17
  18         tst     r3, r6            /*  PGERR  */
  19         bne     exit
  20
  21         add     r0, r0, #2        /*  sram += 2  */
  22         add     r1, r1, #2        /*  flash += 2  */
  23         sub     r2, r2, #0x01     /*  count--  */
  24         cmp     r2, #0
  25         bne     write_half_word
  26 exit:
  27         ldr     r3, [r4, #16]     /*  FLASH->CR  */
  28         bic     r3, r5
  29         str     r3, [r4, #16]     /*  FLASH->CR &= ~FLASH_CR_PG  */
  30         bkpt    #0x00
  31
  32 STM32_FLASH_BASE: .word 0x40022000