1 /**************************************************************************//**
2 * @file core_cm4_simd.h
3 * @brief CMSIS Cortex-M4 SIMD Header File
8 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 ******************************************************************************/
28 #ifndef __CORE_CM4_SIMD_H
29 #define __CORE_CM4_SIMD_H
32 /*******************************************************************************
33 * Hardware Abstraction Layer
34 ******************************************************************************/
37 /* ################### Compiler specific Intrinsics ########################### */
38 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
39 Access to dedicated SIMD instructions
43 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
44 /* ARM armcc specific functions */
46 /*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
47 #define __SADD8 __sadd8
48 #define __QADD8 __qadd8
49 #define __SHADD8 __shadd8
50 #define __UADD8 __uadd8
51 #define __UQADD8 __uqadd8
52 #define __UHADD8 __uhadd8
53 #define __SSUB8 __ssub8
54 #define __QSUB8 __qsub8
55 #define __SHSUB8 __shsub8
56 #define __USUB8 __usub8
57 #define __UQSUB8 __uqsub8
58 #define __UHSUB8 __uhsub8
59 #define __SADD16 __sadd16
60 #define __QADD16 __qadd16
61 #define __SHADD16 __shadd16
62 #define __UADD16 __uadd16
63 #define __UQADD16 __uqadd16
64 #define __UHADD16 __uhadd16
65 #define __SSUB16 __ssub16
66 #define __QSUB16 __qsub16
67 #define __SHSUB16 __shsub16
68 #define __USUB16 __usub16
69 #define __UQSUB16 __uqsub16
70 #define __UHSUB16 __uhsub16
73 #define __SHASX __shasx
75 #define __UQASX __uqasx
76 #define __UHASX __uhasx
79 #define __SHSAX __shsax
81 #define __UQSAX __uqsax
82 #define __UHSAX __uhsax
83 #define __USAD8 __usad8
84 #define __USADA8 __usada8
85 #define __SSAT16 __ssat16
86 #define __USAT16 __usat16
87 #define __UXTB16 __uxtb16
88 #define __UXTAB16 __uxtab16
89 #define __SXTB16 __sxtb16
90 #define __SXTAB16 __sxtab16
91 #define __SMUAD __smuad
92 #define __SMUADX __smuadx
93 #define __SMLAD __smlad
94 #define __SMLADX __smladx
95 #define __SMLALD __smlald
96 #define __SMLALDX __smlaldx
97 #define __SMUSD __smusd
98 #define __SMUSDX __smusdx
99 #define __SMLSD __smlsd
100 #define __SMLSDX __smlsdx
101 #define __SMLSLD __smlsld
102 #define __SMLSLDX __smlsldx
104 #define __QADD __qadd
105 #define __QSUB __qsub
107 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
108 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
110 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
111 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
114 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
118 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
119 /* IAR iccarm specific functions */
121 #include <cmsis_iar.h>
123 /*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
124 /* intrinsic __SADD8 see intrinsics.h */
125 /* intrinsic __QADD8 see intrinsics.h */
126 /* intrinsic __SHADD8 see intrinsics.h */
127 /* intrinsic __UADD8 see intrinsics.h */
128 /* intrinsic __UQADD8 see intrinsics.h */
129 /* intrinsic __UHADD8 see intrinsics.h */
130 /* intrinsic __SSUB8 see intrinsics.h */
131 /* intrinsic __QSUB8 see intrinsics.h */
132 /* intrinsic __SHSUB8 see intrinsics.h */
133 /* intrinsic __USUB8 see intrinsics.h */
134 /* intrinsic __UQSUB8 see intrinsics.h */
135 /* intrinsic __UHSUB8 see intrinsics.h */
136 /* intrinsic __SADD16 see intrinsics.h */
137 /* intrinsic __QADD16 see intrinsics.h */
138 /* intrinsic __SHADD16 see intrinsics.h */
139 /* intrinsic __UADD16 see intrinsics.h */
140 /* intrinsic __UQADD16 see intrinsics.h */
141 /* intrinsic __UHADD16 see intrinsics.h */
142 /* intrinsic __SSUB16 see intrinsics.h */
143 /* intrinsic __QSUB16 see intrinsics.h */
144 /* intrinsic __SHSUB16 see intrinsics.h */
145 /* intrinsic __USUB16 see intrinsics.h */
146 /* intrinsic __UQSUB16 see intrinsics.h */
147 /* intrinsic __UHSUB16 see intrinsics.h */
148 /* intrinsic __SASX see intrinsics.h */
149 /* intrinsic __QASX see intrinsics.h */
150 /* intrinsic __SHASX see intrinsics.h */
151 /* intrinsic __UASX see intrinsics.h */
152 /* intrinsic __UQASX see intrinsics.h */
153 /* intrinsic __UHASX see intrinsics.h */
154 /* intrinsic __SSAX see intrinsics.h */
155 /* intrinsic __QSAX see intrinsics.h */
156 /* intrinsic __SHSAX see intrinsics.h */
157 /* intrinsic __USAX see intrinsics.h */
158 /* intrinsic __UQSAX see intrinsics.h */
159 /* intrinsic __UHSAX see intrinsics.h */
160 /* intrinsic __USAD8 see intrinsics.h */
161 /* intrinsic __USADA8 see intrinsics.h */
162 /* intrinsic __SSAT16 see intrinsics.h */
163 /* intrinsic __USAT16 see intrinsics.h */
164 /* intrinsic __UXTB16 see intrinsics.h */
165 /* intrinsic __SXTB16 see intrinsics.h */
166 /* intrinsic __UXTAB16 see intrinsics.h */
167 /* intrinsic __SXTAB16 see intrinsics.h */
168 /* intrinsic __SMUAD see intrinsics.h */
169 /* intrinsic __SMUADX see intrinsics.h */
170 /* intrinsic __SMLAD see intrinsics.h */
171 /* intrinsic __SMLADX see intrinsics.h */
172 /* intrinsic __SMLALD see intrinsics.h */
173 /* intrinsic __SMLALDX see intrinsics.h */
174 /* intrinsic __SMUSD see intrinsics.h */
175 /* intrinsic __SMUSDX see intrinsics.h */
176 /* intrinsic __SMLSD see intrinsics.h */
177 /* intrinsic __SMLSDX see intrinsics.h */
178 /* intrinsic __SMLSLD see intrinsics.h */
179 /* intrinsic __SMLSLDX see intrinsics.h */
180 /* intrinsic __SEL see intrinsics.h */
181 /* intrinsic __QADD see intrinsics.h */
182 /* intrinsic __QSUB see intrinsics.h */
183 /* intrinsic __PKHBT see intrinsics.h */
184 /* intrinsic __PKHTB see intrinsics.h */
186 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
190 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
191 /* GNU gcc specific functions */
193 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
194 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
198 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
202 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
206 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
210 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
214 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
218 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
222 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
226 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
230 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
234 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
238 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
243 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
247 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
251 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
255 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
259 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
263 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
267 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
271 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
275 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
279 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
283 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
287 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
292 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
296 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
300 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
304 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
308 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
312 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
316 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
320 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
324 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
328 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
332 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
336 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
340 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
344 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
352 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
356 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
360 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
368 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
372 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
376 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
380 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
384 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
392 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
396 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
400 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
404 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
408 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
412 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
416 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
420 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
424 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
428 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
432 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
436 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
440 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
444 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
448 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
452 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
456 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
460 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
464 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
468 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
472 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
476 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
480 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
484 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
488 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
492 __attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
496 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
500 #define __SSAT16(ARG1,ARG2) \
502 uint32_t __RES, __ARG1 = (ARG1); \
503 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
507 #define __USAT16(ARG1,ARG2) \
509 uint32_t __RES, __ARG1 = (ARG1); \
510 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
514 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
518 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
522 __attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
526 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
530 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
534 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
538 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
542 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
546 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
550 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
554 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
558 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
562 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
566 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
570 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
574 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
578 #define __SMLALD(ARG1,ARG2,ARG3) \
580 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
581 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
582 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
585 #define __SMLALDX(ARG1,ARG2,ARG3) \
587 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
588 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
589 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
592 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
596 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
600 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
604 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
608 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
612 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
616 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
620 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
624 #define __SMLSLD(ARG1,ARG2,ARG3) \
626 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
627 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
628 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
631 #define __SMLSLDX(ARG1,ARG2,ARG3) \
633 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
634 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
635 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
638 __attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
642 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
646 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
650 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
654 __attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
658 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
662 #define __PKHBT(ARG1,ARG2,ARG3) \
664 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
665 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
669 #define __PKHTB(ARG1,ARG2,ARG3) \
671 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
673 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
675 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
679 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
683 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
684 /* TASKING carm specific functions */
687 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
688 /* not yet supported */
689 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
694 /*@} end of group CMSIS_SIMD_intrinsics */
697 #endif /* __CORE_CM4_SIMD_H */