2 ******************************************************************************
4 * @author MCD Application Team
7 * @brief Peripheral Device interrupt subroutines
8 ******************************************************************************
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
19 ******************************************************************************
22 /* Includes ------------------------------------------------------------------*/
23 #include "usb_dcd_int.h"
24 /** @addtogroup USB_OTG_DRIVER
28 /** @defgroup USB_DCD_INT
29 * @brief This file contains the interrupt subroutines for the Device mode.
34 /** @defgroup USB_DCD_INT_Private_Defines
42 /** @defgroup USB_DCD_INT_Private_TypesDefinitions
51 /** @defgroup USB_DCD_INT_Private_Macros
59 /** @defgroup USB_DCD_INT_Private_Variables
67 /** @defgroup USB_DCD_INT_Private_FunctionPrototypes
70 /* static functions */
71 static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
73 /* Interrupt Handlers */
74 static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
75 static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
76 static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);
78 static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
79 static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);
81 static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
82 static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
83 static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
84 static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);
86 static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
87 static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
88 #ifdef VBUS_SENSING_ENABLED
89 static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
90 static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
98 /** @defgroup USB_DCD_INT_Private_Functions
103 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
105 * @brief USBD_OTG_EP1OUT_ISR_Handler
106 * handles all USB Interrupts
107 * @param pdev: device instance
110 uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
113 USB_OTG_DOEPINTn_TypeDef doepint;
114 USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
116 doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
117 doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
119 /* Transfer complete */
120 if ( doepint.b.xfercompl )
122 /* Clear the bit in DOEPINTn for this interrupt */
123 CLEAR_OUT_EP_INTR(1, xfercompl);
124 if (pdev->cfg.dma_enable == 1)
126 deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
127 /*ToDo : handle more than one single MPS size packet */
128 pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
131 /* Inform upper layer: data ready */
133 USBD_DCD_INT_fops->DataOutStage(pdev , 1);
137 /* Endpoint disable */
138 if ( doepint.b.epdisabled )
140 /* Clear the bit in DOEPINTn for this interrupt */
141 CLEAR_OUT_EP_INTR(1, epdisabled);
144 if ( doepint.b.ahberr )
146 CLEAR_OUT_EP_INTR(1, ahberr);
152 * @brief USBD_OTG_EP1IN_ISR_Handler
153 * handles all USB Interrupts
154 * @param pdev: device instance
157 uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
160 USB_OTG_DIEPINTn_TypeDef diepint;
161 uint32_t fifoemptymsk, msk, emp;
163 msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
164 emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
165 msk |= ((emp >> 1 ) & 0x1) << 7;
166 diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
168 if ( diepint.b.xfercompl )
170 fifoemptymsk = 0x1 << 1;
171 USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
172 CLEAR_IN_EP_INTR(1, xfercompl);
174 USBD_DCD_INT_fops->DataInStage(pdev , 1);
176 if ( diepint.b.ahberr )
178 CLEAR_IN_EP_INTR(1, ahberr);
180 if ( diepint.b.epdisabled )
182 CLEAR_IN_EP_INTR(1, epdisabled);
184 if ( diepint.b.timeout )
186 CLEAR_IN_EP_INTR(1, timeout);
188 if (diepint.b.intktxfemp)
190 CLEAR_IN_EP_INTR(1, intktxfemp);
192 if (diepint.b.intknepmis)
194 CLEAR_IN_EP_INTR(1, intknepmis);
196 if (diepint.b.inepnakeff)
198 CLEAR_IN_EP_INTR(1, inepnakeff);
200 if (diepint.b.emptyintr)
202 DCD_WriteEmptyTxFifo(pdev , 1);
203 CLEAR_IN_EP_INTR(1, emptyintr);
210 * @brief STM32_USBF_OTG_ISR_Handler
211 * handles all USB Interrupts
212 * @param pdev: device instance
215 uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
217 USB_OTG_GINTSTS_TypeDef gintr_status;
220 if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
222 gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
223 if (!gintr_status.d32) /* avoid spurious interrupt */
228 if (gintr_status.b.outepintr)
230 retval |= DCD_HandleOutEP_ISR(pdev);
233 if (gintr_status.b.inepint)
235 retval |= DCD_HandleInEP_ISR(pdev);
238 if (gintr_status.b.modemismatch)
240 USB_OTG_GINTSTS_TypeDef gintsts;
242 /* Clear interrupt */
244 gintsts.b.modemismatch = 1;
245 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
248 if (gintr_status.b.wkupintr)
250 retval |= DCD_HandleResume_ISR(pdev);
253 if (gintr_status.b.usbsuspend)
255 retval |= DCD_HandleUSBSuspend_ISR(pdev);
257 if (gintr_status.b.sofintr)
259 retval |= DCD_HandleSof_ISR(pdev);
263 if (gintr_status.b.rxstsqlvl)
265 retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
269 if (gintr_status.b.usbreset)
271 retval |= DCD_HandleUsbReset_ISR(pdev);
274 if (gintr_status.b.enumdone)
276 retval |= DCD_HandleEnumDone_ISR(pdev);
279 if (gintr_status.b.incomplisoin)
281 retval |= DCD_IsoINIncomplete_ISR(pdev);
284 if (gintr_status.b.incomplisoout)
286 retval |= DCD_IsoOUTIncomplete_ISR(pdev);
288 #ifdef VBUS_SENSING_ENABLED
289 if (gintr_status.b.sessreqintr)
291 retval |= DCD_SessionRequest_ISR(pdev);
294 if (gintr_status.b.otgintr)
296 retval |= DCD_OTG_ISR(pdev);
303 #ifdef VBUS_SENSING_ENABLED
305 * @brief DCD_SessionRequest_ISR
306 * Indicates that the USB_OTG controller has detected a connection
307 * @param pdev: device instance
310 static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
312 USB_OTG_GINTSTS_TypeDef gintsts;
313 USBD_DCD_INT_fops->DevConnected (pdev);
315 /* Clear interrupt */
317 gintsts.b.sessreqintr = 1;
318 USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
324 * Indicates that the USB_OTG controller has detected an OTG event:
325 * used to detect the end of session i.e. disconnection
326 * @param pdev: device instance
329 static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
332 USB_OTG_GOTGINT_TypeDef gotgint;
334 gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
336 if (gotgint.b.sesenddet)
338 USBD_DCD_INT_fops->DevDisconnected (pdev);
340 /* Clear OTG interrupt */
341 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
346 * @brief DCD_HandleResume_ISR
347 * Indicates that the USB_OTG controller has detected a resume or
348 * remote Wake-up sequence
349 * @param pdev: device instance
352 static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
354 USB_OTG_GINTSTS_TypeDef gintsts;
355 USB_OTG_DCTL_TypeDef devctl;
356 USB_OTG_PCGCCTL_TypeDef power;
358 if(pdev->cfg.low_power)
360 /* un-gate USB Core clock */
361 power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
362 power.b.gatehclk = 0;
363 power.b.stoppclk = 0;
364 USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
367 /* Clear the Remote Wake-up Signaling */
369 devctl.b.rmtwkupsig = 1;
370 USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
372 /* Inform upper layer by the Resume Event */
373 USBD_DCD_INT_fops->Resume (pdev);
375 /* Clear interrupt */
377 gintsts.b.wkupintr = 1;
378 USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
383 * @brief USB_OTG_HandleUSBSuspend_ISR
384 * Indicates that SUSPEND state has been detected on the USB
385 * @param pdev: device instance
388 static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
390 USB_OTG_GINTSTS_TypeDef gintsts;
391 USB_OTG_PCGCCTL_TypeDef power;
392 USB_OTG_DSTS_TypeDef dsts;
394 USBD_DCD_INT_fops->Suspend (pdev);
396 dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
398 /* Clear interrupt */
400 gintsts.b.usbsuspend = 1;
401 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
403 if((pdev->cfg.low_power) && (dsts.b.suspsts == 1))
405 /* switch-off the clocks */
407 power.b.stoppclk = 1;
408 USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
410 power.b.gatehclk = 1;
411 USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
413 /* Request to enter Sleep mode after exit from current ISR */
414 SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
420 * @brief DCD_HandleInEP_ISR
421 * Indicates that an IN EP has a pending Interrupt
422 * @param pdev: device instance
425 static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
427 USB_OTG_DIEPINTn_TypeDef diepint;
431 uint32_t fifoemptymsk;
433 ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
437 if (ep_intr&0x1) /* In ITR */
439 diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */
440 if ( diepint.b.xfercompl )
442 fifoemptymsk = 0x1 << epnum;
443 USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
444 CLEAR_IN_EP_INTR(epnum, xfercompl);
446 USBD_DCD_INT_fops->DataInStage(pdev , epnum);
448 if (pdev->cfg.dma_enable == 1)
450 if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
452 /* prepare to rx more setup packets */
453 USB_OTG_EP0_OutStart(pdev);
457 if ( diepint.b.ahberr )
459 CLEAR_IN_EP_INTR(epnum, ahberr);
461 if ( diepint.b.timeout )
463 CLEAR_IN_EP_INTR(epnum, timeout);
465 if (diepint.b.intktxfemp)
467 CLEAR_IN_EP_INTR(epnum, intktxfemp);
469 if (diepint.b.intknepmis)
471 CLEAR_IN_EP_INTR(epnum, intknepmis);
473 if (diepint.b.inepnakeff)
475 CLEAR_IN_EP_INTR(epnum, inepnakeff);
477 if ( diepint.b.epdisabled )
479 CLEAR_IN_EP_INTR(epnum, epdisabled);
481 if (diepint.b.emptyintr)
484 DCD_WriteEmptyTxFifo(pdev , epnum);
486 CLEAR_IN_EP_INTR(epnum, emptyintr);
497 * @brief DCD_HandleOutEP_ISR
498 * Indicates that an OUT EP has a pending Interrupt
499 * @param pdev: device instance
502 static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
505 USB_OTG_DOEPINTn_TypeDef doepint;
506 USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
511 /* Read in the device interrupt bits */
512 ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
519 doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
521 /* Transfer complete */
522 if ( doepint.b.xfercompl )
524 /* Clear the bit in DOEPINTn for this interrupt */
525 CLEAR_OUT_EP_INTR(epnum, xfercompl);
526 if (pdev->cfg.dma_enable == 1)
528 deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ));
529 /*ToDo : handle more than one single MPS size packet */
530 pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \
533 /* Inform upper layer: data ready */
535 USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
537 if (pdev->cfg.dma_enable == 1)
539 if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
541 /* prepare to rx more setup packets */
542 USB_OTG_EP0_OutStart(pdev);
546 /* Endpoint disable */
547 if ( doepint.b.epdisabled )
549 /* Clear the bit in DOEPINTn for this interrupt */
550 CLEAR_OUT_EP_INTR(epnum, epdisabled);
553 if ( doepint.b.ahberr )
555 CLEAR_OUT_EP_INTR(epnum, ahberr);
557 /* Setup Phase Done (control EPs) */
558 if ( doepint.b.setup )
561 /* inform the upper layer that a setup packet is available */
563 USBD_DCD_INT_fops->SetupStage(pdev);
564 CLEAR_OUT_EP_INTR(epnum, setup);
574 * @brief DCD_HandleSof_ISR
575 * Handles the SOF Interrupts
576 * @param pdev: device instance
579 static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
581 USB_OTG_GINTSTS_TypeDef GINTSTS;
584 USBD_DCD_INT_fops->SOF(pdev);
586 /* Clear interrupt */
588 GINTSTS.b.sofintr = 1;
589 USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
595 * @brief DCD_HandleRxStatusQueueLevel_ISR
596 * Handles the Rx Status Queue Level Interrupt
597 * @param pdev: device instance
600 static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
602 USB_OTG_GINTMSK_TypeDef int_mask;
603 USB_OTG_DRXSTS_TypeDef status;
606 /* Disable the Rx Status Queue Level interrupt */
608 int_mask.b.rxstsqlvl = 1;
609 USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
611 /* Get the Status from the top of the FIFO */
612 status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
614 ep = &pdev->dev.out_ep[status.b.epnum];
616 switch (status.b.pktsts)
623 USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
624 ep->xfer_buff += status.b.bcnt;
625 ep->xfer_count += status.b.bcnt;
633 /* Copy the setup packet received in FIFO into the setup buffer in RAM */
634 USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
635 ep->xfer_count += status.b.bcnt;
641 /* Enable the Rx Status Queue Level interrupt */
642 USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
648 * @brief DCD_WriteEmptyTxFifo
649 * check FIFO for the next packet to be loaded
650 * @param pdev: device instance
653 static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
655 USB_OTG_DTXFSTSn_TypeDef txstatus;
661 ep = &pdev->dev.in_ep[epnum];
663 len = ep->xfer_len - ep->xfer_count;
665 if (len > ep->maxpacket)
670 len32b = (len + 3) / 4;
671 txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
675 while (txstatus.b.txfspcavail > len32b &&
676 ep->xfer_count < ep->xfer_len &&
680 len = ep->xfer_len - ep->xfer_count;
682 if (len > ep->maxpacket)
686 len32b = (len + 3) / 4;
688 USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
690 ep->xfer_buff += len;
691 ep->xfer_count += len;
693 txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
700 * @brief DCD_HandleUsbReset_ISR
701 * This interrupt occurs when a USB Reset is detected
702 * @param pdev: device instance
705 static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
707 USB_OTG_DAINT_TypeDef daintmsk;
708 USB_OTG_DOEPMSK_TypeDef doepmsk;
709 USB_OTG_DIEPMSK_TypeDef diepmsk;
710 USB_OTG_DCFG_TypeDef dcfg;
711 USB_OTG_DCTL_TypeDef dctl;
712 USB_OTG_GINTSTS_TypeDef gintsts;
722 /* Clear the Remote Wake-up Signaling */
723 dctl.b.rmtwkupsig = 1;
724 USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
726 /* Flush the Tx FIFO */
727 USB_OTG_FlushTxFifo(pdev , 0 );
729 for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
731 USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
732 USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
734 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
738 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
741 doepmsk.b.xfercompl = 1;
742 doepmsk.b.ahberr = 1;
743 doepmsk.b.epdisabled = 1;
744 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
745 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
746 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
748 diepmsk.b.xfercompl = 1;
749 diepmsk.b.timeout = 1;
750 diepmsk.b.epdisabled = 1;
751 diepmsk.b.ahberr = 1;
752 diepmsk.b.intknepmis = 1;
753 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
754 #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
755 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
757 /* Reset Device Address */
758 dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
760 USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
763 /* setup EP0 to receive SETUP packets */
764 USB_OTG_EP0_OutStart(pdev);
766 /* Clear interrupt */
768 gintsts.b.usbreset = 1;
769 USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
771 /*Reset internal state machine */
772 USBD_DCD_INT_fops->Reset(pdev);
777 * @brief DCD_HandleEnumDone_ISR
778 * Read the device status register and set the device speed
779 * @param pdev: device instance
782 static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
784 USB_OTG_GINTSTS_TypeDef gintsts;
785 USB_OTG_GUSBCFG_TypeDef gusbcfg;
787 USB_OTG_EP0Activate(pdev);
789 /* Set USB turn-around time based on device speed and PHY interface. */
790 gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
792 /* Full or High speed */
793 if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
795 pdev->cfg.speed = USB_OTG_SPEED_HIGH;
796 pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
797 gusbcfg.b.usbtrdtim = 9;
801 pdev->cfg.speed = USB_OTG_SPEED_FULL;
802 pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
803 gusbcfg.b.usbtrdtim = 5;
806 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
808 /* Clear interrupt */
810 gintsts.b.enumdone = 1;
811 USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 );
817 * @brief DCD_IsoINIncomplete_ISR
818 * handle the ISO IN incomplete interrupt
819 * @param pdev: device instance
822 static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
824 USB_OTG_GINTSTS_TypeDef gintsts;
828 USBD_DCD_INT_fops->IsoINIncomplete (pdev);
830 /* Clear interrupt */
831 gintsts.b.incomplisoin = 1;
832 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
838 * @brief DCD_IsoOUTIncomplete_ISR
839 * handle the ISO OUT incomplete interrupt
840 * @param pdev: device instance
843 static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
845 USB_OTG_GINTSTS_TypeDef gintsts;
849 USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
851 /* Clear interrupt */
852 gintsts.b.incomplisoout = 1;
853 USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
857 * @brief DCD_ReadDevInEP
859 * @param pdev: device instance
862 static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
864 uint32_t v, msk, emp;
865 msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK);
866 emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
867 msk |= ((emp >> epnum) & 0x1) << 7;
868 v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk;
886 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/