2 ******************************************************************************
3 * @file stm32f4xx_tim.c
4 * @author MCD Application Team
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the TIM peripheral:
9 * - TimeBase management
10 * - Output Compare management
11 * - Input Capture management
12 * - Advanced-control timers (TIM1 and TIM8) specific features
13 * - Interrupts, DMA and flags management
15 * - Synchronization management
16 * - Specific interface management
17 * - Specific remapping management
21 * ===================================================================
22 * How to use this driver
23 * ===================================================================
24 * This driver provides functions to configure and program the TIM
25 * of all STM32F4xx devices.
26 * These functions are split in 9 groups:
28 * 1. TIM TimeBase management: this group includes all needed functions
29 * to configure the TM Timebase unit:
31 * - Set/Get Autoreload
32 * - Counter modes configuration
33 * - Set Clock division
34 * - Select the One Pulse mode
35 * - Update Request Configuration
36 * - Update Disable Configuration
37 * - Auto-Preload Configuration
38 * - Enable/Disable the counter
40 * 2. TIM Output Compare management: this group includes all needed
41 * functions to configure the Capture/Compare unit used in Output
43 * - Configure each channel, independently, in Output Compare mode
44 * - Select the output compare modes
45 * - Select the Polarities of each channel
46 * - Set/Get the Capture/Compare register values
47 * - Select the Output Compare Fast mode
48 * - Select the Output Compare Forced mode
49 * - Output Compare-Preload Configuration
50 * - Clear Output Compare Reference
51 * - Select the OCREF Clear signal
52 * - Enable/Disable the Capture/Compare Channels
54 * 3. TIM Input Capture management: this group includes all needed
55 * functions to configure the Capture/Compare unit used in
57 * - Configure each channel in input capture mode
58 * - Configure Channel1/2 in PWM Input mode
59 * - Set the Input Capture Prescaler
60 * - Get the Capture/Compare values
62 * 4. Advanced-control timers (TIM1 and TIM8) specific features
63 * - Configures the Break input, dead time, Lock level, the OSSI,
64 * the OSSR State and the AOE(automatic output enable)
65 * - Enable/Disable the TIM peripheral Main Outputs
66 * - Select the Commutation event
67 * - Set/Reset the Capture Compare Preload Control bit
69 * 5. TIM interrupts, DMA and flags management
70 * - Enable/Disable interrupt sources
72 * - Clear flags/ Pending bits
73 * - Enable/Disable DMA requests
74 * - Configure DMA burst mode
75 * - Select CaptureCompare DMA request
77 * 6. TIM clocks management: this group includes all needed functions
78 * to configure the clock controller unit:
79 * - Select internal/External clock
80 * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
82 * 7. TIM synchronization management: this group includes all needed
83 * functions to configure the Synchronization unit:
84 * - Select Input Trigger
85 * - Select Output Trigger
86 * - Select Master Slave Mode
87 * - ETR Configuration when used as external trigger
89 * 8. TIM specific interface management, this group includes all
90 * needed functions to use the specific TIM interface:
91 * - Encoder Interface Configuration
92 * - Select Hall Sensor
94 * 9. TIM specific remapping management includes the Remapping
95 * configuration of specific timers
99 ******************************************************************************
102 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
103 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
104 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
105 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
106 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
107 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
109 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
110 ******************************************************************************
113 /* Includes ------------------------------------------------------------------*/
114 #include "stm32f4xx_tim.h"
115 #include "stm32f4xx_rcc.h"
117 /** @addtogroup STM32F4xx_StdPeriph_Driver
122 * @brief TIM driver modules
126 /* Private typedef -----------------------------------------------------------*/
127 /* Private define ------------------------------------------------------------*/
129 /* ---------------------- TIM registers bit mask ------------------------ */
130 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
131 #define CCMR_OFFSET ((uint16_t)0x0018)
132 #define CCER_CCE_SET ((uint16_t)0x0001)
133 #define CCER_CCNE_SET ((uint16_t)0x0004)
134 #define CCMR_OC13M_MASK ((uint16_t)0xFF8F)
135 #define CCMR_OC24M_MASK ((uint16_t)0x8FFF)
137 /* Private macro -------------------------------------------------------------*/
138 /* Private variables ---------------------------------------------------------*/
139 /* Private function prototypes -----------------------------------------------*/
140 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
141 uint16_t TIM_ICFilter);
142 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
143 uint16_t TIM_ICFilter);
144 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
145 uint16_t TIM_ICFilter);
146 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
147 uint16_t TIM_ICFilter);
149 /* Private functions ---------------------------------------------------------*/
151 /** @defgroup TIM_Private_Functions
155 /** @defgroup TIM_Group1 TimeBase management functions
156 * @brief TimeBase management functions
159 ===============================================================================
160 TimeBase management functions
161 ===============================================================================
163 ===================================================================
164 TIM Driver: how to use it in Timing(Time base) Mode
165 ===================================================================
166 To use the Timer in Timing(Time base) mode, the following steps are mandatory:
168 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
170 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
172 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
173 with the corresponding configuration
175 4. Enable the NVIC if you need to generate the update interrupt.
177 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
179 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
181 Note1: All other functions can be used separately to modify, if needed,
182 a specific feature of the Timer.
189 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
190 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
194 void TIM_DeInit(TIM_TypeDef* TIMx)
196 /* Check the parameters */
197 assert_param(IS_TIM_ALL_PERIPH(TIMx));
201 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
202 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
204 else if (TIMx == TIM2)
206 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
207 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
209 else if (TIMx == TIM3)
211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
214 else if (TIMx == TIM4)
216 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
219 else if (TIMx == TIM5)
221 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
224 else if (TIMx == TIM6)
226 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
229 else if (TIMx == TIM7)
231 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
234 else if (TIMx == TIM8)
236 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
237 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
239 else if (TIMx == TIM9)
241 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
242 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
244 else if (TIMx == TIM10)
246 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
249 else if (TIMx == TIM11)
251 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
252 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
254 else if (TIMx == TIM12)
256 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
257 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
259 else if (TIMx == TIM13)
261 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
262 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
268 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
269 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
275 * @brief Initializes the TIMx Time Base Unit peripheral according to
276 * the specified parameters in the TIM_TimeBaseInitStruct.
277 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
278 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
279 * that contains the configuration information for the specified TIM peripheral.
282 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
286 /* Check the parameters */
287 assert_param(IS_TIM_ALL_PERIPH(TIMx));
288 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
289 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
293 if((TIMx == TIM1) || (TIMx == TIM8)||
294 (TIMx == TIM2) || (TIMx == TIM3)||
295 (TIMx == TIM4) || (TIMx == TIM5))
297 /* Select the Counter Mode */
298 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
299 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
302 if((TIMx != TIM6) && (TIMx != TIM7))
304 /* Set the clock division */
305 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD);
306 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
311 /* Set the Autoreload value */
312 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
314 /* Set the Prescaler value */
315 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
317 if ((TIMx == TIM1) || (TIMx == TIM8))
319 /* Set the Repetition Counter value */
320 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
323 /* Generate an update event to reload the Prescaler
324 and the repetition counter(only for TIM1 and TIM8) value immediatly */
325 TIMx->EGR = TIM_PSCReloadMode_Immediate;
329 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
330 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
331 * structure which will be initialized.
334 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
336 /* Set the default configuration */
337 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
338 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
339 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
340 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
341 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
345 * @brief Configures the TIMx Prescaler.
346 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
347 * @param Prescaler: specifies the Prescaler Register value
348 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
349 * This parameter can be one of the following values:
350 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
351 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
354 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
356 /* Check the parameters */
357 assert_param(IS_TIM_ALL_PERIPH(TIMx));
358 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
359 /* Set the Prescaler value */
360 TIMx->PSC = Prescaler;
361 /* Set or reset the UG Bit */
362 TIMx->EGR = TIM_PSCReloadMode;
366 * @brief Specifies the TIMx Counter Mode to be used.
367 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
368 * @param TIM_CounterMode: specifies the Counter Mode to be used
369 * This parameter can be one of the following values:
370 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
371 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
372 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
373 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
374 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
377 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
381 /* Check the parameters */
382 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
383 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
387 /* Reset the CMS and DIR Bits */
388 tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
390 /* Set the Counter Mode */
391 tmpcr1 |= TIM_CounterMode;
393 /* Write to TIMx CR1 register */
398 * @brief Sets the TIMx Counter Register value
399 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
400 * @param Counter: specifies the Counter register new value.
403 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
405 /* Check the parameters */
406 assert_param(IS_TIM_ALL_PERIPH(TIMx));
408 /* Set the Counter Register value */
413 * @brief Sets the TIMx Autoreload Register value
414 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
415 * @param Autoreload: specifies the Autoreload register new value.
418 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
420 /* Check the parameters */
421 assert_param(IS_TIM_ALL_PERIPH(TIMx));
423 /* Set the Autoreload Register value */
424 TIMx->ARR = Autoreload;
428 * @brief Gets the TIMx Counter value.
429 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
430 * @retval Counter Register value
432 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
434 /* Check the parameters */
435 assert_param(IS_TIM_ALL_PERIPH(TIMx));
437 /* Get the Counter Register value */
442 * @brief Gets the TIMx Prescaler value.
443 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
444 * @retval Prescaler Register value.
446 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
448 /* Check the parameters */
449 assert_param(IS_TIM_ALL_PERIPH(TIMx));
451 /* Get the Prescaler Register value */
456 * @brief Enables or Disables the TIMx Update event.
457 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
458 * @param NewState: new state of the TIMx UDIS bit
459 * This parameter can be: ENABLE or DISABLE.
462 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
464 /* Check the parameters */
465 assert_param(IS_TIM_ALL_PERIPH(TIMx));
466 assert_param(IS_FUNCTIONAL_STATE(NewState));
468 if (NewState != DISABLE)
470 /* Set the Update Disable Bit */
471 TIMx->CR1 |= TIM_CR1_UDIS;
475 /* Reset the Update Disable Bit */
476 TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
481 * @brief Configures the TIMx Update Request Interrupt source.
482 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
483 * @param TIM_UpdateSource: specifies the Update source.
484 * This parameter can be one of the following values:
485 * @arg TIM_UpdateSource_Regular: Source of update is the counter
486 * overflow/underflow or the setting of UG bit, or an update
487 * generation through the slave mode controller.
488 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
491 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
493 /* Check the parameters */
494 assert_param(IS_TIM_ALL_PERIPH(TIMx));
495 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
497 if (TIM_UpdateSource != TIM_UpdateSource_Global)
499 /* Set the URS Bit */
500 TIMx->CR1 |= TIM_CR1_URS;
504 /* Reset the URS Bit */
505 TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
510 * @brief Enables or disables TIMx peripheral Preload register on ARR.
511 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
512 * @param NewState: new state of the TIMx peripheral Preload register
513 * This parameter can be: ENABLE or DISABLE.
516 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
518 /* Check the parameters */
519 assert_param(IS_TIM_ALL_PERIPH(TIMx));
520 assert_param(IS_FUNCTIONAL_STATE(NewState));
522 if (NewState != DISABLE)
524 /* Set the ARR Preload Bit */
525 TIMx->CR1 |= TIM_CR1_ARPE;
529 /* Reset the ARR Preload Bit */
530 TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
535 * @brief Selects the TIMx's One Pulse Mode.
536 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
537 * @param TIM_OPMode: specifies the OPM Mode to be used.
538 * This parameter can be one of the following values:
539 * @arg TIM_OPMode_Single
540 * @arg TIM_OPMode_Repetitive
543 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
545 /* Check the parameters */
546 assert_param(IS_TIM_ALL_PERIPH(TIMx));
547 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
549 /* Reset the OPM Bit */
550 TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
552 /* Configure the OPM Mode */
553 TIMx->CR1 |= TIM_OPMode;
557 * @brief Sets the TIMx Clock Division value.
558 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
559 * @param TIM_CKD: specifies the clock division value.
560 * This parameter can be one of the following value:
561 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
562 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
563 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
566 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
568 /* Check the parameters */
569 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
570 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
572 /* Reset the CKD Bits */
573 TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
575 /* Set the CKD value */
576 TIMx->CR1 |= TIM_CKD;
580 * @brief Enables or disables the specified TIM peripheral.
581 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
582 * @param NewState: new state of the TIMx peripheral.
583 * This parameter can be: ENABLE or DISABLE.
586 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
588 /* Check the parameters */
589 assert_param(IS_TIM_ALL_PERIPH(TIMx));
590 assert_param(IS_FUNCTIONAL_STATE(NewState));
592 if (NewState != DISABLE)
594 /* Enable the TIM Counter */
595 TIMx->CR1 |= TIM_CR1_CEN;
599 /* Disable the TIM Counter */
600 TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
607 /** @defgroup TIM_Group2 Output Compare management functions
608 * @brief Output Compare management functions
611 ===============================================================================
612 Output Compare management functions
613 ===============================================================================
615 ===================================================================
616 TIM Driver: how to use it in Output Compare Mode
617 ===================================================================
618 To use the Timer in Output Compare mode, the following steps are mandatory:
620 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
622 2. Configure the TIM pins by configuring the corresponding GPIO pins
624 2. Configure the Time base unit as described in the first part of this driver,
625 if needed, else the Timer will run with the default configuration:
626 - Autoreload value = 0xFFFF
627 - Prescaler value = 0x0000
628 - Counter mode = Up counting
629 - Clock Division = TIM_CKD_DIV1
631 3. Fill the TIM_OCInitStruct with the desired parameters including:
632 - The TIM Output Compare mode: TIM_OCMode
633 - TIM Output State: TIM_OutputState
634 - TIM Pulse value: TIM_Pulse
635 - TIM Output Compare Polarity : TIM_OCPolarity
637 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
638 corresponding configuration
640 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
642 Note1: All other functions can be used separately to modify, if needed,
643 a specific feature of the Timer.
645 Note2: In case of PWM mode, this function is mandatory:
646 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
648 Note3: If the corresponding interrupt or DMA request are needed, the user should:
649 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
650 2. Enable the corresponding interrupt (or DMA request) using the function
651 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
658 * @brief Initializes the TIMx Channel1 according to the specified parameters in
659 * the TIM_OCInitStruct.
660 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
661 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
662 * the configuration information for the specified TIM peripheral.
665 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
667 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
669 /* Check the parameters */
670 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
671 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
672 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
673 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
675 /* Disable the Channel 1: Reset the CC1E Bit */
676 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
678 /* Get the TIMx CCER register value */
679 tmpccer = TIMx->CCER;
680 /* Get the TIMx CR2 register value */
683 /* Get the TIMx CCMR1 register value */
684 tmpccmrx = TIMx->CCMR1;
686 /* Reset the Output Compare Mode Bits */
687 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
688 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
689 /* Select the Output Compare Mode */
690 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
692 /* Reset the Output Polarity level */
693 tmpccer &= (uint16_t)~TIM_CCER_CC1P;
694 /* Set the Output Compare Polarity */
695 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
697 /* Set the Output State */
698 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
700 if((TIMx == TIM1) || (TIMx == TIM8))
702 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
703 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
704 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
705 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
707 /* Reset the Output N Polarity level */
708 tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
709 /* Set the Output N Polarity */
710 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
711 /* Reset the Output N State */
712 tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
714 /* Set the Output N State */
715 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
716 /* Reset the Output Compare and Output Compare N IDLE State */
717 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
718 tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
719 /* Set the Output Idle state */
720 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
721 /* Set the Output N Idle state */
722 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
724 /* Write to TIMx CR2 */
727 /* Write to TIMx CCMR1 */
728 TIMx->CCMR1 = tmpccmrx;
730 /* Set the Capture Compare Register value */
731 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
733 /* Write to TIMx CCER */
734 TIMx->CCER = tmpccer;
738 * @brief Initializes the TIMx Channel2 according to the specified parameters
739 * in the TIM_OCInitStruct.
740 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
742 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
743 * the configuration information for the specified TIM peripheral.
746 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
748 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
750 /* Check the parameters */
751 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
752 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
753 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
754 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
756 /* Disable the Channel 2: Reset the CC2E Bit */
757 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
759 /* Get the TIMx CCER register value */
760 tmpccer = TIMx->CCER;
761 /* Get the TIMx CR2 register value */
764 /* Get the TIMx CCMR1 register value */
765 tmpccmrx = TIMx->CCMR1;
767 /* Reset the Output Compare mode and Capture/Compare selection Bits */
768 tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
769 tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
771 /* Select the Output Compare Mode */
772 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
774 /* Reset the Output Polarity level */
775 tmpccer &= (uint16_t)~TIM_CCER_CC2P;
776 /* Set the Output Compare Polarity */
777 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
779 /* Set the Output State */
780 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
782 if((TIMx == TIM1) || (TIMx == TIM8))
784 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
785 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
786 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
787 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
789 /* Reset the Output N Polarity level */
790 tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
791 /* Set the Output N Polarity */
792 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
793 /* Reset the Output N State */
794 tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
796 /* Set the Output N State */
797 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
798 /* Reset the Output Compare and Output Compare N IDLE State */
799 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
800 tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
801 /* Set the Output Idle state */
802 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
803 /* Set the Output N Idle state */
804 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
806 /* Write to TIMx CR2 */
809 /* Write to TIMx CCMR1 */
810 TIMx->CCMR1 = tmpccmrx;
812 /* Set the Capture Compare Register value */
813 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
815 /* Write to TIMx CCER */
816 TIMx->CCER = tmpccer;
820 * @brief Initializes the TIMx Channel3 according to the specified parameters
821 * in the TIM_OCInitStruct.
822 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
823 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
824 * the configuration information for the specified TIM peripheral.
827 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
829 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
831 /* Check the parameters */
832 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
833 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
834 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
835 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
837 /* Disable the Channel 3: Reset the CC2E Bit */
838 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
840 /* Get the TIMx CCER register value */
841 tmpccer = TIMx->CCER;
842 /* Get the TIMx CR2 register value */
845 /* Get the TIMx CCMR2 register value */
846 tmpccmrx = TIMx->CCMR2;
848 /* Reset the Output Compare mode and Capture/Compare selection Bits */
849 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
850 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;
851 /* Select the Output Compare Mode */
852 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
854 /* Reset the Output Polarity level */
855 tmpccer &= (uint16_t)~TIM_CCER_CC3P;
856 /* Set the Output Compare Polarity */
857 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
859 /* Set the Output State */
860 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
862 if((TIMx == TIM1) || (TIMx == TIM8))
864 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
865 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
866 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
867 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
869 /* Reset the Output N Polarity level */
870 tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
871 /* Set the Output N Polarity */
872 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
873 /* Reset the Output N State */
874 tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
876 /* Set the Output N State */
877 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
878 /* Reset the Output Compare and Output Compare N IDLE State */
879 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
880 tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
881 /* Set the Output Idle state */
882 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
883 /* Set the Output N Idle state */
884 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
886 /* Write to TIMx CR2 */
889 /* Write to TIMx CCMR2 */
890 TIMx->CCMR2 = tmpccmrx;
892 /* Set the Capture Compare Register value */
893 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
895 /* Write to TIMx CCER */
896 TIMx->CCER = tmpccer;
900 * @brief Initializes the TIMx Channel4 according to the specified parameters
901 * in the TIM_OCInitStruct.
902 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
903 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
904 * the configuration information for the specified TIM peripheral.
907 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
909 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
911 /* Check the parameters */
912 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
913 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
914 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
915 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
917 /* Disable the Channel 4: Reset the CC4E Bit */
918 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
920 /* Get the TIMx CCER register value */
921 tmpccer = TIMx->CCER;
922 /* Get the TIMx CR2 register value */
925 /* Get the TIMx CCMR2 register value */
926 tmpccmrx = TIMx->CCMR2;
928 /* Reset the Output Compare mode and Capture/Compare selection Bits */
929 tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
930 tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
932 /* Select the Output Compare Mode */
933 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
935 /* Reset the Output Polarity level */
936 tmpccer &= (uint16_t)~TIM_CCER_CC4P;
937 /* Set the Output Compare Polarity */
938 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
940 /* Set the Output State */
941 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
943 if((TIMx == TIM1) || (TIMx == TIM8))
945 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
946 /* Reset the Output Compare IDLE State */
947 tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
948 /* Set the Output Idle state */
949 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
951 /* Write to TIMx CR2 */
954 /* Write to TIMx CCMR2 */
955 TIMx->CCMR2 = tmpccmrx;
957 /* Set the Capture Compare Register value */
958 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
960 /* Write to TIMx CCER */
961 TIMx->CCER = tmpccer;
965 * @brief Fills each TIM_OCInitStruct member with its default value.
966 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
970 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
972 /* Set the default configuration */
973 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
974 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
975 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
976 TIM_OCInitStruct->TIM_Pulse = 0x00000000;
977 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
978 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
979 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
980 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
984 * @brief Selects the TIM Output Compare Mode.
985 * @note This function disables the selected channel before changing the Output
986 * Compare Mode. If needed, user has to enable this channel using
987 * TIM_CCxCmd() and TIM_CCxNCmd() functions.
988 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
989 * @param TIM_Channel: specifies the TIM Channel
990 * This parameter can be one of the following values:
991 * @arg TIM_Channel_1: TIM Channel 1
992 * @arg TIM_Channel_2: TIM Channel 2
993 * @arg TIM_Channel_3: TIM Channel 3
994 * @arg TIM_Channel_4: TIM Channel 4
995 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
996 * This parameter can be one of the following values:
997 * @arg TIM_OCMode_Timing
998 * @arg TIM_OCMode_Active
999 * @arg TIM_OCMode_Toggle
1000 * @arg TIM_OCMode_PWM1
1001 * @arg TIM_OCMode_PWM2
1002 * @arg TIM_ForcedAction_Active
1003 * @arg TIM_ForcedAction_InActive
1006 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
1011 /* Check the parameters */
1012 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1013 assert_param(IS_TIM_CHANNEL(TIM_Channel));
1014 assert_param(IS_TIM_OCM(TIM_OCMode));
1016 tmp = (uint32_t) TIMx;
1019 tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
1021 /* Disable the Channel: Reset the CCxE Bit */
1022 TIMx->CCER &= (uint16_t) ~tmp1;
1024 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
1026 tmp += (TIM_Channel>>1);
1028 /* Reset the OCxM bits in the CCMRx register */
1029 *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
1031 /* Configure the OCxM bits in the CCMRx register */
1032 *(__IO uint32_t *) tmp |= TIM_OCMode;
1036 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
1038 /* Reset the OCxM bits in the CCMRx register */
1039 *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
1041 /* Configure the OCxM bits in the CCMRx register */
1042 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
1047 * @brief Sets the TIMx Capture Compare1 Register value
1048 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1049 * @param Compare1: specifies the Capture Compare1 register new value.
1052 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
1054 /* Check the parameters */
1055 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1057 /* Set the Capture Compare1 Register value */
1058 TIMx->CCR1 = Compare1;
1062 * @brief Sets the TIMx Capture Compare2 Register value
1063 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1065 * @param Compare2: specifies the Capture Compare2 register new value.
1068 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
1070 /* Check the parameters */
1071 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1073 /* Set the Capture Compare2 Register value */
1074 TIMx->CCR2 = Compare2;
1078 * @brief Sets the TIMx Capture Compare3 Register value
1079 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1080 * @param Compare3: specifies the Capture Compare3 register new value.
1083 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
1085 /* Check the parameters */
1086 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1088 /* Set the Capture Compare3 Register value */
1089 TIMx->CCR3 = Compare3;
1093 * @brief Sets the TIMx Capture Compare4 Register value
1094 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1095 * @param Compare4: specifies the Capture Compare4 register new value.
1098 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
1100 /* Check the parameters */
1101 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1103 /* Set the Capture Compare4 Register value */
1104 TIMx->CCR4 = Compare4;
1108 * @brief Forces the TIMx output 1 waveform to active or inactive level.
1109 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1110 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1111 * This parameter can be one of the following values:
1112 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
1113 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
1116 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1118 uint16_t tmpccmr1 = 0;
1120 /* Check the parameters */
1121 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1122 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1123 tmpccmr1 = TIMx->CCMR1;
1125 /* Reset the OC1M Bits */
1126 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
1128 /* Configure The Forced output Mode */
1129 tmpccmr1 |= TIM_ForcedAction;
1131 /* Write to TIMx CCMR1 register */
1132 TIMx->CCMR1 = tmpccmr1;
1136 * @brief Forces the TIMx output 2 waveform to active or inactive level.
1137 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1139 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1140 * This parameter can be one of the following values:
1141 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
1142 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
1145 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1147 uint16_t tmpccmr1 = 0;
1149 /* Check the parameters */
1150 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1151 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1152 tmpccmr1 = TIMx->CCMR1;
1154 /* Reset the OC2M Bits */
1155 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
1157 /* Configure The Forced output Mode */
1158 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
1160 /* Write to TIMx CCMR1 register */
1161 TIMx->CCMR1 = tmpccmr1;
1165 * @brief Forces the TIMx output 3 waveform to active or inactive level.
1166 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1167 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1168 * This parameter can be one of the following values:
1169 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
1170 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
1173 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1175 uint16_t tmpccmr2 = 0;
1177 /* Check the parameters */
1178 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1179 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1181 tmpccmr2 = TIMx->CCMR2;
1183 /* Reset the OC1M Bits */
1184 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
1186 /* Configure The Forced output Mode */
1187 tmpccmr2 |= TIM_ForcedAction;
1189 /* Write to TIMx CCMR2 register */
1190 TIMx->CCMR2 = tmpccmr2;
1194 * @brief Forces the TIMx output 4 waveform to active or inactive level.
1195 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1196 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
1197 * This parameter can be one of the following values:
1198 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
1199 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
1202 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
1204 uint16_t tmpccmr2 = 0;
1206 /* Check the parameters */
1207 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1208 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
1209 tmpccmr2 = TIMx->CCMR2;
1211 /* Reset the OC2M Bits */
1212 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
1214 /* Configure The Forced output Mode */
1215 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
1217 /* Write to TIMx CCMR2 register */
1218 TIMx->CCMR2 = tmpccmr2;
1222 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
1223 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1224 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1225 * This parameter can be one of the following values:
1226 * @arg TIM_OCPreload_Enable
1227 * @arg TIM_OCPreload_Disable
1230 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1232 uint16_t tmpccmr1 = 0;
1234 /* Check the parameters */
1235 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1236 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1238 tmpccmr1 = TIMx->CCMR1;
1240 /* Reset the OC1PE Bit */
1241 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
1243 /* Enable or Disable the Output Compare Preload feature */
1244 tmpccmr1 |= TIM_OCPreload;
1246 /* Write to TIMx CCMR1 register */
1247 TIMx->CCMR1 = tmpccmr1;
1251 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
1252 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1254 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1255 * This parameter can be one of the following values:
1256 * @arg TIM_OCPreload_Enable
1257 * @arg TIM_OCPreload_Disable
1260 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1262 uint16_t tmpccmr1 = 0;
1264 /* Check the parameters */
1265 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1266 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1268 tmpccmr1 = TIMx->CCMR1;
1270 /* Reset the OC2PE Bit */
1271 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
1273 /* Enable or Disable the Output Compare Preload feature */
1274 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
1276 /* Write to TIMx CCMR1 register */
1277 TIMx->CCMR1 = tmpccmr1;
1281 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
1282 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1283 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1284 * This parameter can be one of the following values:
1285 * @arg TIM_OCPreload_Enable
1286 * @arg TIM_OCPreload_Disable
1289 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1291 uint16_t tmpccmr2 = 0;
1293 /* Check the parameters */
1294 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1295 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1297 tmpccmr2 = TIMx->CCMR2;
1299 /* Reset the OC3PE Bit */
1300 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
1302 /* Enable or Disable the Output Compare Preload feature */
1303 tmpccmr2 |= TIM_OCPreload;
1305 /* Write to TIMx CCMR2 register */
1306 TIMx->CCMR2 = tmpccmr2;
1310 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
1311 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1312 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
1313 * This parameter can be one of the following values:
1314 * @arg TIM_OCPreload_Enable
1315 * @arg TIM_OCPreload_Disable
1318 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
1320 uint16_t tmpccmr2 = 0;
1322 /* Check the parameters */
1323 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1324 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
1326 tmpccmr2 = TIMx->CCMR2;
1328 /* Reset the OC4PE Bit */
1329 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
1331 /* Enable or Disable the Output Compare Preload feature */
1332 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
1334 /* Write to TIMx CCMR2 register */
1335 TIMx->CCMR2 = tmpccmr2;
1339 * @brief Configures the TIMx Output Compare 1 Fast feature.
1340 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1341 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1342 * This parameter can be one of the following values:
1343 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1344 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1347 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1349 uint16_t tmpccmr1 = 0;
1351 /* Check the parameters */
1352 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1353 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1355 /* Get the TIMx CCMR1 register value */
1356 tmpccmr1 = TIMx->CCMR1;
1358 /* Reset the OC1FE Bit */
1359 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
1361 /* Enable or Disable the Output Compare Fast Bit */
1362 tmpccmr1 |= TIM_OCFast;
1364 /* Write to TIMx CCMR1 */
1365 TIMx->CCMR1 = tmpccmr1;
1369 * @brief Configures the TIMx Output Compare 2 Fast feature.
1370 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1372 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1373 * This parameter can be one of the following values:
1374 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1375 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1378 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1380 uint16_t tmpccmr1 = 0;
1382 /* Check the parameters */
1383 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1384 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1386 /* Get the TIMx CCMR1 register value */
1387 tmpccmr1 = TIMx->CCMR1;
1389 /* Reset the OC2FE Bit */
1390 tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
1392 /* Enable or Disable the Output Compare Fast Bit */
1393 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
1395 /* Write to TIMx CCMR1 */
1396 TIMx->CCMR1 = tmpccmr1;
1400 * @brief Configures the TIMx Output Compare 3 Fast feature.
1401 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1402 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1403 * This parameter can be one of the following values:
1404 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1405 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1408 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1410 uint16_t tmpccmr2 = 0;
1412 /* Check the parameters */
1413 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1414 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1416 /* Get the TIMx CCMR2 register value */
1417 tmpccmr2 = TIMx->CCMR2;
1419 /* Reset the OC3FE Bit */
1420 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
1422 /* Enable or Disable the Output Compare Fast Bit */
1423 tmpccmr2 |= TIM_OCFast;
1425 /* Write to TIMx CCMR2 */
1426 TIMx->CCMR2 = tmpccmr2;
1430 * @brief Configures the TIMx Output Compare 4 Fast feature.
1431 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1432 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
1433 * This parameter can be one of the following values:
1434 * @arg TIM_OCFast_Enable: TIM output compare fast enable
1435 * @arg TIM_OCFast_Disable: TIM output compare fast disable
1438 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
1440 uint16_t tmpccmr2 = 0;
1442 /* Check the parameters */
1443 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1444 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
1446 /* Get the TIMx CCMR2 register value */
1447 tmpccmr2 = TIMx->CCMR2;
1449 /* Reset the OC4FE Bit */
1450 tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
1452 /* Enable or Disable the Output Compare Fast Bit */
1453 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
1455 /* Write to TIMx CCMR2 */
1456 TIMx->CCMR2 = tmpccmr2;
1460 * @brief Clears or safeguards the OCREF1 signal on an external event
1461 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1462 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1463 * This parameter can be one of the following values:
1464 * @arg TIM_OCClear_Enable: TIM Output clear enable
1465 * @arg TIM_OCClear_Disable: TIM Output clear disable
1468 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1470 uint16_t tmpccmr1 = 0;
1472 /* Check the parameters */
1473 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1474 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1476 tmpccmr1 = TIMx->CCMR1;
1478 /* Reset the OC1CE Bit */
1479 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
1481 /* Enable or Disable the Output Compare Clear Bit */
1482 tmpccmr1 |= TIM_OCClear;
1484 /* Write to TIMx CCMR1 register */
1485 TIMx->CCMR1 = tmpccmr1;
1489 * @brief Clears or safeguards the OCREF2 signal on an external event
1490 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1492 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1493 * This parameter can be one of the following values:
1494 * @arg TIM_OCClear_Enable: TIM Output clear enable
1495 * @arg TIM_OCClear_Disable: TIM Output clear disable
1498 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1500 uint16_t tmpccmr1 = 0;
1502 /* Check the parameters */
1503 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1504 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1506 tmpccmr1 = TIMx->CCMR1;
1508 /* Reset the OC2CE Bit */
1509 tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
1511 /* Enable or Disable the Output Compare Clear Bit */
1512 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
1514 /* Write to TIMx CCMR1 register */
1515 TIMx->CCMR1 = tmpccmr1;
1519 * @brief Clears or safeguards the OCREF3 signal on an external event
1520 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1521 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1522 * This parameter can be one of the following values:
1523 * @arg TIM_OCClear_Enable: TIM Output clear enable
1524 * @arg TIM_OCClear_Disable: TIM Output clear disable
1527 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1529 uint16_t tmpccmr2 = 0;
1531 /* Check the parameters */
1532 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1533 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1535 tmpccmr2 = TIMx->CCMR2;
1537 /* Reset the OC3CE Bit */
1538 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
1540 /* Enable or Disable the Output Compare Clear Bit */
1541 tmpccmr2 |= TIM_OCClear;
1543 /* Write to TIMx CCMR2 register */
1544 TIMx->CCMR2 = tmpccmr2;
1548 * @brief Clears or safeguards the OCREF4 signal on an external event
1549 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1550 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
1551 * This parameter can be one of the following values:
1552 * @arg TIM_OCClear_Enable: TIM Output clear enable
1553 * @arg TIM_OCClear_Disable: TIM Output clear disable
1556 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
1558 uint16_t tmpccmr2 = 0;
1560 /* Check the parameters */
1561 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1562 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
1564 tmpccmr2 = TIMx->CCMR2;
1566 /* Reset the OC4CE Bit */
1567 tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
1569 /* Enable or Disable the Output Compare Clear Bit */
1570 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
1572 /* Write to TIMx CCMR2 register */
1573 TIMx->CCMR2 = tmpccmr2;
1577 * @brief Configures the TIMx channel 1 polarity.
1578 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1579 * @param TIM_OCPolarity: specifies the OC1 Polarity
1580 * This parameter can be one of the following values:
1581 * @arg TIM_OCPolarity_High: Output Compare active high
1582 * @arg TIM_OCPolarity_Low: Output Compare active low
1585 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1587 uint16_t tmpccer = 0;
1589 /* Check the parameters */
1590 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1591 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1593 tmpccer = TIMx->CCER;
1595 /* Set or Reset the CC1P Bit */
1596 tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
1597 tmpccer |= TIM_OCPolarity;
1599 /* Write to TIMx CCER register */
1600 TIMx->CCER = tmpccer;
1604 * @brief Configures the TIMx Channel 1N polarity.
1605 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1606 * @param TIM_OCNPolarity: specifies the OC1N Polarity
1607 * This parameter can be one of the following values:
1608 * @arg TIM_OCNPolarity_High: Output Compare active high
1609 * @arg TIM_OCNPolarity_Low: Output Compare active low
1612 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1614 uint16_t tmpccer = 0;
1615 /* Check the parameters */
1616 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
1617 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1619 tmpccer = TIMx->CCER;
1621 /* Set or Reset the CC1NP Bit */
1622 tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
1623 tmpccer |= TIM_OCNPolarity;
1625 /* Write to TIMx CCER register */
1626 TIMx->CCER = tmpccer;
1630 * @brief Configures the TIMx channel 2 polarity.
1631 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
1633 * @param TIM_OCPolarity: specifies the OC2 Polarity
1634 * This parameter can be one of the following values:
1635 * @arg TIM_OCPolarity_High: Output Compare active high
1636 * @arg TIM_OCPolarity_Low: Output Compare active low
1639 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1641 uint16_t tmpccer = 0;
1643 /* Check the parameters */
1644 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1645 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1647 tmpccer = TIMx->CCER;
1649 /* Set or Reset the CC2P Bit */
1650 tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
1651 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
1653 /* Write to TIMx CCER register */
1654 TIMx->CCER = tmpccer;
1658 * @brief Configures the TIMx Channel 2N polarity.
1659 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1660 * @param TIM_OCNPolarity: specifies the OC2N Polarity
1661 * This parameter can be one of the following values:
1662 * @arg TIM_OCNPolarity_High: Output Compare active high
1663 * @arg TIM_OCNPolarity_Low: Output Compare active low
1666 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1668 uint16_t tmpccer = 0;
1670 /* Check the parameters */
1671 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
1672 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1674 tmpccer = TIMx->CCER;
1676 /* Set or Reset the CC2NP Bit */
1677 tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
1678 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
1680 /* Write to TIMx CCER register */
1681 TIMx->CCER = tmpccer;
1685 * @brief Configures the TIMx channel 3 polarity.
1686 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1687 * @param TIM_OCPolarity: specifies the OC3 Polarity
1688 * This parameter can be one of the following values:
1689 * @arg TIM_OCPolarity_High: Output Compare active high
1690 * @arg TIM_OCPolarity_Low: Output Compare active low
1693 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1695 uint16_t tmpccer = 0;
1697 /* Check the parameters */
1698 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1699 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1701 tmpccer = TIMx->CCER;
1703 /* Set or Reset the CC3P Bit */
1704 tmpccer &= (uint16_t)~TIM_CCER_CC3P;
1705 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
1707 /* Write to TIMx CCER register */
1708 TIMx->CCER = tmpccer;
1712 * @brief Configures the TIMx Channel 3N polarity.
1713 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1714 * @param TIM_OCNPolarity: specifies the OC3N Polarity
1715 * This parameter can be one of the following values:
1716 * @arg TIM_OCNPolarity_High: Output Compare active high
1717 * @arg TIM_OCNPolarity_Low: Output Compare active low
1720 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
1722 uint16_t tmpccer = 0;
1724 /* Check the parameters */
1725 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
1726 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
1728 tmpccer = TIMx->CCER;
1730 /* Set or Reset the CC3NP Bit */
1731 tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
1732 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
1734 /* Write to TIMx CCER register */
1735 TIMx->CCER = tmpccer;
1739 * @brief Configures the TIMx channel 4 polarity.
1740 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
1741 * @param TIM_OCPolarity: specifies the OC4 Polarity
1742 * This parameter can be one of the following values:
1743 * @arg TIM_OCPolarity_High: Output Compare active high
1744 * @arg TIM_OCPolarity_Low: Output Compare active low
1747 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
1749 uint16_t tmpccer = 0;
1751 /* Check the parameters */
1752 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
1753 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
1755 tmpccer = TIMx->CCER;
1757 /* Set or Reset the CC4P Bit */
1758 tmpccer &= (uint16_t)~TIM_CCER_CC4P;
1759 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
1761 /* Write to TIMx CCER register */
1762 TIMx->CCER = tmpccer;
1766 * @brief Enables or disables the TIM Capture Compare Channel x.
1767 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1768 * @param TIM_Channel: specifies the TIM Channel
1769 * This parameter can be one of the following values:
1770 * @arg TIM_Channel_1: TIM Channel 1
1771 * @arg TIM_Channel_2: TIM Channel 2
1772 * @arg TIM_Channel_3: TIM Channel 3
1773 * @arg TIM_Channel_4: TIM Channel 4
1774 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
1775 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
1778 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
1782 /* Check the parameters */
1783 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1784 assert_param(IS_TIM_CHANNEL(TIM_Channel));
1785 assert_param(IS_TIM_CCX(TIM_CCx));
1787 tmp = CCER_CCE_SET << TIM_Channel;
1789 /* Reset the CCxE Bit */
1790 TIMx->CCER &= (uint16_t)~ tmp;
1792 /* Set or reset the CCxE Bit */
1793 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
1797 * @brief Enables or disables the TIM Capture Compare Channel xN.
1798 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
1799 * @param TIM_Channel: specifies the TIM Channel
1800 * This parameter can be one of the following values:
1801 * @arg TIM_Channel_1: TIM Channel 1
1802 * @arg TIM_Channel_2: TIM Channel 2
1803 * @arg TIM_Channel_3: TIM Channel 3
1804 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
1805 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
1808 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
1812 /* Check the parameters */
1813 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
1814 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
1815 assert_param(IS_TIM_CCXN(TIM_CCxN));
1817 tmp = CCER_CCNE_SET << TIM_Channel;
1819 /* Reset the CCxNE Bit */
1820 TIMx->CCER &= (uint16_t) ~tmp;
1822 /* Set or reset the CCxNE Bit */
1823 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
1829 /** @defgroup TIM_Group3 Input Capture management functions
1830 * @brief Input Capture management functions
1833 ===============================================================================
1834 Input Capture management functions
1835 ===============================================================================
1837 ===================================================================
1838 TIM Driver: how to use it in Input Capture Mode
1839 ===================================================================
1840 To use the Timer in Input Capture mode, the following steps are mandatory:
1842 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
1844 2. Configure the TIM pins by configuring the corresponding GPIO pins
1846 2. Configure the Time base unit as described in the first part of this driver,
1847 if needed, else the Timer will run with the default configuration:
1848 - Autoreload value = 0xFFFF
1849 - Prescaler value = 0x0000
1850 - Counter mode = Up counting
1851 - Clock Division = TIM_CKD_DIV1
1853 3. Fill the TIM_ICInitStruct with the desired parameters including:
1854 - TIM Channel: TIM_Channel
1855 - TIM Input Capture polarity: TIM_ICPolarity
1856 - TIM Input Capture selection: TIM_ICSelection
1857 - TIM Input Capture Prescaler: TIM_ICPrescaler
1858 - TIM Input CApture filter value: TIM_ICFilter
1860 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
1861 corresponding configuration and to measure only frequency or duty cycle of the input signal,
1863 Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
1864 corresponding configuration and to measure the frequency and the duty cycle of the input signal
1866 5. Enable the NVIC or the DMA to read the measured frequency.
1868 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
1869 using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
1871 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
1873 8. Use TIM_GetCapturex(TIMx); to read the captured value.
1875 Note1: All other functions can be used separately to modify, if needed,
1876 a specific feature of the Timer.
1883 * @brief Initializes the TIM peripheral according to the specified parameters
1884 * in the TIM_ICInitStruct.
1885 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
1886 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
1887 * the configuration information for the specified TIM peripheral.
1890 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
1892 /* Check the parameters */
1893 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
1894 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
1895 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
1896 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
1897 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
1899 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
1901 /* TI1 Configuration */
1902 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1903 TIM_ICInitStruct->TIM_ICSelection,
1904 TIM_ICInitStruct->TIM_ICFilter);
1905 /* Set the Input Capture Prescaler value */
1906 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1908 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
1910 /* TI2 Configuration */
1911 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1912 TIM_ICInitStruct->TIM_ICSelection,
1913 TIM_ICInitStruct->TIM_ICFilter);
1914 /* Set the Input Capture Prescaler value */
1915 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1917 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
1919 /* TI3 Configuration */
1920 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1921 TIM_ICInitStruct->TIM_ICSelection,
1922 TIM_ICInitStruct->TIM_ICFilter);
1923 /* Set the Input Capture Prescaler value */
1924 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1928 /* TI4 Configuration */
1929 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
1930 TIM_ICInitStruct->TIM_ICSelection,
1931 TIM_ICInitStruct->TIM_ICFilter);
1932 /* Set the Input Capture Prescaler value */
1933 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1938 * @brief Fills each TIM_ICInitStruct member with its default value.
1939 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
1943 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
1945 /* Set the default configuration */
1946 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
1947 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
1948 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
1949 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
1950 TIM_ICInitStruct->TIM_ICFilter = 0x00;
1954 * @brief Configures the TIM peripheral according to the specified parameters
1955 * in the TIM_ICInitStruct to measure an external PWM signal.
1956 * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM
1958 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
1959 * the configuration information for the specified TIM peripheral.
1962 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
1964 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
1965 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
1967 /* Check the parameters */
1968 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
1970 /* Select the Opposite Input Polarity */
1971 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
1973 icoppositepolarity = TIM_ICPolarity_Falling;
1977 icoppositepolarity = TIM_ICPolarity_Rising;
1979 /* Select the Opposite Input */
1980 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
1982 icoppositeselection = TIM_ICSelection_IndirectTI;
1986 icoppositeselection = TIM_ICSelection_DirectTI;
1988 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
1990 /* TI1 Configuration */
1991 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
1992 TIM_ICInitStruct->TIM_ICFilter);
1993 /* Set the Input Capture Prescaler value */
1994 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
1995 /* TI2 Configuration */
1996 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
1997 /* Set the Input Capture Prescaler value */
1998 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2002 /* TI2 Configuration */
2003 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
2004 TIM_ICInitStruct->TIM_ICFilter);
2005 /* Set the Input Capture Prescaler value */
2006 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2007 /* TI1 Configuration */
2008 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
2009 /* Set the Input Capture Prescaler value */
2010 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
2015 * @brief Gets the TIMx Input Capture 1 value.
2016 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
2017 * @retval Capture Compare 1 Register value.
2019 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
2021 /* Check the parameters */
2022 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
2024 /* Get the Capture 1 Register value */
2029 * @brief Gets the TIMx Input Capture 2 value.
2030 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
2032 * @retval Capture Compare 2 Register value.
2034 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
2036 /* Check the parameters */
2037 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2039 /* Get the Capture 2 Register value */
2044 * @brief Gets the TIMx Input Capture 3 value.
2045 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2046 * @retval Capture Compare 3 Register value.
2048 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
2050 /* Check the parameters */
2051 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2053 /* Get the Capture 3 Register value */
2058 * @brief Gets the TIMx Input Capture 4 value.
2059 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2060 * @retval Capture Compare 4 Register value.
2062 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
2064 /* Check the parameters */
2065 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2067 /* Get the Capture 4 Register value */
2072 * @brief Sets the TIMx Input Capture 1 prescaler.
2073 * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
2074 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
2075 * This parameter can be one of the following values:
2076 * @arg TIM_ICPSC_DIV1: no prescaler
2077 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2078 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2079 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2082 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2084 /* Check the parameters */
2085 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
2086 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2088 /* Reset the IC1PSC Bits */
2089 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
2091 /* Set the IC1PSC value */
2092 TIMx->CCMR1 |= TIM_ICPSC;
2096 * @brief Sets the TIMx Input Capture 2 prescaler.
2097 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
2099 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
2100 * This parameter can be one of the following values:
2101 * @arg TIM_ICPSC_DIV1: no prescaler
2102 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2103 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2104 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2107 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2109 /* Check the parameters */
2110 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2111 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2113 /* Reset the IC2PSC Bits */
2114 TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
2116 /* Set the IC2PSC value */
2117 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
2121 * @brief Sets the TIMx Input Capture 3 prescaler.
2122 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2123 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
2124 * This parameter can be one of the following values:
2125 * @arg TIM_ICPSC_DIV1: no prescaler
2126 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2127 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2128 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2131 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2133 /* Check the parameters */
2134 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2135 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2137 /* Reset the IC3PSC Bits */
2138 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
2140 /* Set the IC3PSC value */
2141 TIMx->CCMR2 |= TIM_ICPSC;
2145 * @brief Sets the TIMx Input Capture 4 prescaler.
2146 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2147 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
2148 * This parameter can be one of the following values:
2149 * @arg TIM_ICPSC_DIV1: no prescaler
2150 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
2151 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
2152 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
2155 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
2157 /* Check the parameters */
2158 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2159 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
2161 /* Reset the IC4PSC Bits */
2162 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
2164 /* Set the IC4PSC value */
2165 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
2171 /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
2172 * @brief Advanced-control timers (TIM1 and TIM8) specific features
2175 ===============================================================================
2176 Advanced-control timers (TIM1 and TIM8) specific features
2177 ===============================================================================
2179 ===================================================================
2180 TIM Driver: how to use the Break feature
2181 ===================================================================
2182 After configuring the Timer channel(s) in the appropriate Output Compare mode:
2184 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
2185 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
2186 AOE(automatic output enable).
2188 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
2190 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
2192 4. Once the break even occurs, the Timer's output signals are put in reset
2193 state or in a known state (according to the configuration made in
2194 TIM_BDTRConfig() function).
2201 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2202 * and the AOE(automatic output enable).
2203 * @param TIMx: where x can be 1 or 8 to select the TIM
2204 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
2205 * contains the BDTR Register configuration information for the TIM peripheral.
2208 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
2210 /* Check the parameters */
2211 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
2212 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
2213 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
2214 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
2215 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
2216 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
2217 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
2219 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2220 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2221 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
2222 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
2223 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
2224 TIM_BDTRInitStruct->TIM_AutomaticOutput;
2228 * @brief Fills each TIM_BDTRInitStruct member with its default value.
2229 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
2230 * will be initialized.
2233 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
2235 /* Set the default configuration */
2236 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
2237 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
2238 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
2239 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
2240 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
2241 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
2242 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
2246 * @brief Enables or disables the TIM peripheral Main Outputs.
2247 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
2248 * @param NewState: new state of the TIM peripheral Main Outputs.
2249 * This parameter can be: ENABLE or DISABLE.
2252 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
2254 /* Check the parameters */
2255 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
2256 assert_param(IS_FUNCTIONAL_STATE(NewState));
2258 if (NewState != DISABLE)
2260 /* Enable the TIM Main Output */
2261 TIMx->BDTR |= TIM_BDTR_MOE;
2265 /* Disable the TIM Main Output */
2266 TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
2271 * @brief Selects the TIM peripheral Commutation event.
2272 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
2273 * @param NewState: new state of the Commutation event.
2274 * This parameter can be: ENABLE or DISABLE.
2277 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
2279 /* Check the parameters */
2280 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
2281 assert_param(IS_FUNCTIONAL_STATE(NewState));
2283 if (NewState != DISABLE)
2285 /* Set the COM Bit */
2286 TIMx->CR2 |= TIM_CR2_CCUS;
2290 /* Reset the COM Bit */
2291 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
2296 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
2297 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
2298 * @param NewState: new state of the Capture Compare Preload Control bit
2299 * This parameter can be: ENABLE or DISABLE.
2302 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
2304 /* Check the parameters */
2305 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
2306 assert_param(IS_FUNCTIONAL_STATE(NewState));
2307 if (NewState != DISABLE)
2309 /* Set the CCPC Bit */
2310 TIMx->CR2 |= TIM_CR2_CCPC;
2314 /* Reset the CCPC Bit */
2315 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
2322 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions
2323 * @brief Interrupts, DMA and flags management functions
2326 ===============================================================================
2327 Interrupts, DMA and flags management functions
2328 ===============================================================================
2335 * @brief Enables or disables the specified TIM interrupts.
2336 * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral.
2337 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
2338 * This parameter can be any combination of the following values:
2339 * @arg TIM_IT_Update: TIM update Interrupt source
2340 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2341 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2342 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2343 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2344 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2345 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2346 * @arg TIM_IT_Break: TIM Break Interrupt source
2348 * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
2349 * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
2350 * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
2351 * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
2352 * be used: TIM_IT_Update or TIM_IT_CC1
2353 * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8
2355 * @param NewState: new state of the TIM interrupts.
2356 * This parameter can be: ENABLE or DISABLE.
2359 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
2361 /* Check the parameters */
2362 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2363 assert_param(IS_TIM_IT(TIM_IT));
2364 assert_param(IS_FUNCTIONAL_STATE(NewState));
2366 if (NewState != DISABLE)
2368 /* Enable the Interrupt sources */
2369 TIMx->DIER |= TIM_IT;
2373 /* Disable the Interrupt sources */
2374 TIMx->DIER &= (uint16_t)~TIM_IT;
2379 * @brief Configures the TIMx event to be generate by software.
2380 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
2381 * @param TIM_EventSource: specifies the event source.
2382 * This parameter can be one or more of the following values:
2383 * @arg TIM_EventSource_Update: Timer update Event source
2384 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
2385 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
2386 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
2387 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
2388 * @arg TIM_EventSource_COM: Timer COM event source
2389 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
2390 * @arg TIM_EventSource_Break: Timer Break event source
2392 * @note TIM6 and TIM7 can only generate an update event.
2393 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
2397 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
2399 /* Check the parameters */
2400 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2401 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
2403 /* Set the event sources */
2404 TIMx->EGR = TIM_EventSource;
2408 * @brief Checks whether the specified TIM flag is set or not.
2409 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
2410 * @param TIM_FLAG: specifies the flag to check.
2411 * This parameter can be one of the following values:
2412 * @arg TIM_FLAG_Update: TIM update Flag
2413 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
2414 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
2415 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
2416 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
2417 * @arg TIM_FLAG_COM: TIM Commutation Flag
2418 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
2419 * @arg TIM_FLAG_Break: TIM Break Flag
2420 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
2421 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
2422 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
2423 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
2425 * @note TIM6 and TIM7 can have only one update flag.
2426 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
2428 * @retval The new state of TIM_FLAG (SET or RESET).
2430 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2432 ITStatus bitstatus = RESET;
2433 /* Check the parameters */
2434 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2435 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
2438 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
2450 * @brief Clears the TIMx's pending flags.
2451 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
2452 * @param TIM_FLAG: specifies the flag bit to clear.
2453 * This parameter can be any combination of the following values:
2454 * @arg TIM_FLAG_Update: TIM update Flag
2455 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
2456 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
2457 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
2458 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
2459 * @arg TIM_FLAG_COM: TIM Commutation Flag
2460 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
2461 * @arg TIM_FLAG_Break: TIM Break Flag
2462 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
2463 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
2464 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
2465 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
2467 * @note TIM6 and TIM7 can have only one update flag.
2468 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
2472 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
2474 /* Check the parameters */
2475 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2477 /* Clear the flags */
2478 TIMx->SR = (uint16_t)~TIM_FLAG;
2482 * @brief Checks whether the TIM interrupt has occurred or not.
2483 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
2484 * @param TIM_IT: specifies the TIM interrupt source to check.
2485 * This parameter can be one of the following values:
2486 * @arg TIM_IT_Update: TIM update Interrupt source
2487 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2488 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2489 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2490 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2491 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2492 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2493 * @arg TIM_IT_Break: TIM Break Interrupt source
2495 * @note TIM6 and TIM7 can generate only an update interrupt.
2496 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
2498 * @retval The new state of the TIM_IT(SET or RESET).
2500 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2502 ITStatus bitstatus = RESET;
2503 uint16_t itstatus = 0x0, itenable = 0x0;
2504 /* Check the parameters */
2505 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2506 assert_param(IS_TIM_GET_IT(TIM_IT));
2508 itstatus = TIMx->SR & TIM_IT;
2510 itenable = TIMx->DIER & TIM_IT;
2511 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
2523 * @brief Clears the TIMx's interrupt pending bits.
2524 * @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
2525 * @param TIM_IT: specifies the pending bit to clear.
2526 * This parameter can be any combination of the following values:
2527 * @arg TIM_IT_Update: TIM1 update Interrupt source
2528 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
2529 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
2530 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
2531 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
2532 * @arg TIM_IT_COM: TIM Commutation Interrupt source
2533 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
2534 * @arg TIM_IT_Break: TIM Break Interrupt source
2536 * @note TIM6 and TIM7 can generate only an update interrupt.
2537 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
2541 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
2543 /* Check the parameters */
2544 assert_param(IS_TIM_ALL_PERIPH(TIMx));
2546 /* Clear the IT pending Bit */
2547 TIMx->SR = (uint16_t)~TIM_IT;
2551 * @brief Configures the TIMx's DMA interface.
2552 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2553 * @param TIM_DMABase: DMA Base address.
2554 * This parameter can be one of the following values:
2555 * @arg TIM_DMABase_CR1
2556 * @arg TIM_DMABase_CR2
2557 * @arg TIM_DMABase_SMCR
2558 * @arg TIM_DMABase_DIER
2559 * @arg TIM1_DMABase_SR
2560 * @arg TIM_DMABase_EGR
2561 * @arg TIM_DMABase_CCMR1
2562 * @arg TIM_DMABase_CCMR2
2563 * @arg TIM_DMABase_CCER
2564 * @arg TIM_DMABase_CNT
2565 * @arg TIM_DMABase_PSC
2566 * @arg TIM_DMABase_ARR
2567 * @arg TIM_DMABase_RCR
2568 * @arg TIM_DMABase_CCR1
2569 * @arg TIM_DMABase_CCR2
2570 * @arg TIM_DMABase_CCR3
2571 * @arg TIM_DMABase_CCR4
2572 * @arg TIM_DMABase_BDTR
2573 * @arg TIM_DMABase_DCR
2574 * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
2575 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
2578 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
2580 /* Check the parameters */
2581 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2582 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
2583 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
2585 /* Set the DMA Base and the DMA Burst Length */
2586 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
2590 * @brief Enables or disables the TIMx's DMA Requests.
2591 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
2592 * @param TIM_DMASource: specifies the DMA Request sources.
2593 * This parameter can be any combination of the following values:
2594 * @arg TIM_DMA_Update: TIM update Interrupt source
2595 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
2596 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
2597 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
2598 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
2599 * @arg TIM_DMA_COM: TIM Commutation DMA source
2600 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
2601 * @param NewState: new state of the DMA Request sources.
2602 * This parameter can be: ENABLE or DISABLE.
2605 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
2607 /* Check the parameters */
2608 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
2609 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
2610 assert_param(IS_FUNCTIONAL_STATE(NewState));
2612 if (NewState != DISABLE)
2614 /* Enable the DMA sources */
2615 TIMx->DIER |= TIM_DMASource;
2619 /* Disable the DMA sources */
2620 TIMx->DIER &= (uint16_t)~TIM_DMASource;
2625 * @brief Selects the TIMx peripheral Capture Compare DMA source.
2626 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2627 * @param NewState: new state of the Capture Compare DMA source
2628 * This parameter can be: ENABLE or DISABLE.
2631 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
2633 /* Check the parameters */
2634 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2635 assert_param(IS_FUNCTIONAL_STATE(NewState));
2637 if (NewState != DISABLE)
2639 /* Set the CCDS Bit */
2640 TIMx->CR2 |= TIM_CR2_CCDS;
2644 /* Reset the CCDS Bit */
2645 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
2652 /** @defgroup TIM_Group6 Clocks management functions
2653 * @brief Clocks management functions
2656 ===============================================================================
2657 Clocks management functions
2658 ===============================================================================
2665 * @brief Configures the TIMx internal Clock
2666 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
2670 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
2672 /* Check the parameters */
2673 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2675 /* Disable slave mode to clock the prescaler directly with the internal clock */
2676 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
2680 * @brief Configures the TIMx Internal Trigger as External Clock
2681 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
2683 * @param TIM_InputTriggerSource: Trigger source.
2684 * This parameter can be one of the following values:
2685 * @arg TIM_TS_ITR0: Internal Trigger 0
2686 * @arg TIM_TS_ITR1: Internal Trigger 1
2687 * @arg TIM_TS_ITR2: Internal Trigger 2
2688 * @arg TIM_TS_ITR3: Internal Trigger 3
2691 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
2693 /* Check the parameters */
2694 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2695 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
2697 /* Select the Internal Trigger */
2698 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
2700 /* Select the External clock mode1 */
2701 TIMx->SMCR |= TIM_SlaveMode_External1;
2705 * @brief Configures the TIMx Trigger as External Clock
2706 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
2707 * to select the TIM peripheral.
2708 * @param TIM_TIxExternalCLKSource: Trigger source.
2709 * This parameter can be one of the following values:
2710 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
2711 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
2712 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
2713 * @param TIM_ICPolarity: specifies the TIx Polarity.
2714 * This parameter can be one of the following values:
2715 * @arg TIM_ICPolarity_Rising
2716 * @arg TIM_ICPolarity_Falling
2717 * @param ICFilter: specifies the filter value.
2718 * This parameter must be a value between 0x0 and 0xF.
2721 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
2722 uint16_t TIM_ICPolarity, uint16_t ICFilter)
2724 /* Check the parameters */
2725 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
2726 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
2727 assert_param(IS_TIM_IC_FILTER(ICFilter));
2729 /* Configure the Timer Input Clock Source */
2730 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
2732 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
2736 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
2738 /* Select the Trigger source */
2739 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
2740 /* Select the External clock mode1 */
2741 TIMx->SMCR |= TIM_SlaveMode_External1;
2745 * @brief Configures the External clock Mode1
2746 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2747 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
2748 * This parameter can be one of the following values:
2749 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
2750 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
2751 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
2752 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
2753 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
2754 * This parameter can be one of the following values:
2755 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
2756 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
2757 * @param ExtTRGFilter: External Trigger Filter.
2758 * This parameter must be a value between 0x00 and 0x0F
2761 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
2762 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
2764 uint16_t tmpsmcr = 0;
2766 /* Check the parameters */
2767 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2768 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
2769 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
2770 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
2771 /* Configure the ETR Clock source */
2772 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
2774 /* Get the TIMx SMCR register value */
2775 tmpsmcr = TIMx->SMCR;
2777 /* Reset the SMS Bits */
2778 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
2780 /* Select the External clock mode1 */
2781 tmpsmcr |= TIM_SlaveMode_External1;
2783 /* Select the Trigger selection : ETRF */
2784 tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
2785 tmpsmcr |= TIM_TS_ETRF;
2787 /* Write to TIMx SMCR */
2788 TIMx->SMCR = tmpsmcr;
2792 * @brief Configures the External clock Mode2
2793 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2794 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
2795 * This parameter can be one of the following values:
2796 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
2797 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
2798 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
2799 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
2800 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
2801 * This parameter can be one of the following values:
2802 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
2803 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
2804 * @param ExtTRGFilter: External Trigger Filter.
2805 * This parameter must be a value between 0x00 and 0x0F
2808 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
2809 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
2811 /* Check the parameters */
2812 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
2813 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
2814 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
2815 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
2817 /* Configure the ETR Clock source */
2818 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
2820 /* Enable the External clock mode2 */
2821 TIMx->SMCR |= TIM_SMCR_ECE;
2827 /** @defgroup TIM_Group7 Synchronization management functions
2828 * @brief Synchronization management functions
2831 ===============================================================================
2832 Synchronization management functions
2833 ===============================================================================
2835 ===================================================================
2836 TIM Driver: how to use it in synchronization Mode
2837 ===================================================================
2838 Case of two/several Timers
2839 **************************
2840 1. Configure the Master Timers using the following functions:
2841 - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
2842 - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
2843 2. Configure the Slave Timers using the following functions:
2844 - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
2845 - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
2847 Case of Timers and external trigger(ETR pin)
2848 ********************************************
2849 1. Configure the External trigger using this function:
2850 - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
2851 uint16_t ExtTRGFilter);
2852 2. Configure the Slave Timers using the following functions:
2853 - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
2854 - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
2861 * @brief Selects the Input Trigger source
2862 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
2863 * to select the TIM peripheral.
2864 * @param TIM_InputTriggerSource: The Input Trigger source.
2865 * This parameter can be one of the following values:
2866 * @arg TIM_TS_ITR0: Internal Trigger 0
2867 * @arg TIM_TS_ITR1: Internal Trigger 1
2868 * @arg TIM_TS_ITR2: Internal Trigger 2
2869 * @arg TIM_TS_ITR3: Internal Trigger 3
2870 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
2871 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
2872 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
2873 * @arg TIM_TS_ETRF: External Trigger input
2876 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
2878 uint16_t tmpsmcr = 0;
2880 /* Check the parameters */
2881 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
2882 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
2884 /* Get the TIMx SMCR register value */
2885 tmpsmcr = TIMx->SMCR;
2887 /* Reset the TS Bits */
2888 tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
2890 /* Set the Input Trigger source */
2891 tmpsmcr |= TIM_InputTriggerSource;
2893 /* Write to TIMx SMCR */
2894 TIMx->SMCR = tmpsmcr;
2898 * @brief Selects the TIMx Trigger Output Mode.
2899 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
2901 * @param TIM_TRGOSource: specifies the Trigger Output source.
2902 * This parameter can be one of the following values:
2905 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
2906 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
2907 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
2909 * - For all TIMx except TIM6 and TIM7
2910 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
2911 * is to be set, as soon as a capture or compare match occurs(TRGO)
2912 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
2913 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
2914 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
2915 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
2919 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
2921 /* Check the parameters */
2922 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
2923 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
2925 /* Reset the MMS Bits */
2926 TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
2927 /* Select the TRGO source */
2928 TIMx->CR2 |= TIM_TRGOSource;
2932 * @brief Selects the TIMx Slave Mode.
2933 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
2934 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
2935 * This parameter can be one of the following values:
2936 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize
2937 * the counter and triggers an update of the registers
2938 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high
2939 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI
2940 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
2943 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
2945 /* Check the parameters */
2946 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2947 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
2949 /* Reset the SMS Bits */
2950 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
2952 /* Select the Slave Mode */
2953 TIMx->SMCR |= TIM_SlaveMode;
2957 * @brief Sets or Resets the TIMx Master/Slave Mode.
2958 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
2959 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
2960 * This parameter can be one of the following values:
2961 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
2962 * and its slaves (through TRGO)
2963 * @arg TIM_MasterSlaveMode_Disable: No action
2966 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
2968 /* Check the parameters */
2969 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
2970 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
2972 /* Reset the MSM Bit */
2973 TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
2975 /* Set or Reset the MSM Bit */
2976 TIMx->SMCR |= TIM_MasterSlaveMode;
2980 * @brief Configures the TIMx External Trigger (ETR).
2981 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
2982 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
2983 * This parameter can be one of the following values:
2984 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
2985 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
2986 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
2987 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
2988 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
2989 * This parameter can be one of the following values:
2990 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
2991 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
2992 * @param ExtTRGFilter: External Trigger Filter.
2993 * This parameter must be a value between 0x00 and 0x0F
2996 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
2997 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
2999 uint16_t tmpsmcr = 0;
3001 /* Check the parameters */
3002 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
3003 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
3004 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
3005 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
3007 tmpsmcr = TIMx->SMCR;
3009 /* Reset the ETR Bits */
3010 tmpsmcr &= SMCR_ETR_MASK;
3012 /* Set the Prescaler, the Filter value and the Polarity */
3013 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
3015 /* Write to TIMx SMCR */
3016 TIMx->SMCR = tmpsmcr;
3022 /** @defgroup TIM_Group8 Specific interface management functions
3023 * @brief Specific interface management functions
3026 ===============================================================================
3027 Specific interface management functions
3028 ===============================================================================
3035 * @brief Configures the TIMx Encoder Interface.
3036 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
3038 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
3039 * This parameter can be one of the following values:
3040 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
3041 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
3042 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
3043 * on the level of the other input.
3044 * @param TIM_IC1Polarity: specifies the IC1 Polarity
3045 * This parameter can be one of the following values:
3046 * @arg TIM_ICPolarity_Falling: IC Falling edge.
3047 * @arg TIM_ICPolarity_Rising: IC Rising edge.
3048 * @param TIM_IC2Polarity: specifies the IC2 Polarity
3049 * This parameter can be one of the following values:
3050 * @arg TIM_ICPolarity_Falling: IC Falling edge.
3051 * @arg TIM_ICPolarity_Rising: IC Rising edge.
3054 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
3055 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
3057 uint16_t tmpsmcr = 0;
3058 uint16_t tmpccmr1 = 0;
3059 uint16_t tmpccer = 0;
3061 /* Check the parameters */
3062 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
3063 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
3064 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
3065 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
3067 /* Get the TIMx SMCR register value */
3068 tmpsmcr = TIMx->SMCR;
3070 /* Get the TIMx CCMR1 register value */
3071 tmpccmr1 = TIMx->CCMR1;
3073 /* Get the TIMx CCER register value */
3074 tmpccer = TIMx->CCER;
3076 /* Set the encoder Mode */
3077 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
3078 tmpsmcr |= TIM_EncoderMode;
3080 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
3081 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
3082 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
3084 /* Set the TI1 and the TI2 Polarities */
3085 tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
3086 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
3088 /* Write to TIMx SMCR */
3089 TIMx->SMCR = tmpsmcr;
3091 /* Write to TIMx CCMR1 */
3092 TIMx->CCMR1 = tmpccmr1;
3094 /* Write to TIMx CCER */
3095 TIMx->CCER = tmpccer;
3099 * @brief Enables or disables the TIMx's Hall sensor interface.
3100 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
3102 * @param NewState: new state of the TIMx Hall sensor interface.
3103 * This parameter can be: ENABLE or DISABLE.
3106 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
3108 /* Check the parameters */
3109 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
3110 assert_param(IS_FUNCTIONAL_STATE(NewState));
3112 if (NewState != DISABLE)
3114 /* Set the TI1S Bit */
3115 TIMx->CR2 |= TIM_CR2_TI1S;
3119 /* Reset the TI1S Bit */
3120 TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
3127 /** @defgroup TIM_Group9 Specific remapping management function
3128 * @brief Specific remapping management function
3131 ===============================================================================
3132 Specific remapping management function
3133 ===============================================================================
3140 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
3141 * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
3142 * @param TIM_Remap: specifies the TIM input remapping source.
3143 * This parameter can be one of the following values:
3144 * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
3145 * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
3146 * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
3147 * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
3148 * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
3149 * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
3150 * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
3151 * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
3152 * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
3153 * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
3154 * (HSE divided by a programmable prescaler)
3157 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
3159 /* Check the parameters */
3160 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
3161 assert_param(IS_TIM_REMAP(TIM_Remap));
3163 /* Set the Timer remapping configuration */
3164 TIMx->OR = TIM_Remap;
3171 * @brief Configure the TI1 as Input.
3172 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14
3173 * to select the TIM peripheral.
3174 * @param TIM_ICPolarity : The Input Polarity.
3175 * This parameter can be one of the following values:
3176 * @arg TIM_ICPolarity_Rising
3177 * @arg TIM_ICPolarity_Falling
3178 * @arg TIM_ICPolarity_BothEdge
3179 * @param TIM_ICSelection: specifies the input to be used.
3180 * This parameter can be one of the following values:
3181 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
3182 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
3183 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
3184 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3185 * This parameter must be a value between 0x00 and 0x0F.
3188 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3189 uint16_t TIM_ICFilter)
3191 uint16_t tmpccmr1 = 0, tmpccer = 0;
3193 /* Disable the Channel 1: Reset the CC1E Bit */
3194 TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
3195 tmpccmr1 = TIMx->CCMR1;
3196 tmpccer = TIMx->CCER;
3198 /* Select the Input and set the filter */
3199 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
3200 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
3202 /* Select the Polarity and set the CC1E Bit */
3203 tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
3204 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
3206 /* Write to TIMx CCMR1 and CCER registers */
3207 TIMx->CCMR1 = tmpccmr1;
3208 TIMx->CCER = tmpccer;
3212 * @brief Configure the TI2 as Input.
3213 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM
3215 * @param TIM_ICPolarity : The Input Polarity.
3216 * This parameter can be one of the following values:
3217 * @arg TIM_ICPolarity_Rising
3218 * @arg TIM_ICPolarity_Falling
3219 * @arg TIM_ICPolarity_BothEdge
3220 * @param TIM_ICSelection: specifies the input to be used.
3221 * This parameter can be one of the following values:
3222 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
3223 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
3224 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
3225 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3226 * This parameter must be a value between 0x00 and 0x0F.
3229 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3230 uint16_t TIM_ICFilter)
3232 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
3234 /* Disable the Channel 2: Reset the CC2E Bit */
3235 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
3236 tmpccmr1 = TIMx->CCMR1;
3237 tmpccer = TIMx->CCER;
3238 tmp = (uint16_t)(TIM_ICPolarity << 4);
3240 /* Select the Input and set the filter */
3241 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
3242 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
3243 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
3245 /* Select the Polarity and set the CC2E Bit */
3246 tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
3247 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
3249 /* Write to TIMx CCMR1 and CCER registers */
3250 TIMx->CCMR1 = tmpccmr1 ;
3251 TIMx->CCER = tmpccer;
3255 * @brief Configure the TI3 as Input.
3256 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
3257 * @param TIM_ICPolarity : The Input Polarity.
3258 * This parameter can be one of the following values:
3259 * @arg TIM_ICPolarity_Rising
3260 * @arg TIM_ICPolarity_Falling
3261 * @arg TIM_ICPolarity_BothEdge
3262 * @param TIM_ICSelection: specifies the input to be used.
3263 * This parameter can be one of the following values:
3264 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
3265 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
3266 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
3267 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3268 * This parameter must be a value between 0x00 and 0x0F.
3271 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3272 uint16_t TIM_ICFilter)
3274 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3276 /* Disable the Channel 3: Reset the CC3E Bit */
3277 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
3278 tmpccmr2 = TIMx->CCMR2;
3279 tmpccer = TIMx->CCER;
3280 tmp = (uint16_t)(TIM_ICPolarity << 8);
3282 /* Select the Input and set the filter */
3283 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
3284 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
3286 /* Select the Polarity and set the CC3E Bit */
3287 tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
3288 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
3290 /* Write to TIMx CCMR2 and CCER registers */
3291 TIMx->CCMR2 = tmpccmr2;
3292 TIMx->CCER = tmpccer;
3296 * @brief Configure the TI4 as Input.
3297 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
3298 * @param TIM_ICPolarity : The Input Polarity.
3299 * This parameter can be one of the following values:
3300 * @arg TIM_ICPolarity_Rising
3301 * @arg TIM_ICPolarity_Falling
3302 * @arg TIM_ICPolarity_BothEdge
3303 * @param TIM_ICSelection: specifies the input to be used.
3304 * This parameter can be one of the following values:
3305 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
3306 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
3307 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
3308 * @param TIM_ICFilter: Specifies the Input Capture Filter.
3309 * This parameter must be a value between 0x00 and 0x0F.
3312 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
3313 uint16_t TIM_ICFilter)
3315 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
3317 /* Disable the Channel 4: Reset the CC4E Bit */
3318 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
3319 tmpccmr2 = TIMx->CCMR2;
3320 tmpccer = TIMx->CCER;
3321 tmp = (uint16_t)(TIM_ICPolarity << 12);
3323 /* Select the Input and set the filter */
3324 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
3325 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
3326 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
3328 /* Select the Polarity and set the CC4E Bit */
3329 tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
3330 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
3332 /* Write to TIMx CCMR2 and CCER registers */
3333 TIMx->CCMR2 = tmpccmr2;
3334 TIMx->CCER = tmpccer ;
3349 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/