2 ******************************************************************************
3 * @file stm32f4xx_pwr.c
4 * @author MCD Application Team
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Power Controller (PWR) peripheral:
9 * - Backup Domain Access
11 * - WakeUp pin configuration
12 * - Backup Regulator configuration
13 * - Performance Mode and FLASH Power Down configuration functions
14 * - Low Power modes configuration
17 ******************************************************************************
20 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
21 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
22 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
23 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
24 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
25 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
27 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
28 ******************************************************************************
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f4xx_pwr.h"
33 #include "stm32f4xx_rcc.h"
35 /** @addtogroup STM32F4xx_StdPeriph_Driver
40 * @brief PWR driver modules
44 /* Private typedef -----------------------------------------------------------*/
45 /* Private define ------------------------------------------------------------*/
46 /* --------- PWR registers bit address in the alias region ---------- */
47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
49 /* --- CR Register ---*/
51 /* Alias word address of DBP bit */
52 #define CR_OFFSET (PWR_OFFSET + 0x00)
53 #define DBP_BitNumber 0x08
54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
56 /* Alias word address of PVDE bit */
57 #define PVDE_BitNumber 0x04
58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
60 /* Alias word address of FPDS bit */
61 #define FPDS_BitNumber 0x09
62 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
64 /* Alias word address of PMODE bit */
65 #define PMODE_BitNumber 0x0E
66 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
69 /* --- CSR Register ---*/
71 /* Alias word address of EWUP bit */
72 #define CSR_OFFSET (PWR_OFFSET + 0x04)
73 #define EWUP_BitNumber 0x08
74 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
76 /* Alias word address of BRE bit */
77 #define BRE_BitNumber 0x09
78 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
80 /* ------------------ PWR registers bit mask ------------------------ */
82 /* CR register bit mask */
83 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
84 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
86 /* Private macro -------------------------------------------------------------*/
87 /* Private variables ---------------------------------------------------------*/
88 /* Private function prototypes -----------------------------------------------*/
89 /* Private functions ---------------------------------------------------------*/
91 /** @defgroup PWR_Private_Functions
95 /** @defgroup PWR_Group1 Backup Domain Access function
96 * @brief Backup Domain Access function
99 ===============================================================================
100 Backup Domain Access function
101 ===============================================================================
103 After reset, the backup domain (RTC registers, RTC backup data
104 registers and backup SRAM) is protected against possible unwanted
106 To enable access to the RTC Domain and RTC registers, proceed as follows:
107 - Enable the Power Controller (PWR) APB1 interface clock using the
108 RCC_APB1PeriphClockCmd() function.
109 - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
116 * @brief Deinitializes the PWR peripheral registers to their default reset values.
120 void PWR_DeInit(void)
122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
123 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
127 * @brief Enables or disables access to the backup domain (RTC registers, RTC
128 * backup data registers and backup SRAM).
129 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
130 * Backup Domain Access should be kept enabled.
131 * @param NewState: new state of the access to the backup domain.
132 * This parameter can be: ENABLE or DISABLE.
135 void PWR_BackupAccessCmd(FunctionalState NewState)
137 /* Check the parameters */
138 assert_param(IS_FUNCTIONAL_STATE(NewState));
140 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
147 /** @defgroup PWR_Group2 PVD configuration functions
148 * @brief PVD configuration functions
151 ===============================================================================
152 PVD configuration functions
153 ===============================================================================
155 - The PVD is used to monitor the VDD power supply by comparing it to a threshold
156 selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
157 - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
158 PVD threshold. This event is internally connected to the EXTI line16
159 and can generate an interrupt if enabled through the EXTI registers.
160 - The PVD is stopped in Standby mode.
167 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
168 * @param PWR_PVDLevel: specifies the PVD detection level
169 * This parameter can be one of the following values:
170 * @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
171 * @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
172 * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
173 * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
174 * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
175 * @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
176 * @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
177 * @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
178 * @note Refer to the electrical characteristics of you device datasheet for more details.
181 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
185 /* Check the parameters */
186 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
190 /* Clear PLS[7:5] bits */
191 tmpreg &= CR_PLS_MASK;
193 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
194 tmpreg |= PWR_PVDLevel;
196 /* Store the new value */
201 * @brief Enables or disables the Power Voltage Detector(PVD).
202 * @param NewState: new state of the PVD.
203 * This parameter can be: ENABLE or DISABLE.
206 void PWR_PVDCmd(FunctionalState NewState)
208 /* Check the parameters */
209 assert_param(IS_FUNCTIONAL_STATE(NewState));
211 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
218 /** @defgroup PWR_Group3 WakeUp pin configuration functions
219 * @brief WakeUp pin configuration functions
222 ===============================================================================
223 WakeUp pin configuration functions
224 ===============================================================================
226 - WakeUp pin is used to wakeup the system from Standby mode. This pin is
227 forced in input pull down configuration and is active on rising edges.
228 - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
235 * @brief Enables or disables the WakeUp Pin functionality.
236 * @param NewState: new state of the WakeUp Pin functionality.
237 * This parameter can be: ENABLE or DISABLE.
240 void PWR_WakeUpPinCmd(FunctionalState NewState)
242 /* Check the parameters */
243 assert_param(IS_FUNCTIONAL_STATE(NewState));
245 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
252 /** @defgroup PWR_Group4 Backup Regulator configuration functions
253 * @brief Backup Regulator configuration functions
256 ===============================================================================
257 Backup Regulator configuration functions
258 ===============================================================================
260 - The backup domain includes 4 Kbytes of backup SRAM accessible only from the
261 CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained
262 even in Standby or VBAT mode when the low power backup regulator is enabled.
263 It can be considered as an internal EEPROM when VBAT is always present.
264 You can use the PWR_BackupRegulatorCmd() function to enable the low power
265 backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
268 - When the backup domain is supplied by VDD (analog switch connected to VDD)
269 the backup SRAM is powered from VDD which replaces the VBAT power supply to
272 - The backup SRAM is not mass erased by an tamper event. It is read protected
273 to prevent confidential data, such as cryptographic private key, from being
274 accessed. The backup SRAM can be erased only through the Flash interface when
275 a protection level change from level 1 to level 0 is requested.
276 Refer to the description of Read protection (RDP) in the Flash programming manual.
283 * @brief Enables or disables the Backup Regulator.
284 * @param NewState: new state of the Backup Regulator.
285 * This parameter can be: ENABLE or DISABLE.
288 void PWR_BackupRegulatorCmd(FunctionalState NewState)
290 /* Check the parameters */
291 assert_param(IS_FUNCTIONAL_STATE(NewState));
293 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
300 /** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
301 * @brief Performance Mode and FLASH Power Down configuration functions
304 ===============================================================================
305 Performance Mode and FLASH Power Down configuration functions
306 ===============================================================================
308 - By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
309 function, the high performance mode is selected and the high voltage regulator
310 minimum value should be around 1.2V.
311 When reset, the low performance mode is selected and the low voltage regulator
312 minimum value should be around 1.08V.
314 - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
315 function, the Flash memory also enters power down mode when the device enters
316 Stop mode. When the Flash memory is in power down mode, an additional startup
317 delay is incurred when waking up from Stop mode.
324 * @brief Enables or disables the high performance mode.
325 * @param NewState: new state of the performance mode.
326 * This parameter can be: ENABLE or DISABLE.
329 void PWR_HighPerformanceModeCmd(FunctionalState NewState)
331 /* Check the parameters */
332 assert_param(IS_FUNCTIONAL_STATE(NewState));
334 *(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
338 * @brief Enables or disables the Flash Power Down in STOP mode.
339 * @param NewState: new state of the Flash power mode.
340 * This parameter can be: ENABLE or DISABLE.
343 void PWR_FlashPowerDownCmd(FunctionalState NewState)
345 /* Check the parameters */
346 assert_param(IS_FUNCTIONAL_STATE(NewState));
348 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
355 /** @defgroup PWR_Group6 Low Power modes configuration functions
356 * @brief Low Power modes configuration functions
359 ===============================================================================
360 Low Power modes configuration functions
361 ===============================================================================
363 The devices feature 3 low-power modes:
364 - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
365 - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
366 - Standby mode: 1.2V domain powered off.
371 - The Sleep mode is entered by using the __WFI() or __WFE() functions.
373 - Any peripheral interrupt acknowledged by the nested vectored interrupt
374 controller (NVIC) can wake up the device from Sleep mode.
378 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
379 and the HSE RC oscillators are disabled. Internal SRAM and register contents
381 The voltage regulator can be configured either in normal or low-power mode.
382 To minimize the consumption In Stop mode, FLASH can be powered off before
383 entering the Stop mode. It can be switched on again by software after exiting
384 the Stop mode using the PWR_FlashPowerDownCmd() function.
387 - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
388 function with regulator in LowPower or with Regulator ON.
390 - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
394 The Standby mode allows to achieve the lowest power consumption. It is based
395 on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
396 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
397 the HSE oscillator are also switched off. SRAM and register contents are lost
398 except for the RTC registers, RTC backup registers, backup SRAM and Standby
401 The voltage regulator is OFF.
404 - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
406 - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
407 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
409 Auto-wakeup (AWU) from low-power mode
410 =====================================
411 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
412 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
413 without depending on an external interrupt (Auto-wakeup mode).
415 - RTC auto-wakeup (AWU) from the Stop mode
416 ----------------------------------------
418 - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
419 - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
420 or Event modes) using the EXTI_Init() function.
421 - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
422 - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
423 and RTC_AlarmCmd() functions.
424 - To wake up from the Stop mode with an RTC Tamper or time stamp event, it
426 - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
427 or Event modes) using the EXTI_Init() function.
428 - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
430 - Configure the RTC to detect the tamper or time stamp event using the
431 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
433 - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
434 - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
435 or Event modes) using the EXTI_Init() function.
436 - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
437 - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
438 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
440 - RTC auto-wakeup (AWU) from the Standby mode
441 -------------------------------------------
442 - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
443 - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
444 - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
445 and RTC_AlarmCmd() functions.
446 - To wake up from the Standby mode with an RTC Tamper or time stamp event, it
448 - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
450 - Configure the RTC to detect the tamper or time stamp event using the
451 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
453 - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
454 - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
455 - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
456 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
463 * @brief Enters STOP mode.
465 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
466 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
467 * the HSI RC oscillator is selected as system clock.
468 * @note When the voltage regulator operates in low power mode, an additional
469 * startup delay is incurred when waking up from Stop mode.
470 * By keeping the internal regulator ON during Stop mode, the consumption
471 * is higher although the startup time is reduced.
473 * @param PWR_Regulator: specifies the regulator state in STOP mode.
474 * This parameter can be one of the following values:
475 * @arg PWR_Regulator_ON: STOP mode with regulator ON
476 * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
477 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
478 * This parameter can be one of the following values:
479 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
480 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
483 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
487 /* Check the parameters */
488 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
489 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
491 /* Select the regulator state in STOP mode ---------------------------------*/
493 /* Clear PDDS and LPDSR bits */
494 tmpreg &= CR_DS_MASK;
496 /* Set LPDSR bit according to PWR_Regulator value */
497 tmpreg |= PWR_Regulator;
499 /* Store the new value */
502 /* Set SLEEPDEEP bit of Cortex System Control Register */
503 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
505 /* Select STOP mode entry --------------------------------------------------*/
506 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
508 /* Request Wait For Interrupt */
513 /* Request Wait For Event */
516 /* Reset SLEEPDEEP bit of Cortex System Control Register */
517 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
521 * @brief Enters STANDBY mode.
522 * @note In Standby mode, all I/O pins are high impedance except for:
523 * - Reset pad (still available)
524 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
525 * Alarm out, or RTC clock calibration out.
526 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
527 * - WKUP pin 1 (PA0) if enabled.
531 void PWR_EnterSTANDBYMode(void)
533 /* Clear Wakeup flag */
534 PWR->CR |= PWR_CR_CWUF;
536 /* Select STANDBY mode */
537 PWR->CR |= PWR_CR_PDDS;
539 /* Set SLEEPDEEP bit of Cortex System Control Register */
540 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
542 /* This option is used to ensure that store operations are completed */
543 #if defined ( __CC_ARM )
546 /* Request Wait For Interrupt */
554 /** @defgroup PWR_Group7 Flags management functions
555 * @brief Flags management functions
558 ===============================================================================
559 Flags management functions
560 ===============================================================================
567 * @brief Checks whether the specified PWR flag is set or not.
568 * @param PWR_FLAG: specifies the flag to check.
569 * This parameter can be one of the following values:
570 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
571 * was received from the WKUP pin or from the RTC alarm (Alarm A
572 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
573 * An additional wakeup event is detected if the WKUP pin is enabled
574 * (by setting the EWUP bit) when the WKUP pin level is already high.
575 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
576 * resumed from StandBy mode.
577 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
578 * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
579 * For this reason, this bit is equal to 0 after Standby or reset
580 * until the PVDE bit is set.
581 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
582 * when the device wakes up from Standby mode or by a system reset
584 * @arg PWR_FLAG_REGRDY: Main regulator ready flag.
585 * @retval The new state of PWR_FLAG (SET or RESET).
587 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
589 FlagStatus bitstatus = RESET;
591 /* Check the parameters */
592 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
594 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
602 /* Return the flag status */
607 * @brief Clears the PWR's pending flags.
608 * @param PWR_FLAG: specifies the flag to clear.
609 * This parameter can be one of the following values:
610 * @arg PWR_FLAG_WU: Wake Up flag
611 * @arg PWR_FLAG_SB: StandBy flag
614 void PWR_ClearFlag(uint32_t PWR_FLAG)
616 /* Check the parameters */
617 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
619 PWR->CR |= PWR_FLAG << 2;
638 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/