2 ******************************************************************************
3 * @file stm32f4xx_sdio.h
4 * @author MCD Application Team
7 * @brief This file contains all the functions prototypes for the SDIO firmware
9 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_SDIO_H
25 #define __STM32F4xx_SDIO_H
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f4xx.h"
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
42 /* Exported types ------------------------------------------------------------*/
46 uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
47 This parameter can be a value of @ref SDIO_Clock_Edge */
49 uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
51 This parameter can be a value of @ref SDIO_Clock_Bypass */
53 uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
54 disabled when the bus is idle.
55 This parameter can be a value of @ref SDIO_Clock_Power_Save */
57 uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
58 This parameter can be a value of @ref SDIO_Bus_Wide */
60 uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
61 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
63 uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
64 This parameter can be a value between 0x00 and 0xFF. */
70 uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
71 to a card as part of a command message. If a command
72 contains an argument, it must be loaded into this register
73 before writing the command to the command register */
75 uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
77 uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
78 This parameter can be a value of @ref SDIO_Response_Type */
80 uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
81 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
83 uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
84 is enabled or disabled.
85 This parameter can be a value of @ref SDIO_CPSM_State */
86 } SDIO_CmdInitTypeDef;
90 uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
92 uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
94 uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
95 This parameter can be a value of @ref SDIO_Data_Block_Size */
97 uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
99 This parameter can be a value of @ref SDIO_Transfer_Direction */
101 uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
102 This parameter can be a value of @ref SDIO_Transfer_Type */
104 uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
105 is enabled or disabled.
106 This parameter can be a value of @ref SDIO_DPSM_State */
107 } SDIO_DataInitTypeDef;
110 /* Exported constants --------------------------------------------------------*/
112 /** @defgroup SDIO_Exported_Constants
116 /** @defgroup SDIO_Clock_Edge
120 #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
121 #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
122 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
123 ((EDGE) == SDIO_ClockEdge_Falling))
128 /** @defgroup SDIO_Clock_Bypass
132 #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
133 #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
134 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
135 ((BYPASS) == SDIO_ClockBypass_Enable))
140 /** @defgroup SDIO_Clock_Power_Save
144 #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
145 #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
146 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
147 ((SAVE) == SDIO_ClockPowerSave_Enable))
152 /** @defgroup SDIO_Bus_Wide
156 #define SDIO_BusWide_1b ((uint32_t)0x00000000)
157 #define SDIO_BusWide_4b ((uint32_t)0x00000800)
158 #define SDIO_BusWide_8b ((uint32_t)0x00001000)
159 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
160 ((WIDE) == SDIO_BusWide_8b))
166 /** @defgroup SDIO_Hardware_Flow_Control
170 #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
171 #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
172 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
173 ((CONTROL) == SDIO_HardwareFlowControl_Enable))
178 /** @defgroup SDIO_Power_State
182 #define SDIO_PowerState_OFF ((uint32_t)0x00000000)
183 #define SDIO_PowerState_ON ((uint32_t)0x00000003)
184 #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
190 /** @defgroup SDIO_Interrupt_sources
194 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
195 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
196 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
197 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
198 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
199 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
200 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
201 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
202 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
203 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
204 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
205 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
206 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
207 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
208 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
209 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
210 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
211 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
212 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
213 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
214 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
215 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
216 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
217 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
218 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
223 /** @defgroup SDIO_Command_Index
227 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
232 /** @defgroup SDIO_Response_Type
236 #define SDIO_Response_No ((uint32_t)0x00000000)
237 #define SDIO_Response_Short ((uint32_t)0x00000040)
238 #define SDIO_Response_Long ((uint32_t)0x000000C0)
239 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
240 ((RESPONSE) == SDIO_Response_Short) || \
241 ((RESPONSE) == SDIO_Response_Long))
246 /** @defgroup SDIO_Wait_Interrupt_State
250 #define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
251 #define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
252 #define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
253 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
254 ((WAIT) == SDIO_Wait_Pend))
259 /** @defgroup SDIO_CPSM_State
263 #define SDIO_CPSM_Disable ((uint32_t)0x00000000)
264 #define SDIO_CPSM_Enable ((uint32_t)0x00000400)
265 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
270 /** @defgroup SDIO_Response_Registers
274 #define SDIO_RESP1 ((uint32_t)0x00000000)
275 #define SDIO_RESP2 ((uint32_t)0x00000004)
276 #define SDIO_RESP3 ((uint32_t)0x00000008)
277 #define SDIO_RESP4 ((uint32_t)0x0000000C)
278 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
279 ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
284 /** @defgroup SDIO_Data_Length
288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
293 /** @defgroup SDIO_Data_Block_Size
297 #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
298 #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
299 #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
300 #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
301 #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
302 #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
303 #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
304 #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
305 #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
306 #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
307 #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
308 #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
309 #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
310 #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
311 #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
313 ((SIZE) == SDIO_DataBlockSize_2b) || \
314 ((SIZE) == SDIO_DataBlockSize_4b) || \
315 ((SIZE) == SDIO_DataBlockSize_8b) || \
316 ((SIZE) == SDIO_DataBlockSize_16b) || \
317 ((SIZE) == SDIO_DataBlockSize_32b) || \
318 ((SIZE) == SDIO_DataBlockSize_64b) || \
319 ((SIZE) == SDIO_DataBlockSize_128b) || \
320 ((SIZE) == SDIO_DataBlockSize_256b) || \
321 ((SIZE) == SDIO_DataBlockSize_512b) || \
322 ((SIZE) == SDIO_DataBlockSize_1024b) || \
323 ((SIZE) == SDIO_DataBlockSize_2048b) || \
324 ((SIZE) == SDIO_DataBlockSize_4096b) || \
325 ((SIZE) == SDIO_DataBlockSize_8192b) || \
326 ((SIZE) == SDIO_DataBlockSize_16384b))
331 /** @defgroup SDIO_Transfer_Direction
335 #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
336 #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
338 ((DIR) == SDIO_TransferDir_ToSDIO))
343 /** @defgroup SDIO_Transfer_Type
347 #define SDIO_TransferMode_Block ((uint32_t)0x00000000)
348 #define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
350 ((MODE) == SDIO_TransferMode_Block))
355 /** @defgroup SDIO_DPSM_State
359 #define SDIO_DPSM_Disable ((uint32_t)0x00000000)
360 #define SDIO_DPSM_Enable ((uint32_t)0x00000001)
361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
366 /** @defgroup SDIO_Flags
370 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
371 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
372 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
373 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
374 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
375 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
376 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
377 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
378 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
379 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
380 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
381 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
382 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
383 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
384 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
385 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
386 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
387 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
388 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
389 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
390 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
391 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
392 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
393 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
394 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
395 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
396 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
397 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
398 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
399 ((FLAG) == SDIO_FLAG_RXOVERR) || \
400 ((FLAG) == SDIO_FLAG_CMDREND) || \
401 ((FLAG) == SDIO_FLAG_CMDSENT) || \
402 ((FLAG) == SDIO_FLAG_DATAEND) || \
403 ((FLAG) == SDIO_FLAG_STBITERR) || \
404 ((FLAG) == SDIO_FLAG_DBCKEND) || \
405 ((FLAG) == SDIO_FLAG_CMDACT) || \
406 ((FLAG) == SDIO_FLAG_TXACT) || \
407 ((FLAG) == SDIO_FLAG_RXACT) || \
408 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
409 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
410 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
411 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
412 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
413 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
414 ((FLAG) == SDIO_FLAG_TXDAVL) || \
415 ((FLAG) == SDIO_FLAG_RXDAVL) || \
416 ((FLAG) == SDIO_FLAG_SDIOIT) || \
417 ((FLAG) == SDIO_FLAG_CEATAEND))
419 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
421 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
422 ((IT) == SDIO_IT_DCRCFAIL) || \
423 ((IT) == SDIO_IT_CTIMEOUT) || \
424 ((IT) == SDIO_IT_DTIMEOUT) || \
425 ((IT) == SDIO_IT_TXUNDERR) || \
426 ((IT) == SDIO_IT_RXOVERR) || \
427 ((IT) == SDIO_IT_CMDREND) || \
428 ((IT) == SDIO_IT_CMDSENT) || \
429 ((IT) == SDIO_IT_DATAEND) || \
430 ((IT) == SDIO_IT_STBITERR) || \
431 ((IT) == SDIO_IT_DBCKEND) || \
432 ((IT) == SDIO_IT_CMDACT) || \
433 ((IT) == SDIO_IT_TXACT) || \
434 ((IT) == SDIO_IT_RXACT) || \
435 ((IT) == SDIO_IT_TXFIFOHE) || \
436 ((IT) == SDIO_IT_RXFIFOHF) || \
437 ((IT) == SDIO_IT_TXFIFOF) || \
438 ((IT) == SDIO_IT_RXFIFOF) || \
439 ((IT) == SDIO_IT_TXFIFOE) || \
440 ((IT) == SDIO_IT_RXFIFOE) || \
441 ((IT) == SDIO_IT_TXDAVL) || \
442 ((IT) == SDIO_IT_RXDAVL) || \
443 ((IT) == SDIO_IT_SDIOIT) || \
444 ((IT) == SDIO_IT_CEATAEND))
446 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
452 /** @defgroup SDIO_Read_Wait_Mode
456 #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
457 #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
458 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
459 ((MODE) == SDIO_ReadWaitMode_DATA2))
468 /* Exported macro ------------------------------------------------------------*/
469 /* Exported functions --------------------------------------------------------*/
470 /* Function used to set the SDIO configuration to the default reset state ****/
471 void SDIO_DeInit(void);
473 /* Initialization and Configuration functions *********************************/
474 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
475 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
476 void SDIO_ClockCmd(FunctionalState NewState);
477 void SDIO_SetPowerState(uint32_t SDIO_PowerState);
478 uint32_t SDIO_GetPowerState(void);
480 /* Command path state machine (CPSM) management functions *********************/
481 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
482 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
483 uint8_t SDIO_GetCommandResponse(void);
484 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
486 /* Data path state machine (DPSM) management functions ************************/
487 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
488 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
489 uint32_t SDIO_GetDataCounter(void);
490 uint32_t SDIO_ReadData(void);
491 void SDIO_WriteData(uint32_t Data);
492 uint32_t SDIO_GetFIFOCount(void);
494 /* SDIO IO Cards mode management functions ************************************/
495 void SDIO_StartSDIOReadWait(FunctionalState NewState);
496 void SDIO_StopSDIOReadWait(FunctionalState NewState);
497 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
498 void SDIO_SetSDIOOperation(FunctionalState NewState);
499 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
501 /* CE-ATA mode management functions *******************************************/
502 void SDIO_CommandCompletionCmd(FunctionalState NewState);
503 void SDIO_CEATAITCmd(FunctionalState NewState);
504 void SDIO_SendCEATACmd(FunctionalState NewState);
506 /* DMA transfers management functions *****************************************/
507 void SDIO_DMACmd(FunctionalState NewState);
509 /* Interrupts and flags management functions **********************************/
510 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
511 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
512 void SDIO_ClearFlag(uint32_t SDIO_FLAG);
513 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
514 void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
520 #endif /* __STM32F4xx_SDIO_H */
530 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/