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   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_fsmc.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0RC1
   6   * @date    25-August-2011
   7   * @brief   This file contains all the functions prototypes for the FSMC firmware
   8   *          library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  15   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18   *
  19   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
  20   ******************************************************************************
  21   */
  22
  23 /* Define to prevent recursive inclusion -------------------------------------*/
  24 #ifndef __STM32F4xx_FSMC_H
  25 #define __STM32F4xx_FSMC_H
  26
  27 #ifdef __cplusplus
  28  extern "C" {
  29 #endif
  30
  31 /* Includes ------------------------------------------------------------------*/
  32 #include "stm32f4xx.h"
  33
  34 /** @addtogroup STM32F4xx_StdPeriph_Driver
  35   * @{
  36   */
  37
  38 /** @addtogroup FSMC
  39   * @{
  40   */
  41
  42 /* Exported types ------------------------------------------------------------*/
  43
  44 /**
  45   * @brief  Timing parameters For NOR/SRAM Banks
  46   */
  47 typedef struct
  48 {
  49   uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
  50                                              the duration of the address setup time.
  51                                              This parameter can be a value between 0 and 0xF.
  52                                              @note This parameter is not used with synchronous NOR Flash memories. */
  53
  54   uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
  55                                              the duration of the address hold time.
  56                                              This parameter can be a value between 0 and 0xF.
  57                                              @note This parameter is not used with synchronous NOR Flash memories.*/
  58
  59   uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
  60                                              the duration of the data setup time.
  61                                              This parameter can be a value between 0 and 0xFF.
  62                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
  63
  64   uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
  65                                              the duration of the bus turnaround.
  66                                              This parameter can be a value between 0 and 0xF.
  67                                              @note This parameter is only used for multiplexed NOR Flash memories. */
  68
  69   uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
  70                                              This parameter can be a value between 1 and 0xF.
  71                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
  72
  73   uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
  74                                              to the memory before getting the first data.
  75                                              The parameter value depends on the memory type as shown below:
  76                                               - It must be set to 0 in case of a CRAM
  77                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
  78                                               - It may assume a value between 0 and 0xF in NOR Flash memories
  79                                                 with synchronous burst mode enable */
  80
  81   uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode.
  82                                              This parameter can be a value of @ref FSMC_Access_Mode */
  83 }FSMC_NORSRAMTimingInitTypeDef;
  84
  85 /**
  86   * @brief  FSMC NOR/SRAM Init structure definition
  87   */
  88 typedef struct
  89 {
  90   uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
  91                                           This parameter can be a value of @ref FSMC_NORSRAM_Bank */
  92
  93   uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
  94                                           multiplexed on the databus or not.
  95                                           This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
  96
  97   uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
  98                                           the corresponding memory bank.
  99                                           This parameter can be a value of @ref FSMC_Memory_Type */
 100
 101   uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
 102                                           This parameter can be a value of @ref FSMC_Data_Width */
 103
 104   uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
 105                                           valid only with synchronous burst Flash memories.
 106                                           This parameter can be a value of @ref FSMC_Burst_Access_Mode */
 107
 108   uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
 109                                           valid only with asynchronous Flash memories.
 110                                           This parameter can be a value of @ref FSMC_AsynchronousWait */
 111
 112   uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
 113                                           the Flash memory in burst mode.
 114                                           This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
 115
 116   uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
 117                                           memory, valid only when accessing Flash memories in burst mode.
 118                                           This parameter can be a value of @ref FSMC_Wrap_Mode */
 119
 120   uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
 121                                           clock cycle before the wait state or during the wait state,
 122                                           valid only when accessing memories in burst mode.
 123                                           This parameter can be a value of @ref FSMC_Wait_Timing */
 124
 125   uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC.
 126                                           This parameter can be a value of @ref FSMC_Write_Operation */
 127
 128   uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
 129                                           signal, valid for Flash memory access in burst mode.
 130                                           This parameter can be a value of @ref FSMC_Wait_Signal */
 131
 132   uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
 133                                           This parameter can be a value of @ref FSMC_Extended_Mode */
 134
 135   uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
 136                                           This parameter can be a value of @ref FSMC_Write_Burst */
 137
 138   FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/
 139
 140   FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/
 141 }FSMC_NORSRAMInitTypeDef;
 142
 143 /**
 144   * @brief  Timing parameters For FSMC NAND and PCCARD Banks
 145   */
 146 typedef struct
 147 {
 148   uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
 149                                      the command assertion for NAND-Flash read or write access
 150                                      to common/Attribute or I/O memory space (depending on
 151                                      the memory space timing to be configured).
 152                                      This parameter can be a value between 0 and 0xFF.*/
 153
 154   uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
 155                                      command for NAND-Flash read or write access to
 156                                      common/Attribute or I/O memory space (depending on the
 157                                      memory space timing to be configured).
 158                                      This parameter can be a number between 0x00 and 0xFF */
 159
 160   uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
 161                                      (and data for write access) after the command deassertion
 162                                      for NAND-Flash read or write access to common/Attribute
 163                                      or I/O memory space (depending on the memory space timing
 164                                      to be configured).
 165                                      This parameter can be a number between 0x00 and 0xFF */
 166
 167   uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
 168                                      databus is kept in HiZ after the start of a NAND-Flash
 169                                      write access to common/Attribute or I/O memory space (depending
 170                                      on the memory space timing to be configured).
 171                                      This parameter can be a number between 0x00 and 0xFF */
 172 }FSMC_NAND_PCCARDTimingInitTypeDef;
 173
 174 /**
 175   * @brief  FSMC NAND Init structure definition
 176   */
 177 typedef struct
 178 {
 179   uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
 180                                       This parameter can be a value of @ref FSMC_NAND_Bank */
 181
 182   uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
 183                                        This parameter can be any value of @ref FSMC_Wait_feature */
 184
 185   uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
 186                                        This parameter can be any value of @ref FSMC_Data_Width */
 187
 188   uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
 189                                        This parameter can be any value of @ref FSMC_ECC */
 190
 191   uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
 192                                        This parameter can be any value of @ref FSMC_ECC_Page_Size */
 193
 194   uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
 195                                        delay between CLE low and RE low.
 196                                        This parameter can be a value between 0 and 0xFF. */
 197
 198   uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
 199                                        delay between ALE low and RE low.
 200                                        This parameter can be a number between 0x0 and 0xFF */
 201
 202   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */
 203
 204   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
 205 }FSMC_NANDInitTypeDef;
 206
 207 /**
 208   * @brief  FSMC PCCARD Init structure definition
 209   */
 210
 211 typedef struct
 212 {
 213   uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
 214                                     This parameter can be any value of @ref FSMC_Wait_feature */
 215
 216   uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
 217                                      delay between CLE low and RE low.
 218                                      This parameter can be a value between 0 and 0xFF. */
 219
 220   uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
 221                                      delay between ALE low and RE low.
 222                                      This parameter can be a number between 0x0 and 0xFF */
 223
 224
 225   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
 226
 227   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */
 228
 229   FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
 230 }FSMC_PCCARDInitTypeDef;
 231
 232 /* Exported constants --------------------------------------------------------*/
 233
 234 /** @defgroup FSMC_Exported_Constants
 235   * @{
 236   */
 237
 238 /** @defgroup FSMC_NORSRAM_Bank
 239   * @{
 240   */
 241 #define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
 242 #define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
 243 #define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
 244 #define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
 245 /**
 246   * @}
 247   */
 248
 249 /** @defgroup FSMC_NAND_Bank
 250   * @{
 251   */
 252 #define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
 253 #define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
 254 /**
 255   * @}
 256   */
 257
 258 /** @defgroup FSMC_PCCARD_Bank
 259   * @{
 260   */
 261 #define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
 262 /**
 263   * @}
 264   */
 265
 266 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
 267                                     ((BANK) == FSMC_Bank1_NORSRAM2) || \
 268                                     ((BANK) == FSMC_Bank1_NORSRAM3) || \
 269                                     ((BANK) == FSMC_Bank1_NORSRAM4))
 270
 271 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 272                                  ((BANK) == FSMC_Bank3_NAND))
 273
 274 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 275                                     ((BANK) == FSMC_Bank3_NAND) || \
 276                                     ((BANK) == FSMC_Bank4_PCCARD))
 277
 278 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
 279                                ((BANK) == FSMC_Bank3_NAND) || \
 280                                ((BANK) == FSMC_Bank4_PCCARD))
 281
 282 /** @defgroup FSMC_NOR_SRAM_Controller
 283   * @{
 284   */
 285
 286 /** @defgroup FSMC_Data_Address_Bus_Multiplexing
 287   * @{
 288   */
 289
 290 #define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
 291 #define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
 292 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
 293                           ((MUX) == FSMC_DataAddressMux_Enable))
 294 /**
 295   * @}
 296   */
 297
 298 /** @defgroup FSMC_Memory_Type
 299   * @{
 300   */
 301
 302 #define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
 303 #define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
 304 #define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
 305 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
 306                                 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
 307                                 ((MEMORY) == FSMC_MemoryType_NOR))
 308 /**
 309   * @}
 310   */
 311
 312 /** @defgroup FSMC_Data_Width
 313   * @{
 314   */
 315
 316 #define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
 317 #define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
 318 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
 319                                      ((WIDTH) == FSMC_MemoryDataWidth_16b))
 320 /**
 321   * @}
 322   */
 323
 324 /** @defgroup FSMC_Burst_Access_Mode
 325   * @{
 326   */
 327
 328 #define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000)
 329 #define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
 330 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
 331                                   ((STATE) == FSMC_BurstAccessMode_Enable))
 332 /**
 333   * @}
 334   */
 335
 336 /** @defgroup FSMC_AsynchronousWait
 337   * @{
 338   */
 339 #define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
 340 #define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
 341 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
 342                                  ((STATE) == FSMC_AsynchronousWait_Enable))
 343 /**
 344   * @}
 345   */
 346
 347 /** @defgroup FSMC_Wait_Signal_Polarity
 348   * @{
 349   */
 350 #define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
 351 #define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
 352 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
 353                                          ((POLARITY) == FSMC_WaitSignalPolarity_High))
 354 /**
 355   * @}
 356   */
 357
 358 /** @defgroup FSMC_Wrap_Mode
 359   * @{
 360   */
 361 #define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
 362 #define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400)
 363 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
 364                                  ((MODE) == FSMC_WrapMode_Enable))
 365 /**
 366   * @}
 367   */
 368
 369 /** @defgroup FSMC_Wait_Timing
 370   * @{
 371   */
 372 #define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
 373 #define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800)
 374 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
 375                                             ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
 376 /**
 377   * @}
 378   */
 379
 380 /** @defgroup FSMC_Write_Operation
 381   * @{
 382   */
 383 #define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
 384 #define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
 385 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
 386                                             ((OPERATION) == FSMC_WriteOperation_Enable))
 387 /**
 388   * @}
 389   */
 390
 391 /** @defgroup FSMC_Wait_Signal
 392   * @{
 393   */
 394 #define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
 395 #define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000)
 396 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
 397                                       ((SIGNAL) == FSMC_WaitSignal_Enable))
 398 /**
 399   * @}
 400   */
 401
 402 /** @defgroup FSMC_Extended_Mode
 403   * @{
 404   */
 405 #define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
 406 #define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
 407
 408 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
 409                                      ((MODE) == FSMC_ExtendedMode_Enable))
 410 /**
 411   * @}
 412   */
 413
 414 /** @defgroup FSMC_Write_Burst
 415   * @{
 416   */
 417
 418 #define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
 419 #define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000)
 420 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
 421                                     ((BURST) == FSMC_WriteBurst_Enable))
 422 /**
 423   * @}
 424   */
 425
 426 /** @defgroup FSMC_Address_Setup_Time
 427   * @{
 428   */
 429 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
 430 /**
 431   * @}
 432   */
 433
 434 /** @defgroup FSMC_Address_Hold_Time
 435   * @{
 436   */
 437 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
 438 /**
 439   * @}
 440   */
 441
 442 /** @defgroup FSMC_Data_Setup_Time
 443   * @{
 444   */
 445 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
 446 /**
 447   * @}
 448   */
 449
 450 /** @defgroup FSMC_Bus_Turn_around_Duration
 451   * @{
 452   */
 453 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
 454 /**
 455   * @}
 456   */
 457
 458 /** @defgroup FSMC_CLK_Division
 459   * @{
 460   */
 461 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
 462 /**
 463   * @}
 464   */
 465
 466 /** @defgroup FSMC_Data_Latency
 467   * @{
 468   */
 469 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
 470 /**
 471   * @}
 472   */
 473
 474 /** @defgroup FSMC_Access_Mode
 475   * @{
 476   */
 477 #define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
 478 #define FSMC_AccessMode_B                        ((uint32_t)0x10000000)
 479 #define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
 480 #define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
 481 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
 482                                    ((MODE) == FSMC_AccessMode_B) || \
 483                                    ((MODE) == FSMC_AccessMode_C) || \
 484                                    ((MODE) == FSMC_AccessMode_D))
 485 /**
 486   * @}
 487   */
 488
 489 /**
 490   * @}
 491   */
 492
 493 /** @defgroup FSMC_NAND_PCCARD_Controller
 494   * @{
 495   */
 496
 497 /** @defgroup FSMC_Wait_feature
 498   * @{
 499   */
 500 #define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
 501 #define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
 502 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
 503                                        ((FEATURE) == FSMC_Waitfeature_Enable))
 504 /**
 505   * @}
 506   */
 507
 508
 509 /** @defgroup FSMC_ECC
 510   * @{
 511   */
 512 #define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
 513 #define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
 514 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
 515                                   ((STATE) == FSMC_ECC_Enable))
 516 /**
 517   * @}
 518   */
 519
 520 /** @defgroup FSMC_ECC_Page_Size
 521   * @{
 522   */
 523 #define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
 524 #define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
 525 #define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
 526 #define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
 527 #define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
 528 #define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
 529 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
 530                                     ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
 531                                     ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
 532                                     ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
 533                                     ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
 534                                     ((SIZE) == FSMC_ECCPageSize_8192Bytes))
 535 /**
 536   * @}
 537   */
 538
 539 /** @defgroup FSMC_TCLR_Setup_Time
 540   * @{
 541   */
 542 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
 543 /**
 544   * @}
 545   */
 546
 547 /** @defgroup FSMC_TAR_Setup_Time
 548   * @{
 549   */
 550 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
 551 /**
 552   * @}
 553   */
 554
 555 /** @defgroup FSMC_Setup_Time
 556   * @{
 557   */
 558 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
 559 /**
 560   * @}
 561   */
 562
 563 /** @defgroup FSMC_Wait_Setup_Time
 564   * @{
 565   */
 566 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
 567 /**
 568   * @}
 569   */
 570
 571 /** @defgroup FSMC_Hold_Setup_Time
 572   * @{
 573   */
 574 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
 575 /**
 576   * @}
 577   */
 578
 579 /** @defgroup FSMC_HiZ_Setup_Time
 580   * @{
 581   */
 582 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
 583 /**
 584   * @}
 585   */
 586
 587 /** @defgroup FSMC_Interrupt_sources
 588   * @{
 589   */
 590 #define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
 591 #define FSMC_IT_Level                            ((uint32_t)0x00000010)
 592 #define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
 593 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
 594 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
 595                             ((IT) == FSMC_IT_Level) || \
 596                             ((IT) == FSMC_IT_FallingEdge))
 597 /**
 598   * @}
 599   */
 600
 601 /** @defgroup FSMC_Flags
 602   * @{
 603   */
 604 #define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
 605 #define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
 606 #define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
 607 #define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
 608 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
 609                                 ((FLAG) == FSMC_FLAG_Level) || \
 610                                 ((FLAG) == FSMC_FLAG_FallingEdge) || \
 611                                 ((FLAG) == FSMC_FLAG_FEMPT))
 612
 613 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
 614 /**
 615   * @}
 616   */
 617
 618 /**
 619   * @}
 620   */
 621
 622 /**
 623   * @}
 624   */
 625
 626 /* Exported macro ------------------------------------------------------------*/
 627 /* Exported functions --------------------------------------------------------*/
 628
 629 /* NOR/SRAM Controller functions **********************************************/
 630 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
 631 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
 632 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
 633 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 634
 635 /* NAND Controller functions **************************************************/
 636 void FSMC_NANDDeInit(uint32_t FSMC_Bank);
 637 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
 638 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
 639 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 640 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
 641 uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
 642
 643 /* PCCARD Controller functions ************************************************/
 644 void FSMC_PCCARDDeInit(void);
 645 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
 646 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
 647 void FSMC_PCCARDCmd(FunctionalState NewState);
 648
 649 /* Interrupts and flags management functions **********************************/
 650 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
 651 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
 652 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
 653 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
 654 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
 655
 656 #ifdef __cplusplus
 657 }
 658 #endif
 659
 660 #endif /*__STM32F4xx_FSMC_H */
 661 /**
 662   * @}
 663   */
 664
 665 /**
 666   * @}
 667   */
 668
 669 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/