2 ******************************************************************************
3 * @file stm32f4xx_dma.h
4 * @author MCD Application Team
7 * @brief This file contains all the functions prototypes for the DMA firmware
9 ******************************************************************************
12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
19 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
20 ******************************************************************************
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F4xx_DMA_H
25 #define __STM32F4xx_DMA_H
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f4xx.h"
34 /** @addtogroup STM32F4xx_StdPeriph_Driver
42 /* Exported types ------------------------------------------------------------*/
45 * @brief DMA Init structure definition
50 uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
51 This parameter can be a value of @ref DMA_channel */
53 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
55 uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
56 This memory is the default memory used when double buffer mode is
59 uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
60 from memory to memory or from peripheral to memory.
61 This parameter can be a value of @ref DMA_data_transfer_direction */
63 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
64 The data unit is equal to the configuration set in DMA_PeripheralDataSize
65 or DMA_MemoryDataSize members depending in the transfer direction. */
67 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
68 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
70 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
71 This parameter can be a value of @ref DMA_memory_incremented_mode */
73 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
74 This parameter can be a value of @ref DMA_peripheral_data_size */
76 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
77 This parameter can be a value of @ref DMA_memory_data_size */
79 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
80 This parameter can be a value of @ref DMA_circular_normal_mode
81 @note The circular buffer mode cannot be used if the memory-to-memory
82 data transfer is configured on the selected Stream */
84 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
85 This parameter can be a value of @ref DMA_priority_level */
87 uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
88 This parameter can be a value of @ref DMA_fifo_direct_mode
89 @note The Direct mode (FIFO mode disabled) cannot be used if the
90 memory-to-memory data transfer is configured on the selected Stream */
92 uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
93 This parameter can be a value of @ref DMA_fifo_threshold_level */
95 uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
96 It specifies the amount of data to be transferred in a single non interruptable
97 transaction. This parameter can be a value of @ref DMA_memory_burst
98 @note The burst mode is possible only if the address Increment mode is enabled. */
100 uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
101 It specifies the amount of data to be transferred in a single non interruptable
102 transaction. This parameter can be a value of @ref DMA_peripheral_burst
103 @note The burst mode is possible only if the address Increment mode is enabled. */
106 /* Exported constants --------------------------------------------------------*/
108 /** @defgroup DMA_Exported_Constants
112 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
113 ((PERIPH) == DMA1_Stream1) || \
114 ((PERIPH) == DMA1_Stream2) || \
115 ((PERIPH) == DMA1_Stream3) || \
116 ((PERIPH) == DMA1_Stream4) || \
117 ((PERIPH) == DMA1_Stream5) || \
118 ((PERIPH) == DMA1_Stream6) || \
119 ((PERIPH) == DMA1_Stream7) || \
120 ((PERIPH) == DMA2_Stream0) || \
121 ((PERIPH) == DMA2_Stream1) || \
122 ((PERIPH) == DMA2_Stream2) || \
123 ((PERIPH) == DMA2_Stream3) || \
124 ((PERIPH) == DMA2_Stream4) || \
125 ((PERIPH) == DMA2_Stream5) || \
126 ((PERIPH) == DMA2_Stream6) || \
127 ((PERIPH) == DMA2_Stream7))
129 #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
130 ((CONTROLLER) == DMA2))
132 /** @defgroup DMA_channel
135 #define DMA_Channel_0 ((uint32_t)0x00000000)
136 #define DMA_Channel_1 ((uint32_t)0x02000000)
137 #define DMA_Channel_2 ((uint32_t)0x04000000)
138 #define DMA_Channel_3 ((uint32_t)0x06000000)
139 #define DMA_Channel_4 ((uint32_t)0x08000000)
140 #define DMA_Channel_5 ((uint32_t)0x0A000000)
141 #define DMA_Channel_6 ((uint32_t)0x0C000000)
142 #define DMA_Channel_7 ((uint32_t)0x0E000000)
144 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
145 ((CHANNEL) == DMA_Channel_1) || \
146 ((CHANNEL) == DMA_Channel_2) || \
147 ((CHANNEL) == DMA_Channel_3) || \
148 ((CHANNEL) == DMA_Channel_4) || \
149 ((CHANNEL) == DMA_Channel_5) || \
150 ((CHANNEL) == DMA_Channel_6) || \
151 ((CHANNEL) == DMA_Channel_7))
157 /** @defgroup DMA_data_transfer_direction
160 #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
161 #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
162 #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
164 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
165 ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
166 ((DIRECTION) == DMA_DIR_MemoryToMemory))
172 /** @defgroup DMA_data_buffer_size
175 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
181 /** @defgroup DMA_peripheral_incremented_mode
184 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
185 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
187 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
188 ((STATE) == DMA_PeripheralInc_Disable))
194 /** @defgroup DMA_memory_incremented_mode
197 #define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
198 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
200 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
201 ((STATE) == DMA_MemoryInc_Disable))
207 /** @defgroup DMA_peripheral_data_size
210 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
211 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
212 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
214 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
215 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
216 ((SIZE) == DMA_PeripheralDataSize_Word))
222 /** @defgroup DMA_memory_data_size
225 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
226 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
227 #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
229 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
230 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
231 ((SIZE) == DMA_MemoryDataSize_Word ))
237 /** @defgroup DMA_circular_normal_mode
240 #define DMA_Mode_Normal ((uint32_t)0x00000000)
241 #define DMA_Mode_Circular ((uint32_t)0x00000100)
243 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
244 ((MODE) == DMA_Mode_Circular))
250 /** @defgroup DMA_priority_level
253 #define DMA_Priority_Low ((uint32_t)0x00000000)
254 #define DMA_Priority_Medium ((uint32_t)0x00010000)
255 #define DMA_Priority_High ((uint32_t)0x00020000)
256 #define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
258 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
259 ((PRIORITY) == DMA_Priority_Medium) || \
260 ((PRIORITY) == DMA_Priority_High) || \
261 ((PRIORITY) == DMA_Priority_VeryHigh))
267 /** @defgroup DMA_fifo_direct_mode
270 #define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
271 #define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
273 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
274 ((STATE) == DMA_FIFOMode_Enable))
280 /** @defgroup DMA_fifo_threshold_level
283 #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
284 #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
285 #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
286 #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
288 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
289 ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
290 ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
291 ((THRESHOLD) == DMA_FIFOThreshold_Full))
297 /** @defgroup DMA_memory_burst
300 #define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
301 #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
302 #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
303 #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
305 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
306 ((BURST) == DMA_MemoryBurst_INC4) || \
307 ((BURST) == DMA_MemoryBurst_INC8) || \
308 ((BURST) == DMA_MemoryBurst_INC16))
314 /** @defgroup DMA_peripheral_burst
317 #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
318 #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
319 #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
320 #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
322 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
323 ((BURST) == DMA_PeripheralBurst_INC4) || \
324 ((BURST) == DMA_PeripheralBurst_INC8) || \
325 ((BURST) == DMA_PeripheralBurst_INC16))
331 /** @defgroup DMA_fifo_status_level
334 #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
335 #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
336 #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
337 #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
338 #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
339 #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
341 #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
342 ((STATUS) == DMA_FIFOStatus_HalfFull) || \
343 ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
344 ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
345 ((STATUS) == DMA_FIFOStatus_Full) || \
346 ((STATUS) == DMA_FIFOStatus_Empty))
351 /** @defgroup DMA_flags_definition
354 #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
355 #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
356 #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
357 #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
358 #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
359 #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
360 #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
361 #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
362 #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
363 #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
364 #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
365 #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
366 #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
367 #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
368 #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
369 #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
370 #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
371 #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
372 #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
373 #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
374 #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
375 #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
376 #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
377 #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
378 #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
379 #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
380 #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
381 #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
382 #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
383 #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
384 #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
385 #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
386 #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
387 #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
388 #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
389 #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
390 #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
391 #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
392 #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
393 #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
395 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
396 (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
398 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
399 ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
400 ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
401 ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
402 ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
403 ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
404 ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
405 ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
406 ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
407 ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
408 ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
409 ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
410 ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
411 ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
412 ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
413 ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
414 ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
415 ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
416 ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
417 ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
423 /** @defgroup DMA_interrupt_enable_definitions
426 #define DMA_IT_TC ((uint32_t)0x00000010)
427 #define DMA_IT_HT ((uint32_t)0x00000008)
428 #define DMA_IT_TE ((uint32_t)0x00000004)
429 #define DMA_IT_DME ((uint32_t)0x00000002)
430 #define DMA_IT_FE ((uint32_t)0x00000080)
432 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
438 /** @defgroup DMA_interrupts_definitions
441 #define DMA_IT_FEIF0 ((uint32_t)0x90000001)
442 #define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
443 #define DMA_IT_TEIF0 ((uint32_t)0x10002008)
444 #define DMA_IT_HTIF0 ((uint32_t)0x10004010)
445 #define DMA_IT_TCIF0 ((uint32_t)0x10008020)
446 #define DMA_IT_FEIF1 ((uint32_t)0x90000040)
447 #define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
448 #define DMA_IT_TEIF1 ((uint32_t)0x10002200)
449 #define DMA_IT_HTIF1 ((uint32_t)0x10004400)
450 #define DMA_IT_TCIF1 ((uint32_t)0x10008800)
451 #define DMA_IT_FEIF2 ((uint32_t)0x90010000)
452 #define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
453 #define DMA_IT_TEIF2 ((uint32_t)0x10082000)
454 #define DMA_IT_HTIF2 ((uint32_t)0x10104000)
455 #define DMA_IT_TCIF2 ((uint32_t)0x10208000)
456 #define DMA_IT_FEIF3 ((uint32_t)0x90400000)
457 #define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
458 #define DMA_IT_TEIF3 ((uint32_t)0x12002000)
459 #define DMA_IT_HTIF3 ((uint32_t)0x14004000)
460 #define DMA_IT_TCIF3 ((uint32_t)0x18008000)
461 #define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
462 #define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
463 #define DMA_IT_TEIF4 ((uint32_t)0x20002008)
464 #define DMA_IT_HTIF4 ((uint32_t)0x20004010)
465 #define DMA_IT_TCIF4 ((uint32_t)0x20008020)
466 #define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
467 #define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
468 #define DMA_IT_TEIF5 ((uint32_t)0x20002200)
469 #define DMA_IT_HTIF5 ((uint32_t)0x20004400)
470 #define DMA_IT_TCIF5 ((uint32_t)0x20008800)
471 #define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
472 #define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
473 #define DMA_IT_TEIF6 ((uint32_t)0x20082000)
474 #define DMA_IT_HTIF6 ((uint32_t)0x20104000)
475 #define DMA_IT_TCIF6 ((uint32_t)0x20208000)
476 #define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
477 #define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
478 #define DMA_IT_TEIF7 ((uint32_t)0x22002000)
479 #define DMA_IT_HTIF7 ((uint32_t)0x24004000)
480 #define DMA_IT_TCIF7 ((uint32_t)0x28008000)
482 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
483 (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
484 (((IT) & 0x40820082) == 0x00))
486 #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
487 ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
488 ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
489 ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
490 ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
491 ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
492 ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
493 ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
494 ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
495 ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
496 ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
497 ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
498 ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
499 ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
500 ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
501 ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
502 ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
503 ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
504 ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
505 ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
511 /** @defgroup DMA_peripheral_increment_offset
514 #define DMA_PINCOS_Psize ((uint32_t)0x00000000)
515 #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
517 #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
518 ((SIZE) == DMA_PINCOS_WordAligned))
524 /** @defgroup DMA_flow_controller_definitions
527 #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
528 #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
530 #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
531 ((CTRL) == DMA_FlowCtrl_Peripheral))
537 /** @defgroup DMA_memory_targets_definitions
540 #define DMA_Memory_0 ((uint32_t)0x00000000)
541 #define DMA_Memory_1 ((uint32_t)0x00080000)
543 #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
552 /* Exported macro ------------------------------------------------------------*/
553 /* Exported functions --------------------------------------------------------*/
555 /* Function used to set the DMA configuration to the default reset state *****/
556 void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
558 /* Initialization and Configuration functions *********************************/
559 void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
560 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
561 void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
563 /* Optional Configuration functions *******************************************/
564 void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
565 void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
567 /* Data Counter functions *****************************************************/
568 void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
569 uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
571 /* Double Buffer mode functions ***********************************************/
572 void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
573 uint32_t DMA_CurrentMemory);
574 void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
575 void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
576 uint32_t DMA_MemoryTarget);
577 uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
579 /* Interrupts and flags management functions **********************************/
580 FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
581 uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
582 FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
583 void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
584 void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
585 ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
586 void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
592 #endif /*__STM32F4xx_DMA_H */
603 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/