1 /**************************************************************************//**
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
31 #ifndef __CORE_CM3_H_GENERIC
32 #define __CORE_CM3_H_GENERIC
35 /** \mainpage CMSIS Cortex-M3
37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
40 - Cortex-M Core Register Definitions
42 - Cortex-M instructions
44 The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
45 access to the Cortex-M Core
48 /** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
49 CMSIS violates following MISRA-C2004 Rules:
51 - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
52 Function definitions in header files are used to allow 'inlining'.
54 - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
55 Unions are used for effective representation of core registers.
57 - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
58 Function-like macros are used to allow more efficient code.
63 /*******************************************************************************
65 ******************************************************************************/
66 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
67 This file defines all structures and symbols for CMSIS core:
68 - CMSIS version number
70 - Cortex-M core Revision Number
74 /* CMSIS CM3 definitions */
75 #define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
76 #define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
77 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
79 #define __CORTEX_M (0x03) /*!< Cortex core */
82 #if defined ( __CC_ARM )
83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
86 #elif defined ( __ICCARM__ )
87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
90 #elif defined ( __GNUC__ )
91 #define __ASM __asm /*!< asm keyword for GNU Compiler */
92 #define __INLINE inline /*!< inline keyword for GNU Compiler */
94 #elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
100 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
103 #if defined ( __CC_ARM )
104 #if defined __TARGET_FPU_VFP
105 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #elif defined ( __ICCARM__ )
108 #if defined __ARMVFP__
109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #elif defined ( __GNUC__ )
113 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
114 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
117 #elif defined ( __TASKING__ )
118 /* add preprocessor checks */
121 #include <stdint.h> /*!< standard types definitions */
122 #include "core_cmInstr.h" /*!< Core Instruction Access */
123 #include "core_cmFunc.h" /*!< Core Function Access */
125 #endif /* __CORE_CM3_H_GENERIC */
127 #ifndef __CMSIS_GENERIC
129 #ifndef __CORE_CM3_H_DEPENDANT
130 #define __CORE_CM3_H_DEPENDANT
132 /* check device defines and use defaults */
133 #if defined __CHECK_DEVICE_DEFINES
135 #define __CM3_REV 0x0200
136 #warning "__CM3_REV not defined in device header file; using default!"
139 #ifndef __MPU_PRESENT
140 #define __MPU_PRESENT 0
141 #warning "__MPU_PRESENT not defined in device header file; using default!"
144 #ifndef __NVIC_PRIO_BITS
145 #define __NVIC_PRIO_BITS 4
146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
149 #ifndef __Vendor_SysTickConfig
150 #define __Vendor_SysTickConfig 0
151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
155 /* IO definitions (access restrictions to peripheral registers) */
157 #define __I volatile /*!< defines 'read only' permissions */
159 #define __I volatile const /*!< defines 'read only' permissions */
161 #define __O volatile /*!< defines 'write only' permissions */
162 #define __IO volatile /*!< defines 'read / write' permissions */
164 /*@} end of group CMSIS_core_definitions */
168 /*******************************************************************************
169 * Register Abstraction
170 ******************************************************************************/
171 /** \defgroup CMSIS_core_register CMSIS Core Register
172 Core Register contain:
176 - Core SysTick Register
177 - Core Debug Register
181 /** \ingroup CMSIS_core_register
182 \defgroup CMSIS_CORE CMSIS Core
183 Type definitions for the Cortex-M Core Registers
187 /** \brief Union type to access the Application Program Status Register (APSR).
193 #if (__CORTEX_M != 0x04)
194 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
196 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
197 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
198 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
200 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
201 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
202 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
203 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
204 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
205 } b; /*!< Structure used for bit access */
206 uint32_t w; /*!< Type used for word access */
210 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
216 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
217 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
218 } b; /*!< Structure used for bit access */
219 uint32_t w; /*!< Type used for word access */
223 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
229 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
230 #if (__CORTEX_M != 0x04)
231 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
233 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
234 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
235 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
237 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
238 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
239 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
249 /** \brief Union type to access the Control Registers (CONTROL).
255 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
256 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
257 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
258 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
259 } b; /*!< Structure used for bit access */
260 uint32_t w; /*!< Type used for word access */
263 /*@} end of group CMSIS_CORE */
266 /** \ingroup CMSIS_core_register
267 \defgroup CMSIS_NVIC CMSIS NVIC
268 Type definitions for the Cortex-M NVIC Registers
272 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
276 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
277 uint32_t RESERVED0[24];
278 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
279 uint32_t RSERVED1[24];
280 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
281 uint32_t RESERVED2[24];
282 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
283 uint32_t RESERVED3[24];
284 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
285 uint32_t RESERVED4[56];
286 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
287 uint32_t RESERVED5[644];
288 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
291 /* Software Triggered Interrupt Register Definitions */
292 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
293 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
295 /*@} end of group CMSIS_NVIC */
298 /** \ingroup CMSIS_core_register
299 \defgroup CMSIS_SCB CMSIS SCB
300 Type definitions for the Cortex-M System Control Block Registers
304 /** \brief Structure type to access the System Control Block (SCB).
308 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
309 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
310 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
311 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
312 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
313 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
314 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
316 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
317 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
318 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
319 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
320 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
321 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
322 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
323 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
324 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
325 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
326 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
327 uint32_t RESERVED0[5];
328 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
331 /* SCB CPUID Register Definitions */
332 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
333 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
335 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
336 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
338 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
339 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
341 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
342 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
344 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
345 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
347 /* SCB Interrupt Control State Register Definitions */
348 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
349 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
351 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
352 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
354 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
355 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
357 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
358 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
360 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
361 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
363 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
364 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
366 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
367 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
369 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
370 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
372 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
373 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
375 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
376 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
378 /* SCB Vector Table Offset Register Definitions */
379 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
380 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
382 /* SCB Application Interrupt and Reset Control Register Definitions */
383 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
384 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
386 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
387 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
389 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
390 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
392 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
393 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
395 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
396 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
398 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
399 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
401 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
402 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
404 /* SCB System Control Register Definitions */
405 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
406 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
408 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
409 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
411 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
412 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
414 /* SCB Configuration Control Register Definitions */
415 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
416 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
418 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
419 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
421 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
422 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
424 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
425 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
427 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
428 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
430 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
431 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
433 /* SCB System Handler Control and State Register Definitions */
434 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
435 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
437 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
438 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
440 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
441 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
443 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
444 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
446 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
447 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
449 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
450 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
452 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
453 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
455 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
456 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
458 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
459 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
461 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
462 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
464 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
465 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
467 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
468 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
470 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
471 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
473 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
474 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
476 /* SCB Configurable Fault Status Registers Definitions */
477 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
478 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
480 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
481 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
483 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
484 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
486 /* SCB Hard Fault Status Registers Definitions */
487 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
488 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
490 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
491 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
493 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
494 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
496 /* SCB Debug Fault Status Register Definitions */
497 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
498 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
500 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
501 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
503 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
504 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
506 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
507 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
509 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
510 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
512 /*@} end of group CMSIS_SCB */
515 /** \ingroup CMSIS_core_register
516 \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
517 Type definitions for the Cortex-M System Control and ID Register not in the SCB
521 /** \brief Structure type to access the System Control and ID Register not in the SCB.
525 uint32_t RESERVED0[1];
526 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
527 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
528 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
530 uint32_t RESERVED1[1];
534 /* Interrupt Controller Type Register Definitions */
535 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
536 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
538 /* Auxiliary Control Register Definitions */
540 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
541 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
543 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
544 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
546 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
547 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
549 /*@} end of group CMSIS_SCnotSCB */
552 /** \ingroup CMSIS_core_register
553 \defgroup CMSIS_SysTick CMSIS SysTick
554 Type definitions for the Cortex-M System Timer Registers
558 /** \brief Structure type to access the System Timer (SysTick).
562 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
563 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
564 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
565 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
568 /* SysTick Control / Status Register Definitions */
569 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
570 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
572 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
573 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
575 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
576 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
578 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
579 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
581 /* SysTick Reload Register Definitions */
582 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
583 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
585 /* SysTick Current Register Definitions */
586 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
587 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
589 /* SysTick Calibration Register Definitions */
590 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
591 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
593 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
594 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
596 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
597 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
599 /*@} end of group CMSIS_SysTick */
602 /** \ingroup CMSIS_core_register
603 \defgroup CMSIS_ITM CMSIS ITM
604 Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
608 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
614 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
615 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
616 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
617 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
618 uint32_t RESERVED0[864];
619 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
620 uint32_t RESERVED1[15];
621 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
622 uint32_t RESERVED2[15];
623 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
626 /* ITM Trace Privilege Register Definitions */
627 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
628 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
630 /* ITM Trace Control Register Definitions */
631 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
632 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
634 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
635 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
637 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
638 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
640 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
641 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
643 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
644 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
646 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
647 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
649 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
650 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
652 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
653 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
655 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
656 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
658 /*@}*/ /* end of group CMSIS_ITM */
661 #if (__MPU_PRESENT == 1)
662 /** \ingroup CMSIS_core_register
663 \defgroup CMSIS_MPU CMSIS MPU
664 Type definitions for the Cortex-M Memory Protection Unit (MPU)
668 /** \brief Structure type to access the Memory Protection Unit (MPU).
672 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
673 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
674 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
675 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
676 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
677 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
678 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
679 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
680 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
681 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
682 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
685 /* MPU Type Register */
686 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
687 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
689 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
690 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
692 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
693 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
695 /* MPU Control Register */
696 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
697 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
699 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
700 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
702 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
703 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
705 /* MPU Region Number Register */
706 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
707 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
709 /* MPU Region Base Address Register */
710 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
711 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
713 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
714 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
716 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
717 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
719 /* MPU Region Attribute and Size Register */
720 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
721 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
723 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
724 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
726 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
727 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
729 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
730 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
732 /*@} end of group CMSIS_MPU */
736 /** \ingroup CMSIS_core_register
737 \defgroup CMSIS_CoreDebug CMSIS Core Debug
738 Type definitions for the Cortex-M Core Debug Registers
742 /** \brief Structure type to access the Core Debug Register (CoreDebug).
746 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
747 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
748 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
749 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
752 /* Debug Halting Control and Status Register */
753 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
754 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
756 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
757 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
759 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
760 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
762 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
763 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
765 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
766 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
768 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
769 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
771 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
772 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
774 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
775 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
777 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
778 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
780 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
781 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
783 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
784 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
786 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
787 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
789 /* Debug Core Register Selector Register */
790 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
791 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
793 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
794 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
796 /* Debug Exception and Monitor Control Register */
797 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
798 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
800 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
801 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
803 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
804 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
806 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
807 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
809 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
810 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
812 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
813 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
815 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
816 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
818 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
819 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
821 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
822 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
824 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
825 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
827 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
828 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
830 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
831 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
833 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
834 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
836 /*@} end of group CMSIS_CoreDebug */
839 /** \ingroup CMSIS_core_register
843 /* Memory mapping of Cortex-M3 Hardware */
844 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
845 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
846 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
847 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
848 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
849 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
851 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
852 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
853 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
854 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
855 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
856 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
858 #if (__MPU_PRESENT == 1)
859 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
860 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
867 /*******************************************************************************
868 * Hardware Abstraction Layer
869 ******************************************************************************/
870 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
871 Core Function Interface contains:
872 - Core NVIC Functions
873 - Core SysTick Functions
874 - Core Debug Functions
875 - Core Register Access Functions
880 /* ########################## NVIC functions #################################### */
881 /** \ingroup CMSIS_Core_FunctionInterface
882 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
886 /** \brief Set Priority Grouping
888 This function sets the priority grouping field using the required unlock sequence.
889 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
890 Only values from 0..7 are used.
891 In case of a conflict between priority grouping and available
892 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
894 \param [in] PriorityGroup Priority grouping field
896 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
901 reg_value = SCB->AIRCR; /* read old register configuration */
902 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
903 reg_value = (reg_value |
904 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
905 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
906 SCB->AIRCR = reg_value;
910 /** \brief Get Priority Grouping
912 This function gets the priority grouping from NVIC Interrupt Controller.
913 Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
915 \return Priority grouping field
917 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
919 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
923 /** \brief Enable External Interrupt
925 This function enables a device specific interrupt in the NVIC interrupt controller.
926 The interrupt number cannot be a negative value.
928 \param [in] IRQn Number of the external interrupt to enable
930 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
932 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
936 /** \brief Disable External Interrupt
938 This function disables a device specific interrupt in the NVIC interrupt controller.
939 The interrupt number cannot be a negative value.
941 \param [in] IRQn Number of the external interrupt to disable
943 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
945 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
949 /** \brief Get Pending Interrupt
951 This function reads the pending register in the NVIC and returns the pending bit
952 for the specified interrupt.
954 \param [in] IRQn Number of the interrupt for get pending
955 \return 0 Interrupt status is not pending
956 \return 1 Interrupt status is pending
958 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
960 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
964 /** \brief Set Pending Interrupt
966 This function sets the pending bit for the specified interrupt.
967 The interrupt number cannot be a negative value.
969 \param [in] IRQn Number of the interrupt for set pending
971 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
973 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
977 /** \brief Clear Pending Interrupt
979 This function clears the pending bit for the specified interrupt.
980 The interrupt number cannot be a negative value.
982 \param [in] IRQn Number of the interrupt for clear pending
984 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
986 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
990 /** \brief Get Active Interrupt
992 This function reads the active register in NVIC and returns the active bit.
993 \param [in] IRQn Number of the interrupt for get active
994 \return 0 Interrupt status is not active
995 \return 1 Interrupt status is active
997 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
999 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1003 /** \brief Set Interrupt Priority
1005 This function sets the priority for the specified interrupt. The interrupt
1006 number can be positive to specify an external (device specific)
1007 interrupt, or negative to specify an internal (core) interrupt.
1009 Note: The priority cannot be set for every core interrupt.
1011 \param [in] IRQn Number of the interrupt for set priority
1012 \param [in] priority Priority to set
1014 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1017 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1019 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1023 /** \brief Get Interrupt Priority
1025 This function reads the priority for the specified interrupt. The interrupt
1026 number can be positive to specify an external (device specific)
1027 interrupt, or negative to specify an internal (core) interrupt.
1029 The returned priority value is automatically aligned to the implemented
1030 priority bits of the microcontroller.
1032 \param [in] IRQn Number of the interrupt for get priority
1033 \return Interrupt Priority
1035 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1039 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1041 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1045 /** \brief Encode Priority
1047 This function encodes the priority for an interrupt with the given priority group,
1048 preemptive priority value and sub priority value.
1049 In case of a conflict between priority grouping and available
1050 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1052 The returned priority value can be used for NVIC_SetPriority(...) function
1054 \param [in] PriorityGroup Used priority group
1055 \param [in] PreemptPriority Preemptive priority value (starting from 0)
1056 \param [in] SubPriority Sub priority value (starting from 0)
1057 \return Encoded priority for the interrupt
1059 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1061 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1062 uint32_t PreemptPriorityBits;
1063 uint32_t SubPriorityBits;
1065 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1066 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1069 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1070 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1075 /** \brief Decode Priority
1077 This function decodes an interrupt priority value with the given priority group to
1078 preemptive priority value and sub priority value.
1079 In case of a conflict between priority grouping and available
1080 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1082 The priority value can be retrieved with NVIC_GetPriority(...) function
1084 \param [in] Priority Priority value
1085 \param [in] PriorityGroup Used priority group
1086 \param [out] pPreemptPriority Preemptive priority value (starting from 0)
1087 \param [out] pSubPriority Sub priority value (starting from 0)
1089 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1091 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1092 uint32_t PreemptPriorityBits;
1093 uint32_t SubPriorityBits;
1095 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1096 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1098 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1099 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1103 /** \brief System Reset
1105 This function initiate a system reset request to reset the MCU.
1107 static __INLINE void NVIC_SystemReset(void)
1109 __DSB(); /* Ensure all outstanding memory accesses included
1110 buffered write are completed before reset */
1111 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1112 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1113 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1114 __DSB(); /* Ensure completion of memory access */
1115 while(1); /* wait until reset */
1118 /*@} end of CMSIS_Core_NVICFunctions */
1122 /* ################################## SysTick function ############################################ */
1123 /** \ingroup CMSIS_Core_FunctionInterface
1124 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
1128 #if (__Vendor_SysTickConfig == 0)
1130 /** \brief System Tick Configuration
1132 This function initialises the system tick timer and its interrupt and start the system tick timer.
1133 Counter is in free running mode to generate periodical interrupts.
1135 \param [in] ticks Number of ticks between two interrupts
1136 \return 0 Function succeeded
1137 \return 1 Function failed
1139 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1141 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1143 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1144 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1145 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1146 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1147 SysTick_CTRL_TICKINT_Msk |
1148 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1149 return (0); /* Function successful */
1154 /*@} end of CMSIS_Core_SysTickFunctions */
1158 /* ##################################### Debug In/Output function ########################################### */
1159 /** \ingroup CMSIS_Core_FunctionInterface
1160 \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
1164 extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
1165 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
1168 /** \brief ITM Send Character
1170 This function transmits a character via the ITM channel 0.
1171 It just returns when no debugger is connected that has booked the output.
1172 It is blocking when a debugger is connected, but the previous character send is not transmitted.
1174 \param [in] ch Character to transmit
1175 \return Character to transmit
1177 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1179 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
1180 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1181 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1183 while (ITM->PORT[0].u32 == 0);
1184 ITM->PORT[0].u8 = (uint8_t) ch;
1190 /** \brief ITM Receive Character
1192 This function inputs a character via external variable ITM_RxBuffer.
1193 It just returns when no debugger is connected that has booked the output.
1194 It is blocking when a debugger is connected, but the previous character send is not transmitted.
1196 \return Received character
1197 \return -1 No character received
1199 static __INLINE int32_t ITM_ReceiveChar (void) {
1200 int32_t ch = -1; /* no character available */
1202 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1204 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1211 /** \brief ITM Check Character
1213 This function checks external variable ITM_RxBuffer whether a character is available or not.
1214 It returns '1' if a character is available and '0' if no character is available.
1216 \return 0 No character available
1217 \return 1 Character available
1219 static __INLINE int32_t ITM_CheckChar (void) {
1221 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1222 return (0); /* no character available */
1224 return (1); /* character available */
1228 /*@} end of CMSIS_core_DebugFunctions */
1230 #endif /* __CORE_CM3_H_DEPENDANT */
1232 #endif /* __CMSIS_GENERIC */
projects / fw / stlink / blob