2 ******************************************************************************
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3 * @file stm32l1xx_dma.c
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4 * @author MCD Application Team
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6 * @date 31-December-2010
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7 * @brief This file provides firmware functions to manage the following
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8 * functionalities of the Direct Memory Access controller (DMA):
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9 * - Initialization and Configuration
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11 * - Interrupts and flags management
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15 * ===================================================================
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16 * How to use this driver
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17 * ===================================================================
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18 * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE)
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19 * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE)
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20 * function for DMA2.
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22 * 2. Enable and configure the peripheral to be connected to the DMA channel
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23 * (except for internal SRAM / FLASH memories: no initialization is
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26 * 3. For a given Channel, program the Source and Destination addresses,
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27 * the transfer Direction, the Buffer Size, the Peripheral and Memory
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28 * Incrementation mode and Data Size, the Circular or Normal mode,
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29 * the channel transfer Priority and the Memory-to-Memory transfer
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30 * mode (if needed) using the DMA_Init() function.
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32 * 4. Enable the NVIC and the corresponding interrupt(s) using the function
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33 * DMA_ITConfig() if you need to use DMA interrupts.
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35 * 5. Enable the DMA channel using the DMA_Cmd() function.
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37 * 6. Activate the needed channel Request using PPP_DMACmd() function for
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38 * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
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39 * The function allowing this operation is provided in each PPP peripheral
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40 * driver (ie. SPI_DMACmd for SPI peripheral).
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42 * 7. Optionally, you can configure the number of data to be transferred
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43 * when the channel is disabled (ie. after each Transfer Complete event
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44 * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
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45 * And you can get the number of remaining data to be transferred using
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46 * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
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47 * enabled and running).
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49 * 8. To control DMA events you can use one of the following
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51 * a- Check on DMA channel flags using the function DMA_GetFlagStatus().
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52 * b- Use DMA interrupts through the function DMA_ITConfig() at initialization
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53 * phase and DMA_GetITStatus() function into interrupt routines in
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54 * communication phase.
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55 * After checking on a flag you should clear it using DMA_ClearFlag()
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56 * function. And after checking on an interrupt event you should
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57 * clear it using DMA_ClearITPendingBit() function.
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61 ******************************************************************************
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64 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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65 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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66 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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67 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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68 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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69 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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71 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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72 ******************************************************************************
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75 /* Includes ------------------------------------------------------------------*/
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76 #include "stm32l1xx_dma.h"
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77 #include "stm32l1xx_rcc.h"
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79 /** @addtogroup STM32L1xx_StdPeriph_Driver
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84 * @brief DMA driver modules
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88 /* Private typedef -----------------------------------------------------------*/
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89 /* Private define ------------------------------------------------------------*/
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91 /* DMA1 Channelx interrupt pending bit masks */
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92 #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
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93 #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
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94 #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
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95 #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
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96 #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
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97 #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
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98 #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
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100 /* DMA FLAG mask */
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101 #define FLAG_MASK ((uint32_t)0x10000000)
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103 /* DMA registers Masks */
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104 #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
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106 /* Private macro -------------------------------------------------------------*/
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107 /* Private variables ---------------------------------------------------------*/
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108 /* Private function prototypes -----------------------------------------------*/
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109 /* Private functions ---------------------------------------------------------*/
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112 /** @defgroup DMA_Private_Functions
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116 /** @defgroup DMA_Group1 Initialization and Configuration functions
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117 * @brief Initialization and Configuration functions
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120 ===============================================================================
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121 Initialization and Configuration functions
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122 ===============================================================================
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124 This subsection provides functions allowing to initialize the DMA channel source
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125 and destination addresses, incrementation and data sizes, transfer direction,
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126 buffer size, circular/normal mode selection, memory-to-memory mode selection
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127 and channel priority value.
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129 The DMA_Init() function follows the DMA configuration procedures as described in
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130 reference manual (RM0038).
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137 * @brief Deinitializes the DMAy Channelx registers to their default reset
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139 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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140 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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143 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
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145 /* Check the parameters */
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146 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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148 /* Disable the selected DMAy Channelx */
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149 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
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151 /* Reset DMAy Channelx control register */
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152 DMAy_Channelx->CCR = 0;
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154 /* Reset DMAy Channelx remaining bytes register */
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155 DMAy_Channelx->CNDTR = 0;
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157 /* Reset DMAy Channelx peripheral address register */
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158 DMAy_Channelx->CPAR = 0;
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160 /* Reset DMAy Channelx memory address register */
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161 DMAy_Channelx->CMAR = 0;
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163 if (DMAy_Channelx == DMA1_Channel1)
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165 /* Reset interrupt pending bits for DMA1 Channel1 */
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166 DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
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168 else if (DMAy_Channelx == DMA1_Channel2)
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170 /* Reset interrupt pending bits for DMA1 Channel2 */
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171 DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
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173 else if (DMAy_Channelx == DMA1_Channel3)
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175 /* Reset interrupt pending bits for DMA1 Channel3 */
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176 DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
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178 else if (DMAy_Channelx == DMA1_Channel4)
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180 /* Reset interrupt pending bits for DMA1 Channel4 */
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181 DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
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183 else if (DMAy_Channelx == DMA1_Channel5)
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185 /* Reset interrupt pending bits for DMA1 Channel5 */
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186 DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
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188 else if (DMAy_Channelx == DMA1_Channel6)
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190 /* Reset interrupt pending bits for DMA1 Channel6 */
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191 DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
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195 if (DMAy_Channelx == DMA1_Channel7)
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197 /* Reset interrupt pending bits for DMA1 Channel7 */
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198 DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
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204 * @brief Initializes the DMAy Channelx according to the specified
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205 * parameters in the DMA_InitStruct.
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206 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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207 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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208 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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209 * contains the configuration information for the specified DMA Channel.
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212 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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214 uint32_t tmpreg = 0;
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216 /* Check the parameters */
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217 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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218 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
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219 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
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220 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
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221 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
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222 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
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223 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
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224 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
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225 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
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226 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
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228 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
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229 /* Get the DMAy_Channelx CCR value */
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230 tmpreg = DMAy_Channelx->CCR;
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231 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
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232 tmpreg &= CCR_CLEAR_MASK;
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233 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
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234 /* Set DIR bit according to DMA_DIR value */
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235 /* Set CIRC bit according to DMA_Mode value */
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236 /* Set PINC bit according to DMA_PeripheralInc value */
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237 /* Set MINC bit according to DMA_MemoryInc value */
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238 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
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239 /* Set MSIZE bits according to DMA_MemoryDataSize value */
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240 /* Set PL bits according to DMA_Priority value */
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241 /* Set the MEM2MEM bit according to DMA_M2M value */
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242 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
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243 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
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244 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
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245 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
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247 /* Write to DMAy Channelx CCR */
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248 DMAy_Channelx->CCR = tmpreg;
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250 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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251 /* Write to DMAy Channelx CNDTR */
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252 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
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254 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
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255 /* Write to DMAy Channelx CPAR */
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256 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
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258 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
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259 /* Write to DMAy Channelx CMAR */
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260 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
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264 * @brief Fills each DMA_InitStruct member with its default value.
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265 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
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269 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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271 /*-------------- Reset DMA init structure parameters values ------------------*/
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272 /* Initialize the DMA_PeripheralBaseAddr member */
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273 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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274 /* Initialize the DMA_MemoryBaseAddr member */
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275 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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276 /* Initialize the DMA_DIR member */
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277 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
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278 /* Initialize the DMA_BufferSize member */
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279 DMA_InitStruct->DMA_BufferSize = 0;
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280 /* Initialize the DMA_PeripheralInc member */
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281 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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282 /* Initialize the DMA_MemoryInc member */
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283 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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284 /* Initialize the DMA_PeripheralDataSize member */
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285 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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286 /* Initialize the DMA_MemoryDataSize member */
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287 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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288 /* Initialize the DMA_Mode member */
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289 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
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290 /* Initialize the DMA_Priority member */
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291 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
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292 /* Initialize the DMA_M2M member */
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293 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
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297 * @brief Enables or disables the specified DMAy Channelx.
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298 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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299 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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300 * @param NewState: new state of the DMAy Channelx.
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301 * This parameter can be: ENABLE or DISABLE.
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304 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
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306 /* Check the parameters */
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307 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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308 assert_param(IS_FUNCTIONAL_STATE(NewState));
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310 if (NewState != DISABLE)
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312 /* Enable the selected DMAy Channelx */
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313 DMAy_Channelx->CCR |= DMA_CCR1_EN;
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317 /* Disable the selected DMAy Channelx */
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318 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
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326 /** @defgroup DMA_Group2 Data Counter functions
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327 * @brief Data Counter functions
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330 ===============================================================================
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331 Data Counter functions
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332 ===============================================================================
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334 This subsection provides function allowing to configure and read the buffer size
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335 (number of data to be transferred).
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337 The DMA data counter can be written only when the DMA channel is disabled
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338 (ie. after transfer complete event).
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340 The following function can be used to write the Channel data counter value:
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341 - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
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343 @note It is advised to use this function rather than DMA_Init() in situations where
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344 only the Data buffer needs to be reloaded.
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346 The DMA data counter can be read to indicate the number of remaining transfers for
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347 the relative DMA channel. This counter is decremented at the end of each data
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348 transfer and when the transfer is complete:
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349 - If Normal mode is selected: the counter is set to 0.
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350 - If Circular mode is selected: the counter is reloaded with the initial value
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351 (configured before enabling the DMA channel)
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353 The following function can be used to read the Channel data counter value:
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354 - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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361 * @brief Sets the number of data units in the current DMAy Channelx transfer.
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362 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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363 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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364 * @param DataNumber: The number of data units in the current DMAy Channelx
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366 * @note This function can only be used when the DMAy_Channelx is disabled.
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369 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
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371 /* Check the parameters */
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372 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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374 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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375 /* Write to DMAy Channelx CNDTR */
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376 DMAy_Channelx->CNDTR = DataNumber;
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380 * @brief Returns the number of remaining data units in the current
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381 * DMAy Channelx transfer.
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382 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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383 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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384 * @retval The number of remaining data units in the current DMAy Channelx
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387 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
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389 /* Check the parameters */
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390 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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391 /* Return the number of remaining data units for DMAy Channelx */
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392 return ((uint16_t)(DMAy_Channelx->CNDTR));
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399 /** @defgroup DMA_Group3 Interrupts and flags management functions
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400 * @brief Interrupts and flags management functions
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403 ===============================================================================
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404 Interrupts and flags management functions
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405 ===============================================================================
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407 This subsection provides functions allowing to configure the DMA Interrupts
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408 sources and check or clear the flags or pending bits status.
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409 The user should identify which mode will be used in his application to manage the
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410 DMA controller events: Polling mode or Interrupt mode.
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414 Each DMA channel can be managed through 4 event Flags:
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415 (y : DMA Controller number
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416 x : DMA channel number )
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417 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred
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418 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured
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419 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured.
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420 4. DMAy_FLAG_GLx : to indicate that at least one of the events described
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423 @note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
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424 same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
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426 In this Mode it is advised to use the following functions:
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427 - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
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428 - void DMA_ClearFlag(uint32_t DMA_FLAG);
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432 Each DMA channel can be managed through 4 Interrupts:
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436 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event.
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437 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event.
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438 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event.
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439 4. DMA_IT_GL : to indicate that at least one of the interrupts described
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442 @note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the
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443 same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
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445 In this Mode it is advised to use the following functions:
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446 - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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447 - ITStatus DMA_GetITStatus(uint32_t DMA_IT);
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448 - void DMA_ClearITPendingBit(uint32_t DMA_IT);
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455 * @brief Enables or disables the specified DMAy Channelx interrupts.
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456 * @param DMAy_Channelx: where y can be 1 to select the DMA and
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457 * x can be 1 to 7 for DMA1 to select the DMA Channel.
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458 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
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460 * This parameter can be any combination of the following values:
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461 * @arg DMA_IT_TC: Transfer complete interrupt mask
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462 * @arg DMA_IT_HT: Half transfer interrupt mask
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463 * @arg DMA_IT_TE: Transfer error interrupt mask
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464 * @param NewState: new state of the specified DMA interrupts.
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465 * This parameter can be: ENABLE or DISABLE.
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468 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
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470 /* Check the parameters */
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471 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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472 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
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473 assert_param(IS_FUNCTIONAL_STATE(NewState));
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475 if (NewState != DISABLE)
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477 /* Enable the selected DMA interrupts */
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478 DMAy_Channelx->CCR |= DMA_IT;
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482 /* Disable the selected DMA interrupts */
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483 DMAy_Channelx->CCR &= ~DMA_IT;
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488 * @brief Checks whether the specified DMAy Channelx flag is set or not.
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489 * @param DMA_FLAG: specifies the flag to check.
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490 * This parameter can be one of the following values:
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491 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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492 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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493 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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494 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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495 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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496 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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497 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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498 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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499 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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500 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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501 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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502 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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503 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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504 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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505 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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506 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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507 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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508 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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509 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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510 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
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511 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
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512 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
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513 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
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514 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
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515 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
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516 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
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517 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
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518 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
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521 * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
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522 * relative to the same channel is set (Transfer Complete, Half-transfer
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523 * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
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526 * @retval The new state of DMA_FLAG (SET or RESET).
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528 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
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530 FlagStatus bitstatus = RESET;
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531 uint32_t tmpreg = 0;
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533 /* Check the parameters */
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534 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
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536 /* Calculate the used DMA */
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537 if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)
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539 /* Get DMA1 ISR register value */
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540 tmpreg = DMA1->ISR ;
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543 /* Check the status of the specified DMA flag */
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544 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
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546 /* DMA_FLAG is set */
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551 /* DMA_FLAG is reset */
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555 /* Return the DMA_FLAG status */
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560 * @brief Clears the DMAy Channelx's pending flags.
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561 * @param DMA_FLAG: specifies the flag to clear.
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562 * This parameter can be any combination (for the same DMA) of the following values:
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563 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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564 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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565 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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566 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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567 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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568 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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569 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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570 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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571 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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572 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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573 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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574 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
\r
575 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
\r
576 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
\r
577 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
\r
578 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
\r
579 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
\r
580 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
\r
581 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
\r
582 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
\r
583 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
\r
584 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
\r
585 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
\r
586 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
\r
587 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
\r
588 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
\r
589 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
\r
590 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
\r
593 * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
\r
594 * relative to the same channel (Transfer Complete, Half-transfer Complete and
\r
595 * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
\r
599 void DMA_ClearFlag(uint32_t DMA_FLAG)
\r
601 /* Check the parameters */
\r
602 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
\r
604 if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET)
\r
606 /* Clear the selected DMA flags */
\r
607 DMA1->IFCR = DMA_FLAG;
\r
612 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
\r
613 * @param DMA_IT: specifies the DMA interrupt source to check.
\r
614 * This parameter can be one of the following values:
\r
615 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
\r
616 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
\r
617 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
\r
618 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
\r
619 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
\r
620 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
\r
621 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
\r
622 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
\r
623 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
\r
624 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
\r
625 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
\r
626 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
\r
627 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
\r
628 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
\r
629 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
\r
630 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
\r
631 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
\r
632 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
\r
633 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
\r
634 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
\r
635 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
\r
636 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
\r
637 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
\r
638 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
\r
639 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
\r
640 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
\r
641 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
\r
642 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
\r
645 * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
\r
646 * interrupts relative to the same channel is set (Transfer Complete,
\r
647 * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
\r
648 * DMAy_IT_HTx or DMAy_IT_TEx).
\r
650 * @retval The new state of DMA_IT (SET or RESET).
\r
652 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
\r
654 ITStatus bitstatus = RESET;
\r
655 uint32_t tmpreg = 0;
\r
657 /* Check the parameters */
\r
658 assert_param(IS_DMA_GET_IT(DMA_IT));
\r
660 /* Calculate the used DMA */
\r
661 if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)
\r
663 /* Get DMA1 ISR register value */
\r
664 tmpreg = DMA1->ISR ;
\r
667 /* Check the status of the specified DMA interrupt */
\r
668 if ((tmpreg & DMA_IT) != (uint32_t)RESET)
\r
670 /* DMA_IT is set */
\r
675 /* DMA_IT is reset */
\r
678 /* Return the DMA_IT status */
\r
683 * @brief Clears the DMAy Channelx
\92s interrupt pending bits.
\r
684 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
\r
685 * This parameter can be any combination (for the same DMA) of the following values:
\r
686 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
\r
687 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
\r
688 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
\r
689 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
\r
690 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
\r
691 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
\r
692 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
\r
693 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
\r
694 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
\r
695 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
\r
696 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
\r
697 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
\r
698 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
\r
699 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
\r
700 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
\r
701 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
\r
702 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
\r
703 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
\r
704 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
\r
705 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
\r
706 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
\r
707 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
\r
708 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
\r
709 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
\r
710 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
\r
711 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
\r
712 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
\r
713 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
\r
716 * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
\r
717 * interrupts relative to the same channel (Transfer Complete, Half-transfer
\r
718 * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
\r
723 void DMA_ClearITPendingBit(uint32_t DMA_IT)
\r
725 /* Check the parameters */
\r
726 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
\r
728 /* Calculate the used DMA */
\r
729 if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET)
\r
731 /* Clear the selected DMA interrupt pending bits */
\r
732 DMA1->IFCR = DMA_IT;
\r
752 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r