2 ******************************************************************************
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3 * @file stm32l1xx_tim.h
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4 * @author MCD Application Team
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6 * @date 31-December-2010
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7 * @brief This file contains all the functions prototypes for the TIM firmware
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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20 ******************************************************************************
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef __STM32L1xx_TIM_H
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25 #define __STM32L1xx_TIM_H
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31 /* Includes ------------------------------------------------------------------*/
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32 #include "stm32l1xx.h"
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34 /** @addtogroup STM32L1xx_StdPeriph_Driver
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42 /* Exported types ------------------------------------------------------------*/
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45 * @brief TIM Time Base Init structure definition
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46 * @note This structure is used with all TIMx except for TIM6 and TIM7.
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51 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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52 This parameter can be a number between 0x0000 and 0xFFFF */
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54 uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
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55 This parameter can be a value of @ref TIM_Counter_Mode */
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57 uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
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58 Auto-Reload Register at the next update event.
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59 This parameter must be a number between 0x0000 and 0xFFFF. */
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61 uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
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62 This parameter can be a value of @ref TIM_Clock_Division_CKD */
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64 } TIM_TimeBaseInitTypeDef;
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67 * @brief TIM Output Compare Init structure definition
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72 uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
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73 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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75 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
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76 This parameter can be a value of @ref TIM_Output_Compare_state */
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78 uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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79 This parameter can be a number between 0x0000 and 0xFFFF */
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81 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
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82 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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84 } TIM_OCInitTypeDef;
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87 * @brief TIM Input Capture Init structure definition
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93 uint16_t TIM_Channel; /*!< Specifies the TIM channel.
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94 This parameter can be a value of @ref TIM_Channel */
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96 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
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97 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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99 uint16_t TIM_ICSelection; /*!< Specifies the input.
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100 This parameter can be a value of @ref TIM_Input_Capture_Selection */
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102 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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103 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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105 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
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106 This parameter can be a number between 0x0 and 0xF */
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107 } TIM_ICInitTypeDef;
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109 /* Exported constants --------------------------------------------------------*/
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112 /** @defgroup TIM_Exported_constants
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116 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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117 ((PERIPH) == TIM3) || \
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118 ((PERIPH) == TIM4) || \
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119 ((PERIPH) == TIM6) || \
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120 ((PERIPH) == TIM7) || \
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121 ((PERIPH) == TIM9) || \
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122 ((PERIPH) == TIM10) || \
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123 ((PERIPH) == TIM11))
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125 /* LIST1: TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11 */
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126 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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127 ((PERIPH) == TIM3) || \
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128 ((PERIPH) == TIM4) || \
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129 ((PERIPH) == TIM9) || \
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130 ((PERIPH) == TIM10) || \
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131 ((PERIPH) == TIM11))
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133 /* LIST3: TIM2, TIM3 and TIM4 */
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134 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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135 ((PERIPH) == TIM3) || \
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136 ((PERIPH) == TIM4))
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138 /* LIST2: TIM2, TIM3, TIM4 and TIM9 */
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139 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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140 ((PERIPH) == TIM3) || \
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141 ((PERIPH) == TIM4) ||\
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142 ((PERIPH) == TIM9))
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144 /* LIST5: TIM2, TIM3, TIM4, TIM6, TIM7 and TIM9 */
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145 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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146 ((PERIPH) == TIM3) || \
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147 ((PERIPH) == TIM4) ||\
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148 ((PERIPH) == TIM6) || \
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149 ((PERIPH) == TIM7) ||\
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150 ((PERIPH) == TIM9))
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152 /* LIST4: TIM2, TIM3, TIM4, TIM6 and TIM7 */
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153 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
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154 ((PERIPH) == TIM3) || \
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155 ((PERIPH) == TIM4) ||\
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156 ((PERIPH) == TIM6) || \
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157 ((PERIPH) == TIM7))
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159 /* LIST6: TIM9, TIM10 and TIM11 */
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160 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM9) || \
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161 ((PERIPH) == TIM10) ||\
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162 ((PERIPH) == TIM11))
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166 /** @defgroup TIM_Output_Compare_and_PWM_modes
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170 #define TIM_OCMode_Timing ((uint16_t)0x0000)
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171 #define TIM_OCMode_Active ((uint16_t)0x0010)
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172 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
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173 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
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174 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
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175 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
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176 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
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177 ((MODE) == TIM_OCMode_Active) || \
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178 ((MODE) == TIM_OCMode_Inactive) || \
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179 ((MODE) == TIM_OCMode_Toggle)|| \
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180 ((MODE) == TIM_OCMode_PWM1) || \
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181 ((MODE) == TIM_OCMode_PWM2))
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182 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
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183 ((MODE) == TIM_OCMode_Active) || \
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184 ((MODE) == TIM_OCMode_Inactive) || \
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185 ((MODE) == TIM_OCMode_Toggle)|| \
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186 ((MODE) == TIM_OCMode_PWM1) || \
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187 ((MODE) == TIM_OCMode_PWM2) || \
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188 ((MODE) == TIM_ForcedAction_Active) || \
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189 ((MODE) == TIM_ForcedAction_InActive))
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194 /** @defgroup TIM_One_Pulse_Mode
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198 #define TIM_OPMode_Single ((uint16_t)0x0008)
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199 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
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200 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
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201 ((MODE) == TIM_OPMode_Repetitive))
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206 /** @defgroup TIM_Channel
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210 #define TIM_Channel_1 ((uint16_t)0x0000)
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211 #define TIM_Channel_2 ((uint16_t)0x0004)
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212 #define TIM_Channel_3 ((uint16_t)0x0008)
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213 #define TIM_Channel_4 ((uint16_t)0x000C)
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215 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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216 ((CHANNEL) == TIM_Channel_2) || \
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217 ((CHANNEL) == TIM_Channel_3) || \
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218 ((CHANNEL) == TIM_Channel_4))
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220 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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221 ((CHANNEL) == TIM_Channel_2))
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227 /** @defgroup TIM_Clock_Division_CKD
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231 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
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232 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
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233 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
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234 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
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235 ((DIV) == TIM_CKD_DIV2) || \
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236 ((DIV) == TIM_CKD_DIV4))
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241 /** @defgroup TIM_Counter_Mode
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245 #define TIM_CounterMode_Up ((uint16_t)0x0000)
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246 #define TIM_CounterMode_Down ((uint16_t)0x0010)
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247 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
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248 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
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249 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
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250 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
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251 ((MODE) == TIM_CounterMode_Down) || \
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252 ((MODE) == TIM_CounterMode_CenterAligned1) || \
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253 ((MODE) == TIM_CounterMode_CenterAligned2) || \
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254 ((MODE) == TIM_CounterMode_CenterAligned3))
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259 /** @defgroup TIM_Output_Compare_Polarity
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263 #define TIM_OCPolarity_High ((uint16_t)0x0000)
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264 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
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265 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
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266 ((POLARITY) == TIM_OCPolarity_Low))
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272 /** @defgroup TIM_Output_Compare_state
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276 #define TIM_OutputState_Disable ((uint16_t)0x0000)
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277 #define TIM_OutputState_Enable ((uint16_t)0x0001)
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278 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
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279 ((STATE) == TIM_OutputState_Enable))
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285 /** @defgroup TIM_Capture_Compare_state
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289 #define TIM_CCx_Enable ((uint16_t)0x0001)
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290 #define TIM_CCx_Disable ((uint16_t)0x0000)
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291 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
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292 ((CCX) == TIM_CCx_Disable))
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297 /** @defgroup TIM_Input_Capture_Polarity
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301 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
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302 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
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303 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
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304 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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305 ((POLARITY) == TIM_ICPolarity_Falling)|| \
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306 ((POLARITY) == TIM_ICPolarity_BothEdge))
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311 /** @defgroup TIM_Input_Capture_Selection
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315 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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316 connected to IC1, IC2, IC3 or IC4, respectively */
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317 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
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318 connected to IC2, IC1, IC4 or IC3, respectively. */
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319 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
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320 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
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321 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
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322 ((SELECTION) == TIM_ICSelection_TRC))
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327 /** @defgroup TIM_Input_Capture_Prescaler
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331 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
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332 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
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333 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
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334 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
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335 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
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336 ((PRESCALER) == TIM_ICPSC_DIV2) || \
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337 ((PRESCALER) == TIM_ICPSC_DIV4) || \
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338 ((PRESCALER) == TIM_ICPSC_DIV8))
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343 /** @defgroup TIM_interrupt_sources
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347 #define TIM_IT_Update ((uint16_t)0x0001)
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348 #define TIM_IT_CC1 ((uint16_t)0x0002)
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349 #define TIM_IT_CC2 ((uint16_t)0x0004)
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350 #define TIM_IT_CC3 ((uint16_t)0x0008)
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351 #define TIM_IT_CC4 ((uint16_t)0x0010)
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352 #define TIM_IT_Trigger ((uint16_t)0x0040)
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353 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
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355 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
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356 ((IT) == TIM_IT_CC1) || \
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357 ((IT) == TIM_IT_CC2) || \
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358 ((IT) == TIM_IT_CC3) || \
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359 ((IT) == TIM_IT_CC4) || \
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360 ((IT) == TIM_IT_Trigger))
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365 /** @defgroup TIM_DMA_Base_address
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369 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
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370 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
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371 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
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372 #define TIM_DMABase_DIER ((uint16_t)0x0003)
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373 #define TIM_DMABase_SR ((uint16_t)0x0004)
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374 #define TIM_DMABase_EGR ((uint16_t)0x0005)
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375 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
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376 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
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377 #define TIM_DMABase_CCER ((uint16_t)0x0008)
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378 #define TIM_DMABase_CNT ((uint16_t)0x0009)
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379 #define TIM_DMABase_PSC ((uint16_t)0x000A)
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380 #define TIM_DMABase_ARR ((uint16_t)0x000B)
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381 #define TIM_DMABase_RCR ((uint16_t)0x000C)
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382 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
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383 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
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384 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
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385 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
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386 #define TIM_DMABase_DCR ((uint16_t)0x0012)
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387 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
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388 ((BASE) == TIM_DMABase_CR2) || \
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389 ((BASE) == TIM_DMABase_SMCR) || \
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390 ((BASE) == TIM_DMABase_DIER) || \
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391 ((BASE) == TIM_DMABase_SR) || \
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392 ((BASE) == TIM_DMABase_EGR) || \
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393 ((BASE) == TIM_DMABase_CCMR1) || \
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394 ((BASE) == TIM_DMABase_CCMR2) || \
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395 ((BASE) == TIM_DMABase_CCER) || \
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396 ((BASE) == TIM_DMABase_CNT) || \
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397 ((BASE) == TIM_DMABase_PSC) || \
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398 ((BASE) == TIM_DMABase_ARR) || \
\r
399 ((BASE) == TIM_DMABase_CCR1) || \
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400 ((BASE) == TIM_DMABase_CCR2) || \
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401 ((BASE) == TIM_DMABase_CCR3) || \
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402 ((BASE) == TIM_DMABase_CCR4) || \
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403 ((BASE) == TIM_DMABase_DCR))
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408 /** @defgroup TIM_DMA_Burst_Length
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412 #define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
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413 #define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
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414 #define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
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415 #define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
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416 #define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
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417 #define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
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418 #define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
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419 #define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
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420 #define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
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421 #define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
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422 #define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
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423 #define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
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424 #define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
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425 #define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
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426 #define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
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427 #define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
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428 #define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
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429 #define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
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430 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
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431 ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
\r
432 ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
\r
433 ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
\r
434 ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
\r
435 ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
\r
436 ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
\r
437 ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
\r
438 ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
\r
439 ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
\r
440 ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
\r
441 ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
\r
442 ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
\r
443 ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
\r
444 ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
\r
445 ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
\r
446 ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
\r
447 ((LENGTH) == TIM_DMABurstLength_18Bytes))
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452 /** @defgroup TIM_DMA_sources
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456 #define TIM_DMA_Update ((uint16_t)0x0100)
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457 #define TIM_DMA_CC1 ((uint16_t)0x0200)
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458 #define TIM_DMA_CC2 ((uint16_t)0x0400)
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459 #define TIM_DMA_CC3 ((uint16_t)0x0800)
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460 #define TIM_DMA_CC4 ((uint16_t)0x1000)
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461 #define TIM_DMA_Trigger ((uint16_t)0x4000)
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462 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
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468 /** @defgroup TIM_External_Trigger_Prescaler
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472 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
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473 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
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474 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
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475 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
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476 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
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477 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
\r
478 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
\r
479 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
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484 /** @defgroup TIM_Internal_Trigger_Selection
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488 #define TIM_TS_ITR0 ((uint16_t)0x0000)
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489 #define TIM_TS_ITR1 ((uint16_t)0x0010)
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490 #define TIM_TS_ITR2 ((uint16_t)0x0020)
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491 #define TIM_TS_ITR3 ((uint16_t)0x0030)
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492 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
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493 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
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494 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
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495 #define TIM_TS_ETRF ((uint16_t)0x0070)
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496 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
\r
497 ((SELECTION) == TIM_TS_ITR1) || \
\r
498 ((SELECTION) == TIM_TS_ITR2) || \
\r
499 ((SELECTION) == TIM_TS_ITR3) || \
\r
500 ((SELECTION) == TIM_TS_TI1F_ED) || \
\r
501 ((SELECTION) == TIM_TS_TI1FP1) || \
\r
502 ((SELECTION) == TIM_TS_TI2FP2) || \
\r
503 ((SELECTION) == TIM_TS_ETRF))
\r
504 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
\r
505 ((SELECTION) == TIM_TS_ITR1) || \
\r
506 ((SELECTION) == TIM_TS_ITR2) || \
\r
507 ((SELECTION) == TIM_TS_ITR3))
\r
512 /** @defgroup TIM_TIx_External_Clock_Source
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516 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
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517 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
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518 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
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524 /** @defgroup TIM_External_Trigger_Polarity
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527 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
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528 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
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529 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
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530 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
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535 /** @defgroup TIM_Prescaler_Reload_Mode
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539 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
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540 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
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541 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
\r
542 ((RELOAD) == TIM_PSCReloadMode_Immediate))
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547 /** @defgroup TIM_Forced_Action
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551 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
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552 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
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553 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
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554 ((ACTION) == TIM_ForcedAction_InActive))
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559 /** @defgroup TIM_Encoder_Mode
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563 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
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564 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
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565 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
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566 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
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567 ((MODE) == TIM_EncoderMode_TI2) || \
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568 ((MODE) == TIM_EncoderMode_TI12))
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574 /** @defgroup TIM_Event_Source
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578 #define TIM_EventSource_Update ((uint16_t)0x0001)
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579 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
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580 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
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581 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
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582 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
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583 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
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584 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
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590 /** @defgroup TIM_Update_Source
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594 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
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595 or the setting of UG bit, or an update generation
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596 through the slave mode controller. */
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597 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
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598 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
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599 ((SOURCE) == TIM_UpdateSource_Regular))
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604 /** @defgroup TIM_Output_Compare_Preload_State
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608 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
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609 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
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610 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
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611 ((STATE) == TIM_OCPreload_Disable))
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616 /** @defgroup TIM_Output_Compare_Fast_State
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620 #define TIM_OCFast_Enable ((uint16_t)0x0004)
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621 #define TIM_OCFast_Disable ((uint16_t)0x0000)
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622 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
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623 ((STATE) == TIM_OCFast_Disable))
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629 /** @defgroup TIM_Output_Compare_Clear_State
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633 #define TIM_OCClear_Enable ((uint16_t)0x0080)
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634 #define TIM_OCClear_Disable ((uint16_t)0x0000)
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635 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
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636 ((STATE) == TIM_OCClear_Disable))
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641 /** @defgroup TIM_Trigger_Output_Source
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645 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
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646 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
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647 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
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648 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
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649 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
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650 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
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651 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
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652 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
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653 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
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654 ((SOURCE) == TIM_TRGOSource_Enable) || \
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655 ((SOURCE) == TIM_TRGOSource_Update) || \
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656 ((SOURCE) == TIM_TRGOSource_OC1) || \
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657 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
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658 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
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659 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
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660 ((SOURCE) == TIM_TRGOSource_OC4Ref))
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665 /** @defgroup TIM_Slave_Mode
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669 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
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670 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
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671 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
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672 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
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673 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
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674 ((MODE) == TIM_SlaveMode_Gated) || \
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675 ((MODE) == TIM_SlaveMode_Trigger) || \
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676 ((MODE) == TIM_SlaveMode_External1))
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681 /** @defgroup TIM_Master_Slave_Mode
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685 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
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686 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
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687 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
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688 ((STATE) == TIM_MasterSlaveMode_Disable))
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693 /** @defgroup TIM_Flags
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697 #define TIM_FLAG_Update ((uint16_t)0x0001)
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698 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
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699 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
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700 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
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701 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
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702 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
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703 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
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704 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
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705 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
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706 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
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707 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
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708 ((FLAG) == TIM_FLAG_CC1) || \
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709 ((FLAG) == TIM_FLAG_CC2) || \
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710 ((FLAG) == TIM_FLAG_CC3) || \
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711 ((FLAG) == TIM_FLAG_CC4) || \
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712 ((FLAG) == TIM_FLAG_Trigger) || \
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713 ((FLAG) == TIM_FLAG_CC1OF) || \
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714 ((FLAG) == TIM_FLAG_CC2OF) || \
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715 ((FLAG) == TIM_FLAG_CC3OF) || \
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716 ((FLAG) == TIM_FLAG_CC4OF))
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717 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
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723 /** @defgroup TIM_Input_Capture_Filer_Value
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727 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
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732 /** @defgroup TIM_External_Trigger_Filter
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736 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
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741 /** @defgroup TIM_OCReferenceClear
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744 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
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745 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
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746 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
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747 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
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753 /** @defgroup TIM_Remap
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757 #define TIM9_GPIO ((uint16_t)0x0000)
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758 #define TIM9_LSE ((uint16_t)0x0001)
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760 #define TIM10_GPIO ((uint16_t)0x0000)
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761 #define TIM10_LSI ((uint16_t)0x0001)
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762 #define TIM10_LSE ((uint16_t)0x0002)
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763 #define TIM10_RTC ((uint16_t)0x0003)
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765 #define TIM11_GPIO ((uint16_t)0x0000)
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766 #define TIM11_MSI ((uint16_t)0x0001)
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767 #define TIM11_HSE_RTC ((uint16_t)0x0002)
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769 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\
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770 ((TIM_REMAP) == TIM9_LSE)||\
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771 ((TIM_REMAP) == TIM10_GPIO)||\
\r
772 ((TIM_REMAP) == TIM10_LSI)||\
\r
773 ((TIM_REMAP) == TIM10_LSE)||\
\r
774 ((TIM_REMAP) == TIM10_RTC)||\
\r
775 ((TIM_REMAP) == TIM11_GPIO)||\
\r
776 ((TIM_REMAP) == TIM11_MSI)||\
\r
777 ((TIM_REMAP) == TIM11_HSE_RTC))
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787 /* Exported macro ------------------------------------------------------------*/
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788 /* Exported functions ------------------------------------------------------- */
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790 /* TimeBase management ********************************************************/
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791 void TIM_DeInit(TIM_TypeDef* TIMx);
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792 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
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793 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
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794 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
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795 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
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796 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
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797 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
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798 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
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799 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
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800 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
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801 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
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802 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
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803 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
\r
804 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
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805 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
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807 /* Output Compare management **************************************************/
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808 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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809 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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810 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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811 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
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812 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
\r
813 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
\r
814 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
\r
815 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
\r
816 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
\r
817 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
\r
818 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
\r
819 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
\r
820 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
\r
821 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
\r
822 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
\r
823 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
\r
824 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
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825 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
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826 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
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827 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
\r
828 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
\r
829 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
\r
830 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
\r
831 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
\r
832 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
\r
833 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
\r
834 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
\r
835 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
\r
836 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
\r
837 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
\r
838 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
\r
839 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
\r
841 /* Input Capture management ***************************************************/
\r
842 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
843 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
844 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
\r
845 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
\r
846 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
\r
847 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
\r
848 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
\r
849 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
\r
850 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
\r
851 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
\r
852 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
\r
854 /* Interrupts, DMA and flags management ***************************************/
\r
855 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
\r
856 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
\r
857 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
\r
858 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
\r
859 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
\r
860 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
\r
861 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
\r
862 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
\r
863 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
865 /* Clocks management **********************************************************/
\r
866 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
\r
867 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
\r
868 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
869 uint16_t TIM_ICPolarity, uint16_t ICFilter);
\r
870 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
871 uint16_t ExtTRGFilter);
\r
872 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
873 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
\r
876 /* Synchronization management *************************************************/
\r
877 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
\r
878 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
\r
879 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
\r
880 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
\r
881 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
882 uint16_t ExtTRGFilter);
\r
884 /* Specific interface management **********************************************/
\r
885 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
886 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
\r
887 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
\r
889 /* Specific remapping management **********************************************/
\r
890 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
\r
897 #endif /*__STM32L1xx_TIM_H */
\r
907 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r