2 ******************************************************************************
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3 * @file stm32l1xx_tim.c
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4 * @author MCD Application Team
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6 * @date 31-December-2010
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7 * @brief This file provides firmware functions to manage the following
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8 * functionalities of the TIM peripheral:
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9 * - TimeBase management
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10 * - Output Compare management
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11 * - Input Capture management
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12 * - Interrupts, DMA and flags management
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13 * - Clocks management
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14 * - Synchronization management
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15 * - Specific interface management
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16 * - Specific remapping management
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20 * ===================================================================
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21 * How to use this driver
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22 * ===================================================================
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23 * This driver provides functions to configure and program the TIM
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24 * of all STM32L1xx devices
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25 * These functions are split in 8 groups:
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27 * 1. TIM TimeBase management: this group includes all needed functions
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28 * to configure the TM Timebase unit:
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29 * - Set/Get Prescaler
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30 * - Set/Get Autoreload
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31 * - Counter modes configuration
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32 * - Set Clock division
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33 * - Select the One Pulse mode
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34 * - Update Request Configuration
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35 * - Update Disable Configuration
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36 * - Auto-Preload Configuration
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37 * - Enable/Disable the counter
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39 * 2. TIM Output Compare management: this group includes all needed
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40 * functions to configure the Capture/Compare unit used in Output
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42 * - Configure each channel, independently, in Output Compare mode
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43 * - Select the output compare modes
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44 * - Select the Polarities of each channel
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45 * - Set/Get the Capture/Compare register values
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46 * - Select the Output Compare Fast mode
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47 * - Select the Output Compare Forced mode
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48 * - Output Compare-Preload Configuration
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49 * - Clear Output Compare Reference
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50 * - Select the OCREF Clear signal
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51 * - Enable/Disable the Capture/Compare Channels
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53 * 3. TIM Input Capture management: this group includes all needed
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54 * functions to configure the Capture/Compare unit used in
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55 * Input Capture mode:
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56 * - Configure each channel in input capture mode
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57 * - Configure Channel1/2 in PWM Input mode
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58 * - Set the Input Capture Prescaler
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59 * - Get the Capture/Compare values
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61 * 4. TIM interrupts, DMA and flags management
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62 * - Enable/Disable interrupt sources
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63 * - Get flags status
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64 * - Clear flags/ Pending bits
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65 * - Enable/Disable DMA requests
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66 * - Configure DMA burst mode
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67 * - Select CaptureCompare DMA request
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69 * 5. TIM clocks management: this group includes all needed functions
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70 * to configure the clock controller unit:
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71 * - Select internal/External clock
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72 * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
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74 * 6. TIM synchronization management: this group includes all needed
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75 * functions to configure the Synchronization unit:
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76 * - Select Input Trigger
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77 * - Select Output Trigger
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78 * - Select Master Slave Mode
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79 * - ETR Configuration when used as external trigger
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81 * 7. TIM specific interface management, this group includes all
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82 * needed functions to use the specific TIM interface:
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83 * - Encoder Interface Configuration
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84 * - Select Hall Sensor
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86 * 8. TIM specific remapping management includes the Remapping
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87 * configuration of specific timers
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91 ******************************************************************************
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94 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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95 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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96 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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97 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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98 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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99 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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101 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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102 ******************************************************************************
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105 /* Includes ------------------------------------------------------------------*/
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106 #include "stm32l1xx_tim.h"
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107 #include "stm32l1xx_rcc.h"
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109 /** @addtogroup STM32L1xx_StdPeriph_Driver
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114 * @brief TIM driver modules
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118 /* Private typedef -----------------------------------------------------------*/
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119 /* Private define ------------------------------------------------------------*/
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121 /* ---------------------- TIM registers bit mask ------------------------ */
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122 #define SMCR_ETR_MASK ((uint16_t)0x00FF)
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123 #define CCMR_OFFSET ((uint16_t)0x0018)
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124 #define CCER_CCE_SET ((uint16_t)0x0001)
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126 /* Private macro -------------------------------------------------------------*/
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127 /* Private variables ---------------------------------------------------------*/
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128 /* Private function prototypes -----------------------------------------------*/
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130 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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131 uint16_t TIM_ICFilter);
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132 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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133 uint16_t TIM_ICFilter);
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134 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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135 uint16_t TIM_ICFilter);
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136 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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137 uint16_t TIM_ICFilter);
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138 /* Private functions ---------------------------------------------------------*/
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140 /** @defgroup TIM_Private_Functions
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144 /** @defgroup TIM_Group1 TimeBase management functions
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145 * @brief TimeBase management functions
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148 ===============================================================================
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149 TimeBase management functions
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150 ===============================================================================
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152 ===================================================================
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153 TIM Driver: how to use it in Timing(Time base) Mode
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154 ===================================================================
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155 To use the Timer in Timing(Time base) mode, the following steps are mandatory:
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157 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
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159 2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
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161 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
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162 with the corresponding configuration
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164 4. Enable the NVIC if you need to generate the update interrupt.
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166 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update)
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168 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
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170 Note1: All other functions can be used seperatly to modify, if needed,
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171 a specific feature of the Timer.
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178 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
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179 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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183 void TIM_DeInit(TIM_TypeDef* TIMx)
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185 /* Check the parameters */
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186 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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190 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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191 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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193 else if (TIMx == TIM3)
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195 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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196 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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198 else if (TIMx == TIM4)
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200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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201 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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204 else if (TIMx == TIM6)
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206 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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207 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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209 else if (TIMx == TIM7)
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211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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215 else if (TIMx == TIM9)
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217 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
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218 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
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220 else if (TIMx == TIM10)
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222 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
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223 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
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229 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
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230 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
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237 * @brief Initializes the TIMx Time Base Unit peripheral according to
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238 * the specified parameters in the TIM_TimeBaseInitStruct.
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239 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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240 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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241 * structure that contains the configuration information for
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242 * the specified TIM peripheral.
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245 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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247 uint16_t tmpcr1 = 0;
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249 /* Check the parameters */
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250 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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251 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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252 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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254 tmpcr1 = TIMx->CR1;
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256 if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4))
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258 /* Select the Counter Mode */
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259 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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260 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
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263 if(((TIMx) != TIM6) && ((TIMx) != TIM7))
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265 /* Set the clock division */
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266 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
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267 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
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270 TIMx->CR1 = tmpcr1;
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272 /* Set the Autoreload value */
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273 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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275 /* Set the Prescaler value */
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276 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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278 /* Generate an update event to reload the Prescaler value immediatly */
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279 TIMx->EGR = TIM_PSCReloadMode_Immediate;
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283 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
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284 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
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285 * structure which will be initialized.
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288 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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290 /* Set the default configuration */
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291 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
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292 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
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293 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
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294 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
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298 * @brief Configures the TIMx Prescaler.
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299 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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300 * @param Prescaler: specifies the Prescaler Register value
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301 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
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302 * This parameter can be one of the following values:
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303 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
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304 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
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307 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
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309 /* Check the parameters */
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310 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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311 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
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313 /* Set the Prescaler value */
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314 TIMx->PSC = Prescaler;
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315 /* Set or reset the UG Bit */
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316 TIMx->EGR = TIM_PSCReloadMode;
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320 * @brief Specifies the TIMx Counter Mode to be used.
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321 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
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322 * @param TIM_CounterMode: specifies the Counter Mode to be used
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323 * This parameter can be one of the following values:
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324 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
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325 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
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326 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
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327 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
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328 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
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331 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
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333 uint16_t tmpcr1 = 0;
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335 /* Check the parameters */
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336 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
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337 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
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339 tmpcr1 = TIMx->CR1;
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340 /* Reset the CMS and DIR Bits */
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341 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
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342 /* Set the Counter Mode */
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343 tmpcr1 |= TIM_CounterMode;
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344 /* Write to TIMx CR1 register */
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345 TIMx->CR1 = tmpcr1;
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349 * @brief Sets the TIMx Counter Register value
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350 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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351 * @param Counter: specifies the Counter register new value.
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354 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
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356 /* Check the parameters */
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357 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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359 /* Set the Counter Register value */
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360 TIMx->CNT = Counter;
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364 * @brief Sets the TIMx Autoreload Register value
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365 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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366 * @param Autoreload: specifies the Autoreload register new value.
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369 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
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371 /* Check the parameters */
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372 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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374 /* Set the Autoreload Register value */
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375 TIMx->ARR = Autoreload;
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379 * @brief Gets the TIMx Counter value.
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380 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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381 * @retval Counter Register value.
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383 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
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385 /* Check the parameters */
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386 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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388 /* Get the Counter Register value */
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393 * @brief Gets the TIMx Prescaler value.
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394 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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395 * @retval Prescaler Register value.
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397 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
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399 /* Check the parameters */
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400 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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402 /* Get the Prescaler Register value */
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407 * @brief Enables or Disables the TIMx Update event.
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408 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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409 * @param NewState: new state of the TIMx UDIS bit
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410 * This parameter can be: ENABLE or DISABLE.
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413 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
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415 /* Check the parameters */
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416 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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417 assert_param(IS_FUNCTIONAL_STATE(NewState));
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419 if (NewState != DISABLE)
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421 /* Set the Update Disable Bit */
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422 TIMx->CR1 |= TIM_CR1_UDIS;
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426 /* Reset the Update Disable Bit */
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427 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
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432 * @brief Configures the TIMx Update Request Interrupt source.
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433 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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434 * @param TIM_UpdateSource: specifies the Update source.
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435 * This parameter can be one of the following values:
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436 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
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437 or the setting of UG bit, or an update generation
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438 through the slave mode controller.
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439 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
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442 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
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444 /* Check the parameters */
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445 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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446 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
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448 if (TIM_UpdateSource != TIM_UpdateSource_Global)
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450 /* Set the URS Bit */
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451 TIMx->CR1 |= TIM_CR1_URS;
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455 /* Reset the URS Bit */
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456 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
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461 * @brief Enables or disables TIMx peripheral Preload register on ARR.
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462 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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463 * @param NewState: new state of the TIMx peripheral Preload register
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464 * This parameter can be: ENABLE or DISABLE.
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467 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
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469 /* Check the parameters */
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470 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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471 assert_param(IS_FUNCTIONAL_STATE(NewState));
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473 if (NewState != DISABLE)
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475 /* Set the ARR Preload Bit */
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476 TIMx->CR1 |= TIM_CR1_ARPE;
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480 /* Reset the ARR Preload Bit */
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481 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
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486 * @brief Selects the TIMx
\92s One Pulse Mode.
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487 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
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488 * @param TIM_OPMode: specifies the OPM Mode to be used.
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489 * This parameter can be one of the following values:
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490 * @arg TIM_OPMode_Single
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491 * @arg TIM_OPMode_Repetitive
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494 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
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496 /* Check the parameters */
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497 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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498 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
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500 /* Reset the OPM Bit */
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501 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
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502 /* Configure the OPM Mode */
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503 TIMx->CR1 |= TIM_OPMode;
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507 * @brief Sets the TIMx Clock Division value.
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508 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
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509 * @param TIM_CKD: specifies the clock division value.
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510 * This parameter can be one of the following value:
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511 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
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512 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
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513 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
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516 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
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518 /* Check the parameters */
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519 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
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520 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
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522 /* Reset the CKD Bits */
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523 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
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524 /* Set the CKD value */
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525 TIMx->CR1 |= TIM_CKD;
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529 * @brief Enables or disables the specified TIM peripheral.
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530 * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
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531 * @param NewState: new state of the TIMx peripheral.
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532 * This parameter can be: ENABLE or DISABLE.
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535 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
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537 /* Check the parameters */
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538 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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539 assert_param(IS_FUNCTIONAL_STATE(NewState));
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541 if (NewState != DISABLE)
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543 /* Enable the TIM Counter */
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544 TIMx->CR1 |= TIM_CR1_CEN;
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548 /* Disable the TIM Counter */
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549 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
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557 /** @defgroup TIM_Group2 Output Compare management functions
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558 * @brief Output Compare management functions
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561 ===============================================================================
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562 Output Compare management functions
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563 ===============================================================================
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565 ===================================================================
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566 TIM Driver: how to use it in Output Compare Mode
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567 ===================================================================
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568 To use the Timer in Output Compare mode, the following steps are mandatory:
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570 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
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572 2. Configure the TIM pins by configuring the corresponding GPIO pins
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574 2. Configure the Time base unit as described in the first part of this driver, if needed,
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575 else the Timer will run with the default configuration:
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576 - Autoreload value = 0xFFFF
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577 - Prescaler value = 0x0000
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578 - Counter mode = Up counting
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579 - Clock Division = TIM_CKD_DIV1
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581 3. Fill the TIM_OCInitStruct with the desired parameters including:
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582 - The TIM Output Compare mode: TIM_OCMode
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583 - TIM Output State: TIM_OutputState
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584 - TIM Pulse value: TIM_Pulse
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585 - TIM Output Compare Polarity : TIM_OCPolarity
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587 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the
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588 corresponding configuration
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590 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
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592 Note1: All other functions can be used separately to modify, if needed,
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593 a specific feature of the Timer.
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595 Note2: In case of PWM mode, this function is mandatory:
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596 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE);
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598 Note3: If the corresponding interrupt or DMA request are needed, the user should:
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599 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
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600 2. Enable the corresponding interrupt (or DMA request) using the function
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601 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
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608 * @brief Initializes the TIMx Channel1 according to the specified
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609 * parameters in the TIM_OCInitStruct.
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610 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
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611 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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612 * that contains the configuration information for the specified TIM
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616 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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618 uint16_t tmpccmrx = 0, tmpccer = 0;
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620 /* Check the parameters */
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621 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
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622 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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623 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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624 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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625 /* Disable the Channel 1: Reset the CC1E Bit */
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626 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
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628 /* Get the TIMx CCER register value */
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629 tmpccer = TIMx->CCER;
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631 /* Get the TIMx CCMR1 register value */
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632 tmpccmrx = TIMx->CCMR1;
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634 /* Reset the Output Compare Mode Bits */
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635 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
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636 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
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638 /* Select the Output Compare Mode */
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639 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\r
641 /* Reset the Output Polarity level */
\r
642 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
\r
643 /* Set the Output Compare Polarity */
\r
644 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
\r
646 /* Set the Output State */
\r
647 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
\r
649 /* Set the Capture Compare Register value */
\r
650 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
\r
652 /* Write to TIMx CCMR1 */
\r
653 TIMx->CCMR1 = tmpccmrx;
\r
655 /* Write to TIMx CCER */
\r
656 TIMx->CCER = tmpccer;
\r
660 * @brief Initializes the TIMx Channel2 according to the specified
\r
661 * parameters in the TIM_OCInitStruct.
\r
662 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
663 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
664 * that contains the configuration information for the specified TIM
\r
668 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
670 uint16_t tmpccmrx = 0, tmpccer = 0;
\r
672 /* Check the parameters */
\r
673 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
674 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
675 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
676 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
677 /* Disable the Channel 2: Reset the CC2E Bit */
\r
678 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
\r
680 /* Get the TIMx CCER register value */
\r
681 tmpccer = TIMx->CCER;
\r
683 /* Get the TIMx CCMR1 register value */
\r
684 tmpccmrx = TIMx->CCMR1;
\r
686 /* Reset the Output Compare Mode Bits */
\r
687 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
\r
689 /* Select the Output Compare Mode */
\r
690 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
692 /* Reset the Output Polarity level */
\r
693 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
\r
694 /* Set the Output Compare Polarity */
\r
695 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
\r
697 /* Set the Output State */
\r
698 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
\r
700 /* Set the Capture Compare Register value */
\r
701 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
\r
703 /* Write to TIMx CCMR1 */
\r
704 TIMx->CCMR1 = tmpccmrx;
\r
706 /* Write to TIMx CCER */
\r
707 TIMx->CCER = tmpccer;
\r
711 * @brief Initializes the TIMx Channel3 according to the specified
\r
712 * parameters in the TIM_OCInitStruct.
\r
713 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
714 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
715 * that contains the configuration information for the specified TIM
\r
719 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
721 uint16_t tmpccmrx = 0, tmpccer = 0;
\r
723 /* Check the parameters */
\r
724 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
725 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
726 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
727 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
729 /* Disable the Channel 2: Reset the CC2E Bit */
\r
730 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
\r
732 /* Get the TIMx CCER register value */
\r
733 tmpccer = TIMx->CCER;
\r
735 /* Get the TIMx CCMR2 register value */
\r
736 tmpccmrx = TIMx->CCMR2;
\r
738 /* Reset the Output Compare Mode Bits */
\r
739 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
\r
741 /* Select the Output Compare Mode */
\r
742 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
\r
744 /* Reset the Output Polarity level */
\r
745 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
\r
746 /* Set the Output Compare Polarity */
\r
747 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
\r
749 /* Set the Output State */
\r
750 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
\r
752 /* Set the Capture Compare Register value */
\r
753 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
\r
755 /* Write to TIMx CCMR2 */
\r
756 TIMx->CCMR2 = tmpccmrx;
\r
758 /* Write to TIMx CCER */
\r
759 TIMx->CCER = tmpccer;
\r
763 * @brief Initializes the TIMx Channel4 according to the specified
\r
764 * parameters in the TIM_OCInitStruct.
\r
765 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
766 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
\r
767 * that contains the configuration information for the specified TIM
\r
771 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
773 uint16_t tmpccmrx = 0, tmpccer = 0;
\r
775 /* Check the parameters */
\r
776 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
777 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
\r
778 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
\r
779 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
781 /* Disable the Channel 2: Reset the CC4E Bit */
\r
782 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
\r
784 /* Get the TIMx CCER register value */
\r
785 tmpccer = TIMx->CCER;
\r
787 /* Get the TIMx CCMR2 register value */
\r
788 tmpccmrx = TIMx->CCMR2;
\r
790 /* Reset the Output Compare Mode Bits */
\r
791 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
\r
793 /* Select the Output Compare Mode */
\r
794 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
796 /* Reset the Output Polarity level */
\r
797 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
\r
798 /* Set the Output Compare Polarity */
\r
799 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
\r
801 /* Set the Output State */
\r
802 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
\r
804 /* Set the Capture Compare Register value */
\r
805 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
\r
807 /* Write to TIMx CCMR2 */
\r
808 TIMx->CCMR2 = tmpccmrx;
\r
810 /* Write to TIMx CCER */
\r
811 TIMx->CCER = tmpccer;
\r
815 * @brief Fills each TIM_OCInitStruct member with its default value.
\r
816 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
\r
820 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
822 /* Set the default configuration */
\r
823 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
\r
824 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
\r
825 TIM_OCInitStruct->TIM_Pulse = 0x0000;
\r
826 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
\r
830 * @brief Selects the TIM Output Compare Mode.
\r
831 * @note This function disables the selected channel before changing the Output
\r
833 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
\r
834 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
835 * @param TIM_Channel: specifies the TIM Channel
\r
836 * This parameter can be one of the following values:
\r
837 * @arg TIM_Channel_1: TIM Channel 1
\r
838 * @arg TIM_Channel_2: TIM Channel 2
\r
839 * @arg TIM_Channel_3: TIM Channel 3
\r
840 * @arg TIM_Channel_4: TIM Channel 4
\r
841 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
\r
842 * This parameter can be one of the following values:
\r
843 * @arg TIM_OCMode_Timing
\r
844 * @arg TIM_OCMode_Active
\r
845 * @arg TIM_OCMode_Toggle
\r
846 * @arg TIM_OCMode_PWM1
\r
847 * @arg TIM_OCMode_PWM2
\r
848 * @arg TIM_ForcedAction_Active
\r
849 * @arg TIM_ForcedAction_InActive
\r
852 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
\r
857 /* Check the parameters */
\r
858 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
859 assert_param(IS_TIM_OCM(TIM_OCMode));
\r
861 tmp = (uint32_t) TIMx;
\r
862 tmp += CCMR_OFFSET;
\r
864 tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
\r
866 /* Disable the Channel: Reset the CCxE Bit */
\r
867 TIMx->CCER &= (uint16_t) ~tmp1;
\r
869 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
\r
871 tmp += (TIM_Channel>>1);
\r
873 /* Reset the OCxM bits in the CCMRx register */
\r
874 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
\r
876 /* Configure the OCxM bits in the CCMRx register */
\r
877 *(__IO uint32_t *) tmp |= TIM_OCMode;
\r
881 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
\r
883 /* Reset the OCxM bits in the CCMRx register */
\r
884 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
\r
886 /* Configure the OCxM bits in the CCMRx register */
\r
887 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
\r
892 * @brief Sets the TIMx Capture Compare1 Register value
\r
893 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
894 * @param Compare1: specifies the Capture Compare1 register new value.
\r
898 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
\r
900 /* Check the parameters */
\r
901 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
903 /* Set the Capture Compare1 Register value */
\r
904 TIMx->CCR1 = Compare1;
\r
908 * @brief Sets the TIMx Capture Compare2 Register value
\r
909 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
910 * @param Compare2: specifies the Capture Compare2 register new value.
\r
914 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
\r
916 /* Check the parameters */
\r
917 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
919 /* Set the Capture Compare2 Register value */
\r
920 TIMx->CCR2 = Compare2;
\r
924 * @brief Sets the TIMx Capture Compare3 Register value
\r
925 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
926 * @param Compare3: specifies the Capture Compare3 register new value.
\r
930 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
\r
932 /* Check the parameters */
\r
933 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
935 /* Set the Capture Compare3 Register value */
\r
936 TIMx->CCR3 = Compare3;
\r
940 * @brief Sets the TIMx Capture Compare4 Register value
\r
941 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
942 * @param Compare4: specifies the Capture Compare4 register new value.
\r
946 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
\r
948 /* Check the parameters */
\r
949 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
951 /* Set the Capture Compare4 Register value */
\r
952 TIMx->CCR4 = Compare4;
\r
956 * @brief Forces the TIMx output 1 waveform to active or inactive level.
\r
957 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
958 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
959 * This parameter can be one of the following values:
\r
960 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
\r
961 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
\r
964 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
966 uint16_t tmpccmr1 = 0;
\r
967 /* Check the parameters */
\r
968 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
969 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
970 tmpccmr1 = TIMx->CCMR1;
\r
971 /* Reset the OC1M Bits */
\r
972 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
\r
973 /* Configure The Forced output Mode */
\r
974 tmpccmr1 |= TIM_ForcedAction;
\r
975 /* Write to TIMx CCMR1 register */
\r
976 TIMx->CCMR1 = tmpccmr1;
\r
980 * @brief Forces the TIMx output 2 waveform to active or inactive level.
\r
981 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM
\r
983 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
984 * This parameter can be one of the following values:
\r
985 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
\r
986 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
\r
989 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
991 uint16_t tmpccmr1 = 0;
\r
993 /* Check the parameters */
\r
994 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
995 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
997 tmpccmr1 = TIMx->CCMR1;
\r
998 /* Reset the OC2M Bits */
\r
999 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
\r
1000 /* Configure The Forced output Mode */
\r
1001 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1002 /* Write to TIMx CCMR1 register */
\r
1003 TIMx->CCMR1 = tmpccmr1;
\r
1007 * @brief Forces the TIMx output 3 waveform to active or inactive level.
\r
1008 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1009 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1010 * This parameter can be one of the following values:
\r
1011 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
\r
1012 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
\r
1015 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1017 uint16_t tmpccmr2 = 0;
\r
1019 /* Check the parameters */
\r
1020 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1021 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1023 tmpccmr2 = TIMx->CCMR2;
\r
1024 /* Reset the OC1M Bits */
\r
1025 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
\r
1026 /* Configure The Forced output Mode */
\r
1027 tmpccmr2 |= TIM_ForcedAction;
\r
1028 /* Write to TIMx CCMR2 register */
\r
1029 TIMx->CCMR2 = tmpccmr2;
\r
1033 * @brief Forces the TIMx output 4 waveform to active or inactive level.
\r
1034 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1035 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1036 * This parameter can be one of the following values:
\r
1037 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
\r
1038 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
\r
1041 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1043 uint16_t tmpccmr2 = 0;
\r
1044 /* Check the parameters */
\r
1045 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1046 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1048 tmpccmr2 = TIMx->CCMR2;
\r
1049 /* Reset the OC2M Bits */
\r
1050 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
\r
1051 /* Configure The Forced output Mode */
\r
1052 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1053 /* Write to TIMx CCMR2 register */
\r
1054 TIMx->CCMR2 = tmpccmr2;
\r
1058 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
\r
1059 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1060 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1061 * This parameter can be one of the following values:
\r
1062 * @arg TIM_OCPreload_Enable
\r
1063 * @arg TIM_OCPreload_Disable
\r
1066 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1068 uint16_t tmpccmr1 = 0;
\r
1069 /* Check the parameters */
\r
1070 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1071 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1073 tmpccmr1 = TIMx->CCMR1;
\r
1074 /* Reset the OC1PE Bit */
\r
1075 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
\r
1076 /* Enable or Disable the Output Compare Preload feature */
\r
1077 tmpccmr1 |= TIM_OCPreload;
\r
1078 /* Write to TIMx CCMR1 register */
\r
1079 TIMx->CCMR1 = tmpccmr1;
\r
1083 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
\r
1084 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1085 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1086 * This parameter can be one of the following values:
\r
1087 * @arg TIM_OCPreload_Enable
\r
1088 * @arg TIM_OCPreload_Disable
\r
1091 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1093 uint16_t tmpccmr1 = 0;
\r
1094 /* Check the parameters */
\r
1095 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1096 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1098 tmpccmr1 = TIMx->CCMR1;
\r
1099 /* Reset the OC2PE Bit */
\r
1100 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
\r
1101 /* Enable or Disable the Output Compare Preload feature */
\r
1102 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
\r
1103 /* Write to TIMx CCMR1 register */
\r
1104 TIMx->CCMR1 = tmpccmr1;
\r
1108 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
\r
1109 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1110 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1111 * This parameter can be one of the following values:
\r
1112 * @arg TIM_OCPreload_Enable
\r
1113 * @arg TIM_OCPreload_Disable
\r
1116 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1118 uint16_t tmpccmr2 = 0;
\r
1120 /* Check the parameters */
\r
1121 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1122 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1124 tmpccmr2 = TIMx->CCMR2;
\r
1125 /* Reset the OC3PE Bit */
\r
1126 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
\r
1127 /* Enable or Disable the Output Compare Preload feature */
\r
1128 tmpccmr2 |= TIM_OCPreload;
\r
1129 /* Write to TIMx CCMR2 register */
\r
1130 TIMx->CCMR2 = tmpccmr2;
\r
1134 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
\r
1135 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1136 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1137 * This parameter can be one of the following values:
\r
1138 * @arg TIM_OCPreload_Enable
\r
1139 * @arg TIM_OCPreload_Disable
\r
1142 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1144 uint16_t tmpccmr2 = 0;
\r
1146 /* Check the parameters */
\r
1147 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1148 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1150 tmpccmr2 = TIMx->CCMR2;
\r
1151 /* Reset the OC4PE Bit */
\r
1152 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
\r
1153 /* Enable or Disable the Output Compare Preload feature */
\r
1154 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
\r
1155 /* Write to TIMx CCMR2 register */
\r
1156 TIMx->CCMR2 = tmpccmr2;
\r
1160 * @brief Configures the TIMx Output Compare 1 Fast feature.
\r
1161 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1162 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1163 * This parameter can be one of the following values:
\r
1164 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1165 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1168 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1170 uint16_t tmpccmr1 = 0;
\r
1172 /* Check the parameters */
\r
1173 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1174 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1176 /* Get the TIMx CCMR1 register value */
\r
1177 tmpccmr1 = TIMx->CCMR1;
\r
1178 /* Reset the OC1FE Bit */
\r
1179 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
\r
1180 /* Enable or Disable the Output Compare Fast Bit */
\r
1181 tmpccmr1 |= TIM_OCFast;
\r
1182 /* Write to TIMx CCMR1 */
\r
1183 TIMx->CCMR1 = tmpccmr1;
\r
1187 * @brief Configures the TIMx Output Compare 2 Fast feature.
\r
1188 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1189 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1190 * This parameter can be one of the following values:
\r
1191 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1192 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1195 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1197 uint16_t tmpccmr1 = 0;
\r
1199 /* Check the parameters */
\r
1200 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1201 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1203 /* Get the TIMx CCMR1 register value */
\r
1204 tmpccmr1 = TIMx->CCMR1;
\r
1205 /* Reset the OC2FE Bit */
\r
1206 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
\r
1207 /* Enable or Disable the Output Compare Fast Bit */
\r
1208 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
\r
1209 /* Write to TIMx CCMR1 */
\r
1210 TIMx->CCMR1 = tmpccmr1;
\r
1214 * @brief Configures the TIMx Output Compare 3 Fast feature.
\r
1215 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1216 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1217 * This parameter can be one of the following values:
\r
1218 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1219 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1222 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1224 uint16_t tmpccmr2 = 0;
\r
1226 /* Check the parameters */
\r
1227 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1228 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1230 /* Get the TIMx CCMR2 register value */
\r
1231 tmpccmr2 = TIMx->CCMR2;
\r
1232 /* Reset the OC3FE Bit */
\r
1233 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
\r
1234 /* Enable or Disable the Output Compare Fast Bit */
\r
1235 tmpccmr2 |= TIM_OCFast;
\r
1236 /* Write to TIMx CCMR2 */
\r
1237 TIMx->CCMR2 = tmpccmr2;
\r
1241 * @brief Configures the TIMx Output Compare 4 Fast feature.
\r
1242 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1243 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1244 * This parameter can be one of the following values:
\r
1245 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1246 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1249 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1251 uint16_t tmpccmr2 = 0;
\r
1253 /* Check the parameters */
\r
1254 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1255 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1257 /* Get the TIMx CCMR2 register value */
\r
1258 tmpccmr2 = TIMx->CCMR2;
\r
1259 /* Reset the OC4FE Bit */
\r
1260 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
\r
1261 /* Enable or Disable the Output Compare Fast Bit */
\r
1262 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
\r
1263 /* Write to TIMx CCMR2 */
\r
1264 TIMx->CCMR2 = tmpccmr2;
\r
1268 * @brief Clears or safeguards the OCREF1 signal on an external event
\r
1269 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1270 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1271 * This parameter can be one of the following values:
\r
1272 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1273 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1276 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1278 uint16_t tmpccmr1 = 0;
\r
1280 /* Check the parameters */
\r
1281 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1282 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1284 tmpccmr1 = TIMx->CCMR1;
\r
1285 /* Reset the OC1CE Bit */
\r
1286 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
\r
1287 /* Enable or Disable the Output Compare Clear Bit */
\r
1288 tmpccmr1 |= TIM_OCClear;
\r
1289 /* Write to TIMx CCMR1 register */
\r
1290 TIMx->CCMR1 = tmpccmr1;
\r
1294 * @brief Clears or safeguards the OCREF2 signal on an external event
\r
1295 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1296 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1298 * This parameter can be one of the following values:
\r
1299 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1300 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1303 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1305 uint16_t tmpccmr1 = 0;
\r
1307 /* Check the parameters */
\r
1308 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1309 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1311 tmpccmr1 = TIMx->CCMR1;
\r
1312 /* Reset the OC2CE Bit */
\r
1313 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
\r
1314 /* Enable or Disable the Output Compare Clear Bit */
\r
1315 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
\r
1316 /* Write to TIMx CCMR1 register */
\r
1317 TIMx->CCMR1 = tmpccmr1;
\r
1321 * @brief Clears or safeguards the OCREF3 signal on an external event
\r
1322 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1323 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1324 * This parameter can be one of the following values:
\r
1325 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1326 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1329 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1331 uint16_t tmpccmr2 = 0;
\r
1333 /* Check the parameters */
\r
1334 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1335 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1337 tmpccmr2 = TIMx->CCMR2;
\r
1338 /* Reset the OC3CE Bit */
\r
1339 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
\r
1340 /* Enable or Disable the Output Compare Clear Bit */
\r
1341 tmpccmr2 |= TIM_OCClear;
\r
1342 /* Write to TIMx CCMR2 register */
\r
1343 TIMx->CCMR2 = tmpccmr2;
\r
1347 * @brief Clears or safeguards the OCREF4 signal on an external event
\r
1348 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1349 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1350 * This parameter can be one of the following values:
\r
1351 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1352 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1355 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1357 uint16_t tmpccmr2 = 0;
\r
1359 /* Check the parameters */
\r
1360 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1361 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1363 tmpccmr2 = TIMx->CCMR2;
\r
1364 /* Reset the OC4CE Bit */
\r
1365 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
\r
1366 /* Enable or Disable the Output Compare Clear Bit */
\r
1367 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
\r
1368 /* Write to TIMx CCMR2 register */
\r
1369 TIMx->CCMR2 = tmpccmr2;
\r
1373 * @brief Configures the TIMx channel 1 polarity.
\r
1374 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1375 * @param TIM_OCPolarity: specifies the OC1 Polarity
\r
1376 * This parmeter can be one of the following values:
\r
1377 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1378 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1381 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1383 uint16_t tmpccer = 0;
\r
1385 /* Check the parameters */
\r
1386 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1387 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1389 tmpccer = TIMx->CCER;
\r
1390 /* Set or Reset the CC1P Bit */
\r
1391 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
\r
1392 tmpccer |= TIM_OCPolarity;
\r
1393 /* Write to TIMx CCER register */
\r
1394 TIMx->CCER = tmpccer;
\r
1398 * @brief Configures the TIMx channel 2 polarity.
\r
1399 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1400 * @param TIM_OCPolarity: specifies the OC2 Polarity
\r
1401 * This parmeter can be one of the following values:
\r
1402 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1403 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1406 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1408 uint16_t tmpccer = 0;
\r
1410 /* Check the parameters */
\r
1411 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1412 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1414 tmpccer = TIMx->CCER;
\r
1415 /* Set or Reset the CC2P Bit */
\r
1416 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
\r
1417 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
\r
1418 /* Write to TIMx CCER register */
\r
1419 TIMx->CCER = tmpccer;
\r
1423 * @brief Configures the TIMx channel 3 polarity.
\r
1424 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1425 * @param TIM_OCPolarity: specifies the OC3 Polarity
\r
1426 * This parmeter can be one of the following values:
\r
1427 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1428 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1431 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1433 uint16_t tmpccer = 0;
\r
1435 /* Check the parameters */
\r
1436 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1437 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1439 tmpccer = TIMx->CCER;
\r
1440 /* Set or Reset the CC3P Bit */
\r
1441 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
\r
1442 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
\r
1443 /* Write to TIMx CCER register */
\r
1444 TIMx->CCER = tmpccer;
\r
1448 * @brief Configures the TIMx channel 4 polarity.
\r
1449 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1450 * @param TIM_OCPolarity: specifies the OC4 Polarity
\r
1451 * This parmeter can be one of the following values:
\r
1452 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1453 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1456 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1458 uint16_t tmpccer = 0;
\r
1460 /* Check the parameters */
\r
1461 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1462 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1464 tmpccer = TIMx->CCER;
\r
1465 /* Set or Reset the CC4P Bit */
\r
1466 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
\r
1467 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
\r
1468 /* Write to TIMx CCER register */
\r
1469 TIMx->CCER = tmpccer;
\r
1473 * @brief Selects the OCReference Clear source.
\r
1474 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1475 * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
\r
1476 * This parameter can be one of the following values:
\r
1477 * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
\r
1478 * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
\r
1481 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
\r
1483 /* Check the parameters */
\r
1484 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1485 assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
\r
1487 /* Set the TIM_OCReferenceClear source */
\r
1488 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
\r
1489 TIMx->SMCR |= TIM_OCReferenceClear;
\r
1493 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
1494 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1495 * @param TIM_Channel: specifies the TIM Channel
\r
1496 * This parameter can be one of the following values:
\r
1497 * @arg TIM_Channel_1: TIM Channel 1
\r
1498 * @arg TIM_Channel_2: TIM Channel 2
\r
1499 * @arg TIM_Channel_3: TIM Channel 3
\r
1500 * @arg TIM_Channel_4: TIM Channel 4
\r
1501 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
\r
1502 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
\r
1505 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
\r
1509 /* Check the parameters */
\r
1510 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1511 assert_param(IS_TIM_CCX(TIM_CCx));
\r
1513 tmp = CCER_CCE_SET << TIM_Channel;
\r
1515 /* Reset the CCxE Bit */
\r
1516 TIMx->CCER &= (uint16_t)~ tmp;
\r
1518 /* Set or reset the CCxE Bit */
\r
1519 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
\r
1526 /** @defgroup TIM_Group3 Input Capture management functions
\r
1527 * @brief Input Capture management functions
\r
1530 ===============================================================================
\r
1531 Input Capture management functions
\r
1532 ===============================================================================
\r
1534 ===================================================================
\r
1535 TIM Driver: how to use it in Input Capture Mode
\r
1536 ===================================================================
\r
1537 To use the Timer in Input Capture mode, the following steps are mandatory:
\r
1539 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
\r
1541 2. Configure the TIM pins by configuring the corresponding GPIO pins
\r
1543 2. Configure the Time base unit as described in the first part of this driver, if needed,
\r
1544 else the Timer will run with the default configuration:
\r
1545 - Autoreload value = 0xFFFF
\r
1546 - Prescaler value = 0x0000
\r
1547 - Counter mode = Up counting
\r
1548 - Clock Division = TIM_CKD_DIV1
\r
1550 3. Fill the TIM_ICInitStruct with the desired parameters including:
\r
1551 - TIM Channel: TIM_Channel
\r
1552 - TIM Input Capture polarity: TIM_ICPolarity
\r
1553 - TIM Input Capture selection: TIM_ICSelection
\r
1554 - TIM Input Capture Prescaler: TIM_ICPrescaler
\r
1555 - TIM Input CApture filter value: TIM_ICFilter
\r
1557 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the
\r
1558 corresponding configuration and to measure only frequency or duty cycle of the input signal,
\r
1560 Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the
\r
1561 corresponding configuration and to measure the frequency and the duty cycle of the input signal
\r
1563 5. Enable the NVIC or the DMA to read the measured frequency.
\r
1565 6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
\r
1566 using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))
\r
1568 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
\r
1570 8. Use TIM_GetCapturex(TIMx); to read the captured value.
\r
1572 Note1: All other functions can be used seperatly to modify, if needed,
\r
1573 a specific feature of the Timer.
\r
1580 * @brief Initializes the TIM peripheral according to the specified
\r
1581 * parameters in the TIM_ICInitStruct.
\r
1582 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1583 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
1584 * that contains the configuration information for the specified TIM
\r
1588 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
1590 /* Check the parameters */
\r
1591 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1592 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
\r
1593 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
\r
1594 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
\r
1595 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
\r
1597 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
1599 /* TI1 Configuration */
\r
1600 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1601 TIM_ICInitStruct->TIM_ICSelection,
\r
1602 TIM_ICInitStruct->TIM_ICFilter);
\r
1603 /* Set the Input Capture Prescaler value */
\r
1604 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1606 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
\r
1608 /* TI2 Configuration */
\r
1609 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1610 TIM_ICInitStruct->TIM_ICSelection,
\r
1611 TIM_ICInitStruct->TIM_ICFilter);
\r
1612 /* Set the Input Capture Prescaler value */
\r
1613 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1615 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
\r
1617 /* TI3 Configuration */
\r
1618 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1619 TIM_ICInitStruct->TIM_ICSelection,
\r
1620 TIM_ICInitStruct->TIM_ICFilter);
\r
1621 /* Set the Input Capture Prescaler value */
\r
1622 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1626 /* TI4 Configuration */
\r
1627 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
1628 TIM_ICInitStruct->TIM_ICSelection,
\r
1629 TIM_ICInitStruct->TIM_ICFilter);
\r
1630 /* Set the Input Capture Prescaler value */
\r
1631 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1636 * @brief Fills each TIM_ICInitStruct member with its default value.
\r
1637 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
\r
1641 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
1643 /* Set the default configuration */
\r
1644 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
\r
1645 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
\r
1646 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
\r
1647 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
\r
1648 TIM_ICInitStruct->TIM_ICFilter = 0x00;
\r
1652 * @brief Configures the TIM peripheral according to the specified
\r
1653 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
\r
1654 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1655 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
1656 * that contains the configuration information for the specified TIM
\r
1660 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
1662 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
\r
1663 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
\r
1664 /* Check the parameters */
\r
1665 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1666 /* Select the Opposite Input Polarity */
\r
1667 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
\r
1669 icoppositepolarity = TIM_ICPolarity_Falling;
\r
1673 icoppositepolarity = TIM_ICPolarity_Rising;
\r
1675 /* Select the Opposite Input */
\r
1676 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
\r
1678 icoppositeselection = TIM_ICSelection_IndirectTI;
\r
1682 icoppositeselection = TIM_ICSelection_DirectTI;
\r
1684 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
1686 /* TI1 Configuration */
\r
1687 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
1688 TIM_ICInitStruct->TIM_ICFilter);
\r
1689 /* Set the Input Capture Prescaler value */
\r
1690 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1691 /* TI2 Configuration */
\r
1692 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
1693 /* Set the Input Capture Prescaler value */
\r
1694 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1698 /* TI2 Configuration */
\r
1699 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
1700 TIM_ICInitStruct->TIM_ICFilter);
\r
1701 /* Set the Input Capture Prescaler value */
\r
1702 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1703 /* TI1 Configuration */
\r
1704 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
1705 /* Set the Input Capture Prescaler value */
\r
1706 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
1711 * @brief Gets the TIMx Input Capture 1 value.
\r
1712 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1713 * @retval Capture Compare 1 Register value.
\r
1716 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
\r
1718 /* Check the parameters */
\r
1719 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1721 /* Get the Capture 1 Register value */
\r
1722 return TIMx->CCR1;
\r
1726 * @brief Gets the TIMx Input Capture 2 value.
\r
1727 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1728 * @retval Capture Compare 2 Register value.
\r
1731 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
\r
1733 /* Check the parameters */
\r
1734 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1736 /* Get the Capture 2 Register value */
\r
1737 return TIMx->CCR2;
\r
1741 * @brief Gets the TIMx Input Capture 3 value.
\r
1742 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1743 * @retval Capture Compare 3 Register value.
\r
1745 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
\r
1747 /* Check the parameters */
\r
1748 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1750 /* Get the Capture 3 Register value */
\r
1751 return TIMx->CCR3;
\r
1755 * @brief Gets the TIMx Input Capture 4 value.
\r
1756 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1757 * @retval Capture Compare 4 Register value.
\r
1759 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
\r
1761 /* Check the parameters */
\r
1762 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1764 /* Get the Capture 4 Register value */
\r
1765 return TIMx->CCR4;
\r
1769 * @brief Sets the TIMx Input Capture 1 prescaler.
\r
1770 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
1771 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
\r
1772 * This parameter can be one of the following values:
\r
1773 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1774 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1775 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1776 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1779 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
1781 /* Check the parameters */
\r
1782 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
1783 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
1785 /* Reset the IC1PSC Bits */
\r
1786 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
\r
1787 /* Set the IC1PSC value */
\r
1788 TIMx->CCMR1 |= TIM_ICPSC;
\r
1792 * @brief Sets the TIMx Input Capture 2 prescaler.
\r
1793 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
1794 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
\r
1795 * This parameter can be one of the following values:
\r
1796 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1797 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1798 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1799 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1802 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
1804 /* Check the parameters */
\r
1805 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
1806 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
1808 /* Reset the IC2PSC Bits */
\r
1809 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
\r
1810 /* Set the IC2PSC value */
\r
1811 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
\r
1815 * @brief Sets the TIMx Input Capture 3 prescaler.
\r
1816 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1817 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
\r
1818 * This parameter can be one of the following values:
\r
1819 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1820 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1821 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1822 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1825 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
1827 /* Check the parameters */
\r
1828 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1829 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
1831 /* Reset the IC3PSC Bits */
\r
1832 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
\r
1833 /* Set the IC3PSC value */
\r
1834 TIMx->CCMR2 |= TIM_ICPSC;
\r
1838 * @brief Sets the TIMx Input Capture 4 prescaler.
\r
1839 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
1840 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
\r
1841 * This parameter can be one of the following values:
\r
1842 * @arg TIM_ICPSC_DIV1: no prescaler
\r
1843 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
1844 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
1845 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
1848 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
1850 /* Check the parameters */
\r
1851 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
1852 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
1854 /* Reset the IC4PSC Bits */
\r
1855 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
\r
1856 /* Set the IC4PSC value */
\r
1857 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
\r
1864 /** @defgroup TIM_Group4 Interrupts DMA and flags management functions
\r
1865 * @brief Interrupts, DMA and flags management functions
\r
1868 ===============================================================================
\r
1869 Interrupts, DMA and flags management functions
\r
1870 ===============================================================================
\r
1877 * @brief Enables or disables the specified TIM interrupts.
\r
1878 * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral.
\r
1879 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
\r
1880 * This parameter can be any combination of the following values:
\r
1881 * @arg TIM_IT_Update: TIM update Interrupt source
\r
1882 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
1883 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
1884 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
1885 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
1886 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
1888 * - TIM6 and TIM7 can only generate an update interrupt.
\r
1889 * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11
\r
1890 * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9.
\r
1891 * @param NewState: new state of the TIM interrupts.
\r
1892 * This parameter can be: ENABLE or DISABLE.
\r
1895 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
\r
1897 /* Check the parameters */
\r
1898 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1899 assert_param(IS_TIM_IT(TIM_IT));
\r
1900 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1902 if (NewState != DISABLE)
\r
1904 /* Enable the Interrupt sources */
\r
1905 TIMx->DIER |= TIM_IT;
\r
1909 /* Disable the Interrupt sources */
\r
1910 TIMx->DIER &= (uint16_t)~TIM_IT;
\r
1915 * @brief Configures the TIMx event to be generate by software.
\r
1916 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1917 * @param TIM_EventSource: specifies the event source.
\r
1918 * This parameter can be one or more of the following values:
\r
1919 * @arg TIM_EventSource_Update: Timer update Event source
\r
1920 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
\r
1921 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
\r
1922 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
\r
1923 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
\r
1924 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
\r
1926 * - TIM6 and TIM7 can only generate an update event.
\r
1927 * - TIM9 can only generate an update event, Capture Compare 1 event,
\r
1928 * Capture Compare 2 event and TIM_EventSource_Trigger.
\r
1929 * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event.
\r
1932 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
\r
1934 /* Check the parameters */
\r
1935 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1936 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
\r
1937 /* Set the event sources */
\r
1938 TIMx->EGR = TIM_EventSource;
\r
1942 * @brief Checks whether the specified TIM flag is set or not.
\r
1943 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1944 * @param TIM_FLAG: specifies the flag to check.
\r
1945 * This parameter can be one of the following values:
\r
1946 * @arg TIM_FLAG_Update: TIM update Flag
\r
1947 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
1948 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
1949 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
1950 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
1951 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
1952 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
1953 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
1954 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
1955 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
1957 * - TIM6 and TIM7 can have only one update flag.
\r
1958 * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger,
\r
1959 * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
\r
1960 * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags
\r
1961 * @retval The new state of TIM_FLAG (SET or RESET).
\r
1963 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
1965 ITStatus bitstatus = RESET;
\r
1967 /* Check the parameters */
\r
1968 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1969 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
\r
1971 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
\r
1977 bitstatus = RESET;
\r
1983 * @brief Clears the TIMx's pending flags.
\r
1984 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
1985 * @param TIM_FLAG: specifies the flag bit to clear.
\r
1986 * This parameter can be any combination of the following values:
\r
1987 * @arg TIM_FLAG_Update: TIM update Flag
\r
1988 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
1989 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
1990 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
1991 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
1992 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
1993 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
1994 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
1995 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
1996 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
1998 * - TIM6 and TIM7 can have only one update flag.
\r
1999 * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags
\r
2000 * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags
\r
2001 * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1
\r
2002 * or TIM_FLAG_CC1OF flags
\r
2005 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2007 /* Check the parameters */
\r
2008 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2009 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
\r
2011 /* Clear the flags */
\r
2012 TIMx->SR = (uint16_t)~TIM_FLAG;
\r
2016 * @brief Checks whether the TIM interrupt has occurred or not.
\r
2017 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2018 * @param TIM_IT: specifies the TIM interrupt source to check.
\r
2019 * This parameter can be one of the following values:
\r
2020 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2021 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2022 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2023 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2024 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2025 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2027 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2028 * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2,
\r
2029 * interrupt and TIM_IT_Trigger interrupt.
\r
2030 * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1
\r
2032 * @retval The new state of the TIM_IT(SET or RESET).
\r
2034 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2036 ITStatus bitstatus = RESET;
\r
2037 uint16_t itstatus = 0x0, itenable = 0x0;
\r
2039 /* Check the parameters */
\r
2040 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2041 assert_param(IS_TIM_GET_IT(TIM_IT));
\r
2043 itstatus = TIMx->SR & TIM_IT;
\r
2045 itenable = TIMx->DIER & TIM_IT;
\r
2046 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
\r
2052 bitstatus = RESET;
\r
2058 * @brief Clears the TIMx's interrupt pending bits.
\r
2059 * @param TIMx: where x can be 2 to 11 to select the TIM peripheral.
\r
2060 * @param TIM_IT: specifies the pending bit to clear.
\r
2061 * This parameter can be any combination of the following values:
\r
2062 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2063 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2064 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2065 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2066 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2067 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2069 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2070 * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2,
\r
2071 * and TIM_IT_Trigger interrupt.
\r
2072 * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1
\r
2076 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2078 /* Check the parameters */
\r
2079 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2080 assert_param(IS_TIM_IT(TIM_IT));
\r
2082 /* Clear the IT pending Bit */
\r
2083 TIMx->SR = (uint16_t)~TIM_IT;
\r
2087 * @brief Configures the TIMx
\92s DMA interface.
\r
2088 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2089 * @param TIM_DMABase: DMA Base address.
\r
2090 * This parameter can be one of the following values:
\r
2091 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
\r
2092 * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
\r
2093 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
\r
2094 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
\r
2095 * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
\r
2096 * TIM_DMABase_CCR4, TIM_DMABase_DCR.
\r
2097 * @param TIM_DMABurstLength: DMA Burst length.
\r
2098 * This parameter can be one value between:
\r
2099 * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
\r
2102 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
\r
2104 /* Check the parameters */
\r
2105 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2106 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
\r
2107 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
\r
2108 /* Set the DMA Base and the DMA Burst Length */
\r
2109 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
\r
2113 * @brief Enables or disables the TIMx
\92s DMA Requests.
\r
2114 * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral.
\r
2115 * @param TIM_DMASource: specifies the DMA Request sources.
\r
2116 * This parameter can be any combination of the following values:
\r
2117 * @arg TIM_DMA_Update: TIM update Interrupt source
\r
2118 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
2119 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
2120 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
2121 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
2122 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
\r
2123 * @param NewState: new state of the DMA Request sources.
\r
2124 * This parameter can be: ENABLE or DISABLE.
\r
2127 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
\r
2129 /* Check the parameters */
\r
2130 assert_param(IS_TIM_LIST4_PERIPH(TIMx));
\r
2131 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
\r
2132 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2134 if (NewState != DISABLE)
\r
2136 /* Enable the DMA sources */
\r
2137 TIMx->DIER |= TIM_DMASource;
\r
2141 /* Disable the DMA sources */
\r
2142 TIMx->DIER &= (uint16_t)~TIM_DMASource;
\r
2147 * @brief Selects the TIMx peripheral Capture Compare DMA source.
\r
2148 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2149 * @param NewState: new state of the Capture Compare DMA source
\r
2150 * This parameter can be: ENABLE or DISABLE.
\r
2153 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2155 /* Check the parameters */
\r
2156 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2157 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2159 if (NewState != DISABLE)
\r
2161 /* Set the CCDS Bit */
\r
2162 TIMx->CR2 |= TIM_CR2_CCDS;
\r
2166 /* Reset the CCDS Bit */
\r
2167 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
\r
2175 /** @defgroup TIM_Group5 Clocks management functions
\r
2176 * @brief Clocks management functions
\r
2179 ===============================================================================
\r
2180 Clocks management functions
\r
2181 ===============================================================================
\r
2188 * @brief Configures the TIMx internal Clock
\r
2189 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2192 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
\r
2194 /* Check the parameters */
\r
2195 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2196 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
2197 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2201 * @brief Configures the TIMx Internal Trigger as External Clock
\r
2202 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2203 * @param TIM_ITRSource: Trigger source.
\r
2204 * This parameter can be one of the following values:
\r
2205 * @param TIM_TS_ITR0: Internal Trigger 0
\r
2206 * @param TIM_TS_ITR1: Internal Trigger 1
\r
2207 * @param TIM_TS_ITR2: Internal Trigger 2
\r
2208 * @param TIM_TS_ITR3: Internal Trigger 3
\r
2211 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
2213 /* Check the parameters */
\r
2214 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2215 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
2216 /* Select the Internal Trigger */
\r
2217 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
\r
2218 /* Select the External clock mode1 */
\r
2219 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
2223 * @brief Configures the TIMx Trigger as External Clock
\r
2224 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2225 * @param TIM_TIxExternalCLKSource: Trigger source.
\r
2226 * This parameter can be one of the following values:
\r
2227 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
\r
2228 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
\r
2229 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
\r
2230 * @param TIM_ICPolarity: specifies the TIx Polarity.
\r
2231 * This parameter can be one of the following values:
\r
2232 * @arg TIM_ICPolarity_Rising
\r
2233 * @arg TIM_ICPolarity_Falling
\r
2234 * @param ICFilter : specifies the filter value.
\r
2235 * This parameter must be a value between 0x0 and 0xF.
\r
2238 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
2239 uint16_t TIM_ICPolarity, uint16_t ICFilter)
\r
2241 /* Check the parameters */
\r
2242 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2243 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
\r
2244 assert_param(IS_TIM_IC_FILTER(ICFilter));
\r
2246 /* Configure the Timer Input Clock Source */
\r
2247 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
\r
2249 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
2253 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
2255 /* Select the Trigger source */
\r
2256 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
\r
2257 /* Select the External clock mode1 */
\r
2258 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
2262 * @brief Configures the External clock Mode1
\r
2263 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2264 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2265 * This parameter can be one of the following values:
\r
2266 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2267 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2268 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2269 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2270 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2271 * This parameter can be one of the following values:
\r
2272 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2273 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2274 * @param ExtTRGFilter: External Trigger Filter.
\r
2275 * This parameter must be a value between 0x00 and 0x0F
\r
2278 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
2279 uint16_t ExtTRGFilter)
\r
2281 uint16_t tmpsmcr = 0;
\r
2283 /* Check the parameters */
\r
2284 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2285 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2286 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2287 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2289 /* Configure the ETR Clock source */
\r
2290 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
2292 /* Get the TIMx SMCR register value */
\r
2293 tmpsmcr = TIMx->SMCR;
\r
2294 /* Reset the SMS Bits */
\r
2295 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2296 /* Select the External clock mode1 */
\r
2297 tmpsmcr |= TIM_SlaveMode_External1;
\r
2298 /* Select the Trigger selection : ETRF */
\r
2299 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
2300 tmpsmcr |= TIM_TS_ETRF;
\r
2301 /* Write to TIMx SMCR */
\r
2302 TIMx->SMCR = tmpsmcr;
\r
2306 * @brief Configures the External clock Mode2
\r
2307 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2308 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2309 * This parameter can be one of the following values:
\r
2310 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2311 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2312 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2313 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2314 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2315 * This parameter can be one of the following values:
\r
2316 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2317 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2318 * @param ExtTRGFilter: External Trigger Filter.
\r
2319 * This parameter must be a value between 0x00 and 0x0F
\r
2322 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
2323 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
\r
2325 /* Check the parameters */
\r
2326 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
2327 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2328 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2329 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2331 /* Configure the ETR Clock source */
\r
2332 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
2333 /* Enable the External clock mode2 */
\r
2334 TIMx->SMCR |= TIM_SMCR_ECE;
\r
2341 /** @defgroup TIM_Group6 Synchronization management functions
\r
2342 * @brief Synchronization management functions
\r
2345 ===============================================================================
\r
2346 Synchronization management functions
\r
2347 ===============================================================================
\r
2349 ===================================================================
\r
2350 TIM Driver: how to use it in synchronization Mode
\r
2351 ===================================================================
\r
2352 Case of two/several Timers
\r
2353 **************************
\r
2354 1. Configure the Master Timers using the following functions:
\r
2355 - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
\r
2356 - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
\r
2357 2. Configure the Slave Timers using the following functions:
\r
2358 - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
\r
2359 - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
\r
2361 Case of Timers and external trigger(ETR pin)
\r
2362 ********************************************
\r
2363 1. Configure the Etrenal trigger using this function:
\r
2364 - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
2365 uint16_t ExtTRGFilter);
\r
2366 2. Configure the Slave Timers using the following functions:
\r
2367 - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
\r
2368 - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
\r
2375 * @brief Selects the Input Trigger source
\r
2376 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2377 * @param TIM_InputTriggerSource: The Input Trigger source.
\r
2378 * This parameter can be one of the following values:
\r
2379 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
2380 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
2381 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
2382 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
2383 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
2384 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
2385 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
2386 * @arg TIM_TS_ETRF: External Trigger input
\r
2389 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
2391 uint16_t tmpsmcr = 0;
\r
2393 /* Check the parameters */
\r
2394 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
2395 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
2397 /* Get the TIMx SMCR register value */
\r
2398 tmpsmcr = TIMx->SMCR;
\r
2399 /* Reset the TS Bits */
\r
2400 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
\r
2401 /* Set the Input Trigger source */
\r
2402 tmpsmcr |= TIM_InputTriggerSource;
\r
2403 /* Write to TIMx SMCR */
\r
2404 TIMx->SMCR = tmpsmcr;
\r
2408 * @brief Selects the TIMx Trigger Output Mode.
\r
2409 * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral.
\r
2410 * @param TIM_TRGOSource: specifies the Trigger Output source.
\r
2411 * This paramter can be one of the following values:
\r
2414 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
\r
2415 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
\r
2416 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
\r
2418 * - For all TIMx except TIM6 and TIM7
\r
2419 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
\r
2420 * is to be set, as soon as a capture or compare match occurs (TRGO).
\r
2421 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
\r
2423 * - For all TIMx except TIM6, TIM7, TIM10 and TIM11
\r
2424 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
\r
2426 * - For TIM2, TIM3 and TIM4
\r
2427 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
\r
2428 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
\r
2432 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
\r
2434 /* Check the parameters */
\r
2435 assert_param(IS_TIM_LIST5_PERIPH(TIMx));
\r
2436 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
\r
2438 /* Reset the MMS Bits */
\r
2439 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
\r
2440 /* Select the TRGO source */
\r
2441 TIMx->CR2 |= TIM_TRGOSource;
\r
2445 * @brief Selects the TIMx Slave Mode.
\r
2446 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2447 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
\r
2448 * This paramter can be one of the following values:
\r
2449 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
\r
2450 * the counter and triggers an update of the registers.
\r
2451 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
\r
2452 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
\r
2453 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
\r
2456 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
\r
2458 /* Check the parameters */
\r
2459 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2460 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
\r
2462 /* Reset the SMS Bits */
\r
2463 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
\r
2464 /* Select the Slave Mode */
\r
2465 TIMx->SMCR |= TIM_SlaveMode;
\r
2469 * @brief Sets or Resets the TIMx Master/Slave Mode.
\r
2470 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2471 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
\r
2472 * This paramter can be one of the following values:
\r
2473 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
\r
2474 * and its slaves (through TRGO).
\r
2475 * @arg TIM_MasterSlaveMode_Disable: No action
\r
2478 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
\r
2480 /* Check the parameters */
\r
2481 assert_param(IS_TIM_LIST2_PERIPH(TIMx));
\r
2482 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
\r
2484 /* Reset the MSM Bit */
\r
2485 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
\r
2487 /* Set or Reset the MSM Bit */
\r
2488 TIMx->SMCR |= TIM_MasterSlaveMode;
\r
2492 * @brief Configures the TIMx External Trigger (ETR).
\r
2493 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2494 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
2495 * This parameter can be one of the following values:
\r
2496 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
2497 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
2498 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
2499 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
2500 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
2501 * This parameter can be one of the following values:
\r
2502 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
2503 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
2504 * @param ExtTRGFilter: External Trigger Filter.
\r
2505 * This parameter must be a value between 0x00 and 0x0F
\r
2508 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
2509 uint16_t ExtTRGFilter)
\r
2511 uint16_t tmpsmcr = 0;
\r
2513 /* Check the parameters */
\r
2514 assert_param(IS_TIM_LIST1_PERIPH(TIMx));
\r
2515 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
2516 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
2517 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
2519 tmpsmcr = TIMx->SMCR;
\r
2520 /* Reset the ETR Bits */
\r
2521 tmpsmcr &= SMCR_ETR_MASK;
\r
2522 /* Set the Prescaler, the Filter value and the Polarity */
\r
2523 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
\r
2524 /* Write to TIMx SMCR */
\r
2525 TIMx->SMCR = tmpsmcr;
\r
2532 /** @defgroup TIM_Group7 Specific interface management functions
\r
2533 * @brief Specific interface management functions
\r
2536 ===============================================================================
\r
2537 Specific interface management functions
\r
2538 ===============================================================================
\r
2545 * @brief Configures the TIMx Encoder Interface.
\r
2546 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2547 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
\r
2548 * This parameter can be one of the following values:
\r
2549 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
\r
2550 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
\r
2551 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
\r
2552 * on the level of the other input.
\r
2553 * @param TIM_IC1Polarity: specifies the IC1 Polarity
\r
2554 * This parmeter can be one of the following values:
\r
2555 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
2556 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
2557 * @param TIM_IC2Polarity: specifies the IC2 Polarity
\r
2558 * This parmeter can be one of the following values:
\r
2559 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
2560 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
2563 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
2564 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
\r
2566 uint16_t tmpsmcr = 0;
\r
2567 uint16_t tmpccmr1 = 0;
\r
2568 uint16_t tmpccer = 0;
\r
2570 /* Check the parameters */
\r
2571 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2572 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
\r
2573 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
\r
2574 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
\r
2576 /* Get the TIMx SMCR register value */
\r
2577 tmpsmcr = TIMx->SMCR;
\r
2578 /* Get the TIMx CCMR1 register value */
\r
2579 tmpccmr1 = TIMx->CCMR1;
\r
2580 /* Get the TIMx CCER register value */
\r
2581 tmpccer = TIMx->CCER;
\r
2582 /* Set the encoder Mode */
\r
2583 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
\r
2584 tmpsmcr |= TIM_EncoderMode;
\r
2585 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
2586 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
\r
2587 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
\r
2588 /* Set the TI1 and the TI2 Polarities */
\r
2589 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
\r
2590 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
\r
2591 /* Write to TIMx SMCR */
\r
2592 TIMx->SMCR = tmpsmcr;
\r
2593 /* Write to TIMx CCMR1 */
\r
2594 TIMx->CCMR1 = tmpccmr1;
\r
2595 /* Write to TIMx CCER */
\r
2596 TIMx->CCER = tmpccer;
\r
2600 * @brief Enables or disables the TIMx
\92s Hall sensor interface.
\r
2601 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2602 * @param NewState: new state of the TIMx Hall sensor interface.
\r
2603 * This parameter can be: ENABLE or DISABLE.
\r
2606 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2608 /* Check the parameters */
\r
2609 assert_param(IS_TIM_LIST3_PERIPH(TIMx));
\r
2610 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2612 if (NewState != DISABLE)
\r
2614 /* Set the TI1S Bit */
\r
2615 TIMx->CR2 |= TIM_CR2_TI1S;
\r
2619 /* Reset the TI1S Bit */
\r
2620 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
\r
2628 /** @defgroup TIM_Group8 Specific remapping management function
\r
2629 * @brief Specific remapping management function
\r
2632 ===============================================================================
\r
2633 Specific remapping management function
\r
2634 ===============================================================================
\r
2641 * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities.
\r
2642 * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral.
\r
2643 * @param TIM_Remap: specifies the TIM input remapping source.
\r
2644 * This parameter can be one of the following values:
\r
2645 * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default)
\r
2646 * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock.
\r
2647 * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default)
\r
2648 * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock.
\r
2649 * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock.
\r
2650 * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event.
\r
2651 * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default)
\r
2652 * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock.
\r
2653 * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock.
\r
2656 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
\r
2658 /* Check the parameters */
\r
2659 assert_param(IS_TIM_LIST6_PERIPH(TIMx));
\r
2660 assert_param(IS_TIM_REMAP(TIM_Remap));
\r
2662 /* Set the Timer remapping configuration */
\r
2663 TIMx->OR = TIM_Remap;
\r
2671 * @brief Configure the TI1 as Input.
\r
2672 * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral.
\r
2673 * @param TIM_ICPolarity : The Input Polarity.
\r
2674 * This parameter can be one of the following values:
\r
2675 * @arg TIM_ICPolarity_Rising
\r
2676 * @arg TIM_ICPolarity_Falling
\r
2677 * @param TIM_ICSelection: specifies the input to be used.
\r
2678 * This parameter can be one of the following values:
\r
2679 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
2680 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
2681 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
2682 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2683 * This parameter must be a value between 0x00 and 0x0F.
\r
2686 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2687 uint16_t TIM_ICFilter)
\r
2689 uint16_t tmpccmr1 = 0, tmpccer = 0;
\r
2691 /* Disable the Channel 1: Reset the CC1E Bit */
\r
2692 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
\r
2693 tmpccmr1 = TIMx->CCMR1;
\r
2694 tmpccer = TIMx->CCER;
\r
2695 /* Select the Input and set the filter */
\r
2696 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
\r
2697 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2698 /* Select the Polarity and set the CC1E Bit */
\r
2699 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
\r
2700 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
\r
2701 /* Write to TIMx CCMR1 and CCER registers */
\r
2702 TIMx->CCMR1 = tmpccmr1;
\r
2703 TIMx->CCER = tmpccer;
\r
2707 * @brief Configure the TI2 as Input.
\r
2708 * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral.
\r
2709 * @param TIM_ICPolarity : The Input Polarity.
\r
2710 * This parameter can be one of the following values:
\r
2711 * @arg TIM_ICPolarity_Rising
\r
2712 * @arg TIM_ICPolarity_Falling
\r
2713 * @param TIM_ICSelection: specifies the input to be used.
\r
2714 * This parameter can be one of the following values:
\r
2715 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
2716 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
2717 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
2718 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2719 * This parameter must be a value between 0x00 and 0x0F.
\r
2722 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2723 uint16_t TIM_ICFilter)
\r
2725 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
\r
2727 /* Disable the Channel 2: Reset the CC2E Bit */
\r
2728 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
\r
2729 tmpccmr1 = TIMx->CCMR1;
\r
2730 tmpccer = TIMx->CCER;
\r
2731 tmp = (uint16_t)(TIM_ICPolarity << 4);
\r
2732 /* Select the Input and set the filter */
\r
2733 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
\r
2734 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
\r
2735 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
\r
2736 /* Select the Polarity and set the CC2E Bit */
\r
2737 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
\r
2738 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
\r
2739 /* Write to TIMx CCMR1 and CCER registers */
\r
2740 TIMx->CCMR1 = tmpccmr1 ;
\r
2741 TIMx->CCER = tmpccer;
\r
2745 * @brief Configure the TI3 as Input.
\r
2746 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2747 * @param TIM_ICPolarity : The Input Polarity.
\r
2748 * This parameter can be one of the following values:
\r
2749 * @arg TIM_ICPolarity_Rising
\r
2750 * @arg TIM_ICPolarity_Falling
\r
2751 * @param TIM_ICSelection: specifies the input to be used.
\r
2752 * This parameter can be one of the following values:
\r
2753 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
2754 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
2755 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
2756 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2757 * This parameter must be a value between 0x00 and 0x0F.
\r
2760 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2761 uint16_t TIM_ICFilter)
\r
2763 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2765 /* Disable the Channel 3: Reset the CC3E Bit */
\r
2766 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
\r
2767 tmpccmr2 = TIMx->CCMR2;
\r
2768 tmpccer = TIMx->CCER;
\r
2769 tmp = (uint16_t)(TIM_ICPolarity << 8);
\r
2770 /* Select the Input and set the filter */
\r
2771 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
\r
2772 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2773 /* Select the Polarity and set the CC3E Bit */
\r
2774 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
\r
2775 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
\r
2776 /* Write to TIMx CCMR2 and CCER registers */
\r
2777 TIMx->CCMR2 = tmpccmr2;
\r
2778 TIMx->CCER = tmpccer;
\r
2782 * @brief Configure the TI4 as Input.
\r
2783 * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral.
\r
2784 * @param TIM_ICPolarity : The Input Polarity.
\r
2785 * This parameter can be one of the following values:
\r
2786 * @arg TIM_ICPolarity_Rising
\r
2787 * @arg TIM_ICPolarity_Falling
\r
2788 * @param TIM_ICSelection: specifies the input to be used.
\r
2789 * This parameter can be one of the following values:
\r
2790 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
2791 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
2792 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
2793 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2794 * This parameter must be a value between 0x00 and 0x0F.
\r
2797 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2798 uint16_t TIM_ICFilter)
\r
2800 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2802 /* Disable the Channel 4: Reset the CC4E Bit */
\r
2803 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
\r
2804 tmpccmr2 = TIMx->CCMR2;
\r
2805 tmpccer = TIMx->CCER;
\r
2806 tmp = (uint16_t)(TIM_ICPolarity << 12);
\r
2807 /* Select the Input and set the filter */
\r
2808 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
\r
2809 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
\r
2810 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
\r
2812 /* Select the Polarity and set the CC4E Bit */
\r
2813 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
\r
2814 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
\r
2815 /* Write to TIMx CCMR2 and CCER registers */
\r
2816 TIMx->CCMR2 = tmpccmr2;
\r
2817 TIMx->CCER = tmpccer ;
\r
2832 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r