2 ******************************************************************************
\r
3 * @file stm32l1xx_pwr.c
\r
4 * @author MCD Application Team
\r
6 * @date 31-December-2010
\r
7 * @brief This file provides firmware functions to manage the following
\r
8 * functionalities of the Power Controller (PWR) peripheral:
\r
9 * - RTC Domain Access
\r
10 * - PVD configuration
\r
11 * - WakeUp pins configuration
\r
12 * - Ultra Low Power mode configuration
\r
13 * - Voltage Scaling configuration
\r
14 * - Low Power modes configuration
\r
15 * - Flags management
\r
17 ******************************************************************************
\r
20 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
21 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
\r
22 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
\r
23 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
\r
24 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
\r
25 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
27 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
\r
28 ******************************************************************************
\r
31 /* Includes ------------------------------------------------------------------*/
\r
32 #include "stm32l1xx_pwr.h"
\r
33 #include "stm32l1xx_rcc.h"
\r
35 /** @addtogroup STM32L1xx_StdPeriph_Driver
\r
40 * @brief PWR driver modules
\r
44 /* Private typedef -----------------------------------------------------------*/
\r
45 /* Private define ------------------------------------------------------------*/
\r
46 /* --------- PWR registers bit address in the alias region ---------- */
\r
47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
\r
49 /* --- CR Register ---*/
\r
51 /* Alias word address of DBP bit */
\r
52 #define CR_OFFSET (PWR_OFFSET + 0x00)
\r
53 #define DBP_BitNumber 0x08
\r
54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
\r
56 /* Alias word address of PVDE bit */
\r
57 #define PVDE_BitNumber 0x04
\r
58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
\r
60 /* Alias word address of ULP bit */
\r
61 #define ULP_BitNumber 0x09
\r
62 #define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
\r
64 /* Alias word address of FWU bit */
\r
65 #define FWU_BitNumber 0x0A
\r
66 #define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
\r
68 /* --- CSR Register ---*/
\r
70 /* Alias word address of EWUP bit */
\r
71 #define CSR_OFFSET (PWR_OFFSET + 0x04)
\r
72 #define EWUP_BitNumber 0x08
\r
73 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
\r
75 /* ------------------ PWR registers bit mask ------------------------ */
\r
77 /* CR register bit mask */
\r
78 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
\r
79 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
\r
80 #define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
\r
82 /* Private macro -------------------------------------------------------------*/
\r
83 /* Private variables ---------------------------------------------------------*/
\r
84 /* Private function prototypes -----------------------------------------------*/
\r
85 /* Private functions ---------------------------------------------------------*/
\r
87 /** @defgroup PWR_Private_Functions
\r
91 /** @defgroup PWR_Group1 RTC Domain Access function
\r
92 * @brief RTC Domain Access function
\r
95 ===============================================================================
\r
96 RTC Domain Access function
\r
97 ===============================================================================
\r
99 After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup
\r
100 registers) are protected against possible stray write accesses.
\r
101 To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.
\r
108 * @brief Deinitializes the PWR peripheral registers to their default reset values.
\r
109 * @note Before calling this function, the VOS[1:0] bits should be configured
\r
110 * to "10" and the system frequency has to be configured accordingly.
\r
111 * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
\r
113 * @note ULP and FWU bits are not reset by this function.
\r
117 void PWR_DeInit(void)
\r
119 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
\r
120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
\r
124 * @brief Enables or disables access to the RTC and backup registers.
\r
125 * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
\r
126 * RTC Domain Access should be kept enabled.
\r
127 * @param NewState: new state of the access to the RTC and backup registers.
\r
128 * This parameter can be: ENABLE or DISABLE.
\r
131 void PWR_RTCAccessCmd(FunctionalState NewState)
\r
133 /* Check the parameters */
\r
134 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
136 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
\r
143 /** @defgroup PWR_Group2 PVD configuration functions
\r
144 * @brief PVD configuration functions
\r
147 ===============================================================================
\r
148 PVD configuration functions
\r
149 ===============================================================================
\r
151 - The PVD is used to monitor the VDD power supply by comparing it to a threshold
\r
152 selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
\r
153 - The PVD can use an external input analog voltage (PVD_IN) which is compared
\r
154 internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
\r
155 when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
\r
156 - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
\r
157 PVD threshold. This event is internally connected to the EXTI line16
\r
158 and can generate an interrupt if enabled through the EXTI registers.
\r
159 - The PVD is stopped in Standby mode.
\r
166 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
\r
167 * @param PWR_PVDLevel: specifies the PVD detection level
\r
168 * This parameter can be one of the following values:
\r
169 * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
\r
170 * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
\r
171 * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
\r
172 * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
\r
173 * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
\r
174 * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
\r
175 * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
\r
176 * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT)
\r
179 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
\r
181 uint32_t tmpreg = 0;
\r
183 /* Check the parameters */
\r
184 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
\r
188 /* Clear PLS[7:5] bits */
\r
189 tmpreg &= CR_PLS_MASK;
\r
191 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
\r
192 tmpreg |= PWR_PVDLevel;
\r
194 /* Store the new value */
\r
199 * @brief Enables or disables the Power Voltage Detector(PVD).
\r
200 * @param NewState: new state of the PVD.
\r
201 * This parameter can be: ENABLE or DISABLE.
\r
204 void PWR_PVDCmd(FunctionalState NewState)
\r
206 /* Check the parameters */
\r
207 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
209 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
\r
216 /** @defgroup PWR_Group3 WakeUp pins configuration functions
\r
217 * @brief WakeUp pins configuration functions
\r
220 ===============================================================================
\r
221 WakeUp pins configuration functions
\r
222 ===============================================================================
\r
224 - WakeUp pins are used to wakeup the system from Standby mode. These pins are
\r
225 forced in input pull down configuration and are active on rising edges.
\r
226 - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
\r
227 WakeUp Pin 3 on PE.06.
\r
234 * @brief Enables or disables the WakeUp Pin functionality.
\r
235 * @param PWR_WakeUpPin: specifies the WakeUpPin.
\r
236 * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
\r
237 * @param NewState: new state of the WakeUp Pin functionality.
\r
238 * This parameter can be: ENABLE or DISABLE.
\r
241 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
\r
243 __IO uint32_t tmp = 0;
\r
245 /* Check the parameters */
\r
246 assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
\r
248 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
250 tmp = CSR_EWUP_BB + PWR_WakeUpPin;
\r
252 *(__IO uint32_t *) (tmp) = (uint32_t)NewState;
\r
259 /** @defgroup PWR_Group4 Ultra Low Power mode configuration functions
\r
260 * @brief Ultra Low Power mode configuration functions
\r
263 ===============================================================================
\r
264 Ultra Low Power mode configuration functions
\r
265 ===============================================================================
\r
267 - The internal voltage reference consumption is not negligible, in particular
\r
268 in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()
\r
269 function (ULP bit (Ultra low power) in the PWR_CR register) to disable the
\r
270 internal voltage reference. However, in this case, when exiting from the
\r
271 Stop/Standby mode, the functions managed through the internal voltage reference
\r
272 are not reliable during the internal voltage reference startup time (up to 3 ms).
\r
273 To reduce the wakeup time, the device can exit from Stop/Standby mode without
\r
274 waiting for the internal voltage reference startup time. This is performed
\r
275 by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
\r
276 wakeup) in the PWR_CR register) before entering Stop/Standby mode.
\r
283 * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
\r
284 * @param NewState: new state of the Fast WakeUp functionality.
\r
285 * This parameter can be: ENABLE or DISABLE.
\r
288 void PWR_FastWakeUpCmd(FunctionalState NewState)
\r
290 /* Check the parameters */
\r
291 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
293 *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
\r
297 * @brief Enables or disables the Ultra Low Power mode.
\r
298 * @param NewState: new state of the Ultra Low Power mode.
\r
299 * This parameter can be: ENABLE or DISABLE.
\r
302 void PWR_UltraLowPowerCmd(FunctionalState NewState)
\r
304 /* Check the parameters */
\r
305 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
307 *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
\r
314 /** @defgroup PWR_Group5 Voltage Scaling configuration functions
\r
315 * @brief Voltage Scaling configuration functions
\r
318 ===============================================================================
\r
319 Voltage Scaling configuration functions
\r
320 ===============================================================================
\r
322 - The dynamic voltage scaling is a power management technique which consists in
\r
323 increasing or decreasing the voltage used for the digital peripherals (VCORE),
\r
324 according to the circumstances.
\r
326 Depending on the device voltage range, the maximum frequency and FLASH wait
\r
327 state should be adapted accordingly:
\r
329 +------------------------------------------------------------------+
\r
330 | Wait states | HCLK clock frequency (MHz) |
\r
331 | |------------------------------------------------|
\r
332 | (Latency) | voltage range | voltage range |
\r
333 | | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
\r
334 | |----------------|---------------|---------------|
\r
335 | | Range 3 | Range 2 | Range 1 |
\r
336 | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
\r
337 |---------------- |----------------|---------------|---------------|
\r
338 | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
\r
339 |-----------------|----------------|---------------|---------------|
\r
340 | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
\r
341 |-----------------|----------------|---------------|---------------|
\r
342 | CPU Performance | Low | Medium | High |
\r
343 |-----__----------|----------------|---------------|---------------|
\r
344 |Power Performance| High | Medium | Low |
\r
345 +------------------------------------------------------------------+
\r
347 - To modify the Product voltage range, user application has to:
\r
348 - Check VDD to identify which ranges are allowed (see table above)
\r
349 - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus()
\r
350 function and wait until it is reset.
\r
351 - Configure the Voltage range using the PWR_VoltageScalingConfig() function.
\r
353 - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must
\r
354 reconfigure the system:
\r
355 - Detect that VDD drops below 2.0 V using the PVD Level 1
\r
356 - Adapt the clock frequency to the voltage range that will be selected at next step
\r
357 - Select the required voltage range
\r
358 - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system
\r
359 reconfiguration is required.
\r
361 - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected
\r
362 - When the voltage range is above the targeted voltage range (e.g. from range
\r
364 - Adapt the clock frequency to the lower voltage range that will be selected
\r
366 - Select the required voltage range.
\r
367 - When the voltage range is below the targeted voltage range (e.g. from range
\r
369 - Select the required voltage range.
\r
370 - Tune the clock frequency if needed.
\r
372 - When VDD is below 2.0 V, only range 2 and 3 can be selected:
\r
373 - From range 2 to range 3
\r
374 - Adapt the clock frequency to voltage range 3.
\r
375 - Select voltage range 3.
\r
376 - From range 3 to range 2
\r
377 - Select the voltage range 2.
\r
378 - Tune the clock frequency if needed.
\r
385 * @brief Configures the voltage scaling range.
\r
386 * @note During voltage scaling configuration, the system clock is stopped
\r
387 * until the regulator is stabilized (VOSF = 0). This must be taken
\r
388 * into account during application developement, in case a critical
\r
389 * reaction time to interrupt is needed, and depending on peripheral
\r
390 * used (timer, communication,...).
\r
392 * @param PWR_VoltageScaling: specifies the voltage scaling range.
\r
393 * This parameter can be:
\r
394 * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V)
\r
395 * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V)
\r
396 * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V)
\r
399 void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
\r
403 /* Check the parameters */
\r
404 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
\r
408 tmp &= CR_VOS_MASK;
\r
409 tmp |= PWR_VoltageScaling;
\r
411 PWR->CR = tmp & 0xFFFFFFF3;
\r
419 /** @defgroup PWR_Group6 Low Power modes configuration functions
\r
420 * @brief Low Power modes configuration functions
\r
423 ===============================================================================
\r
424 Low Power modes configuration functions
\r
425 ===============================================================================
\r
427 The devices feature five low-power modes:
\r
428 - Low power run mode: regulator in low power mode, limited clock frequency,
\r
429 limited number of peripherals running.
\r
430 - Sleep mode: Cortex-M3 core stopped, peripherals kept running.
\r
431 - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
\r
432 limited number of peripherals running, regulator in low power mode.
\r
433 - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
\r
434 - Standby mode: VCORE domain powered off
\r
436 Low power run mode (LP run)
\r
437 ===========================
\r
439 - Decrease the system frequency.
\r
440 - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()
\r
443 - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()
\r
445 - Increase the system frequency if needed.
\r
450 - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,)
\r
451 function with regulator ON.
\r
453 - Any peripheral interrupt acknowledged by the nested vectored interrupt
\r
454 controller (NVIC) can wake up the device from Sleep mode.
\r
456 Low power sleep mode (LP sleep)
\r
457 ===============================
\r
459 - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()
\r
461 - Decrease the system frequency.
\r
462 - The regulator is forced in low power mode and the WFI or WFE instructions
\r
463 are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function
\r
464 with regulator in LowPower.
\r
466 - Any peripheral interrupt acknowledged by the nested vectored interrupt
\r
467 controller (NVIC) can wake up the device from Sleep LP mode.
\r
471 In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
\r
472 the HSI and the HSE RC oscillators are disabled. Internal SRAM and register
\r
473 contents are preserved.
\r
474 The voltage regulator can be configured either in normal or low-power mode.
\r
475 To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
\r
476 sensor can be switched off before entering the Stop mode. They can be switched
\r
477 on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()
\r
481 - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
\r
482 function with regulator in LowPower or with Regulator ON.
\r
484 - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
\r
488 The Standby mode allows to achieve the lowest power consumption. It is based
\r
489 on the Cortex-M3 deepsleep mode, with the voltage regulator disabled.
\r
490 The VCORE domain is consequently powered off. The PLL, the MSI, the HSI
\r
491 oscillator and the HSE oscillator are also switched off. SRAM and register
\r
492 contents are lost except for the RTC registers, RTC backup registers and
\r
495 The voltage regulator is OFF.
\r
497 To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
\r
498 sensor can be switched off before entering the Standby mode. They can be switched
\r
499 on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()
\r
503 - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
\r
505 - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
\r
506 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
\r
508 Auto-wakeup (AWU) from low-power mode
\r
509 =====================================
\r
510 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
\r
511 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
\r
512 without depending on an external interrupt (Auto-wakeup mode).
\r
514 - RTC auto-wakeup (AWU) from the Stop mode
\r
515 ----------------------------------------
\r
517 - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
\r
518 - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
\r
519 or Event modes) using the EXTI_Init() function.
\r
520 - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
\r
521 - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
\r
522 and RTC_AlarmCmd() functions.
\r
523 - To wake up from the Stop mode with an RTC Tamper or time stamp event, it
\r
525 - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
\r
526 or Event modes) using the EXTI_Init() function.
\r
527 - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
\r
529 - Configure the RTC to detect the tamper or time stamp event using the
\r
530 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
\r
532 - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
\r
533 - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
\r
534 or Event modes) using the EXTI_Init() function.
\r
535 - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
\r
536 - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
\r
537 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
\r
539 - RTC auto-wakeup (AWU) from the Standby mode
\r
540 -------------------------------------------
\r
541 - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
\r
542 - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
\r
543 - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
\r
544 and RTC_AlarmCmd() functions.
\r
545 - To wake up from the Standby mode with an RTC Tamper or time stamp event, it
\r
547 - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
\r
549 - Configure the RTC to detect the tamper or time stamp event using the
\r
550 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
\r
552 - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
\r
553 - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
\r
554 - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
\r
555 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
\r
557 - Comparator auto-wakeup (AWU) from the Stop mode
\r
558 -----------------------------------------------
\r
559 - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
\r
560 event, it is necessary to:
\r
561 - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
\r
562 to be sensitive to to the selected edges (falling, rising or falling
\r
563 and rising) (Interrupt or Event modes) using the EXTI_Init() function.
\r
564 - Configure the comparator to generate the event.
\r
571 * @brief Enters/Exits the Low Power Run mode.
\r
572 * @note Low power run mode can only be entered when VCORE is in range 2.
\r
573 * In addition, the dynamic voltage scaling must not be used when Low
\r
574 * power run mode is selected. Only Stop and Sleep modes with regulator
\r
575 * configured in Low power mode is allowed when Low power run mode is
\r
577 * @note In Low power run mode, all I/O pins keep the same state as in Run mode.
\r
578 * @param NewState: new state of the Low Power Run mode.
\r
579 * This parameter can be: ENABLE or DISABLE.
\r
582 void PWR_EnterLowPowerRunMode(FunctionalState NewState)
\r
584 /* Check the parameters */
\r
585 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
587 if (NewState != DISABLE)
\r
589 PWR->CR |= PWR_CR_LPSDSR;
\r
590 PWR->CR |= PWR_CR_LPRUN;
\r
594 PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
\r
595 PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
\r
600 * @brief Enters Sleep mode.
\r
601 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
\r
602 * @param PWR_Regulator: specifies the regulator state in Sleep mode.
\r
603 * This parameter can be one of the following values:
\r
604 * @arg PWR_Regulator_ON: Sleep mode with regulator ON
\r
605 * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
\r
606 * @note Low power sleep mode can only be entered when VCORE is in range 2.
\r
607 * @note When the voltage regulator operates in low power mode, an additional
\r
608 * startup delay is incurred when waking up from Low power sleep mode.
\r
610 * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
\r
611 * This parameter can be one of the following values:
\r
612 * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
\r
613 * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
\r
616 void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
\r
618 uint32_t tmpreg = 0;
\r
620 /* Check the parameters */
\r
621 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
\r
623 assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
\r
625 /* Select the regulator state in Sleep mode ---------------------------------*/
\r
628 /* Clear PDDS and LPDSR bits */
\r
629 tmpreg &= CR_DS_MASK;
\r
631 /* Set LPDSR bit according to PWR_Regulator value */
\r
632 tmpreg |= PWR_Regulator;
\r
634 /* Store the new value */
\r
637 /* Clear SLEEPDEEP bit of Cortex System Control Register */
\r
638 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
\r
640 /* Select SLEEP mode entry -------------------------------------------------*/
\r
641 if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
\r
643 /* Request Wait For Interrupt */
\r
648 /* Request Wait For Event */
\r
654 * @brief Enters STOP mode.
\r
655 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
\r
656 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
\r
657 * the MSI RC oscillator is selected as system clock.
\r
658 * @note When the voltage regulator operates in low power mode, an additional
\r
659 * startup delay is incurred when waking up from Stop mode.
\r
660 * By keeping the internal regulator ON during Stop mode, the consumption
\r
661 * is higher although the startup time is reduced.
\r
662 * @param PWR_Regulator: specifies the regulator state in STOP mode.
\r
663 * This parameter can be one of the following values:
\r
664 * @arg PWR_Regulator_ON: STOP mode with regulator ON
\r
665 * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
\r
666 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
\r
667 * This parameter can be one of the following values:
\r
668 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
\r
669 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
\r
672 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
\r
674 uint32_t tmpreg = 0;
\r
676 /* Check the parameters */
\r
677 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
\r
678 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
\r
680 /* Select the regulator state in STOP mode ---------------------------------*/
\r
682 /* Clear PDDS and LPDSR bits */
\r
683 tmpreg &= CR_DS_MASK;
\r
685 /* Set LPDSR bit according to PWR_Regulator value */
\r
686 tmpreg |= PWR_Regulator;
\r
688 /* Store the new value */
\r
691 /* Set SLEEPDEEP bit of Cortex System Control Register */
\r
692 SCB->SCR |= SCB_SCR_SLEEPDEEP;
\r
694 /* Select STOP mode entry --------------------------------------------------*/
\r
695 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
\r
697 /* Request Wait For Interrupt */
\r
702 /* Request Wait For Event */
\r
705 /* Reset SLEEPDEEP bit of Cortex System Control Register */
\r
706 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
\r
710 * @brief Enters STANDBY mode.
\r
711 * @note In Standby mode, all I/O pins are high impedance except for:
\r
712 * - Reset pad (still available)
\r
713 * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
\r
714 * time-stamp, RTC Alarm out, or RTC clock calibration out.
\r
715 * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
\r
719 void PWR_EnterSTANDBYMode(void)
\r
721 /* Clear Wakeup flag */
\r
722 PWR->CR |= PWR_CR_CWUF;
\r
724 /* Select STANDBY mode */
\r
725 PWR->CR |= PWR_CR_PDDS;
\r
727 /* Set SLEEPDEEP bit of Cortex System Control Register */
\r
728 SCB->SCR |= SCB_SCR_SLEEPDEEP;
\r
730 /* This option is used to ensure that store operations are completed */
\r
731 #if defined ( __CC_ARM )
\r
734 /* Request Wait For Interrupt */
\r
742 /** @defgroup PWR_Group7 Flags management functions
\r
743 * @brief Flags management functions
\r
746 ===============================================================================
\r
747 Flags management functions
\r
748 ===============================================================================
\r
755 * @brief Checks whether the specified PWR flag is set or not.
\r
756 * @param PWR_FLAG: specifies the flag to check.
\r
757 * This parameter can be one of the following values:
\r
758 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
\r
759 * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
\r
760 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
\r
761 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
\r
762 * resumed from StandBy mode.
\r
763 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
\r
764 * by the PWR_PVDCmd() function.
\r
765 * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
\r
766 * flag indicates the state of the internal voltage reference, VREFINT.
\r
767 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
\r
768 * the internal regulator to be ready after the voltage range is changed.
\r
769 * The VOSF flag indicates that the regulator has reached the voltage level
\r
770 * defined with bits VOS[1:0] of PWR_CR register.
\r
771 * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware
\r
772 * when the MCU is in Low power run mode.
\r
773 * When the MCU exits from Low power run mode, this flag stays SET until
\r
774 * the regulator is ready in main mode. A polling on this flag is
\r
775 * recommended to wait for the regulator main mode.
\r
776 * This flag is RESET by hardware when the regulator is ready.
\r
777 * @retval The new state of PWR_FLAG (SET or RESET).
\r
779 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
\r
781 FlagStatus bitstatus = RESET;
\r
782 /* Check the parameters */
\r
783 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
\r
785 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
\r
793 /* Return the flag status */
\r
798 * @brief Clears the PWR's pending flags.
\r
799 * @param PWR_FLAG: specifies the flag to clear.
\r
800 * This parameter can be one of the following values:
\r
801 * @arg PWR_FLAG_WU: Wake Up flag
\r
802 * @arg PWR_FLAG_SB: StandBy flag
\r
805 void PWR_ClearFlag(uint32_t PWR_FLAG)
\r
807 /* Check the parameters */
\r
808 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
\r
810 PWR->CR |= PWR_FLAG << 2;
\r
829 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r