2 ******************************************************************************
\r
3 * @file stm32f10x_sdio.c
\r
4 * @author MCD Application Team
\r
7 * @brief This file provides all the SDIO firmware functions.
\r
8 ******************************************************************************
\r
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
\r
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
\r
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
\r
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
\r
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
\r
21 /* Includes ------------------------------------------------------------------*/
\r
22 #include "stm32f10x_sdio.h"
\r
23 #include "stm32f10x_rcc.h"
\r
25 /** @addtogroup STM32F10x_StdPeriph_Driver
\r
30 * @brief SDIO driver modules
\r
34 /** @defgroup SDIO_Private_TypesDefinitions
\r
38 /* ------------ SDIO registers bit address in the alias region ----------- */
\r
39 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
\r
41 /* --- CLKCR Register ---*/
\r
43 /* Alias word address of CLKEN bit */
\r
44 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
\r
45 #define CLKEN_BitNumber 0x08
\r
46 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
\r
48 /* --- CMD Register ---*/
\r
50 /* Alias word address of SDIOSUSPEND bit */
\r
51 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
\r
52 #define SDIOSUSPEND_BitNumber 0x0B
\r
53 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
\r
55 /* Alias word address of ENCMDCOMPL bit */
\r
56 #define ENCMDCOMPL_BitNumber 0x0C
\r
57 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
\r
59 /* Alias word address of NIEN bit */
\r
60 #define NIEN_BitNumber 0x0D
\r
61 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
\r
63 /* Alias word address of ATACMD bit */
\r
64 #define ATACMD_BitNumber 0x0E
\r
65 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
\r
67 /* --- DCTRL Register ---*/
\r
69 /* Alias word address of DMAEN bit */
\r
70 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
\r
71 #define DMAEN_BitNumber 0x03
\r
72 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
\r
74 /* Alias word address of RWSTART bit */
\r
75 #define RWSTART_BitNumber 0x08
\r
76 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
\r
78 /* Alias word address of RWSTOP bit */
\r
79 #define RWSTOP_BitNumber 0x09
\r
80 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
\r
82 /* Alias word address of RWMOD bit */
\r
83 #define RWMOD_BitNumber 0x0A
\r
84 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
\r
86 /* Alias word address of SDIOEN bit */
\r
87 #define SDIOEN_BitNumber 0x0B
\r
88 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
\r
90 /* ---------------------- SDIO registers bit mask ------------------------ */
\r
92 /* --- CLKCR Register ---*/
\r
94 /* CLKCR register clear mask */
\r
95 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
\r
97 /* --- PWRCTRL Register ---*/
\r
99 /* SDIO PWRCTRL Mask */
\r
100 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
\r
102 /* --- DCTRL Register ---*/
\r
104 /* SDIO DCTRL Clear Mask */
\r
105 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
\r
107 /* --- CMD Register ---*/
\r
109 /* CMD Register clear mask */
\r
110 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
\r
112 /* SDIO RESP Registers Address */
\r
113 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
\r
119 /** @defgroup SDIO_Private_Defines
\r
127 /** @defgroup SDIO_Private_Macros
\r
135 /** @defgroup SDIO_Private_Variables
\r
143 /** @defgroup SDIO_Private_FunctionPrototypes
\r
151 /** @defgroup SDIO_Private_Functions
\r
156 * @brief Deinitializes the SDIO peripheral registers to their default reset values.
\r
160 void SDIO_DeInit(void)
\r
162 SDIO->POWER = 0x00000000;
\r
163 SDIO->CLKCR = 0x00000000;
\r
164 SDIO->ARG = 0x00000000;
\r
165 SDIO->CMD = 0x00000000;
\r
166 SDIO->DTIMER = 0x00000000;
\r
167 SDIO->DLEN = 0x00000000;
\r
168 SDIO->DCTRL = 0x00000000;
\r
169 SDIO->ICR = 0x00C007FF;
\r
170 SDIO->MASK = 0x00000000;
\r
174 * @brief Initializes the SDIO peripheral according to the specified
\r
175 * parameters in the SDIO_InitStruct.
\r
176 * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
\r
177 * that contains the configuration information for the SDIO peripheral.
\r
180 void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
\r
182 uint32_t tmpreg = 0;
\r
184 /* Check the parameters */
\r
185 assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
\r
186 assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
\r
187 assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
\r
188 assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
\r
189 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
\r
191 /*---------------------------- SDIO CLKCR Configuration ------------------------*/
\r
192 /* Get the SDIO CLKCR value */
\r
193 tmpreg = SDIO->CLKCR;
\r
195 /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
\r
196 tmpreg &= CLKCR_CLEAR_MASK;
\r
198 /* Set CLKDIV bits according to SDIO_ClockDiv value */
\r
199 /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
\r
200 /* Set BYPASS bit according to SDIO_ClockBypass value */
\r
201 /* Set WIDBUS bits according to SDIO_BusWide value */
\r
202 /* Set NEGEDGE bits according to SDIO_ClockEdge value */
\r
203 /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
\r
204 tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
\r
205 SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
\r
206 SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
\r
208 /* Write to SDIO CLKCR */
\r
209 SDIO->CLKCR = tmpreg;
\r
213 * @brief Fills each SDIO_InitStruct member with its default value.
\r
214 * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
\r
215 * will be initialized.
\r
218 void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
\r
220 /* SDIO_InitStruct members default value */
\r
221 SDIO_InitStruct->SDIO_ClockDiv = 0x00;
\r
222 SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
\r
223 SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
\r
224 SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
\r
225 SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
\r
226 SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
\r
230 * @brief Enables or disables the SDIO Clock.
\r
231 * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
\r
234 void SDIO_ClockCmd(FunctionalState NewState)
\r
236 /* Check the parameters */
\r
237 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
239 *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
\r
243 * @brief Sets the power status of the controller.
\r
244 * @param SDIO_PowerState: new state of the Power state.
\r
245 * This parameter can be one of the following values:
\r
246 * @arg SDIO_PowerState_OFF
\r
247 * @arg SDIO_PowerState_ON
\r
250 void SDIO_SetPowerState(uint32_t SDIO_PowerState)
\r
252 /* Check the parameters */
\r
253 assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
\r
255 SDIO->POWER &= PWR_PWRCTRL_MASK;
\r
256 SDIO->POWER |= SDIO_PowerState;
\r
260 * @brief Gets the power status of the controller.
\r
262 * @retval Power status of the controller. The returned value can
\r
263 * be one of the following:
\r
264 * - 0x00: Power OFF
\r
266 * - 0x03: Power ON
\r
268 uint32_t SDIO_GetPowerState(void)
\r
270 return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
\r
274 * @brief Enables or disables the SDIO interrupts.
\r
275 * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
\r
276 * This parameter can be one or a combination of the following values:
\r
277 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
278 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
279 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
280 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
281 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
282 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
283 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
284 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
285 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
286 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
287 * bus mode interrupt
\r
288 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
289 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
290 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
291 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
292 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
293 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
294 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
295 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
296 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
297 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
298 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
299 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
300 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
301 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
\r
302 * @param NewState: new state of the specified SDIO interrupts.
\r
303 * This parameter can be: ENABLE or DISABLE.
\r
306 void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
\r
308 /* Check the parameters */
\r
309 assert_param(IS_SDIO_IT(SDIO_IT));
\r
310 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
312 if (NewState != DISABLE)
\r
314 /* Enable the SDIO interrupts */
\r
315 SDIO->MASK |= SDIO_IT;
\r
319 /* Disable the SDIO interrupts */
\r
320 SDIO->MASK &= ~SDIO_IT;
\r
325 * @brief Enables or disables the SDIO DMA request.
\r
326 * @param NewState: new state of the selected SDIO DMA request.
\r
327 * This parameter can be: ENABLE or DISABLE.
\r
330 void SDIO_DMACmd(FunctionalState NewState)
\r
332 /* Check the parameters */
\r
333 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
335 *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
\r
339 * @brief Initializes the SDIO Command according to the specified
\r
340 * parameters in the SDIO_CmdInitStruct and send the command.
\r
341 * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
\r
342 * structure that contains the configuration information for the SDIO command.
\r
345 void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
\r
347 uint32_t tmpreg = 0;
\r
349 /* Check the parameters */
\r
350 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
\r
351 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
\r
352 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
\r
353 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
\r
355 /*---------------------------- SDIO ARG Configuration ------------------------*/
\r
356 /* Set the SDIO Argument value */
\r
357 SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
\r
359 /*---------------------------- SDIO CMD Configuration ------------------------*/
\r
360 /* Get the SDIO CMD value */
\r
361 tmpreg = SDIO->CMD;
\r
362 /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
\r
363 tmpreg &= CMD_CLEAR_MASK;
\r
364 /* Set CMDINDEX bits according to SDIO_CmdIndex value */
\r
365 /* Set WAITRESP bits according to SDIO_Response value */
\r
366 /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
\r
367 /* Set CPSMEN bits according to SDIO_CPSM value */
\r
368 tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
\r
369 | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
\r
371 /* Write to SDIO CMD */
\r
372 SDIO->CMD = tmpreg;
\r
376 * @brief Fills each SDIO_CmdInitStruct member with its default value.
\r
377 * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
\r
378 * structure which will be initialized.
\r
381 void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
\r
383 /* SDIO_CmdInitStruct members default value */
\r
384 SDIO_CmdInitStruct->SDIO_Argument = 0x00;
\r
385 SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
\r
386 SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
\r
387 SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
\r
388 SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
\r
392 * @brief Returns command index of last command for which response received.
\r
394 * @retval Returns the command index of the last command response received.
\r
396 uint8_t SDIO_GetCommandResponse(void)
\r
398 return (uint8_t)(SDIO->RESPCMD);
\r
402 * @brief Returns response received from the card for the last command.
\r
403 * @param SDIO_RESP: Specifies the SDIO response register.
\r
404 * This parameter can be one of the following values:
\r
405 * @arg SDIO_RESP1: Response Register 1
\r
406 * @arg SDIO_RESP2: Response Register 2
\r
407 * @arg SDIO_RESP3: Response Register 3
\r
408 * @arg SDIO_RESP4: Response Register 4
\r
409 * @retval The Corresponding response register value.
\r
411 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
\r
413 __IO uint32_t tmp = 0;
\r
415 /* Check the parameters */
\r
416 assert_param(IS_SDIO_RESP(SDIO_RESP));
\r
418 tmp = SDIO_RESP_ADDR + SDIO_RESP;
\r
420 return (*(__IO uint32_t *) tmp);
\r
424 * @brief Initializes the SDIO data path according to the specified
\r
425 * parameters in the SDIO_DataInitStruct.
\r
426 * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
\r
427 * contains the configuration information for the SDIO command.
\r
430 void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
\r
432 uint32_t tmpreg = 0;
\r
434 /* Check the parameters */
\r
435 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
\r
436 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
\r
437 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
\r
438 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
\r
439 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
\r
441 /*---------------------------- SDIO DTIMER Configuration ---------------------*/
\r
442 /* Set the SDIO Data TimeOut value */
\r
443 SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
\r
445 /*---------------------------- SDIO DLEN Configuration -----------------------*/
\r
446 /* Set the SDIO DataLength value */
\r
447 SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
\r
449 /*---------------------------- SDIO DCTRL Configuration ----------------------*/
\r
450 /* Get the SDIO DCTRL value */
\r
451 tmpreg = SDIO->DCTRL;
\r
452 /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
\r
453 tmpreg &= DCTRL_CLEAR_MASK;
\r
454 /* Set DEN bit according to SDIO_DPSM value */
\r
455 /* Set DTMODE bit according to SDIO_TransferMode value */
\r
456 /* Set DTDIR bit according to SDIO_TransferDir value */
\r
457 /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
\r
458 tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
\r
459 | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
\r
461 /* Write to SDIO DCTRL */
\r
462 SDIO->DCTRL = tmpreg;
\r
466 * @brief Fills each SDIO_DataInitStruct member with its default value.
\r
467 * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
\r
468 * will be initialized.
\r
471 void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
\r
473 /* SDIO_DataInitStruct members default value */
\r
474 SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
\r
475 SDIO_DataInitStruct->SDIO_DataLength = 0x00;
\r
476 SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
\r
477 SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
\r
478 SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
\r
479 SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
\r
483 * @brief Returns number of remaining data bytes to be transferred.
\r
485 * @retval Number of remaining data bytes to be transferred
\r
487 uint32_t SDIO_GetDataCounter(void)
\r
489 return SDIO->DCOUNT;
\r
493 * @brief Read one data word from Rx FIFO.
\r
495 * @retval Data received
\r
497 uint32_t SDIO_ReadData(void)
\r
503 * @brief Write one data word to Tx FIFO.
\r
504 * @param Data: 32-bit data word to write.
\r
507 void SDIO_WriteData(uint32_t Data)
\r
513 * @brief Returns the number of words left to be written to or read from FIFO.
\r
515 * @retval Remaining number of words.
\r
517 uint32_t SDIO_GetFIFOCount(void)
\r
519 return SDIO->FIFOCNT;
\r
523 * @brief Starts the SD I/O Read Wait operation.
\r
524 * @param NewState: new state of the Start SDIO Read Wait operation.
\r
525 * This parameter can be: ENABLE or DISABLE.
\r
528 void SDIO_StartSDIOReadWait(FunctionalState NewState)
\r
530 /* Check the parameters */
\r
531 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
533 *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
\r
537 * @brief Stops the SD I/O Read Wait operation.
\r
538 * @param NewState: new state of the Stop SDIO Read Wait operation.
\r
539 * This parameter can be: ENABLE or DISABLE.
\r
542 void SDIO_StopSDIOReadWait(FunctionalState NewState)
\r
544 /* Check the parameters */
\r
545 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
547 *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
\r
551 * @brief Sets one of the two options of inserting read wait interval.
\r
552 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
\r
553 * This parametre can be:
\r
554 * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
\r
555 * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
\r
558 void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
\r
560 /* Check the parameters */
\r
561 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
\r
563 *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
\r
567 * @brief Enables or disables the SD I/O Mode Operation.
\r
568 * @param NewState: new state of SDIO specific operation.
\r
569 * This parameter can be: ENABLE or DISABLE.
\r
572 void SDIO_SetSDIOOperation(FunctionalState NewState)
\r
574 /* Check the parameters */
\r
575 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
577 *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
\r
581 * @brief Enables or disables the SD I/O Mode suspend command sending.
\r
582 * @param NewState: new state of the SD I/O Mode suspend command.
\r
583 * This parameter can be: ENABLE or DISABLE.
\r
586 void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
\r
588 /* Check the parameters */
\r
589 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
591 *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
\r
595 * @brief Enables or disables the command completion signal.
\r
596 * @param NewState: new state of command completion signal.
\r
597 * This parameter can be: ENABLE or DISABLE.
\r
600 void SDIO_CommandCompletionCmd(FunctionalState NewState)
\r
602 /* Check the parameters */
\r
603 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
605 *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
\r
609 * @brief Enables or disables the CE-ATA interrupt.
\r
610 * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
\r
613 void SDIO_CEATAITCmd(FunctionalState NewState)
\r
615 /* Check the parameters */
\r
616 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
618 *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
\r
622 * @brief Sends CE-ATA command (CMD61).
\r
623 * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
\r
626 void SDIO_SendCEATACmd(FunctionalState NewState)
\r
628 /* Check the parameters */
\r
629 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
631 *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
\r
635 * @brief Checks whether the specified SDIO flag is set or not.
\r
636 * @param SDIO_FLAG: specifies the flag to check.
\r
637 * This parameter can be one of the following values:
\r
638 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
639 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
640 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
641 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
\r
642 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
\r
643 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
\r
644 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
645 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
646 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
647 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
\r
649 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
\r
650 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
\r
651 * @arg SDIO_FLAG_TXACT: Data transmit in progress
\r
652 * @arg SDIO_FLAG_RXACT: Data receive in progress
\r
653 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
\r
654 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
\r
655 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
\r
656 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
\r
657 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
\r
658 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
\r
659 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
\r
660 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
\r
661 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
662 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
663 * @retval The new state of SDIO_FLAG (SET or RESET).
\r
665 FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
\r
667 FlagStatus bitstatus = RESET;
\r
669 /* Check the parameters */
\r
670 assert_param(IS_SDIO_FLAG(SDIO_FLAG));
\r
672 if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
\r
684 * @brief Clears the SDIO's pending flags.
\r
685 * @param SDIO_FLAG: specifies the flag to clear.
\r
686 * This parameter can be one or a combination of the following values:
\r
687 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
\r
688 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
\r
689 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
\r
690 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
\r
691 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
\r
692 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
\r
693 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
\r
694 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
\r
695 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
\r
696 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
\r
698 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
\r
699 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
\r
700 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
\r
703 void SDIO_ClearFlag(uint32_t SDIO_FLAG)
\r
705 /* Check the parameters */
\r
706 assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
\r
708 SDIO->ICR = SDIO_FLAG;
\r
712 * @brief Checks whether the specified SDIO interrupt has occurred or not.
\r
713 * @param SDIO_IT: specifies the SDIO interrupt source to check.
\r
714 * This parameter can be one of the following values:
\r
715 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
716 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
717 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
718 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
719 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
720 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
721 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
722 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
723 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
724 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
725 * bus mode interrupt
\r
726 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
\r
727 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
\r
728 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
\r
729 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
\r
730 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
\r
731 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
\r
732 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
\r
733 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
\r
734 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
\r
735 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
\r
736 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
\r
737 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
\r
738 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
739 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
\r
740 * @retval The new state of SDIO_IT (SET or RESET).
\r
742 ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
\r
744 ITStatus bitstatus = RESET;
\r
746 /* Check the parameters */
\r
747 assert_param(IS_SDIO_GET_IT(SDIO_IT));
\r
748 if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
\r
760 * @brief Clears the SDIO
\92s interrupt pending bits.
\r
761 * @param SDIO_IT: specifies the interrupt pending bit to clear.
\r
762 * This parameter can be one or a combination of the following values:
\r
763 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
\r
764 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
\r
765 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
\r
766 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
\r
767 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
\r
768 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
\r
769 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
\r
770 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
\r
771 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
\r
772 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
\r
773 * bus mode interrupt
\r
774 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
\r
775 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
\r
778 void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
\r
780 /* Check the parameters */
\r
781 assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
\r
783 SDIO->ICR = SDIO_IT;
\r
798 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r