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   1 /**\r
   2   ******************************************************************************\r
   3   * @file    stm32f10x_fsmc.c\r
   4   * @author  MCD Application Team\r
   5   * @version V3.3.0\r
   6   * @date    04/16/2010\r
   7   * @brief   This file provides all the FSMC firmware functions.\r
   8   ******************************************************************************\r
   9   * @copy\r
  10   *\r
  11   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
  12   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
  13   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
  14   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
  15   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
  16   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
  17   *\r
  18   * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
  19   */ \r
  20 \r
  21 /* Includes ------------------------------------------------------------------*/\r
  22 #include "stm32f10x_fsmc.h"\r
  23 #include "stm32f10x_rcc.h"\r
  24 \r
  25 /** @addtogroup STM32F10x_StdPeriph_Driver\r
  26   * @{\r
  27   */\r
  28 \r
  29 /** @defgroup FSMC \r
  30   * @brief FSMC driver modules\r
  31   * @{\r
  32   */ \r
  33 \r
  34 /** @defgroup FSMC_Private_TypesDefinitions\r
  35   * @{\r
  36   */ \r
  37 /**\r
  38   * @}\r
  39   */\r
  40 \r
  41 /** @defgroup FSMC_Private_Defines\r
  42   * @{\r
  43   */\r
  44 \r
  45 /* --------------------- FSMC registers bit mask ---------------------------- */\r
  46 \r
  47 /* FSMC BCRx Mask */\r
  48 #define BCR_MBKEN_Set                       ((uint32_t)0x00000001)\r
  49 #define BCR_MBKEN_Reset                     ((uint32_t)0x000FFFFE)\r
  50 #define BCR_FACCEN_Set                      ((uint32_t)0x00000040)\r
  51 \r
  52 /* FSMC PCRx Mask */\r
  53 #define PCR_PBKEN_Set                       ((uint32_t)0x00000004)\r
  54 #define PCR_PBKEN_Reset                     ((uint32_t)0x000FFFFB)\r
  55 #define PCR_ECCEN_Set                       ((uint32_t)0x00000040)\r
  56 #define PCR_ECCEN_Reset                     ((uint32_t)0x000FFFBF)\r
  57 #define PCR_MemoryType_NAND                 ((uint32_t)0x00000008)\r
  58 /**\r
  59   * @}\r
  60   */\r
  61 \r
  62 /** @defgroup FSMC_Private_Macros\r
  63   * @{\r
  64   */\r
  65 \r
  66 /**\r
  67   * @}\r
  68   */\r
  69 \r
  70 /** @defgroup FSMC_Private_Variables\r
  71   * @{\r
  72   */\r
  73 \r
  74 /**\r
  75   * @}\r
  76   */\r
  77 \r
  78 /** @defgroup FSMC_Private_FunctionPrototypes\r
  79   * @{\r
  80   */\r
  81 \r
  82 /**\r
  83   * @}\r
  84   */\r
  85 \r
  86 /** @defgroup FSMC_Private_Functions\r
  87   * @{\r
  88   */\r
  89 \r
  90 /**\r
  91   * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
  92   *   reset values.\r
  93   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
  94   *   This parameter can be one of the following values:\r
  95   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
  96   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
  97   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
  98   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
  99   * @retval None\r
 100   */\r
 101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
 102 {\r
 103   /* Check the parameter */\r
 104   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 105   \r
 106   /* FSMC_Bank1_NORSRAM1 */\r
 107   if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
 108   {\r
 109     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    \r
 110   }\r
 111   /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
 112   else\r
 113   {   \r
 114     FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
 115   }\r
 116   FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
 117   FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  \r
 118 }\r
 119 \r
 120 /**\r
 121   * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.\r
 122   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 123   *   This parameter can be one of the following values:\r
 124   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 125   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
 126   * @retval None\r
 127   */\r
 128 void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
 129 {\r
 130   /* Check the parameter */\r
 131   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 132   \r
 133   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 134   {\r
 135     /* Set the FSMC_Bank2 registers to their reset values */\r
 136     FSMC_Bank2->PCR2 = 0x00000018;\r
 137     FSMC_Bank2->SR2 = 0x00000040;\r
 138     FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
 139     FSMC_Bank2->PATT2 = 0xFCFCFCFC;  \r
 140   }\r
 141   /* FSMC_Bank3_NAND */  \r
 142   else\r
 143   {\r
 144     /* Set the FSMC_Bank3 registers to their reset values */\r
 145     FSMC_Bank3->PCR3 = 0x00000018;\r
 146     FSMC_Bank3->SR3 = 0x00000040;\r
 147     FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
 148     FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
 149   }  \r
 150 }\r
 151 \r
 152 /**\r
 153   * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
 154   * @param  None                       \r
 155   * @retval None\r
 156   */\r
 157 void FSMC_PCCARDDeInit(void)\r
 158 {\r
 159   /* Set the FSMC_Bank4 registers to their reset values */\r
 160   FSMC_Bank4->PCR4 = 0x00000018; \r
 161   FSMC_Bank4->SR4 = 0x00000000; \r
 162   FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
 163   FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
 164   FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
 165 }\r
 166 \r
 167 /**\r
 168   * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified\r
 169   *   parameters in the FSMC_NORSRAMInitStruct.\r
 170   * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
 171   *   structure that contains the configuration information for \r
 172   *   the FSMC NOR/SRAM specified Banks.                       \r
 173   * @retval None\r
 174   */\r
 175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 176 { \r
 177   /* Check the parameters */\r
 178   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
 179   assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
 180   assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
 181   assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
 182   assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
 183   assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
 184   assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
 185   assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
 186   assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
 187   assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
 188   assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
 189   assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  \r
 190   assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
 191   assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
 192   assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
 193   assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
 194   assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
 195   assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
 196   assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
 197   \r
 198   /* Bank1 NOR/SRAM control register configuration */ \r
 199   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 200             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
 201             FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
 202             FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
 203             FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
 204             FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
 205             FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
 206             FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
 207             FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
 208             FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
 209             FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
 210             FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
 211   if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
 212   {\r
 213     FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
 214   }\r
 215   /* Bank1 NOR/SRAM timing register configuration */\r
 216   FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
 217             (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
 218             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
 219             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 220             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
 221             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
 222             (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
 223              FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
 224             \r
 225     \r
 226   /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
 227   if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
 228   {\r
 229     assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
 230     assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
 231     assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
 232     assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
 233     assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
 234     assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
 235     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
 236               (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
 237               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
 238               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
 239               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
 240               (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
 241                FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
 242   }\r
 243   else\r
 244   {\r
 245     FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
 246   }\r
 247 }\r
 248 \r
 249 /**\r
 250   * @brief  Initializes the FSMC NAND Banks according to the specified \r
 251   *   parameters in the FSMC_NANDInitStruct.\r
 252   * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
 253   *   structure that contains the configuration information for the FSMC NAND specified Banks.                       \r
 254   * @retval None\r
 255   */\r
 256 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 257 {\r
 258   uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
 259     \r
 260   /* Check the parameters */\r
 261   assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
 262   assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
 263   assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
 264   assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
 265   assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
 266   assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
 267   assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
 268   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 269   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 270   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 271   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 272   assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 273   assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 274   assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 275   assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 276   \r
 277   /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
 278   tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
 279             PCR_MemoryType_NAND |\r
 280             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
 281             FSMC_NANDInitStruct->FSMC_ECC |\r
 282             FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
 283             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
 284             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
 285             \r
 286   /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
 287   tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 288             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 289             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 290             (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 291             \r
 292   /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 293   tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 294             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 295             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 296             (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
 297   \r
 298   if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
 299   {\r
 300     /* FSMC_Bank2_NAND registers configuration */\r
 301     FSMC_Bank2->PCR2 = tmppcr;\r
 302     FSMC_Bank2->PMEM2 = tmppmem;\r
 303     FSMC_Bank2->PATT2 = tmppatt;\r
 304   }\r
 305   else\r
 306   {\r
 307     /* FSMC_Bank3_NAND registers configuration */\r
 308     FSMC_Bank3->PCR3 = tmppcr;\r
 309     FSMC_Bank3->PMEM3 = tmppmem;\r
 310     FSMC_Bank3->PATT3 = tmppatt;\r
 311   }\r
 312 }\r
 313 \r
 314 /**\r
 315   * @brief  Initializes the FSMC PCCARD Bank according to the specified \r
 316   *   parameters in the FSMC_PCCARDInitStruct.\r
 317   * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
 318   *   structure that contains the configuration information for the FSMC PCCARD Bank.                       \r
 319   * @retval None\r
 320   */\r
 321 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 322 {\r
 323   /* Check the parameters */\r
 324   assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
 325   assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
 326   assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
 327  \r
 328   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
 329   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
 330   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
 331   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
 332   \r
 333   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
 334   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
 335   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
 336   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
 337   assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
 338   assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
 339   assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
 340   assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
 341   \r
 342   /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
 343   FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
 344                      FSMC_MemoryDataWidth_16b |  \r
 345                      (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
 346                      (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
 347             \r
 348   /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
 349   FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
 350                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 351                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 352                       (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
 353             \r
 354   /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
 355   FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
 356                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 357                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 358                       (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);        \r
 359             \r
 360   /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
 361   FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
 362                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
 363                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
 364                      (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             \r
 365 }\r
 366 \r
 367 /**\r
 368   * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.\r
 369   * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
 370   *   structure which will be initialized.\r
 371   * @retval None\r
 372   */\r
 373 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
 374 {  \r
 375   /* Reset NOR/SRAM Init structure parameters values */\r
 376   FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
 377   FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
 378   FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
 379   FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 380   FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
 381   FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
 382   FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
 383   FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
 384   FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
 385   FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
 386   FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
 387   FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
 388   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 389   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 390   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 391   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 392   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 393   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
 394   FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
 395   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
 396   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
 397   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
 398   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
 399   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
 400   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
 401   FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
 402 }\r
 403 \r
 404 /**\r
 405   * @brief  Fills each FSMC_NANDInitStruct member with its default value.\r
 406   * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
 407   *   structure which will be initialized.\r
 408   * @retval None\r
 409   */\r
 410 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
 411 { \r
 412   /* Reset NAND Init structure parameters values */\r
 413   FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
 414   FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 415   FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
 416   FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
 417   FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
 418   FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 419   FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
 420   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 421   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 422   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 423   FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 424   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 425   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 426   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 427   FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;         \r
 428 }\r
 429 \r
 430 /**\r
 431   * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.\r
 432   * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
 433   *   structure which will be initialized.\r
 434   * @retval None\r
 435   */\r
 436 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
 437 {\r
 438   /* Reset PCCARD Init structure parameters values */\r
 439   FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
 440   FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
 441   FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
 442   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 443   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 444   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 445   FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 446   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 447   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 448   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 449   FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;     \r
 450   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
 451   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
 452   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
 453   FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
 454 }\r
 455 \r
 456 /**\r
 457   * @brief  Enables or disables the specified NOR/SRAM Memory Bank.\r
 458   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 459   *   This parameter can be one of the following values:\r
 460   *     @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  \r
 461   *     @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
 462   *     @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
 463   *     @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
 464   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
 465   * @retval None\r
 466   */\r
 467 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 468 {\r
 469   assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
 470   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 471   \r
 472   if (NewState != DISABLE)\r
 473   {\r
 474     /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
 475     FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
 476   }\r
 477   else\r
 478   {\r
 479     /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
 480     FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
 481   }\r
 482 }\r
 483 \r
 484 /**\r
 485   * @brief  Enables or disables the specified NAND Memory Bank.\r
 486   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 487   *   This parameter can be one of the following values:\r
 488   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 489   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 490   * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
 491   * @retval None\r
 492   */\r
 493 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 494 {\r
 495   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 496   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 497   \r
 498   if (NewState != DISABLE)\r
 499   {\r
 500     /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
 501     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 502     {\r
 503       FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
 504     }\r
 505     else\r
 506     {\r
 507       FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
 508     }\r
 509   }\r
 510   else\r
 511   {\r
 512     /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
 513     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 514     {\r
 515       FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
 516     }\r
 517     else\r
 518     {\r
 519       FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
 520     }\r
 521   }\r
 522 }\r
 523 \r
 524 /**\r
 525   * @brief  Enables or disables the PCCARD Memory Bank.\r
 526   * @param  NewState: new state of the PCCARD Memory Bank.  \r
 527   *   This parameter can be: ENABLE or DISABLE.\r
 528   * @retval None\r
 529   */\r
 530 void FSMC_PCCARDCmd(FunctionalState NewState)\r
 531 {\r
 532   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 533   \r
 534   if (NewState != DISABLE)\r
 535   {\r
 536     /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
 537     FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
 538   }\r
 539   else\r
 540   {\r
 541     /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
 542     FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
 543   }\r
 544 }\r
 545 \r
 546 /**\r
 547   * @brief  Enables or disables the FSMC NAND ECC feature.\r
 548   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 549   *   This parameter can be one of the following values:\r
 550   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 551   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 552   * @param  NewState: new state of the FSMC NAND ECC feature.  \r
 553   *   This parameter can be: ENABLE or DISABLE.\r
 554   * @retval None\r
 555   */\r
 556 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
 557 {\r
 558   assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
 559   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 560   \r
 561   if (NewState != DISABLE)\r
 562   {\r
 563     /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
 564     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 565     {\r
 566       FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
 567     }\r
 568     else\r
 569     {\r
 570       FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
 571     }\r
 572   }\r
 573   else\r
 574   {\r
 575     /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
 576     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 577     {\r
 578       FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
 579     }\r
 580     else\r
 581     {\r
 582       FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
 583     }\r
 584   }\r
 585 }\r
 586 \r
 587 /**\r
 588   * @brief  Returns the error correction code register value.\r
 589   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 590   *   This parameter can be one of the following values:\r
 591   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 592   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 593   * @retval The Error Correction Code (ECC) value.\r
 594   */\r
 595 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
 596 {\r
 597   uint32_t eccval = 0x00000000;\r
 598   \r
 599   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 600   {\r
 601     /* Get the ECCR2 register value */\r
 602     eccval = FSMC_Bank2->ECCR2;\r
 603   }\r
 604   else\r
 605   {\r
 606     /* Get the ECCR3 register value */\r
 607     eccval = FSMC_Bank3->ECCR3;\r
 608   }\r
 609   /* Return the error correction code value */\r
 610   return(eccval);\r
 611 }\r
 612 \r
 613 /**\r
 614   * @brief  Enables or disables the specified FSMC interrupts.\r
 615   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 616   *   This parameter can be one of the following values:\r
 617   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 618   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 619   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 620   * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
 621   *   This parameter can be any combination of the following values:\r
 622   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 623   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 624   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 625   * @param  NewState: new state of the specified FSMC interrupts.\r
 626   *   This parameter can be: ENABLE or DISABLE.\r
 627   * @retval None\r
 628   */\r
 629 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
 630 {\r
 631   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 632   assert_param(IS_FSMC_IT(FSMC_IT));    \r
 633   assert_param(IS_FUNCTIONAL_STATE(NewState));\r
 634   \r
 635   if (NewState != DISABLE)\r
 636   {\r
 637     /* Enable the selected FSMC_Bank2 interrupts */\r
 638     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 639     {\r
 640       FSMC_Bank2->SR2 |= FSMC_IT;\r
 641     }\r
 642     /* Enable the selected FSMC_Bank3 interrupts */\r
 643     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 644     {\r
 645       FSMC_Bank3->SR3 |= FSMC_IT;\r
 646     }\r
 647     /* Enable the selected FSMC_Bank4 interrupts */\r
 648     else\r
 649     {\r
 650       FSMC_Bank4->SR4 |= FSMC_IT;    \r
 651     }\r
 652   }\r
 653   else\r
 654   {\r
 655     /* Disable the selected FSMC_Bank2 interrupts */\r
 656     if(FSMC_Bank == FSMC_Bank2_NAND)\r
 657     {\r
 658       \r
 659       FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
 660     }\r
 661     /* Disable the selected FSMC_Bank3 interrupts */\r
 662     else if (FSMC_Bank == FSMC_Bank3_NAND)\r
 663     {\r
 664       FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
 665     }\r
 666     /* Disable the selected FSMC_Bank4 interrupts */\r
 667     else\r
 668     {\r
 669       FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    \r
 670     }\r
 671   }\r
 672 }\r
 673 \r
 674 /**\r
 675   * @brief  Checks whether the specified FSMC flag is set or not.\r
 676   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 677   *   This parameter can be one of the following values:\r
 678   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 679   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 680   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 681   * @param  FSMC_FLAG: specifies the flag to check.\r
 682   *   This parameter can be one of the following values:\r
 683   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 684   *     @arg FSMC_FLAG_Level: Level detection Flag.\r
 685   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 686   *     @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
 687   * @retval The new state of FSMC_FLAG (SET or RESET).\r
 688   */\r
 689 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 690 {\r
 691   FlagStatus bitstatus = RESET;\r
 692   uint32_t tmpsr = 0x00000000;\r
 693   \r
 694   /* Check the parameters */\r
 695   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 696   assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
 697   \r
 698   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 699   {\r
 700     tmpsr = FSMC_Bank2->SR2;\r
 701   }  \r
 702   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 703   {\r
 704     tmpsr = FSMC_Bank3->SR3;\r
 705   }\r
 706   /* FSMC_Bank4_PCCARD*/\r
 707   else\r
 708   {\r
 709     tmpsr = FSMC_Bank4->SR4;\r
 710   } \r
 711   \r
 712   /* Get the flag status */\r
 713   if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
 714   {\r
 715     bitstatus = SET;\r
 716   }\r
 717   else\r
 718   {\r
 719     bitstatus = RESET;\r
 720   }\r
 721   /* Return the flag status */\r
 722   return bitstatus;\r
 723 }\r
 724 \r
 725 /**\r
 726   * @brief  Clears the FSMC\92s pending flags.\r
 727   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 728   *   This parameter can be one of the following values:\r
 729   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 730   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 731   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 732   * @param  FSMC_FLAG: specifies the flag to clear.\r
 733   *   This parameter can be any combination of the following values:\r
 734   *     @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
 735   *     @arg FSMC_FLAG_Level: Level detection Flag.\r
 736   *     @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
 737   * @retval None\r
 738   */\r
 739 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
 740 {\r
 741  /* Check the parameters */\r
 742   assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
 743   assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
 744     \r
 745   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 746   {\r
 747     FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
 748   }  \r
 749   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 750   {\r
 751     FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
 752   }\r
 753   /* FSMC_Bank4_PCCARD*/\r
 754   else\r
 755   {\r
 756     FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
 757   }\r
 758 }\r
 759 \r
 760 /**\r
 761   * @brief  Checks whether the specified FSMC interrupt has occurred or not.\r
 762   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 763   *   This parameter can be one of the following values:\r
 764   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 765   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 766   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 767   * @param  FSMC_IT: specifies the FSMC interrupt source to check.\r
 768   *   This parameter can be one of the following values:\r
 769   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 770   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 771   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
 772   * @retval The new state of FSMC_IT (SET or RESET).\r
 773   */\r
 774 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 775 {\r
 776   ITStatus bitstatus = RESET;\r
 777   uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
 778   \r
 779   /* Check the parameters */\r
 780   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 781   assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
 782   \r
 783   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 784   {\r
 785     tmpsr = FSMC_Bank2->SR2;\r
 786   }  \r
 787   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 788   {\r
 789     tmpsr = FSMC_Bank3->SR3;\r
 790   }\r
 791   /* FSMC_Bank4_PCCARD*/\r
 792   else\r
 793   {\r
 794     tmpsr = FSMC_Bank4->SR4;\r
 795   } \r
 796   \r
 797   itstatus = tmpsr & FSMC_IT;\r
 798   \r
 799   itenable = tmpsr & (FSMC_IT >> 3);\r
 800   if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))\r
 801   {\r
 802     bitstatus = SET;\r
 803   }\r
 804   else\r
 805   {\r
 806     bitstatus = RESET;\r
 807   }\r
 808   return bitstatus; \r
 809 }\r
 810 \r
 811 /**\r
 812   * @brief  Clears the FSMC\92s interrupt pending bits.\r
 813   * @param  FSMC_Bank: specifies the FSMC Bank to be used\r
 814   *   This parameter can be one of the following values:\r
 815   *     @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
 816   *     @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
 817   *     @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
 818   * @param  FSMC_IT: specifies the interrupt pending bit to clear.\r
 819   *   This parameter can be any combination of the following values:\r
 820   *     @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
 821   *     @arg FSMC_IT_Level: Level edge detection interrupt.\r
 822   *     @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
 823   * @retval None\r
 824   */\r
 825 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
 826 {\r
 827   /* Check the parameters */\r
 828   assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
 829   assert_param(IS_FSMC_IT(FSMC_IT));\r
 830     \r
 831   if(FSMC_Bank == FSMC_Bank2_NAND)\r
 832   {\r
 833     FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
 834   }  \r
 835   else if(FSMC_Bank == FSMC_Bank3_NAND)\r
 836   {\r
 837     FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
 838   }\r
 839   /* FSMC_Bank4_PCCARD*/\r
 840   else\r
 841   {\r
 842     FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
 843   }\r
 844 }\r
 845 \r
 846 /**\r
 847   * @}\r
 848   */ \r
 849 \r
 850 /**\r
 851   * @}\r
 852   */\r
 853 \r
 854 /**\r
 855   * @}\r
 856   */\r
 857 \r
 858 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r