2 ******************************************************************************
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3 * @file stm32f10x_fsmc.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the FSMC firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_fsmc.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup STM32F10x_StdPeriph_Driver
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30 * @brief FSMC driver modules
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34 /** @defgroup FSMC_Private_TypesDefinitions
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41 /** @defgroup FSMC_Private_Defines
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45 /* --------------------- FSMC registers bit mask ---------------------------- */
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47 /* FSMC BCRx Mask */
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48 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
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49 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
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50 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
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52 /* FSMC PCRx Mask */
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53 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
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54 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
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55 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
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56 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
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57 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
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62 /** @defgroup FSMC_Private_Macros
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70 /** @defgroup FSMC_Private_Variables
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78 /** @defgroup FSMC_Private_FunctionPrototypes
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86 /** @defgroup FSMC_Private_Functions
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91 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
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93 * @param FSMC_Bank: specifies the FSMC Bank to be used
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94 * This parameter can be one of the following values:
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95 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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96 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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97 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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98 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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101 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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103 /* Check the parameter */
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104 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
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106 /* FSMC_Bank1_NORSRAM1 */
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107 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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109 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
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111 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
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114 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
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116 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
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117 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
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121 * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
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122 * @param FSMC_Bank: specifies the FSMC Bank to be used
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123 * This parameter can be one of the following values:
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124 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
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125 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
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128 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
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130 /* Check the parameter */
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131 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
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133 if(FSMC_Bank == FSMC_Bank2_NAND)
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135 /* Set the FSMC_Bank2 registers to their reset values */
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136 FSMC_Bank2->PCR2 = 0x00000018;
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137 FSMC_Bank2->SR2 = 0x00000040;
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138 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
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139 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
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141 /* FSMC_Bank3_NAND */
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144 /* Set the FSMC_Bank3 registers to their reset values */
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145 FSMC_Bank3->PCR3 = 0x00000018;
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146 FSMC_Bank3->SR3 = 0x00000040;
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147 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
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148 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
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153 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
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157 void FSMC_PCCARDDeInit(void)
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159 /* Set the FSMC_Bank4 registers to their reset values */
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160 FSMC_Bank4->PCR4 = 0x00000018;
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161 FSMC_Bank4->SR4 = 0x00000000;
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162 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
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163 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
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164 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
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168 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
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169 * parameters in the FSMC_NORSRAMInitStruct.
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170 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
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171 * structure that contains the configuration information for
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172 * the FSMC NOR/SRAM specified Banks.
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175 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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177 /* Check the parameters */
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178 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
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179 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
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180 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
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181 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
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182 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
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183 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
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184 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
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185 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
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186 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
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187 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
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188 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
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189 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
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190 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
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191 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
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192 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
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193 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
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194 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
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195 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
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196 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
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198 /* Bank1 NOR/SRAM control register configuration */
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199 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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200 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
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201 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
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202 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
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203 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
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204 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
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205 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
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206 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
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207 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
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208 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
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209 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
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210 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
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211 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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213 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
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215 /* Bank1 NOR/SRAM timing register configuration */
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216 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
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217 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
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218 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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219 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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220 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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221 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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222 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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223 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
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226 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
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227 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
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229 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
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230 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
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231 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
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232 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
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233 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
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234 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
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235 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
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236 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
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237 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
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238 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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239 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
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240 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
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241 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
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245 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
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250 * @brief Initializes the FSMC NAND Banks according to the specified
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251 * parameters in the FSMC_NANDInitStruct.
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252 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
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253 * structure that contains the configuration information for the FSMC NAND specified Banks.
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256 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
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258 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
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260 /* Check the parameters */
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261 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
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262 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
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263 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
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264 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
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265 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
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266 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
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267 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
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268 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
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269 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
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270 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
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271 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
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272 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
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273 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
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274 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
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275 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
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277 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
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278 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
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279 PCR_MemoryType_NAND |
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280 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
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281 FSMC_NANDInitStruct->FSMC_ECC |
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282 FSMC_NANDInitStruct->FSMC_ECCPageSize |
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283 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
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284 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
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286 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
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287 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
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288 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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289 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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290 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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292 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
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293 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
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294 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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295 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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296 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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298 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
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300 /* FSMC_Bank2_NAND registers configuration */
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301 FSMC_Bank2->PCR2 = tmppcr;
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302 FSMC_Bank2->PMEM2 = tmppmem;
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303 FSMC_Bank2->PATT2 = tmppatt;
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307 /* FSMC_Bank3_NAND registers configuration */
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308 FSMC_Bank3->PCR3 = tmppcr;
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309 FSMC_Bank3->PMEM3 = tmppmem;
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310 FSMC_Bank3->PATT3 = tmppatt;
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315 * @brief Initializes the FSMC PCCARD Bank according to the specified
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316 * parameters in the FSMC_PCCARDInitStruct.
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317 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
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318 * structure that contains the configuration information for the FSMC PCCARD Bank.
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321 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
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323 /* Check the parameters */
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324 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
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325 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
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326 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
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328 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
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329 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
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330 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
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331 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
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333 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
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334 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
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335 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
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336 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
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337 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
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338 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
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339 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
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340 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
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342 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
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343 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
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344 FSMC_MemoryDataWidth_16b |
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345 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
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346 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
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348 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
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349 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
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350 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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351 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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352 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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354 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
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355 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
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356 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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357 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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358 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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360 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
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361 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
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362 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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363 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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364 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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368 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
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369 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
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370 * structure which will be initialized.
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373 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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375 /* Reset NOR/SRAM Init structure parameters values */
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376 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
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377 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
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378 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
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379 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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380 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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381 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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382 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
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383 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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384 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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385 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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386 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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387 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
\r
388 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\r
389 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\r
390 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\r
391 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
\r
392 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
\r
393 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
\r
394 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
\r
395 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
\r
396 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
\r
397 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
\r
398 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
\r
399 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
\r
400 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
\r
401 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
\r
405 * @brief Fills each FSMC_NANDInitStruct member with its default value.
\r
406 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
\r
407 * structure which will be initialized.
\r
410 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
\r
412 /* Reset NAND Init structure parameters values */
\r
413 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
\r
414 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
\r
415 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
\r
416 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
\r
417 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
\r
418 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
\r
419 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
\r
420 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
\r
421 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
\r
422 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
\r
423 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
\r
424 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
\r
425 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
\r
426 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
\r
427 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
\r
431 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
\r
432 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
\r
433 * structure which will be initialized.
\r
436 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
\r
438 /* Reset PCCARD Init structure parameters values */
\r
439 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
\r
440 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
\r
441 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
\r
442 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
\r
443 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
\r
444 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
\r
445 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
\r
446 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
\r
447 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
\r
448 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
\r
449 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
\r
450 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
\r
451 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
\r
452 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
\r
453 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
\r
457 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
\r
458 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
459 * This parameter can be one of the following values:
\r
460 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
\r
461 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
\r
462 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
\r
463 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
\r
464 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
\r
467 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
\r
469 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
\r
470 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
472 if (NewState != DISABLE)
\r
474 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
\r
475 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
\r
479 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
\r
480 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
\r
485 * @brief Enables or disables the specified NAND Memory Bank.
\r
486 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
487 * This parameter can be one of the following values:
\r
488 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
489 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
490 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
\r
493 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
\r
495 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
\r
496 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
498 if (NewState != DISABLE)
\r
500 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
\r
501 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
503 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
\r
507 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
\r
512 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
\r
513 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
515 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
\r
519 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
\r
525 * @brief Enables or disables the PCCARD Memory Bank.
\r
526 * @param NewState: new state of the PCCARD Memory Bank.
\r
527 * This parameter can be: ENABLE or DISABLE.
\r
530 void FSMC_PCCARDCmd(FunctionalState NewState)
\r
532 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
534 if (NewState != DISABLE)
\r
536 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
\r
537 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
\r
541 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
\r
542 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
\r
547 * @brief Enables or disables the FSMC NAND ECC feature.
\r
548 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
549 * This parameter can be one of the following values:
\r
550 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
551 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
552 * @param NewState: new state of the FSMC NAND ECC feature.
\r
553 * This parameter can be: ENABLE or DISABLE.
\r
556 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
\r
558 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
\r
559 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
561 if (NewState != DISABLE)
\r
563 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
\r
564 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
566 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
\r
570 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
\r
575 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
\r
576 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
578 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
\r
582 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
\r
588 * @brief Returns the error correction code register value.
\r
589 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
590 * This parameter can be one of the following values:
\r
591 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
592 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
593 * @retval The Error Correction Code (ECC) value.
\r
595 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
\r
597 uint32_t eccval = 0x00000000;
\r
599 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
601 /* Get the ECCR2 register value */
\r
602 eccval = FSMC_Bank2->ECCR2;
\r
606 /* Get the ECCR3 register value */
\r
607 eccval = FSMC_Bank3->ECCR3;
\r
609 /* Return the error correction code value */
\r
614 * @brief Enables or disables the specified FSMC interrupts.
\r
615 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
616 * This parameter can be one of the following values:
\r
617 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
618 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
619 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
\r
620 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
\r
621 * This parameter can be any combination of the following values:
\r
622 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
\r
623 * @arg FSMC_IT_Level: Level edge detection interrupt.
\r
624 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
\r
625 * @param NewState: new state of the specified FSMC interrupts.
\r
626 * This parameter can be: ENABLE or DISABLE.
\r
629 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
\r
631 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
\r
632 assert_param(IS_FSMC_IT(FSMC_IT));
\r
633 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
635 if (NewState != DISABLE)
\r
637 /* Enable the selected FSMC_Bank2 interrupts */
\r
638 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
640 FSMC_Bank2->SR2 |= FSMC_IT;
\r
642 /* Enable the selected FSMC_Bank3 interrupts */
\r
643 else if (FSMC_Bank == FSMC_Bank3_NAND)
\r
645 FSMC_Bank3->SR3 |= FSMC_IT;
\r
647 /* Enable the selected FSMC_Bank4 interrupts */
\r
650 FSMC_Bank4->SR4 |= FSMC_IT;
\r
655 /* Disable the selected FSMC_Bank2 interrupts */
\r
656 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
659 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
\r
661 /* Disable the selected FSMC_Bank3 interrupts */
\r
662 else if (FSMC_Bank == FSMC_Bank3_NAND)
\r
664 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
\r
666 /* Disable the selected FSMC_Bank4 interrupts */
\r
669 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
\r
675 * @brief Checks whether the specified FSMC flag is set or not.
\r
676 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
677 * This parameter can be one of the following values:
\r
678 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
679 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
680 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
\r
681 * @param FSMC_FLAG: specifies the flag to check.
\r
682 * This parameter can be one of the following values:
\r
683 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
\r
684 * @arg FSMC_FLAG_Level: Level detection Flag.
\r
685 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
\r
686 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
\r
687 * @retval The new state of FSMC_FLAG (SET or RESET).
\r
689 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
\r
691 FlagStatus bitstatus = RESET;
\r
692 uint32_t tmpsr = 0x00000000;
\r
694 /* Check the parameters */
\r
695 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
\r
696 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
\r
698 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
700 tmpsr = FSMC_Bank2->SR2;
\r
702 else if(FSMC_Bank == FSMC_Bank3_NAND)
\r
704 tmpsr = FSMC_Bank3->SR3;
\r
706 /* FSMC_Bank4_PCCARD*/
\r
709 tmpsr = FSMC_Bank4->SR4;
\r
712 /* Get the flag status */
\r
713 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
\r
721 /* Return the flag status */
\r
726 * @brief Clears the FSMC
\92s pending flags.
\r
727 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
728 * This parameter can be one of the following values:
\r
729 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
730 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
731 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
\r
732 * @param FSMC_FLAG: specifies the flag to clear.
\r
733 * This parameter can be any combination of the following values:
\r
734 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
\r
735 * @arg FSMC_FLAG_Level: Level detection Flag.
\r
736 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
\r
739 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
\r
741 /* Check the parameters */
\r
742 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
\r
743 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
\r
745 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
747 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
\r
749 else if(FSMC_Bank == FSMC_Bank3_NAND)
\r
751 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
\r
753 /* FSMC_Bank4_PCCARD*/
\r
756 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
\r
761 * @brief Checks whether the specified FSMC interrupt has occurred or not.
\r
762 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
763 * This parameter can be one of the following values:
\r
764 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
765 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
766 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
\r
767 * @param FSMC_IT: specifies the FSMC interrupt source to check.
\r
768 * This parameter can be one of the following values:
\r
769 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
\r
770 * @arg FSMC_IT_Level: Level edge detection interrupt.
\r
771 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
\r
772 * @retval The new state of FSMC_IT (SET or RESET).
\r
774 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
\r
776 ITStatus bitstatus = RESET;
\r
777 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
\r
779 /* Check the parameters */
\r
780 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
\r
781 assert_param(IS_FSMC_GET_IT(FSMC_IT));
\r
783 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
785 tmpsr = FSMC_Bank2->SR2;
\r
787 else if(FSMC_Bank == FSMC_Bank3_NAND)
\r
789 tmpsr = FSMC_Bank3->SR3;
\r
791 /* FSMC_Bank4_PCCARD*/
\r
794 tmpsr = FSMC_Bank4->SR4;
\r
797 itstatus = tmpsr & FSMC_IT;
\r
799 itenable = tmpsr & (FSMC_IT >> 3);
\r
800 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
\r
812 * @brief Clears the FSMC
\92s interrupt pending bits.
\r
813 * @param FSMC_Bank: specifies the FSMC Bank to be used
\r
814 * This parameter can be one of the following values:
\r
815 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
\r
816 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
\r
817 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
\r
818 * @param FSMC_IT: specifies the interrupt pending bit to clear.
\r
819 * This parameter can be any combination of the following values:
\r
820 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
\r
821 * @arg FSMC_IT_Level: Level edge detection interrupt.
\r
822 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
\r
825 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
\r
827 /* Check the parameters */
\r
828 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
\r
829 assert_param(IS_FSMC_IT(FSMC_IT));
\r
831 if(FSMC_Bank == FSMC_Bank2_NAND)
\r
833 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
\r
835 else if(FSMC_Bank == FSMC_Bank3_NAND)
\r
837 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
\r
839 /* FSMC_Bank4_PCCARD*/
\r
842 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
\r
858 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r