2 ******************************************************************************
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3 * @file stm32f10x_dma.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the DMA firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_dma.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup STM32F10x_StdPeriph_Driver
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30 * @brief DMA driver modules
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34 /** @defgroup DMA_Private_TypesDefinitions
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41 /** @defgroup DMA_Private_Defines
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45 /* DMA ENABLE mask */
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46 #define CCR_ENABLE_Set ((uint32_t)0x00000001)
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47 #define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
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49 /* DMA1 Channelx interrupt pending bit masks */
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50 #define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
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51 #define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
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52 #define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
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53 #define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
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54 #define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
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55 #define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
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56 #define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
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58 /* DMA2 Channelx interrupt pending bit masks */
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59 #define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
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60 #define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
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61 #define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
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62 #define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
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63 #define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
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65 /* DMA2 FLAG mask */
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66 #define FLAG_Mask ((uint32_t)0x10000000)
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68 /* DMA registers Masks */
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69 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
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75 /** @defgroup DMA_Private_Macros
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83 /** @defgroup DMA_Private_Variables
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91 /** @defgroup DMA_Private_FunctionPrototypes
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99 /** @defgroup DMA_Private_Functions
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104 * @brief Deinitializes the DMAy Channelx registers to their default reset
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106 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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107 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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110 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
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112 /* Check the parameters */
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113 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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114 /* Disable the selected DMAy Channelx */
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115 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
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116 /* Reset DMAy Channelx control register */
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117 DMAy_Channelx->CCR = 0;
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119 /* Reset DMAy Channelx remaining bytes register */
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120 DMAy_Channelx->CNDTR = 0;
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122 /* Reset DMAy Channelx peripheral address register */
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123 DMAy_Channelx->CPAR = 0;
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125 /* Reset DMAy Channelx memory address register */
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126 DMAy_Channelx->CMAR = 0;
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128 if (DMAy_Channelx == DMA1_Channel1)
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130 /* Reset interrupt pending bits for DMA1 Channel1 */
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131 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
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133 else if (DMAy_Channelx == DMA1_Channel2)
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135 /* Reset interrupt pending bits for DMA1 Channel2 */
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136 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
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138 else if (DMAy_Channelx == DMA1_Channel3)
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140 /* Reset interrupt pending bits for DMA1 Channel3 */
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141 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
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143 else if (DMAy_Channelx == DMA1_Channel4)
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145 /* Reset interrupt pending bits for DMA1 Channel4 */
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146 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
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148 else if (DMAy_Channelx == DMA1_Channel5)
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150 /* Reset interrupt pending bits for DMA1 Channel5 */
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151 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
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153 else if (DMAy_Channelx == DMA1_Channel6)
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155 /* Reset interrupt pending bits for DMA1 Channel6 */
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156 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
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158 else if (DMAy_Channelx == DMA1_Channel7)
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160 /* Reset interrupt pending bits for DMA1 Channel7 */
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161 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
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163 else if (DMAy_Channelx == DMA2_Channel1)
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165 /* Reset interrupt pending bits for DMA2 Channel1 */
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166 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
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168 else if (DMAy_Channelx == DMA2_Channel2)
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170 /* Reset interrupt pending bits for DMA2 Channel2 */
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171 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
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173 else if (DMAy_Channelx == DMA2_Channel3)
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175 /* Reset interrupt pending bits for DMA2 Channel3 */
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176 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
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178 else if (DMAy_Channelx == DMA2_Channel4)
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180 /* Reset interrupt pending bits for DMA2 Channel4 */
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181 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
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185 if (DMAy_Channelx == DMA2_Channel5)
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187 /* Reset interrupt pending bits for DMA2 Channel5 */
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188 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
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194 * @brief Initializes the DMAy Channelx according to the specified
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195 * parameters in the DMA_InitStruct.
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196 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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197 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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198 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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199 * contains the configuration information for the specified DMA Channel.
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202 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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204 uint32_t tmpreg = 0;
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206 /* Check the parameters */
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207 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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208 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
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209 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
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210 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
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211 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
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212 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
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213 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
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214 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
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215 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
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216 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
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218 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
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219 /* Get the DMAy_Channelx CCR value */
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220 tmpreg = DMAy_Channelx->CCR;
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221 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
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222 tmpreg &= CCR_CLEAR_Mask;
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223 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
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224 /* Set DIR bit according to DMA_DIR value */
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225 /* Set CIRC bit according to DMA_Mode value */
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226 /* Set PINC bit according to DMA_PeripheralInc value */
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227 /* Set MINC bit according to DMA_MemoryInc value */
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228 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
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229 /* Set MSIZE bits according to DMA_MemoryDataSize value */
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230 /* Set PL bits according to DMA_Priority value */
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231 /* Set the MEM2MEM bit according to DMA_M2M value */
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232 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
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233 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
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234 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
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235 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
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237 /* Write to DMAy Channelx CCR */
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238 DMAy_Channelx->CCR = tmpreg;
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240 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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241 /* Write to DMAy Channelx CNDTR */
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242 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
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244 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
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245 /* Write to DMAy Channelx CPAR */
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246 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
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248 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
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249 /* Write to DMAy Channelx CMAR */
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250 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
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254 * @brief Fills each DMA_InitStruct member with its default value.
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255 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
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259 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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261 /*-------------- Reset DMA init structure parameters values ------------------*/
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262 /* Initialize the DMA_PeripheralBaseAddr member */
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263 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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264 /* Initialize the DMA_MemoryBaseAddr member */
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265 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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266 /* Initialize the DMA_DIR member */
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267 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
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268 /* Initialize the DMA_BufferSize member */
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269 DMA_InitStruct->DMA_BufferSize = 0;
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270 /* Initialize the DMA_PeripheralInc member */
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271 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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272 /* Initialize the DMA_MemoryInc member */
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273 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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274 /* Initialize the DMA_PeripheralDataSize member */
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275 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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276 /* Initialize the DMA_MemoryDataSize member */
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277 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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278 /* Initialize the DMA_Mode member */
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279 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
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280 /* Initialize the DMA_Priority member */
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281 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
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282 /* Initialize the DMA_M2M member */
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283 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
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287 * @brief Enables or disables the specified DMAy Channelx.
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288 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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289 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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290 * @param NewState: new state of the DMAy Channelx.
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291 * This parameter can be: ENABLE or DISABLE.
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294 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
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296 /* Check the parameters */
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297 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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298 assert_param(IS_FUNCTIONAL_STATE(NewState));
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300 if (NewState != DISABLE)
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302 /* Enable the selected DMAy Channelx */
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303 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
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307 /* Disable the selected DMAy Channelx */
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308 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
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313 * @brief Enables or disables the specified DMAy Channelx interrupts.
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314 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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315 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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316 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
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318 * This parameter can be any combination of the following values:
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319 * @arg DMA_IT_TC: Transfer complete interrupt mask
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320 * @arg DMA_IT_HT: Half transfer interrupt mask
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321 * @arg DMA_IT_TE: Transfer error interrupt mask
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322 * @param NewState: new state of the specified DMA interrupts.
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323 * This parameter can be: ENABLE or DISABLE.
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326 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
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328 /* Check the parameters */
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329 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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330 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
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331 assert_param(IS_FUNCTIONAL_STATE(NewState));
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332 if (NewState != DISABLE)
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334 /* Enable the selected DMA interrupts */
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335 DMAy_Channelx->CCR |= DMA_IT;
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339 /* Disable the selected DMA interrupts */
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340 DMAy_Channelx->CCR &= ~DMA_IT;
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345 * @brief Returns the number of remaining data units in the current
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346 * DMAy Channelx transfer.
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347 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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348 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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349 * @retval The number of remaining data units in the current DMAy Channelx
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352 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
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354 /* Check the parameters */
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355 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
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356 /* Return the number of remaining data units for DMAy Channelx */
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357 return ((uint16_t)(DMAy_Channelx->CNDTR));
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361 * @brief Checks whether the specified DMAy Channelx flag is set or not.
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362 * @param DMA_FLAG: specifies the flag to check.
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363 * This parameter can be one of the following values:
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364 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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365 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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366 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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367 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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368 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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369 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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370 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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371 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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372 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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373 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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374 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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375 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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376 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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377 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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378 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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379 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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380 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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381 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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382 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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383 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
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384 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
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385 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
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386 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
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387 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
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388 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
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389 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
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390 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
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391 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
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392 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
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393 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
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394 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
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395 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
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396 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
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397 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
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398 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
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399 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
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400 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
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401 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
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402 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
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403 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
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404 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
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405 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
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406 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
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407 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
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408 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
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409 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
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410 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
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411 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
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412 * @retval The new state of DMA_FLAG (SET or RESET).
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414 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
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416 FlagStatus bitstatus = RESET;
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417 uint32_t tmpreg = 0;
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418 /* Check the parameters */
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419 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
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421 /* Calculate the used DMA */
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422 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
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424 /* Get DMA2 ISR register value */
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425 tmpreg = DMA2->ISR ;
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429 /* Get DMA1 ISR register value */
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430 tmpreg = DMA1->ISR ;
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433 /* Check the status of the specified DMA flag */
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434 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
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436 /* DMA_FLAG is set */
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441 /* DMA_FLAG is reset */
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445 /* Return the DMA_FLAG status */
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450 * @brief Clears the DMAy Channelx's pending flags.
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451 * @param DMA_FLAG: specifies the flag to clear.
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452 * This parameter can be any combination (for the same DMA) of the following values:
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453 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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454 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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455 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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456 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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457 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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458 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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459 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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460 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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461 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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462 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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463 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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464 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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465 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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466 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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467 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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468 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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469 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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470 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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471 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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472 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
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473 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
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474 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
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475 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
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476 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
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477 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
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478 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
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479 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
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480 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
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481 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
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482 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
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483 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
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484 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
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485 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
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486 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
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487 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
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488 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
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489 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
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490 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
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491 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
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492 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
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493 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
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494 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
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495 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
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496 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
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497 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
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498 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
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499 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
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500 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
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503 void DMA_ClearFlag(uint32_t DMA_FLAG)
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505 /* Check the parameters */
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506 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
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507 /* Calculate the used DMA */
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509 if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
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511 /* Clear the selected DMA flags */
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512 DMA2->IFCR = DMA_FLAG;
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516 /* Clear the selected DMA flags */
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517 DMA1->IFCR = DMA_FLAG;
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522 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
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523 * @param DMA_IT: specifies the DMA interrupt source to check.
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524 * This parameter can be one of the following values:
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525 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
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526 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
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527 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
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528 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
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529 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
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530 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
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531 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
\r
532 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
\r
533 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
\r
534 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
\r
535 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
\r
536 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
\r
537 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
\r
538 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
\r
539 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
\r
540 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
\r
541 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
\r
542 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
\r
543 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
\r
544 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
\r
545 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
\r
546 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
\r
547 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
\r
548 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
\r
549 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
\r
550 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
\r
551 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
\r
552 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
\r
553 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
\r
554 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
\r
555 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
\r
556 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
\r
557 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
\r
558 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
\r
559 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
\r
560 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
\r
561 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
\r
562 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
\r
563 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
\r
564 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
\r
565 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
\r
566 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
\r
567 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
\r
568 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
\r
569 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
\r
570 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
\r
571 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
\r
572 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
\r
573 * @retval The new state of DMA_IT (SET or RESET).
\r
575 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
\r
577 ITStatus bitstatus = RESET;
\r
578 uint32_t tmpreg = 0;
\r
579 /* Check the parameters */
\r
580 assert_param(IS_DMA_GET_IT(DMA_IT));
\r
582 /* Calculate the used DMA */
\r
583 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
\r
585 /* Get DMA2 ISR register value */
\r
586 tmpreg = DMA2->ISR ;
\r
590 /* Get DMA1 ISR register value */
\r
591 tmpreg = DMA1->ISR ;
\r
594 /* Check the status of the specified DMA interrupt */
\r
595 if ((tmpreg & DMA_IT) != (uint32_t)RESET)
\r
597 /* DMA_IT is set */
\r
602 /* DMA_IT is reset */
\r
605 /* Return the DMA_IT status */
\r
610 * @brief Clears the DMAy Channelx
\92s interrupt pending bits.
\r
611 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
\r
612 * This parameter can be any combination (for the same DMA) of the following values:
\r
613 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
\r
614 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
\r
615 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
\r
616 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
\r
617 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
\r
618 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
\r
619 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
\r
620 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
\r
621 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
\r
622 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
\r
623 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
\r
624 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
\r
625 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
\r
626 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
\r
627 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
\r
628 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
\r
629 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
\r
630 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
\r
631 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
\r
632 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
\r
633 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
\r
634 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
\r
635 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
\r
636 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
\r
637 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
\r
638 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
\r
639 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
\r
640 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
\r
641 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
\r
642 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
\r
643 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
\r
644 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
\r
645 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
\r
646 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
\r
647 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
\r
648 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
\r
649 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
\r
650 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
\r
651 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
\r
652 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
\r
653 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
\r
654 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
\r
655 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
\r
656 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
\r
657 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
\r
658 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
\r
659 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
\r
660 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
\r
663 void DMA_ClearITPendingBit(uint32_t DMA_IT)
\r
665 /* Check the parameters */
\r
666 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
\r
668 /* Calculate the used DMA */
\r
669 if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
\r
671 /* Clear the selected DMA interrupt pending bits */
\r
672 DMA2->IFCR = DMA_IT;
\r
676 /* Clear the selected DMA interrupt pending bits */
\r
677 DMA1->IFCR = DMA_IT;
\r
693 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r