2 ******************************************************************************
\r
3 * @file stm32f10x_cec.c
\r
4 * @author MCD Application Team
\r
7 * @brief This file provides all the CEC firmware functions.
\r
8 ******************************************************************************
\r
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
\r
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
\r
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
\r
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
\r
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
\r
21 /* Includes ------------------------------------------------------------------*/
\r
22 #include "stm32f10x_cec.h"
\r
23 #include "stm32f10x_rcc.h"
\r
25 /** @addtogroup STM32F10x_StdPeriph_Driver
\r
30 * @brief CEC driver modules
\r
34 /** @defgroup CEC_Private_TypesDefinitions
\r
43 /** @defgroup CEC_Private_Defines
\r
47 /* ------------ CEC registers bit address in the alias region ----------- */
\r
48 #define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
\r
50 /* --- CFGR Register ---*/
\r
52 /* Alias word address of PE bit */
\r
53 #define CFGR_OFFSET (CEC_OFFSET + 0x00)
\r
54 #define PE_BitNumber 0x00
\r
55 #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
\r
57 /* Alias word address of IE bit */
\r
58 #define IE_BitNumber 0x01
\r
59 #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
\r
61 /* --- CSR Register ---*/
\r
63 /* Alias word address of TSOM bit */
\r
64 #define CSR_OFFSET (CEC_OFFSET + 0x10)
\r
65 #define TSOM_BitNumber 0x00
\r
66 #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
\r
68 /* Alias word address of TEOM bit */
\r
69 #define TEOM_BitNumber 0x01
\r
70 #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
\r
72 #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
\r
73 #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
\r
80 /** @defgroup CEC_Private_Macros
\r
89 /** @defgroup CEC_Private_Variables
\r
98 /** @defgroup CEC_Private_FunctionPrototypes
\r
107 /** @defgroup CEC_Private_Functions
\r
112 * @brief Deinitializes the CEC peripheral registers to their default reset
\r
117 void CEC_DeInit(void)
\r
119 /* Enable CEC reset state */
\r
120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
\r
121 /* Release CEC from reset state */
\r
122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
\r
127 * @brief Initializes the CEC peripheral according to the specified
\r
128 * parameters in the CEC_InitStruct.
\r
129 * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
\r
130 * contains the configuration information for the specified
\r
134 void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
\r
136 uint16_t tmpreg = 0;
\r
138 /* Check the parameters */
\r
139 assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
\r
140 assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
\r
142 /*---------------------------- CEC CFGR Configuration -----------------*/
\r
143 /* Get the CEC CFGR value */
\r
144 tmpreg = CEC->CFGR;
\r
146 /* Clear BTEM and BPEM bits */
\r
147 tmpreg &= CFGR_CLEAR_Mask;
\r
149 /* Configure CEC: Bit Timing Error and Bit Period Error */
\r
150 tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
\r
152 /* Write to CEC CFGR register*/
\r
153 CEC->CFGR = tmpreg;
\r
158 * @brief Enables or disables the specified CEC peripheral.
\r
159 * @param NewState: new state of the CEC peripheral.
\r
160 * This parameter can be: ENABLE or DISABLE.
\r
163 void CEC_Cmd(FunctionalState NewState)
\r
165 /* Check the parameters */
\r
166 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
168 *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
\r
170 if(NewState == DISABLE)
\r
172 /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
\r
173 while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
\r
180 * @brief Enables or disables the CEC interrupt.
\r
181 * @param NewState: new state of the CEC interrupt.
\r
182 * This parameter can be: ENABLE or DISABLE.
\r
185 void CEC_ITConfig(FunctionalState NewState)
\r
187 /* Check the parameters */
\r
188 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
190 *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
\r
194 * @brief Defines the Own Address of the CEC device.
\r
195 * @param CEC_OwnAddress: The CEC own address
\r
198 void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
\r
200 /* Check the parameters */
\r
201 assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
\r
203 /* Set the CEC own address */
\r
204 CEC->OAR = CEC_OwnAddress;
\r
208 * @brief Sets the CEC prescaler value.
\r
209 * @param CEC_Prescaler: CEC prescaler new value
\r
212 void CEC_SetPrescaler(uint16_t CEC_Prescaler)
\r
214 /* Check the parameters */
\r
215 assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
\r
217 /* Set the Prescaler value*/
\r
218 CEC->PRES = CEC_Prescaler;
\r
222 * @brief Transmits single data through the CEC peripheral.
\r
223 * @param Data: the data to transmit.
\r
226 void CEC_SendDataByte(uint8_t Data)
\r
228 /* Transmit Data */
\r
234 * @brief Returns the most recent received data by the CEC peripheral.
\r
236 * @retval The received data.
\r
238 uint8_t CEC_ReceiveDataByte(void)
\r
241 return (uint8_t)(CEC->RXD);
\r
245 * @brief Starts a new message.
\r
249 void CEC_StartOfMessage(void)
\r
251 /* Starts of new message */
\r
252 *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
\r
256 * @brief Transmits message with or without an EOM bit.
\r
257 * @param NewState: new state of the CEC Tx End Of Message.
\r
258 * This parameter can be: ENABLE or DISABLE.
\r
261 void CEC_EndOfMessageCmd(FunctionalState NewState)
\r
263 /* Check the parameters */
\r
264 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
266 /* The data byte will be transmitted with or without an EOM bit*/
\r
267 *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
\r
271 * @brief Gets the CEC flag status
\r
272 * @param CEC_FLAG: specifies the CEC flag to check.
\r
273 * This parameter can be one of the following values:
\r
274 * @arg CEC_FLAG_BTE: Bit Timing Error
\r
275 * @arg CEC_FLAG_BPE: Bit Period Error
\r
276 * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
\r
277 * @arg CEC_FLAG_SBE: Start Bit Error
\r
278 * @arg CEC_FLAG_ACKE: Block Acknowledge Error
\r
279 * @arg CEC_FLAG_LINE: Line Error
\r
280 * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error
\r
281 * @arg CEC_FLAG_TEOM: Tx End Of Message
\r
282 * @arg CEC_FLAG_TERR: Tx Error
\r
283 * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
\r
284 * @arg CEC_FLAG_RSOM: Rx Start Of Message
\r
285 * @arg CEC_FLAG_REOM: Rx End Of Message
\r
286 * @arg CEC_FLAG_RERR: Rx Error
\r
287 * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
\r
288 * @retval The new state of CEC_FLAG (SET or RESET)
\r
290 FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
\r
292 FlagStatus bitstatus = RESET;
\r
293 uint32_t cecreg = 0, cecbase = 0;
\r
295 /* Check the parameters */
\r
296 assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
\r
298 /* Get the CEC peripheral base address */
\r
299 cecbase = (uint32_t)(CEC_BASE);
\r
301 /* Read flag register index */
\r
302 cecreg = CEC_FLAG >> 28;
\r
304 /* Get bit[23:0] of the flag */
\r
305 CEC_FLAG &= FLAG_Mask;
\r
309 /* Flag in CEC ESR Register */
\r
310 CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
\r
312 /* Get the CEC ESR register address */
\r
317 /* Get the CEC CSR register address */
\r
321 if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
\r
323 /* CEC_FLAG is set */
\r
328 /* CEC_FLAG is reset */
\r
332 /* Return the CEC_FLAG status */
\r
337 * @brief Clears the CEC's pending flags.
\r
338 * @param CEC_FLAG: specifies the flag to clear.
\r
339 * This parameter can be any combination of the following values:
\r
340 * @arg CEC_FLAG_TERR: Tx Error
\r
341 * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
\r
342 * @arg CEC_FLAG_RSOM: Rx Start Of Message
\r
343 * @arg CEC_FLAG_REOM: Rx End Of Message
\r
344 * @arg CEC_FLAG_RERR: Rx Error
\r
345 * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
\r
348 void CEC_ClearFlag(uint32_t CEC_FLAG)
\r
350 uint32_t tmp = 0x0;
\r
352 /* Check the parameters */
\r
353 assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
\r
355 tmp = CEC->CSR & 0x2;
\r
357 /* Clear the selected CEC flags */
\r
358 CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
\r
362 * @brief Checks whether the specified CEC interrupt has occurred or not.
\r
363 * @param CEC_IT: specifies the CEC interrupt source to check.
\r
364 * This parameter can be one of the following values:
\r
365 * @arg CEC_IT_TERR: Tx Error
\r
366 * @arg CEC_IT_TBTF: Tx Block Transfer Finished
\r
367 * @arg CEC_IT_RERR: Rx Error
\r
368 * @arg CEC_IT_RBTF: Rx Block Transfer Finished
\r
369 * @retval The new state of CEC_IT (SET or RESET).
\r
371 ITStatus CEC_GetITStatus(uint8_t CEC_IT)
\r
373 ITStatus bitstatus = RESET;
\r
374 uint32_t enablestatus = 0;
\r
376 /* Check the parameters */
\r
377 assert_param(IS_CEC_GET_IT(CEC_IT));
\r
379 /* Get the CEC IT enable bit status */
\r
380 enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
\r
382 /* Check the status of the specified CEC interrupt */
\r
383 if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
\r
385 /* CEC_IT is set */
\r
390 /* CEC_IT is reset */
\r
393 /* Return the CEC_IT status */
\r
398 * @brief Clears the CEC's interrupt pending bits.
\r
399 * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
\r
400 * This parameter can be any combination of the following values:
\r
401 * @arg CEC_IT_TERR: Tx Error
\r
402 * @arg CEC_IT_TBTF: Tx Block Transfer Finished
\r
403 * @arg CEC_IT_RERR: Rx Error
\r
404 * @arg CEC_IT_RBTF: Rx Block Transfer Finished
\r
407 void CEC_ClearITPendingBit(uint16_t CEC_IT)
\r
409 uint32_t tmp = 0x0;
\r
411 /* Check the parameters */
\r
412 assert_param(IS_CEC_GET_IT(CEC_IT));
\r
414 tmp = CEC->CSR & 0x2;
\r
416 /* Clear the selected CEC interrupt pending bits */
\r
417 CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
\r
432 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r