2 ******************************************************************************
\r
3 * @file stm32f10x_adc.c
\r
4 * @author MCD Application Team
\r
7 * @brief This file provides all the ADC firmware functions.
\r
8 ******************************************************************************
\r
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
\r
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
\r
13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
\r
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
\r
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
\r
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
\r
18 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
\r
21 /* Includes ------------------------------------------------------------------*/
\r
22 #include "stm32f10x_adc.h"
\r
23 #include "stm32f10x_rcc.h"
\r
25 /** @addtogroup STM32F10x_StdPeriph_Driver
\r
30 * @brief ADC driver modules
\r
34 /** @defgroup ADC_Private_TypesDefinitions
\r
42 /** @defgroup ADC_Private_Defines
\r
46 /* ADC DISCNUM mask */
\r
47 #define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
\r
49 /* ADC DISCEN mask */
\r
50 #define CR1_DISCEN_Set ((uint32_t)0x00000800)
\r
51 #define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
\r
53 /* ADC JAUTO mask */
\r
54 #define CR1_JAUTO_Set ((uint32_t)0x00000400)
\r
55 #define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
\r
57 /* ADC JDISCEN mask */
\r
58 #define CR1_JDISCEN_Set ((uint32_t)0x00001000)
\r
59 #define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
\r
61 /* ADC AWDCH mask */
\r
62 #define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
\r
64 /* ADC Analog watchdog enable mode mask */
\r
65 #define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
\r
67 /* CR1 register Mask */
\r
68 #define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
\r
71 #define CR2_ADON_Set ((uint32_t)0x00000001)
\r
72 #define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
\r
75 #define CR2_DMA_Set ((uint32_t)0x00000100)
\r
76 #define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
\r
78 /* ADC RSTCAL mask */
\r
79 #define CR2_RSTCAL_Set ((uint32_t)0x00000008)
\r
82 #define CR2_CAL_Set ((uint32_t)0x00000004)
\r
84 /* ADC SWSTART mask */
\r
85 #define CR2_SWSTART_Set ((uint32_t)0x00400000)
\r
87 /* ADC EXTTRIG mask */
\r
88 #define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
\r
89 #define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
\r
91 /* ADC Software start mask */
\r
92 #define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
\r
93 #define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
\r
95 /* ADC JEXTSEL mask */
\r
96 #define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
\r
98 /* ADC JEXTTRIG mask */
\r
99 #define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
\r
100 #define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
\r
102 /* ADC JSWSTART mask */
\r
103 #define CR2_JSWSTART_Set ((uint32_t)0x00200000)
\r
105 /* ADC injected software start mask */
\r
106 #define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
\r
107 #define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
\r
109 /* ADC TSPD mask */
\r
110 #define CR2_TSVREFE_Set ((uint32_t)0x00800000)
\r
111 #define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
\r
113 /* CR2 register Mask */
\r
114 #define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
\r
117 #define SQR3_SQ_Set ((uint32_t)0x0000001F)
\r
118 #define SQR2_SQ_Set ((uint32_t)0x0000001F)
\r
119 #define SQR1_SQ_Set ((uint32_t)0x0000001F)
\r
121 /* SQR1 register Mask */
\r
122 #define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
\r
124 /* ADC JSQx mask */
\r
125 #define JSQR_JSQ_Set ((uint32_t)0x0000001F)
\r
128 #define JSQR_JL_Set ((uint32_t)0x00300000)
\r
129 #define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
\r
131 /* ADC SMPx mask */
\r
132 #define SMPR1_SMP_Set ((uint32_t)0x00000007)
\r
133 #define SMPR2_SMP_Set ((uint32_t)0x00000007)
\r
135 /* ADC JDRx registers offset */
\r
136 #define JDR_Offset ((uint8_t)0x28)
\r
138 /* ADC1 DR register base address */
\r
139 #define DR_ADDRESS ((uint32_t)0x4001244C)
\r
145 /** @defgroup ADC_Private_Macros
\r
153 /** @defgroup ADC_Private_Variables
\r
161 /** @defgroup ADC_Private_FunctionPrototypes
\r
169 /** @defgroup ADC_Private_Functions
\r
174 * @brief Deinitializes the ADCx peripheral registers to their default reset values.
\r
175 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
178 void ADC_DeInit(ADC_TypeDef* ADCx)
\r
180 /* Check the parameters */
\r
181 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
185 /* Enable ADC1 reset state */
\r
186 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
\r
187 /* Release ADC1 from reset state */
\r
188 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
\r
190 else if (ADCx == ADC2)
\r
192 /* Enable ADC2 reset state */
\r
193 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
\r
194 /* Release ADC2 from reset state */
\r
195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
\r
201 /* Enable ADC3 reset state */
\r
202 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
\r
203 /* Release ADC3 from reset state */
\r
204 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
\r
210 * @brief Initializes the ADCx peripheral according to the specified parameters
\r
211 * in the ADC_InitStruct.
\r
212 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
213 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
\r
214 * the configuration information for the specified ADC peripheral.
\r
217 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
\r
219 uint32_t tmpreg1 = 0;
\r
220 uint8_t tmpreg2 = 0;
\r
221 /* Check the parameters */
\r
222 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
223 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
\r
224 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
\r
225 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
\r
226 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
\r
227 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
\r
228 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
\r
230 /*---------------------------- ADCx CR1 Configuration -----------------*/
\r
231 /* Get the ADCx CR1 value */
\r
232 tmpreg1 = ADCx->CR1;
\r
233 /* Clear DUALMOD and SCAN bits */
\r
234 tmpreg1 &= CR1_CLEAR_Mask;
\r
235 /* Configure ADCx: Dual mode and scan conversion mode */
\r
236 /* Set DUALMOD bits according to ADC_Mode value */
\r
237 /* Set SCAN bit according to ADC_ScanConvMode value */
\r
238 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
\r
239 /* Write to ADCx CR1 */
\r
240 ADCx->CR1 = tmpreg1;
\r
242 /*---------------------------- ADCx CR2 Configuration -----------------*/
\r
243 /* Get the ADCx CR2 value */
\r
244 tmpreg1 = ADCx->CR2;
\r
245 /* Clear CONT, ALIGN and EXTSEL bits */
\r
246 tmpreg1 &= CR2_CLEAR_Mask;
\r
247 /* Configure ADCx: external trigger event and continuous conversion mode */
\r
248 /* Set ALIGN bit according to ADC_DataAlign value */
\r
249 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
\r
250 /* Set CONT bit according to ADC_ContinuousConvMode value */
\r
251 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
\r
252 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
\r
253 /* Write to ADCx CR2 */
\r
254 ADCx->CR2 = tmpreg1;
\r
256 /*---------------------------- ADCx SQR1 Configuration -----------------*/
\r
257 /* Get the ADCx SQR1 value */
\r
258 tmpreg1 = ADCx->SQR1;
\r
260 tmpreg1 &= SQR1_CLEAR_Mask;
\r
261 /* Configure ADCx: regular channel sequence length */
\r
262 /* Set L bits according to ADC_NbrOfChannel value */
\r
263 tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
\r
264 tmpreg1 |= (uint32_t)tmpreg2 << 20;
\r
265 /* Write to ADCx SQR1 */
\r
266 ADCx->SQR1 = tmpreg1;
\r
270 * @brief Fills each ADC_InitStruct member with its default value.
\r
271 * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
\r
274 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
\r
276 /* Reset ADC init structure parameters values */
\r
277 /* Initialize the ADC_Mode member */
\r
278 ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
\r
279 /* initialize the ADC_ScanConvMode member */
\r
280 ADC_InitStruct->ADC_ScanConvMode = DISABLE;
\r
281 /* Initialize the ADC_ContinuousConvMode member */
\r
282 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
\r
283 /* Initialize the ADC_ExternalTrigConv member */
\r
284 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
\r
285 /* Initialize the ADC_DataAlign member */
\r
286 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
\r
287 /* Initialize the ADC_NbrOfChannel member */
\r
288 ADC_InitStruct->ADC_NbrOfChannel = 1;
\r
292 * @brief Enables or disables the specified ADC peripheral.
\r
293 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
294 * @param NewState: new state of the ADCx peripheral.
\r
295 * This parameter can be: ENABLE or DISABLE.
\r
298 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
300 /* Check the parameters */
\r
301 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
302 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
303 if (NewState != DISABLE)
\r
305 /* Set the ADON bit to wake up the ADC from power down mode */
\r
306 ADCx->CR2 |= CR2_ADON_Set;
\r
310 /* Disable the selected ADC peripheral */
\r
311 ADCx->CR2 &= CR2_ADON_Reset;
\r
316 * @brief Enables or disables the specified ADC DMA request.
\r
317 * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
\r
318 * Note: ADC2 hasn't a DMA capability.
\r
319 * @param NewState: new state of the selected ADC DMA transfer.
\r
320 * This parameter can be: ENABLE or DISABLE.
\r
323 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
325 /* Check the parameters */
\r
326 assert_param(IS_ADC_DMA_PERIPH(ADCx));
\r
327 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
328 if (NewState != DISABLE)
\r
330 /* Enable the selected ADC DMA request */
\r
331 ADCx->CR2 |= CR2_DMA_Set;
\r
335 /* Disable the selected ADC DMA request */
\r
336 ADCx->CR2 &= CR2_DMA_Reset;
\r
341 * @brief Enables or disables the specified ADC interrupts.
\r
342 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
343 * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
\r
344 * This parameter can be any combination of the following values:
\r
345 * @arg ADC_IT_EOC: End of conversion interrupt mask
\r
346 * @arg ADC_IT_AWD: Analog watchdog interrupt mask
\r
347 * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
\r
348 * @param NewState: new state of the specified ADC interrupts.
\r
349 * This parameter can be: ENABLE or DISABLE.
\r
352 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
\r
354 uint8_t itmask = 0;
\r
355 /* Check the parameters */
\r
356 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
357 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
358 assert_param(IS_ADC_IT(ADC_IT));
\r
359 /* Get the ADC IT index */
\r
360 itmask = (uint8_t)ADC_IT;
\r
361 if (NewState != DISABLE)
\r
363 /* Enable the selected ADC interrupts */
\r
364 ADCx->CR1 |= itmask;
\r
368 /* Disable the selected ADC interrupts */
\r
369 ADCx->CR1 &= (~(uint32_t)itmask);
\r
374 * @brief Resets the selected ADC calibration registers.
\r
375 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
378 void ADC_ResetCalibration(ADC_TypeDef* ADCx)
\r
380 /* Check the parameters */
\r
381 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
382 /* Resets the selected ADC calibartion registers */
\r
383 ADCx->CR2 |= CR2_RSTCAL_Set;
\r
387 * @brief Gets the selected ADC reset calibration registers status.
\r
388 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
389 * @retval The new state of ADC reset calibration registers (SET or RESET).
\r
391 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
\r
393 FlagStatus bitstatus = RESET;
\r
394 /* Check the parameters */
\r
395 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
396 /* Check the status of RSTCAL bit */
\r
397 if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
\r
399 /* RSTCAL bit is set */
\r
404 /* RSTCAL bit is reset */
\r
407 /* Return the RSTCAL bit status */
\r
412 * @brief Starts the selected ADC calibration process.
\r
413 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
416 void ADC_StartCalibration(ADC_TypeDef* ADCx)
\r
418 /* Check the parameters */
\r
419 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
420 /* Enable the selected ADC calibration process */
\r
421 ADCx->CR2 |= CR2_CAL_Set;
\r
425 * @brief Gets the selected ADC calibration status.
\r
426 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
427 * @retval The new state of ADC calibration (SET or RESET).
\r
429 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
\r
431 FlagStatus bitstatus = RESET;
\r
432 /* Check the parameters */
\r
433 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
434 /* Check the status of CAL bit */
\r
435 if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
\r
437 /* CAL bit is set: calibration on going */
\r
442 /* CAL bit is reset: end of calibration */
\r
445 /* Return the CAL bit status */
\r
450 * @brief Enables or disables the selected ADC software start conversion .
\r
451 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
452 * @param NewState: new state of the selected ADC software start conversion.
\r
453 * This parameter can be: ENABLE or DISABLE.
\r
456 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
458 /* Check the parameters */
\r
459 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
460 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
461 if (NewState != DISABLE)
\r
463 /* Enable the selected ADC conversion on external event and start the selected
\r
465 ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
\r
469 /* Disable the selected ADC conversion on external event and stop the selected
\r
471 ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
\r
476 * @brief Gets the selected ADC Software start conversion Status.
\r
477 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
478 * @retval The new state of ADC software start conversion (SET or RESET).
\r
480 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
\r
482 FlagStatus bitstatus = RESET;
\r
483 /* Check the parameters */
\r
484 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
485 /* Check the status of SWSTART bit */
\r
486 if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
\r
488 /* SWSTART bit is set */
\r
493 /* SWSTART bit is reset */
\r
496 /* Return the SWSTART bit status */
\r
501 * @brief Configures the discontinuous mode for the selected ADC regular
\r
503 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
504 * @param Number: specifies the discontinuous mode regular channel
\r
505 * count value. This number must be between 1 and 8.
\r
508 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
\r
510 uint32_t tmpreg1 = 0;
\r
511 uint32_t tmpreg2 = 0;
\r
512 /* Check the parameters */
\r
513 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
514 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
\r
515 /* Get the old register value */
\r
516 tmpreg1 = ADCx->CR1;
\r
517 /* Clear the old discontinuous mode channel count */
\r
518 tmpreg1 &= CR1_DISCNUM_Reset;
\r
519 /* Set the discontinuous mode channel count */
\r
520 tmpreg2 = Number - 1;
\r
521 tmpreg1 |= tmpreg2 << 13;
\r
522 /* Store the new register value */
\r
523 ADCx->CR1 = tmpreg1;
\r
527 * @brief Enables or disables the discontinuous mode on regular group
\r
528 * channel for the specified ADC
\r
529 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
530 * @param NewState: new state of the selected ADC discontinuous mode
\r
531 * on regular group channel.
\r
532 * This parameter can be: ENABLE or DISABLE.
\r
535 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
537 /* Check the parameters */
\r
538 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
539 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
540 if (NewState != DISABLE)
\r
542 /* Enable the selected ADC regular discontinuous mode */
\r
543 ADCx->CR1 |= CR1_DISCEN_Set;
\r
547 /* Disable the selected ADC regular discontinuous mode */
\r
548 ADCx->CR1 &= CR1_DISCEN_Reset;
\r
553 * @brief Configures for the selected ADC regular channel its corresponding
\r
554 * rank in the sequencer and its sample time.
\r
555 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
556 * @param ADC_Channel: the ADC channel to configure.
\r
557 * This parameter can be one of the following values:
\r
558 * @arg ADC_Channel_0: ADC Channel0 selected
\r
559 * @arg ADC_Channel_1: ADC Channel1 selected
\r
560 * @arg ADC_Channel_2: ADC Channel2 selected
\r
561 * @arg ADC_Channel_3: ADC Channel3 selected
\r
562 * @arg ADC_Channel_4: ADC Channel4 selected
\r
563 * @arg ADC_Channel_5: ADC Channel5 selected
\r
564 * @arg ADC_Channel_6: ADC Channel6 selected
\r
565 * @arg ADC_Channel_7: ADC Channel7 selected
\r
566 * @arg ADC_Channel_8: ADC Channel8 selected
\r
567 * @arg ADC_Channel_9: ADC Channel9 selected
\r
568 * @arg ADC_Channel_10: ADC Channel10 selected
\r
569 * @arg ADC_Channel_11: ADC Channel11 selected
\r
570 * @arg ADC_Channel_12: ADC Channel12 selected
\r
571 * @arg ADC_Channel_13: ADC Channel13 selected
\r
572 * @arg ADC_Channel_14: ADC Channel14 selected
\r
573 * @arg ADC_Channel_15: ADC Channel15 selected
\r
574 * @arg ADC_Channel_16: ADC Channel16 selected
\r
575 * @arg ADC_Channel_17: ADC Channel17 selected
\r
576 * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
\r
577 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
\r
578 * This parameter can be one of the following values:
\r
579 * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
\r
580 * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
\r
581 * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
\r
582 * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
\r
583 * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
\r
584 * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
\r
585 * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
\r
586 * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
\r
589 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
\r
591 uint32_t tmpreg1 = 0, tmpreg2 = 0;
\r
592 /* Check the parameters */
\r
593 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
594 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
595 assert_param(IS_ADC_REGULAR_RANK(Rank));
\r
596 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
\r
597 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
\r
598 if (ADC_Channel > ADC_Channel_9)
\r
600 /* Get the old register value */
\r
601 tmpreg1 = ADCx->SMPR1;
\r
602 /* Calculate the mask to clear */
\r
603 tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
\r
604 /* Clear the old channel sample time */
\r
605 tmpreg1 &= ~tmpreg2;
\r
606 /* Calculate the mask to set */
\r
607 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
\r
608 /* Set the new channel sample time */
\r
609 tmpreg1 |= tmpreg2;
\r
610 /* Store the new register value */
\r
611 ADCx->SMPR1 = tmpreg1;
\r
613 else /* ADC_Channel include in ADC_Channel_[0..9] */
\r
615 /* Get the old register value */
\r
616 tmpreg1 = ADCx->SMPR2;
\r
617 /* Calculate the mask to clear */
\r
618 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
\r
619 /* Clear the old channel sample time */
\r
620 tmpreg1 &= ~tmpreg2;
\r
621 /* Calculate the mask to set */
\r
622 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
\r
623 /* Set the new channel sample time */
\r
624 tmpreg1 |= tmpreg2;
\r
625 /* Store the new register value */
\r
626 ADCx->SMPR2 = tmpreg1;
\r
628 /* For Rank 1 to 6 */
\r
631 /* Get the old register value */
\r
632 tmpreg1 = ADCx->SQR3;
\r
633 /* Calculate the mask to clear */
\r
634 tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
\r
635 /* Clear the old SQx bits for the selected rank */
\r
636 tmpreg1 &= ~tmpreg2;
\r
637 /* Calculate the mask to set */
\r
638 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
\r
639 /* Set the SQx bits for the selected rank */
\r
640 tmpreg1 |= tmpreg2;
\r
641 /* Store the new register value */
\r
642 ADCx->SQR3 = tmpreg1;
\r
644 /* For Rank 7 to 12 */
\r
645 else if (Rank < 13)
\r
647 /* Get the old register value */
\r
648 tmpreg1 = ADCx->SQR2;
\r
649 /* Calculate the mask to clear */
\r
650 tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
\r
651 /* Clear the old SQx bits for the selected rank */
\r
652 tmpreg1 &= ~tmpreg2;
\r
653 /* Calculate the mask to set */
\r
654 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
\r
655 /* Set the SQx bits for the selected rank */
\r
656 tmpreg1 |= tmpreg2;
\r
657 /* Store the new register value */
\r
658 ADCx->SQR2 = tmpreg1;
\r
660 /* For Rank 13 to 16 */
\r
663 /* Get the old register value */
\r
664 tmpreg1 = ADCx->SQR1;
\r
665 /* Calculate the mask to clear */
\r
666 tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
\r
667 /* Clear the old SQx bits for the selected rank */
\r
668 tmpreg1 &= ~tmpreg2;
\r
669 /* Calculate the mask to set */
\r
670 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
\r
671 /* Set the SQx bits for the selected rank */
\r
672 tmpreg1 |= tmpreg2;
\r
673 /* Store the new register value */
\r
674 ADCx->SQR1 = tmpreg1;
\r
679 * @brief Enables or disables the ADCx conversion through external trigger.
\r
680 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
681 * @param NewState: new state of the selected ADC external trigger start of conversion.
\r
682 * This parameter can be: ENABLE or DISABLE.
\r
685 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
687 /* Check the parameters */
\r
688 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
689 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
690 if (NewState != DISABLE)
\r
692 /* Enable the selected ADC conversion on external event */
\r
693 ADCx->CR2 |= CR2_EXTTRIG_Set;
\r
697 /* Disable the selected ADC conversion on external event */
\r
698 ADCx->CR2 &= CR2_EXTTRIG_Reset;
\r
703 * @brief Returns the last ADCx conversion result data for regular channel.
\r
704 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
705 * @retval The Data conversion value.
\r
707 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
\r
709 /* Check the parameters */
\r
710 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
711 /* Return the selected ADC conversion value */
\r
712 return (uint16_t) ADCx->DR;
\r
716 * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
\r
717 * @retval The Data conversion value.
\r
719 uint32_t ADC_GetDualModeConversionValue(void)
\r
721 /* Return the dual mode conversion value */
\r
722 return (*(__IO uint32_t *) DR_ADDRESS);
\r
726 * @brief Enables or disables the selected ADC automatic injected group
\r
727 * conversion after regular one.
\r
728 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
729 * @param NewState: new state of the selected ADC auto injected conversion
\r
730 * This parameter can be: ENABLE or DISABLE.
\r
733 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
735 /* Check the parameters */
\r
736 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
737 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
738 if (NewState != DISABLE)
\r
740 /* Enable the selected ADC automatic injected group conversion */
\r
741 ADCx->CR1 |= CR1_JAUTO_Set;
\r
745 /* Disable the selected ADC automatic injected group conversion */
\r
746 ADCx->CR1 &= CR1_JAUTO_Reset;
\r
751 * @brief Enables or disables the discontinuous mode for injected group
\r
752 * channel for the specified ADC
\r
753 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
754 * @param NewState: new state of the selected ADC discontinuous mode
\r
755 * on injected group channel.
\r
756 * This parameter can be: ENABLE or DISABLE.
\r
759 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
761 /* Check the parameters */
\r
762 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
763 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
764 if (NewState != DISABLE)
\r
766 /* Enable the selected ADC injected discontinuous mode */
\r
767 ADCx->CR1 |= CR1_JDISCEN_Set;
\r
771 /* Disable the selected ADC injected discontinuous mode */
\r
772 ADCx->CR1 &= CR1_JDISCEN_Reset;
\r
777 * @brief Configures the ADCx external trigger for injected channels conversion.
\r
778 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
779 * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
\r
780 * This parameter can be one of the following values:
\r
781 * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
\r
782 * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
\r
783 * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
\r
784 * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
\r
785 * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
\r
786 * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
\r
787 * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
\r
788 * capture compare4 event selected (for ADC1 and ADC2)
\r
789 * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
\r
790 * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
\r
791 * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
\r
792 * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
\r
793 * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
\r
794 * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
\r
795 * by external trigger (for ADC1, ADC2 and ADC3)
\r
798 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
\r
800 uint32_t tmpreg = 0;
\r
801 /* Check the parameters */
\r
802 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
803 assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
\r
804 /* Get the old register value */
\r
805 tmpreg = ADCx->CR2;
\r
806 /* Clear the old external event selection for injected group */
\r
807 tmpreg &= CR2_JEXTSEL_Reset;
\r
808 /* Set the external event selection for injected group */
\r
809 tmpreg |= ADC_ExternalTrigInjecConv;
\r
810 /* Store the new register value */
\r
811 ADCx->CR2 = tmpreg;
\r
815 * @brief Enables or disables the ADCx injected channels conversion through
\r
817 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
818 * @param NewState: new state of the selected ADC external trigger start of
\r
819 * injected conversion.
\r
820 * This parameter can be: ENABLE or DISABLE.
\r
823 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
825 /* Check the parameters */
\r
826 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
827 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
828 if (NewState != DISABLE)
\r
830 /* Enable the selected ADC external event selection for injected group */
\r
831 ADCx->CR2 |= CR2_JEXTTRIG_Set;
\r
835 /* Disable the selected ADC external event selection for injected group */
\r
836 ADCx->CR2 &= CR2_JEXTTRIG_Reset;
\r
841 * @brief Enables or disables the selected ADC start of the injected
\r
842 * channels conversion.
\r
843 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
844 * @param NewState: new state of the selected ADC software start injected conversion.
\r
845 * This parameter can be: ENABLE or DISABLE.
\r
848 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
850 /* Check the parameters */
\r
851 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
852 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
853 if (NewState != DISABLE)
\r
855 /* Enable the selected ADC conversion for injected group on external event and start the selected
\r
856 ADC injected conversion */
\r
857 ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
\r
861 /* Disable the selected ADC conversion on external event for injected group and stop the selected
\r
862 ADC injected conversion */
\r
863 ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
\r
868 * @brief Gets the selected ADC Software start injected conversion Status.
\r
869 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
870 * @retval The new state of ADC software start injected conversion (SET or RESET).
\r
872 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
\r
874 FlagStatus bitstatus = RESET;
\r
875 /* Check the parameters */
\r
876 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
877 /* Check the status of JSWSTART bit */
\r
878 if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
\r
880 /* JSWSTART bit is set */
\r
885 /* JSWSTART bit is reset */
\r
888 /* Return the JSWSTART bit status */
\r
893 * @brief Configures for the selected ADC injected channel its corresponding
\r
894 * rank in the sequencer and its sample time.
\r
895 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
896 * @param ADC_Channel: the ADC channel to configure.
\r
897 * This parameter can be one of the following values:
\r
898 * @arg ADC_Channel_0: ADC Channel0 selected
\r
899 * @arg ADC_Channel_1: ADC Channel1 selected
\r
900 * @arg ADC_Channel_2: ADC Channel2 selected
\r
901 * @arg ADC_Channel_3: ADC Channel3 selected
\r
902 * @arg ADC_Channel_4: ADC Channel4 selected
\r
903 * @arg ADC_Channel_5: ADC Channel5 selected
\r
904 * @arg ADC_Channel_6: ADC Channel6 selected
\r
905 * @arg ADC_Channel_7: ADC Channel7 selected
\r
906 * @arg ADC_Channel_8: ADC Channel8 selected
\r
907 * @arg ADC_Channel_9: ADC Channel9 selected
\r
908 * @arg ADC_Channel_10: ADC Channel10 selected
\r
909 * @arg ADC_Channel_11: ADC Channel11 selected
\r
910 * @arg ADC_Channel_12: ADC Channel12 selected
\r
911 * @arg ADC_Channel_13: ADC Channel13 selected
\r
912 * @arg ADC_Channel_14: ADC Channel14 selected
\r
913 * @arg ADC_Channel_15: ADC Channel15 selected
\r
914 * @arg ADC_Channel_16: ADC Channel16 selected
\r
915 * @arg ADC_Channel_17: ADC Channel17 selected
\r
916 * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
\r
917 * @param ADC_SampleTime: The sample time value to be set for the selected channel.
\r
918 * This parameter can be one of the following values:
\r
919 * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
\r
920 * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
\r
921 * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
\r
922 * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
\r
923 * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
\r
924 * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
\r
925 * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
\r
926 * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
\r
929 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
\r
931 uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
\r
932 /* Check the parameters */
\r
933 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
934 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
935 assert_param(IS_ADC_INJECTED_RANK(Rank));
\r
936 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
\r
937 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
\r
938 if (ADC_Channel > ADC_Channel_9)
\r
940 /* Get the old register value */
\r
941 tmpreg1 = ADCx->SMPR1;
\r
942 /* Calculate the mask to clear */
\r
943 tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
\r
944 /* Clear the old channel sample time */
\r
945 tmpreg1 &= ~tmpreg2;
\r
946 /* Calculate the mask to set */
\r
947 tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
\r
948 /* Set the new channel sample time */
\r
949 tmpreg1 |= tmpreg2;
\r
950 /* Store the new register value */
\r
951 ADCx->SMPR1 = tmpreg1;
\r
953 else /* ADC_Channel include in ADC_Channel_[0..9] */
\r
955 /* Get the old register value */
\r
956 tmpreg1 = ADCx->SMPR2;
\r
957 /* Calculate the mask to clear */
\r
958 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
\r
959 /* Clear the old channel sample time */
\r
960 tmpreg1 &= ~tmpreg2;
\r
961 /* Calculate the mask to set */
\r
962 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
\r
963 /* Set the new channel sample time */
\r
964 tmpreg1 |= tmpreg2;
\r
965 /* Store the new register value */
\r
966 ADCx->SMPR2 = tmpreg1;
\r
968 /* Rank configuration */
\r
969 /* Get the old register value */
\r
970 tmpreg1 = ADCx->JSQR;
\r
971 /* Get JL value: Number = JL+1 */
\r
972 tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
\r
973 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
\r
974 tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
\r
975 /* Clear the old JSQx bits for the selected rank */
\r
976 tmpreg1 &= ~tmpreg2;
\r
977 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
\r
978 tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
\r
979 /* Set the JSQx bits for the selected rank */
\r
980 tmpreg1 |= tmpreg2;
\r
981 /* Store the new register value */
\r
982 ADCx->JSQR = tmpreg1;
\r
986 * @brief Configures the sequencer length for injected channels
\r
987 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
988 * @param Length: The sequencer length.
\r
989 * This parameter must be a number between 1 to 4.
\r
992 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
\r
994 uint32_t tmpreg1 = 0;
\r
995 uint32_t tmpreg2 = 0;
\r
996 /* Check the parameters */
\r
997 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
998 assert_param(IS_ADC_INJECTED_LENGTH(Length));
\r
1000 /* Get the old register value */
\r
1001 tmpreg1 = ADCx->JSQR;
\r
1002 /* Clear the old injected sequnence lenght JL bits */
\r
1003 tmpreg1 &= JSQR_JL_Reset;
\r
1004 /* Set the injected sequnence lenght JL bits */
\r
1005 tmpreg2 = Length - 1;
\r
1006 tmpreg1 |= tmpreg2 << 20;
\r
1007 /* Store the new register value */
\r
1008 ADCx->JSQR = tmpreg1;
\r
1012 * @brief Set the injected channels conversion value offset
\r
1013 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1014 * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
\r
1015 * This parameter can be one of the following values:
\r
1016 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
\r
1017 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
\r
1018 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
\r
1019 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
\r
1020 * @param Offset: the offset value for the selected ADC injected channel
\r
1021 * This parameter must be a 12bit value.
\r
1024 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
\r
1026 __IO uint32_t tmp = 0;
\r
1028 /* Check the parameters */
\r
1029 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1030 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
\r
1031 assert_param(IS_ADC_OFFSET(Offset));
\r
1033 tmp = (uint32_t)ADCx;
\r
1034 tmp += ADC_InjectedChannel;
\r
1036 /* Set the selected injected channel data offset */
\r
1037 *(__IO uint32_t *) tmp = (uint32_t)Offset;
\r
1041 * @brief Returns the ADC injected channel conversion result
\r
1042 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1043 * @param ADC_InjectedChannel: the converted ADC injected channel.
\r
1044 * This parameter can be one of the following values:
\r
1045 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
\r
1046 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
\r
1047 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
\r
1048 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
\r
1049 * @retval The Data conversion value.
\r
1051 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
\r
1053 __IO uint32_t tmp = 0;
\r
1055 /* Check the parameters */
\r
1056 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1057 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
\r
1059 tmp = (uint32_t)ADCx;
\r
1060 tmp += ADC_InjectedChannel + JDR_Offset;
\r
1062 /* Returns the selected injected channel conversion data value */
\r
1063 return (uint16_t) (*(__IO uint32_t*) tmp);
\r
1067 * @brief Enables or disables the analog watchdog on single/all regular
\r
1068 * or injected channels
\r
1069 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1070 * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
\r
1071 * This parameter can be one of the following values:
\r
1072 * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
\r
1073 * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
\r
1074 * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
\r
1075 * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
\r
1076 * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
\r
1077 * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
\r
1078 * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
\r
1081 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
\r
1083 uint32_t tmpreg = 0;
\r
1084 /* Check the parameters */
\r
1085 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1086 assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
\r
1087 /* Get the old register value */
\r
1088 tmpreg = ADCx->CR1;
\r
1089 /* Clear AWDEN, AWDENJ and AWDSGL bits */
\r
1090 tmpreg &= CR1_AWDMode_Reset;
\r
1091 /* Set the analog watchdog enable mode */
\r
1092 tmpreg |= ADC_AnalogWatchdog;
\r
1093 /* Store the new register value */
\r
1094 ADCx->CR1 = tmpreg;
\r
1098 * @brief Configures the high and low thresholds of the analog watchdog.
\r
1099 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1100 * @param HighThreshold: the ADC analog watchdog High threshold value.
\r
1101 * This parameter must be a 12bit value.
\r
1102 * @param LowThreshold: the ADC analog watchdog Low threshold value.
\r
1103 * This parameter must be a 12bit value.
\r
1106 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
\r
1107 uint16_t LowThreshold)
\r
1109 /* Check the parameters */
\r
1110 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1111 assert_param(IS_ADC_THRESHOLD(HighThreshold));
\r
1112 assert_param(IS_ADC_THRESHOLD(LowThreshold));
\r
1113 /* Set the ADCx high threshold */
\r
1114 ADCx->HTR = HighThreshold;
\r
1115 /* Set the ADCx low threshold */
\r
1116 ADCx->LTR = LowThreshold;
\r
1120 * @brief Configures the analog watchdog guarded single channel
\r
1121 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1122 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
\r
1123 * This parameter can be one of the following values:
\r
1124 * @arg ADC_Channel_0: ADC Channel0 selected
\r
1125 * @arg ADC_Channel_1: ADC Channel1 selected
\r
1126 * @arg ADC_Channel_2: ADC Channel2 selected
\r
1127 * @arg ADC_Channel_3: ADC Channel3 selected
\r
1128 * @arg ADC_Channel_4: ADC Channel4 selected
\r
1129 * @arg ADC_Channel_5: ADC Channel5 selected
\r
1130 * @arg ADC_Channel_6: ADC Channel6 selected
\r
1131 * @arg ADC_Channel_7: ADC Channel7 selected
\r
1132 * @arg ADC_Channel_8: ADC Channel8 selected
\r
1133 * @arg ADC_Channel_9: ADC Channel9 selected
\r
1134 * @arg ADC_Channel_10: ADC Channel10 selected
\r
1135 * @arg ADC_Channel_11: ADC Channel11 selected
\r
1136 * @arg ADC_Channel_12: ADC Channel12 selected
\r
1137 * @arg ADC_Channel_13: ADC Channel13 selected
\r
1138 * @arg ADC_Channel_14: ADC Channel14 selected
\r
1139 * @arg ADC_Channel_15: ADC Channel15 selected
\r
1140 * @arg ADC_Channel_16: ADC Channel16 selected
\r
1141 * @arg ADC_Channel_17: ADC Channel17 selected
\r
1144 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
\r
1146 uint32_t tmpreg = 0;
\r
1147 /* Check the parameters */
\r
1148 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1149 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
1150 /* Get the old register value */
\r
1151 tmpreg = ADCx->CR1;
\r
1152 /* Clear the Analog watchdog channel select bits */
\r
1153 tmpreg &= CR1_AWDCH_Reset;
\r
1154 /* Set the Analog watchdog channel */
\r
1155 tmpreg |= ADC_Channel;
\r
1156 /* Store the new register value */
\r
1157 ADCx->CR1 = tmpreg;
\r
1161 * @brief Enables or disables the temperature sensor and Vrefint channel.
\r
1162 * @param NewState: new state of the temperature sensor.
\r
1163 * This parameter can be: ENABLE or DISABLE.
\r
1166 void ADC_TempSensorVrefintCmd(FunctionalState NewState)
\r
1168 /* Check the parameters */
\r
1169 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1170 if (NewState != DISABLE)
\r
1172 /* Enable the temperature sensor and Vrefint channel*/
\r
1173 ADC1->CR2 |= CR2_TSVREFE_Set;
\r
1177 /* Disable the temperature sensor and Vrefint channel*/
\r
1178 ADC1->CR2 &= CR2_TSVREFE_Reset;
\r
1183 * @brief Checks whether the specified ADC flag is set or not.
\r
1184 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1185 * @param ADC_FLAG: specifies the flag to check.
\r
1186 * This parameter can be one of the following values:
\r
1187 * @arg ADC_FLAG_AWD: Analog watchdog flag
\r
1188 * @arg ADC_FLAG_EOC: End of conversion flag
\r
1189 * @arg ADC_FLAG_JEOC: End of injected group conversion flag
\r
1190 * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
\r
1191 * @arg ADC_FLAG_STRT: Start of regular group conversion flag
\r
1192 * @retval The new state of ADC_FLAG (SET or RESET).
\r
1194 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
\r
1196 FlagStatus bitstatus = RESET;
\r
1197 /* Check the parameters */
\r
1198 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1199 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
\r
1200 /* Check the status of the specified ADC flag */
\r
1201 if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
\r
1203 /* ADC_FLAG is set */
\r
1208 /* ADC_FLAG is reset */
\r
1209 bitstatus = RESET;
\r
1211 /* Return the ADC_FLAG status */
\r
1216 * @brief Clears the ADCx's pending flags.
\r
1217 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1218 * @param ADC_FLAG: specifies the flag to clear.
\r
1219 * This parameter can be any combination of the following values:
\r
1220 * @arg ADC_FLAG_AWD: Analog watchdog flag
\r
1221 * @arg ADC_FLAG_EOC: End of conversion flag
\r
1222 * @arg ADC_FLAG_JEOC: End of injected group conversion flag
\r
1223 * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
\r
1224 * @arg ADC_FLAG_STRT: Start of regular group conversion flag
\r
1227 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
\r
1229 /* Check the parameters */
\r
1230 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1231 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
\r
1232 /* Clear the selected ADC flags */
\r
1233 ADCx->SR = ~(uint32_t)ADC_FLAG;
\r
1237 * @brief Checks whether the specified ADC interrupt has occurred or not.
\r
1238 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1239 * @param ADC_IT: specifies the ADC interrupt source to check.
\r
1240 * This parameter can be one of the following values:
\r
1241 * @arg ADC_IT_EOC: End of conversion interrupt mask
\r
1242 * @arg ADC_IT_AWD: Analog watchdog interrupt mask
\r
1243 * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
\r
1244 * @retval The new state of ADC_IT (SET or RESET).
\r
1246 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
\r
1248 ITStatus bitstatus = RESET;
\r
1249 uint32_t itmask = 0, enablestatus = 0;
\r
1250 /* Check the parameters */
\r
1251 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1252 assert_param(IS_ADC_GET_IT(ADC_IT));
\r
1253 /* Get the ADC IT index */
\r
1254 itmask = ADC_IT >> 8;
\r
1255 /* Get the ADC_IT enable bit status */
\r
1256 enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
\r
1257 /* Check the status of the specified ADC interrupt */
\r
1258 if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
\r
1260 /* ADC_IT is set */
\r
1265 /* ADC_IT is reset */
\r
1266 bitstatus = RESET;
\r
1268 /* Return the ADC_IT status */
\r
1273 * @brief Clears the ADCx
\92s interrupt pending bits.
\r
1274 * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
\r
1275 * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
\r
1276 * This parameter can be any combination of the following values:
\r
1277 * @arg ADC_IT_EOC: End of conversion interrupt mask
\r
1278 * @arg ADC_IT_AWD: Analog watchdog interrupt mask
\r
1279 * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
\r
1282 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
\r
1284 uint8_t itmask = 0;
\r
1285 /* Check the parameters */
\r
1286 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1287 assert_param(IS_ADC_IT(ADC_IT));
\r
1288 /* Get the ADC IT index */
\r
1289 itmask = (uint8_t)(ADC_IT >> 8);
\r
1290 /* Clear the selected ADC interrupt pending bits */
\r
1291 ADCx->SR = ~(uint32_t)itmask;
\r
1306 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r