2 ******************************************************************************
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3 * @file stm32l1xx_dma.h
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4 * @author MCD Application Team
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6 * @date 31-December-2010
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7 * @brief This file contains all the functions prototypes for the DMA firmware
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9 ******************************************************************************
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12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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19 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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20 ******************************************************************************
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23 /* Define to prevent recursive inclusion -------------------------------------*/
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24 #ifndef __STM32L1xx_DMA_H
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25 #define __STM32L1xx_DMA_H
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31 /* Includes ------------------------------------------------------------------*/
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32 #include "stm32l1xx.h"
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34 /** @addtogroup STM32L1xx_StdPeriph_Driver
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42 /* Exported types ------------------------------------------------------------*/
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45 * @brief DMA Init structure definition
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50 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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52 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
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54 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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55 This parameter can be a value of @ref DMA_data_transfer_direction */
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57 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
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58 The data unit is equal to the configuration set in DMA_PeripheralDataSize
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59 or DMA_MemoryDataSize members depending in the transfer direction. */
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61 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
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62 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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64 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
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65 This parameter can be a value of @ref DMA_memory_incremented_mode */
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67 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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68 This parameter can be a value of @ref DMA_peripheral_data_size */
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70 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
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71 This parameter can be a value of @ref DMA_memory_data_size */
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73 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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74 This parameter can be a value of @ref DMA_circular_normal_mode.
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75 @note: The circular buffer mode cannot be used if the memory-to-memory
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76 data transfer is configured on the selected Channel */
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78 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
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79 This parameter can be a value of @ref DMA_priority_level */
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81 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
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82 This parameter can be a value of @ref DMA_memory_to_memory */
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85 /* Exported constants --------------------------------------------------------*/
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87 /** @defgroup DMA_Exported_Constants
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91 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
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92 ((PERIPH) == DMA1_Channel2) || \
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93 ((PERIPH) == DMA1_Channel3) || \
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94 ((PERIPH) == DMA1_Channel4) || \
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95 ((PERIPH) == DMA1_Channel5) || \
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96 ((PERIPH) == DMA1_Channel6) || \
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97 ((PERIPH) == DMA1_Channel7))
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99 /** @defgroup DMA_data_transfer_direction
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103 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
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104 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
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105 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
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106 ((DIR) == DMA_DIR_PeripheralSRC))
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111 /** @defgroup DMA_peripheral_incremented_mode
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115 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
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116 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
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117 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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118 ((STATE) == DMA_PeripheralInc_Disable))
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123 /** @defgroup DMA_memory_incremented_mode
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127 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
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128 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
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129 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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130 ((STATE) == DMA_MemoryInc_Disable))
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135 /** @defgroup DMA_peripheral_data_size
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139 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
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140 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
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141 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
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142 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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143 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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144 ((SIZE) == DMA_PeripheralDataSize_Word))
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149 /** @defgroup DMA_memory_data_size
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153 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
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154 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
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155 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
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156 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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157 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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158 ((SIZE) == DMA_MemoryDataSize_Word))
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163 /** @defgroup DMA_circular_normal_mode
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167 #define DMA_Mode_Circular ((uint32_t)0x00000020)
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168 #define DMA_Mode_Normal ((uint32_t)0x00000000)
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169 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
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174 /** @defgroup DMA_priority_level
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178 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
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179 #define DMA_Priority_High ((uint32_t)0x00002000)
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180 #define DMA_Priority_Medium ((uint32_t)0x00001000)
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181 #define DMA_Priority_Low ((uint32_t)0x00000000)
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182 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
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183 ((PRIORITY) == DMA_Priority_High) || \
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184 ((PRIORITY) == DMA_Priority_Medium) || \
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185 ((PRIORITY) == DMA_Priority_Low))
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190 /** @defgroup DMA_memory_to_memory
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194 #define DMA_M2M_Enable ((uint32_t)0x00004000)
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195 #define DMA_M2M_Disable ((uint32_t)0x00000000)
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196 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
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202 /** @defgroup DMA_interrupts_definition
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206 #define DMA_IT_TC ((uint32_t)0x00000002)
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207 #define DMA_IT_HT ((uint32_t)0x00000004)
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208 #define DMA_IT_TE ((uint32_t)0x00000008)
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209 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
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211 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
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212 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
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213 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
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214 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
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215 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
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216 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
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217 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
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218 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
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219 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
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220 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
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221 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
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222 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
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223 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
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224 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
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225 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
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226 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
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227 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
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228 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
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229 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
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230 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
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231 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
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232 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
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233 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
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234 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
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235 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
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236 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
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237 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
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238 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
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240 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))
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242 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
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243 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
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244 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
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245 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
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246 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
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247 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
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248 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
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249 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
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250 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
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251 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
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252 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
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253 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
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254 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
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255 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))
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261 /** @defgroup DMA_flags_definition
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264 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
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265 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
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266 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
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267 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
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268 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
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269 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
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270 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
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271 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
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272 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
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273 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
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274 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
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275 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
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276 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
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277 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
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278 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
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279 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
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280 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
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281 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
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282 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
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283 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
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284 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
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285 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
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286 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
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287 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
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288 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
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289 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
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290 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
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291 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
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293 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))
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295 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
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296 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
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297 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
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298 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
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299 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
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300 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
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301 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
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302 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
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303 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
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304 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
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305 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
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306 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
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307 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
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308 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))
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313 /** @defgroup DMA_Buffer_Size
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317 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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327 /* Exported macro ------------------------------------------------------------*/
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328 /* Exported functions ------------------------------------------------------- */
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330 /* Function used to set the DMA configuration to the default reset state *****/
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331 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
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333 /* Initialization and Configuration functions *********************************/
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334 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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335 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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336 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
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338 /* Data Counter functions *****************************************************/
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339 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
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340 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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342 /* Interrupts and flags management functions **********************************/
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343 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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344 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
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345 void DMA_ClearFlag(uint32_t DMA_FLAG);
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346 ITStatus DMA_GetITStatus(uint32_t DMA_IT);
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347 void DMA_ClearITPendingBit(uint32_t DMA_IT);
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353 #endif /*__STM32L1xx_DMA_H */
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363 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
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