2 ******************************************************************************
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3 * @file system_stm32f10x.c
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4 * @author MCD Application Team
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7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 ******************************************************************************
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10 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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12 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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14 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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18 ******************************************************************************
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21 /** @addtogroup CMSIS
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25 /** @addtogroup stm32f10x_system
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29 /** @addtogroup STM32F10x_System_Private_Includes
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33 #include "stm32f10x.h"
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39 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
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47 /** @addtogroup STM32F10x_System_Private_Defines
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51 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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52 frequency (after reset the HSI is used as SYSCLK source)
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56 1. After each device reset the HSI is used as System clock source.
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58 2. Please make sure that the selected System clock doesn't exceed your device's
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61 3. If none of the define below is enabled, the HSI is used as System clock
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64 4. The System clock configuration functions provided within this file assume that:
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65 - For Low and Medium density Value line devices an external 8MHz crystal
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66 is used to drive the System clock.
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67 - For Low, Medium and High density devices an external 8MHz crystal is
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68 used to drive the System clock.
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69 - For Connectivity line devices an external 25MHz crystal is used to drive
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71 If you are using different crystal you have to adapt those functions accordingly.
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74 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL)
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75 /* #define SYSCLK_FREQ_HSE HSE_Value */
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76 #define SYSCLK_FREQ_24MHz 24000000
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78 /* #define SYSCLK_FREQ_HSE HSE_Value */
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79 /* #define SYSCLK_FREQ_24MHz 24000000 */
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80 /* #define SYSCLK_FREQ_36MHz 36000000 */
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81 /* #define SYSCLK_FREQ_48MHz 48000000 */
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82 /* #define SYSCLK_FREQ_56MHz 56000000 */
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83 #define SYSCLK_FREQ_72MHz 72000000
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86 /*!< Uncomment the following line if you need to use external SRAM mounted
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87 on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory */
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88 #if defined (STM32F10X_HD) || (defined STM32F10X_XL)
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89 /* #define DATA_IN_ExtSRAM */
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96 /** @addtogroup STM32F10x_System_Private_Macros
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104 /** @addtogroup STM32F10x_System_Private_Variables
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108 /*******************************************************************************
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109 * Clock Definitions
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110 *******************************************************************************/
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111 #ifdef SYSCLK_FREQ_HSE
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112 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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113 #elif defined SYSCLK_FREQ_24MHz
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114 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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115 #elif defined SYSCLK_FREQ_36MHz
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116 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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117 #elif defined SYSCLK_FREQ_48MHz
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118 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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119 #elif defined SYSCLK_FREQ_56MHz
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120 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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121 #elif defined SYSCLK_FREQ_72MHz
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122 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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123 #else /*!< HSI Selected as System Clock source */
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124 uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */
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127 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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132 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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136 static void SetSysClock(void);
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138 #ifdef SYSCLK_FREQ_HSE
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139 static void SetSysClockToHSE(void);
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140 #elif defined SYSCLK_FREQ_24MHz
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141 static void SetSysClockTo24(void);
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142 #elif defined SYSCLK_FREQ_36MHz
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143 static void SetSysClockTo36(void);
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144 #elif defined SYSCLK_FREQ_48MHz
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145 static void SetSysClockTo48(void);
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146 #elif defined SYSCLK_FREQ_56MHz
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147 static void SetSysClockTo56(void);
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148 #elif defined SYSCLK_FREQ_72MHz
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149 static void SetSysClockTo72(void);
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152 #ifdef DATA_IN_ExtSRAM
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153 static void SystemInit_ExtMemCtl(void);
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154 #endif /* DATA_IN_ExtSRAM */
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160 /** @addtogroup STM32F10x_System_Private_Functions
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165 * @brief Setup the microcontroller system
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166 * Initialize the Embedded Flash Interface, the PLL and update the
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167 * SystemCoreClock variable.
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168 * @note This function should be used only after reset.
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172 void SystemInit (void)
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174 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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175 /* Set HSION bit */
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176 RCC->CR |= (uint32_t)0x00000001;
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178 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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179 #ifndef STM32F10X_CL
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180 RCC->CFGR &= (uint32_t)0xF8FF0000;
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182 RCC->CFGR &= (uint32_t)0xF0FF0000;
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183 #endif /* STM32F10X_CL */
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185 /* Reset HSEON, CSSON and PLLON bits */
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186 RCC->CR &= (uint32_t)0xFEF6FFFF;
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188 /* Reset HSEBYP bit */
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189 RCC->CR &= (uint32_t)0xFFFBFFFF;
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191 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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192 RCC->CFGR &= (uint32_t)0xFF80FFFF;
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194 #ifdef STM32F10X_CL
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195 /* Reset PLL2ON and PLL3ON bits */
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196 RCC->CR &= (uint32_t)0xEBFFFFFF;
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198 /* Disable all interrupts and clear pending bits */
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199 RCC->CIR = 0x00FF0000;
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201 /* Reset CFGR2 register */
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202 RCC->CFGR2 = 0x00000000;
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203 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
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204 /* Disable all interrupts and clear pending bits */
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205 RCC->CIR = 0x009F0000;
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207 /* Reset CFGR2 register */
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208 RCC->CFGR2 = 0x00000000;
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210 /* Disable all interrupts and clear pending bits */
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211 RCC->CIR = 0x009F0000;
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212 #endif /* STM32F10X_CL */
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214 #if defined (STM32F10X_HD) || (defined STM32F10X_XL)
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215 #ifdef DATA_IN_ExtSRAM
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216 SystemInit_ExtMemCtl();
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217 #endif /* DATA_IN_ExtSRAM */
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220 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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221 /* Configure the Flash Latency cycles and enable prefetch buffer */
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226 * @brief Update SystemCoreClock according to Clock Register Values
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231 void SystemCoreClockUpdate (void)
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233 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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235 #ifdef STM32F10X_CL
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236 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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237 #endif /* STM32F10X_CL */
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239 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
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240 uint32_t prediv1factor = 0;
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241 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */
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243 /* Get SYSCLK source -------------------------------------------------------*/
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244 tmp = RCC->CFGR & RCC_CFGR_SWS;
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248 case 0x00: /* HSI used as system clock */
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249 SystemCoreClock = HSI_Value;
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251 case 0x04: /* HSE used as system clock */
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252 SystemCoreClock = HSE_Value;
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254 case 0x08: /* PLL used as system clock */
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256 /* Get PLL clock source and multiplication factor ----------------------*/
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257 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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258 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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260 #ifndef STM32F10X_CL
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261 pllmull = ( pllmull >> 18) + 2;
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263 if (pllsource == 0x00)
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265 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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266 SystemCoreClock = (HSI_Value >> 1) * pllmull;
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270 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
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271 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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272 /* HSE oscillator clock selected as PREDIV1 clock entry */
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273 SystemCoreClock = (HSE_Value / prediv1factor) * pllmull;
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275 /* HSE selected as PLL clock entry */
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276 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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277 {/* HSE oscillator clock divided by 2 */
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278 SystemCoreClock = (HSE_Value >> 1) * pllmull;
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282 SystemCoreClock = HSE_Value * pllmull;
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287 pllmull = pllmull >> 18;
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289 if (pllmull != 0x0D)
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294 { /* PLL multiplication factor = PLL input clock * 6.5 */
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298 if (pllsource == 0x00)
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300 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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301 SystemCoreClock = (HSI_Value >> 1) * pllmull;
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304 {/* PREDIV1 selected as PLL clock entry */
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306 /* Get PREDIV1 clock source and division factor */
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307 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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308 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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310 if (prediv1source == 0)
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312 /* HSE oscillator clock selected as PREDIV1 clock entry */
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313 SystemCoreClock = (HSE_Value / prediv1factor) * pllmull;
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316 {/* PLL2 clock selected as PREDIV1 clock entry */
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318 /* Get PREDIV2 division factor and PLL2 multiplication factor */
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319 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
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320 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
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321 SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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324 #endif /* STM32F10X_CL */
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328 SystemCoreClock = HSI_Value;
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332 /* Compute HCLK clock frequency ----------------*/
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333 /* Get HCLK prescaler */
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334 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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335 /* HCLK clock frequency */
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336 SystemCoreClock >>= tmp;
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340 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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344 static void SetSysClock(void)
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346 #ifdef SYSCLK_FREQ_HSE
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347 SetSysClockToHSE();
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348 #elif defined SYSCLK_FREQ_24MHz
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350 #elif defined SYSCLK_FREQ_36MHz
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352 #elif defined SYSCLK_FREQ_48MHz
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354 #elif defined SYSCLK_FREQ_56MHz
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355 SetSysClockTo56();
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356 #elif defined SYSCLK_FREQ_72MHz
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360 /* If none of the define above is enabled, the HSI is used as System clock
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361 source (default after reset) */
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365 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
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366 * before jump to __main
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370 #ifdef DATA_IN_ExtSRAM
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372 * @brief Setup the external memory controller.
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373 * Called in startup_stm32f10x_xx.s/.c before jump to main.
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374 * This function configures the external SRAM mounted on STM3210E-EVAL
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375 * board (STM32 High density devices). This SRAM will be used as program
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376 * data memory (including heap and stack).
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380 void SystemInit_ExtMemCtl(void)
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382 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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383 required, then adjust the Register Addresses */
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385 /* Enable FSMC clock */
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386 RCC->AHBENR = 0x00000114;
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388 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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389 RCC->APB2ENR = 0x000001E0;
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391 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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392 /*---------------- SRAM Address lines configuration -------------------------*/
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393 /*---------------- NOE and NWE configuration --------------------------------*/
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394 /*---------------- NE3 configuration ----------------------------------------*/
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395 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
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397 GPIOD->CRL = 0x44BB44BB;
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398 GPIOD->CRH = 0xBBBBBBBB;
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400 GPIOE->CRL = 0xB44444BB;
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401 GPIOE->CRH = 0xBBBBBBBB;
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403 GPIOF->CRL = 0x44BBBBBB;
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404 GPIOF->CRH = 0xBBBB4444;
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406 GPIOG->CRL = 0x44BBBBBB;
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407 GPIOG->CRH = 0x44444B44;
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409 /*---------------- FSMC Configuration ---------------------------------------*/
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410 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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412 FSMC_Bank1->BTCR[4] = 0x00001011;
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413 FSMC_Bank1->BTCR[5] = 0x00000200;
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415 #endif /* DATA_IN_ExtSRAM */
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417 #ifdef SYSCLK_FREQ_HSE
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419 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
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420 * and PCLK1 prescalers.
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421 * @note This function should be used only after reset.
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425 static void SetSysClockToHSE(void)
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427 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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429 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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431 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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433 /* Wait till HSE is ready and if Time out is reached exit */
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436 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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438 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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440 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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442 HSEStatus = (uint32_t)0x01;
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446 HSEStatus = (uint32_t)0x00;
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449 if (HSEStatus == (uint32_t)0x01)
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452 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
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453 /* Enable Prefetch Buffer */
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454 FLASH->ACR |= FLASH_ACR_PRFTBE;
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456 /* Flash 0 wait state */
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457 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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459 #ifndef STM32F10X_CL
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460 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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462 if (HSE_Value <= 24000000)
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464 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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468 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
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470 #endif /* STM32F10X_CL */
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473 /* HCLK = SYSCLK */
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474 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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477 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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480 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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482 /* Select HSE as system clock source */
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483 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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484 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
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486 /* Wait till HSE is used as system clock source */
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487 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
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492 { /* If HSE fails to start-up, the application will have wrong clock
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493 configuration. User can add here some code to deal with this error */
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496 #elif defined SYSCLK_FREQ_24MHz
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498 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
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499 * and PCLK1 prescalers.
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500 * @note This function should be used only after reset.
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504 static void SetSysClockTo24(void)
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506 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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508 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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510 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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512 /* Wait till HSE is ready and if Time out is reached exit */
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515 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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517 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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519 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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521 HSEStatus = (uint32_t)0x01;
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525 HSEStatus = (uint32_t)0x00;
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528 if (HSEStatus == (uint32_t)0x01)
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530 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL
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531 /* Enable Prefetch Buffer */
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532 FLASH->ACR |= FLASH_ACR_PRFTBE;
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534 /* Flash 0 wait state */
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535 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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536 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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539 /* HCLK = SYSCLK */
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540 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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543 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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546 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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548 #ifdef STM32F10X_CL
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549 /* Configure PLLs ------------------------------------------------------*/
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550 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
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551 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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552 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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553 RCC_CFGR_PLLMULL6);
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555 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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556 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
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557 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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558 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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559 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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560 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
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563 RCC->CR |= RCC_CR_PLL2ON;
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564 /* Wait till PLL2 is ready */
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565 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
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568 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
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569 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
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570 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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571 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
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573 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
\r
574 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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575 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
\r
576 #endif /* STM32F10X_CL */
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579 RCC->CR |= RCC_CR_PLLON;
\r
581 /* Wait till PLL is ready */
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582 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
586 /* Select PLL as system clock source */
\r
587 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
588 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
590 /* Wait till PLL is used as system clock source */
\r
591 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
596 { /* If HSE fails to start-up, the application will have wrong clock
\r
597 configuration. User can add here some code to deal with this error */
\r
600 #elif defined SYSCLK_FREQ_36MHz
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602 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
\r
603 * and PCLK1 prescalers.
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604 * @note This function should be used only after reset.
\r
608 static void SetSysClockTo36(void)
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610 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
612 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
614 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
616 /* Wait till HSE is ready and if Time out is reached exit */
\r
619 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
621 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
623 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
625 HSEStatus = (uint32_t)0x01;
\r
629 HSEStatus = (uint32_t)0x00;
\r
632 if (HSEStatus == (uint32_t)0x01)
\r
634 /* Enable Prefetch Buffer */
\r
635 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
637 /* Flash 1 wait state */
\r
638 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
639 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
641 /* HCLK = SYSCLK */
\r
642 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
645 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
648 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
\r
650 #ifdef STM32F10X_CL
\r
651 /* Configure PLLs ------------------------------------------------------*/
\r
653 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
\r
654 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
655 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
656 RCC_CFGR_PLLMULL9);
\r
658 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
659 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
\r
661 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
662 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
663 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
664 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
\r
667 RCC->CR |= RCC_CR_PLL2ON;
\r
668 /* Wait till PLL2 is ready */
\r
669 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
674 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
\r
675 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
676 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
\r
677 #endif /* STM32F10X_CL */
\r
680 RCC->CR |= RCC_CR_PLLON;
\r
682 /* Wait till PLL is ready */
\r
683 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
687 /* Select PLL as system clock source */
\r
688 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
689 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
691 /* Wait till PLL is used as system clock source */
\r
692 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
697 { /* If HSE fails to start-up, the application will have wrong clock
\r
698 configuration. User can add here some code to deal with this error */
\r
701 #elif defined SYSCLK_FREQ_48MHz
\r
703 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
\r
704 * and PCLK1 prescalers.
\r
705 * @note This function should be used only after reset.
\r
709 static void SetSysClockTo48(void)
\r
711 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
713 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
715 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
717 /* Wait till HSE is ready and if Time out is reached exit */
\r
720 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
722 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
724 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
726 HSEStatus = (uint32_t)0x01;
\r
730 HSEStatus = (uint32_t)0x00;
\r
733 if (HSEStatus == (uint32_t)0x01)
\r
735 /* Enable Prefetch Buffer */
\r
736 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
738 /* Flash 1 wait state */
\r
739 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
740 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
742 /* HCLK = SYSCLK */
\r
743 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
746 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
749 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
751 #ifdef STM32F10X_CL
\r
752 /* Configure PLLs ------------------------------------------------------*/
\r
753 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
754 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
756 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
757 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
758 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
759 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
762 RCC->CR |= RCC_CR_PLL2ON;
\r
763 /* Wait till PLL2 is ready */
\r
764 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
769 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
\r
770 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
771 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
772 RCC_CFGR_PLLMULL6);
\r
774 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
\r
775 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
776 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
\r
777 #endif /* STM32F10X_CL */
\r
780 RCC->CR |= RCC_CR_PLLON;
\r
782 /* Wait till PLL is ready */
\r
783 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
787 /* Select PLL as system clock source */
\r
788 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
789 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
791 /* Wait till PLL is used as system clock source */
\r
792 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
797 { /* If HSE fails to start-up, the application will have wrong clock
\r
798 configuration. User can add here some code to deal with this error */
\r
802 #elif defined SYSCLK_FREQ_56MHz
\r
804 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
\r
805 * and PCLK1 prescalers.
\r
806 * @note This function should be used only after reset.
\r
810 static void SetSysClockTo56(void)
\r
812 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
814 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
816 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
818 /* Wait till HSE is ready and if Time out is reached exit */
\r
821 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
823 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
825 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
827 HSEStatus = (uint32_t)0x01;
\r
831 HSEStatus = (uint32_t)0x00;
\r
834 if (HSEStatus == (uint32_t)0x01)
\r
836 /* Enable Prefetch Buffer */
\r
837 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
839 /* Flash 2 wait state */
\r
840 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
841 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
843 /* HCLK = SYSCLK */
\r
844 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
847 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
850 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
852 #ifdef STM32F10X_CL
\r
853 /* Configure PLLs ------------------------------------------------------*/
\r
854 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
855 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
857 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
858 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
859 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
860 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
863 RCC->CR |= RCC_CR_PLL2ON;
\r
864 /* Wait till PLL2 is ready */
\r
865 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
870 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
\r
871 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
872 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
873 RCC_CFGR_PLLMULL7);
\r
875 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
\r
876 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
877 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
\r
879 #endif /* STM32F10X_CL */
\r
882 RCC->CR |= RCC_CR_PLLON;
\r
884 /* Wait till PLL is ready */
\r
885 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
889 /* Select PLL as system clock source */
\r
890 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
891 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
893 /* Wait till PLL is used as system clock source */
\r
894 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
899 { /* If HSE fails to start-up, the application will have wrong clock
\r
900 configuration. User can add here some code to deal with this error */
\r
904 #elif defined SYSCLK_FREQ_72MHz
\r
906 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
\r
907 * and PCLK1 prescalers.
\r
908 * @note This function should be used only after reset.
\r
912 static void SetSysClockTo72(void)
\r
914 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
916 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
918 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
920 /* Wait till HSE is ready and if Time out is reached exit */
\r
923 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
925 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
927 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
929 HSEStatus = (uint32_t)0x01;
\r
933 HSEStatus = (uint32_t)0x00;
\r
936 if (HSEStatus == (uint32_t)0x01)
\r
938 /* Enable Prefetch Buffer */
\r
939 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
941 /* Flash 2 wait state */
\r
942 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
943 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
946 /* HCLK = SYSCLK */
\r
947 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
950 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
953 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
955 #ifdef STM32F10X_CL
\r
956 /* Configure PLLs ------------------------------------------------------*/
\r
957 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
958 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
960 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
961 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
962 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
963 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
966 RCC->CR |= RCC_CR_PLL2ON;
\r
967 /* Wait till PLL2 is ready */
\r
968 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
973 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
\r
974 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
975 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
976 RCC_CFGR_PLLMULL9);
\r
978 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
\r
979 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
\r
980 RCC_CFGR_PLLMULL));
\r
981 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
\r
982 #endif /* STM32F10X_CL */
\r
985 RCC->CR |= RCC_CR_PLLON;
\r
987 /* Wait till PLL is ready */
\r
988 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
992 /* Select PLL as system clock source */
\r
993 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
994 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
996 /* Wait till PLL is used as system clock source */
\r
997 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
1002 { /* If HSE fails to start-up, the application will have wrong clock
\r
1003 configuration. User can add here some code to deal with this error */
\r
1019 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r