1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (openocd)
27 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (openocd) version @value{VERSION}, @value{UPDATED}.
45 * About:: About Openocd.
46 * Developers:: Openocd developers
47 * Building:: Building Openocd
48 * Running:: Running Openocd
49 * Configuration:: Openocd Configuration.
50 * Commands:: Openocd Commands
51 * Sample Scripts:: Sample Target Scripts
52 * GDB and Openocd:: Using GDB and Openocd
53 * Upgrading:: Deprecated/Removed Commands
54 * FAQ:: Frequently Asked Questions
55 * License:: GNU Free Documentation License
63 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
64 and boundary-scan testing for embedded target devices. The targets are interfaced
65 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
66 connection types in the future.
68 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
69 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
70 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
71 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
73 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
74 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
75 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
81 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
82 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
83 Others interested in improving the state of free and open debug and testing technology
84 are welcome to participate.
86 Other developers have contributed support for additional targets and flashes as well
87 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
91 @cindex building openocd
93 You can download the current SVN version with SVN client of your choice from the
94 following repositories:
96 (@uref{svn://svn.berlios.de/openocd/trunk})
100 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
102 Using the SVN command line client, you could use the following command to fetch the
103 latest version (make sure there is no (non-svn) directory called "openocd" in the
107 svn checkout svn://svn.berlios.de/openocd/trunk openocd
110 Building the OpenOCD requires a recent version of the GNU autotools.
111 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
112 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
113 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
114 paths, resulting in obscure dependency errors (This is an observation I've gathered
115 from the logs of one user - correct me if I'm wrong).
117 You further need the appropriate driver files, if you want to build support for
118 a FTDI FT2232 based interface:
120 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
121 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
122 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
123 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
126 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
127 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
129 In general, the D2XX driver provides superior performance (several times as fast),
130 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
131 a kernel module, only a user space library.
133 To build OpenOCD (on both Linux and Cygwin), use the following commands:
137 Bootstrap generates the configure script, and prepares building on your system.
141 Configure generates the Makefiles used to build OpenOCD.
145 Make builds the OpenOCD, and places the final executable in ./src/.
147 The configure script takes several options, specifying which JTAG interfaces
152 @option{--enable-parport}
154 @option{--enable-parport_ppdev}
156 @option{--enable-parport_giveio}
158 @option{--enable-amtjtagaccel}
160 @option{--enable-ft2232_ftd2xx}
161 @footnote{Using the latest D2XX drivers from FTDI and following their installation
162 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
165 @option{--enable-ft2232_libftdi}
167 @option{--with-ftd2xx=/path/to/d2xx/}
169 @option{--enable-gw16012}
171 @option{--enable-usbprog}
173 @option{--enable-presto_libftdi}
175 @option{--enable-presto_ftd2xx}
178 If you want to access the parallel port using the PPDEV interface you have to specify
179 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
180 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
181 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
183 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
184 absolute path containing no spaces.
186 Linux users should copy the various parts of the D2XX package to the appropriate
187 locations, i.e. /usr/include, /usr/lib.
191 @cindex running openocd
193 @cindex --debug_level
196 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
197 Run with @option{--help} or @option{-h} to view the available command line arguments.
199 It reads its configuration by default from the file openocd.cfg located in the current
200 working directory. This may be overwritten with the @option{-f <configfile>} command line
201 switch. @option{-f} can be specified multiple times, in which case the config files
202 are executed in order.
204 Also it is possible to interleave commands w/config scripts using the @option{-c}.
206 To enable debug output (when reporting problems or working on OpenOCD itself), use
207 the @option{-d} command line switch. This sets the debug_level to "3", outputting
208 the most information, including debug messages. The default setting is "2", outputting
209 only informational messages, warnings and errors. You can also change this setting
210 from within a telnet or gdb session (@option{debug_level <n>}).
212 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
214 Search paths for config/script files can be added to openocd by using
215 the @option{-s <search>} switch. The current directory and the OpenOCD target library
216 is in the search path by default.
218 NB! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
219 with the target. In general, it is possible for the JTAG controller to be unresponsive until
220 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
223 @chapter Configuration
224 @cindex configuration
225 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
226 by default from the file openocd.cfg in the current directory. A different configuration
227 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
229 The configuration file is used to specify on which ports the daemon listens for new
230 connections, the JTAG interface used to connect to the target, the layout of the JTAG
231 chain, the targets that should be debugged, and connected flashes.
233 @section Daemon configuration
236 @item @b{init} This command terminates the configuration stage and enters the normal
237 command mode. This can be useful to add commands to the startup scripts and commands
238 such as resetting the target, programming flash, etc.
240 @item @b{telnet_port} <@var{number}>
242 Port on which to listen for incoming telnet connections
243 @item @b{gdb_port} <@var{number}>
245 First port on which to listen for incoming GDB connections. The GDB port for the
246 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
247 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
249 Configures what openocd will do when gdb detaches from the daeman.
250 Default behaviour is <@var{resume}>
251 @item @b{gdb_memory_map} <@var{enable|disable}>
252 @cindex gdb_memory_map
253 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
254 requested. gdb will then know when to set hardware breakpoints, and program flash
255 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
256 for flash programming to work.
257 Default behaviour is <@var{disable}>
258 @item @b{gdb_flash_program} <@var{enable|disable}>
259 @cindex gdb_flash_program
260 Set to <@var{enable}> so that openocd will program the flash memory when a
261 vFlash packet is received.
262 Default behaviour is <@var{disable}>
263 @item @b{daemon_startup} <@var{mode}>
264 @cindex daemon_startup
265 @option{mode} can either @option{attach} or @option{reset}
266 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
267 if it should just attach to the target.
270 @section JTAG interface configuration
273 @item @b{interface} <@var{name}>
275 Use the interface driver <@var{name}> to connect to the target. Currently supported
279 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
282 @item @b{amt_jtagaccel}
283 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
288 FTDI FT2232 based devices using either the open-source libftdi or the binary only
289 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
290 platform. The libftdi uses libusb, and should be portable to all systems that provide
295 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
299 ASIX PRESTO USB JTAG programmer.
303 usbprog is a freely programmable USB adapter.
307 Gateworks GW16012 JTAG programmer.
312 @item @b{jtag_speed} <@var{reset speed}> <@var{post reset speed}>
314 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
315 speed. The actual effect of this option depends on the JTAG interface used. Reset
316 speed is used during reset and post reset speed after reset. post reset speed
317 is optional, in which case the reset speed is used.
320 @item wiggler: maximum speed / @var{number}
321 @item ft2232: 6MHz / (@var{number}+1)
322 @item amt jtagaccel: 8 / 2**@var{number}
325 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
326 especially true for synthesized cores (-S).
328 @item @b{jtag_khz} <@var{reset speed kHz}> <@var{post reset speed kHz}>
330 Same as jtag_speed, except that the speed is specified in maximum kHz. If
331 the device can not support the rate asked for, or can not translate from
332 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
333 is not supported, then an error is reported.
335 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
337 The configuration of the reset signals available on the JTAG interface AND the target.
338 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
339 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
340 @option{srst_only} or @option{trst_and_srst}.
342 [@var{combination}] is an optional value specifying broken reset signal implementations.
343 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
344 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
345 that the system is reset together with the test logic (only hypothetical, I haven't
346 seen hardware with such a bug, and can be worked around).
347 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
348 The default behaviour if no option given is @option{separate}.
350 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
351 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
352 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
353 (default) and @option{srst_push_pull} for the system reset. These values only affect
354 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
356 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
358 Describes the devices that form the JTAG daisy chain, with the first device being
359 the one closest to TDO. The parameters are the length of the instruction register
360 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
361 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
362 The IDCODE instruction will in future be used to query devices for their JTAG
363 identification code. This line is the same for all ARM7 and ARM9 devices.
364 Other devices, like CPLDs, require different parameters. An example configuration
365 line for a Xilinx XC9500 CPLD would look like this:
367 jtag_device 8 0x01 0x0e3 0xfe
369 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
370 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
371 The IDCODE instruction is 0xfe.
373 @item @b{jtag_nsrst_delay} <@var{ms}>
374 @cindex jtag_nsrst_delay
375 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
376 starting new JTAG operations.
377 @item @b{jtag_ntrst_delay} <@var{ms}>
378 @cindex jtag_ntrst_delay
379 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
380 starting new JTAG operations.
382 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
383 or on-chip features) keep a reset line asserted for some time after the external reset
387 @section parport options
390 @item @b{parport_port} <@var{number}>
392 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
393 the @file{/dev/parport} device
395 When using PPDEV to access the parallel port, use the number of the parallel port:
396 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
397 you may encounter a problem.
398 @item @b{parport_cable} <@var{name}>
399 @cindex parport_cable
400 The layout of the parallel port cable used to connect to the target.
401 Currently supported cables are
405 Original Wiggler layout, also supported by several clones, such
406 as the Olimex ARM-JTAG
407 @item @b{old_amt_wiggler}
408 @cindex old_amt_wiggler
409 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
410 version available from the website uses the original Wiggler layout ('@var{wiggler}')
413 Describes the connection of the Amontec Chameleon's CPLD when operated in
414 configuration mode. This is only used to program the Chameleon itself, not
418 Xilinx Parallel cable III.
421 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
422 This is also the layout used by the HollyGates design
423 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
428 @item @b{parport_write_on_exit} <@var{on|off}>
429 @cindex parport_write_on_exit
430 This will configure the parallel driver to write a known value to the parallel
431 interface on exiting openocd
434 @section amt_jtagaccel options
436 @item @b{parport_port} <@var{number}>
438 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
439 @file{/dev/parport} device
441 @section ft2232 options
444 @item @b{ft2232_device_desc} <@var{description}>
445 @cindex ft2232_device_desc
446 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
447 default value is used. This setting is only valid if compiled with FTD2XX support.
448 @item @b{ft2232_layout} <@var{name}>
449 @cindex ft2232_layout
450 The layout of the FT2232 GPIO signals used to control output-enables and reset
451 signals. Valid layouts are
454 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
456 Amontec JTAGkey and JTAGkey-tiny
459 @item @b{olimex-jtag}
462 American Microsystems M5960
463 @item @b{evb_lm3s811}
464 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
465 SRST signals on external connector
469 Hitex STM32 Performance Stick
471 Tin Can Tools Flyswatter
472 @item @b{turtelizer2}
473 egnite Software turtelizer2
478 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
479 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
480 default values are used. This command is not available on Windows.
481 @item @b{ft2232_latency} <@var{ms}>
482 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
483 ft2232_read() fails to return the expected number of bytes. This can be caused by
484 USB communication delays and has proved hard to reproduce and debug. Setting the
485 FT2232 latency timer to a larger value increases delays for short USB packages but it
486 also reduces the risk of timeouts before receiving the expected number of bytes.
487 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
490 @section ep93xx options
491 @cindex ep93xx options
492 Currently, there are no options available for the ep93xx interface.
495 @section Target configuration
498 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
501 Defines a target that should be debugged. Currently supported types are:
515 If you want to use a target board that is not on this list, see Adding a new
518 Endianess may be @option{little} or @option{big}.
520 The reset_mode specifies what should happen to the target when a reset occurs:
524 Immediately request a target halt after reset. This allows targets to be debugged
525 from the very first instruction. This is only possible with targets and JTAG
526 interfaces that correctly implement the reset signals.
529 Similar to @option{reset_halt}, but executes the script file defined to handle the
530 'reset' event for the target. Like @option{reset_halt} this only works with
531 correct reset implementations.
534 Simply let the target run after a reset.
535 @item @b{run_and_halt}
537 Let the target run for some time (default: 1s), and then request halt.
538 @item @b{run_and_init}
540 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
541 to run for some time, then halted, and the @option{reset} event script is executed.
544 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
545 completely independent (like the LPC2000 series), or where the JTAG interface is
546 unavailable for some time during startup (like the STR7 series), you can't use
547 @option{reset_halt} or @option{reset_init}.
549 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
550 @cindex target_script
551 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
553 TODO: describe exact semantic of events
554 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
555 @cindex run_and_halt_time
556 The amount of time the debugger should wait after releasing reset before it asserts
557 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
559 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
560 <@var{backup}|@var{nobackup}>
562 Specifies a working area for the debugger to use. This may be used to speed-up
563 downloads to target memory and flash operations, or to perform otherwise unavailable
564 operations (some coprocessor operations on ARM7/9 systems, for example). The last
565 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
566 a working_area that doesn't need to be backed up, as that slows down operation.
569 @subsection arm7tdmi options
570 @cindex arm7tdmi options
571 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
572 The arm7tdmi target definition requires at least one additional argument, specifying
573 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
574 The optional [@var{variant}] parameter has been removed in recent versions.
575 The correct feature set is determined at runtime.
577 @subsection arm720t options
578 @cindex arm720t options
579 ARM720t options are similar to ARM7TDMI options.
581 @subsection arm9tdmi options
582 @cindex arm9tdmi options
583 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
584 @option{arm920t}, @option{arm922t} and @option{arm940t}.
585 This enables the hardware single-stepping support found on these cores.
587 @subsection arm920t options
588 @cindex arm920t options
589 ARM920t options are similar to ARM9TDMI options.
591 @subsection arm966e options
592 @cindex arm966e options
593 ARM966e options are similar to ARM9TDMI options.
595 @subsection xscale options
596 @cindex xscale options
597 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
598 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
600 @section Flash configuration
601 @cindex Flash configuration
604 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
605 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
607 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
608 and <@var{bus_width}> bytes using the selected flash <driver>.
610 @item @b{flash auto_erase} <@option{on}|@option{off}>
611 @cindex flash auto_erase
612 auto erase flash banks prior to writing. Currently only works when using
613 @option{flash write_image} command. Default is @option{off}.
616 @subsection lpc2000 options
617 @cindex lpc2000 options
619 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
620 <@var{clock}> [@var{calc_checksum}]
621 LPC flashes don't require the chip and bus width to be specified. Additional
622 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
623 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
624 of the target this flash belongs to (first is 0), the frequency at which the core
625 is currently running (in kHz - must be an integral number), and the optional keyword
626 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
629 @subsection cfi options
632 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
634 CFI flashes require the number of the target they're connected to as an additional
635 argument. The CFI driver makes use of a working area (specified for the target)
636 to significantly speed up operation.
638 @var{chip_width} and @var{bus_width} are specified in bytes.
640 @subsection at91sam7 options
641 @cindex at91sam7 options
643 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
644 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
645 reading the chip-id and type.
647 @subsection str7 options
650 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
651 variant can be either STR71x, STR73x or STR75x.
653 @subsection str9 options
656 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
657 The str9 needs the flash controller to be configured prior to Flash programming, eg.
659 str9x flash_config 0 4 2 0 0x80000
661 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
663 @subsection str9 options (str9xpec driver)
665 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
666 Before using the flash commands the turbo mode will need enabling using str9xpec
667 @option{enable_turbo} <@var{num>.}
669 Only use this driver for locking/unlocking the device or configuring the option bytes.
670 Use the standard str9 driver for programming.
672 @subsection stellaris (LM3Sxxx) options
673 @cindex stellaris (LM3Sxxx) options
675 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
676 stellaris flash plugin only require the @var{target#}.
678 @subsection stm32x options
679 @cindex stm32x options
681 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
682 stm32x flash plugin only require the @var{target#}.
685 @chapter Target library
686 @cindex Target library
688 OpenOCD comes with a target configuration script library. These scripts can be
689 used as-is or serve as a starting point.
691 The target library is published together with the openocd executable and
692 the path to the target library is in the OpenOCD script search path.
693 Similarly there are example scripts for configuring the JTAG interface.
695 The command line below uses the example parport configuration scripts
696 that ships with OpenOCD, then configures the str710.cfg target and
697 finally issues the init and reset command. The communication speed
698 is set to 10kHz for reset and 8MHz for post reset.
702 openocd -f interface/parport.cfg -c "jtag_khz 10 8000" -f target/str710.cfg -c "init" -c "reset"
706 To list the target scripts available:
709 $ ls /usr/local/lib/openocd/target
711 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
712 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
713 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
714 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
722 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
723 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
724 is available from both the telnet interface and a GDB session. To issue commands to the
725 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
726 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
732 @item @b{sleep} <@var{msec}>
734 Wait for n milliseconds before resuming. Useful in connection with script files
735 (@var{script} command and @var{target_script} configuration).
739 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
741 @item @b{debug_level} [@var{n}]
743 Display or adjust debug level to n<0-3>
745 @item @b{log_output} <@var{file}>
747 Redirect logging to <file> (default: stderr)
749 @item @b{script} <@var{file}>
751 Execute commands from <file>
755 @subsection Target state handling
757 @item @b{poll} [@option{on}|@option{off}]
759 Poll the target for its current state. If the target is in debug mode, architecture
760 specific information about the current state are printed. An optional parameter
761 allows continuous polling to be enabled and disabled.
763 @item @b{halt} [@option{ms}]
765 Send a halt request to the target and waits for it to halt for [@option{ms}].
766 Default [@option{ms}] is 5 seconds if no arg given.
767 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
768 will stop openocd from waiting.
770 @item @b{wait_halt} [@option{ms}]
772 Wait for the target to enter debug mode. Optional [@option{ms}] is
773 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
776 @item @b{resume} [@var{address}]
778 Resume the target at its current code position, or at an optional address.
779 Openocd will wait 5 seconds for the target to resume.
781 @item @b{step} [@var{address}]
783 Single-step the target at its current code position, or at an optional address.
785 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
786 |@option{run_and_init}]
788 Do a hard-reset. The optional parameter specifies what should happen after the reset.
789 This optional parameter overwrites the setting specified in the configuration file,
790 making the new behaviour the default for the @option{reset} command.
797 Immediately halt the target (works only with certain configurations).
800 Immediately halt the target, and execute the reset script (works only with certain
802 @item @b{run_and_halt}
803 @cindex reset run_and_halt
804 Let the target run for a certain amount of time, then request a halt.
805 @item @b{run_and_init}
806 @cindex reset run_and_init
807 Let the target run for a certain amount of time, then request a halt. Execute the
808 reset script once the target entered debug mode.
812 @subsection Memory access commands
813 These commands allow accesses of a specific size to the memory system:
815 @item @b{mdw} <@var{addr}> [@var{count}]
818 @item @b{mdh} <@var{addr}> [@var{count}]
820 display memory half-words
821 @item @b{mdb} <@var{addr}> [@var{count}]
824 @item @b{mww} <@var{addr}> <@var{value}>
827 @item @b{mwh} <@var{addr}> <@var{value}>
829 write memory half-word
830 @item @b{mwb} <@var{addr}> <@var{value}>
834 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
836 Load image <@var{file}> to target memory at <@var{address}>
837 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
839 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
840 (binary) <@var{file}>.
841 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
843 Verify <@var{file}> to target memory starting at <@var{address}>.
844 This will first attempt using a crc checksum, if this fails it will try a binary compare.
847 @subsection Flash commands
848 @cindex Flash commands
850 @item @b{flash banks}
852 List configured flash banks
853 @item @b{flash info} <@var{num}>
855 Print info about flash bank <@option{num}>
856 @item @b{flash probe} <@var{num}>
858 Identify the flash, or validate the parameters of the configured flash. Operation
859 depends on the flash type.
860 @item @b{flash erase_check} <@var{num}>
861 @cindex flash erase_check
862 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
863 updates the erase state information displayed by @option{flash info}. That means you have
864 to issue an @option{erase_check} command after erasing or programming the device to get
866 @item @b{flash protect_check} <@var{num}>
867 @cindex flash protect_check
868 Check protection state of sectors in flash bank <num>.
869 @option{flash erase_sector} using the same syntax.
870 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
871 @cindex flash erase_sector
872 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
873 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
874 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
876 @item @b{flash erase_address} <@var{address}> <@var{length}>
877 @cindex flash erase_address
878 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
879 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
880 @cindex flash write_bank
881 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
882 <@option{offset}> bytes from the beginning of the bank.
883 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
884 @cindex flash write_image
885 Write the image <@var{file}> to the current target's flash bank(s). A relocation
886 [@var{offset}] can be specified and the file [@var{type}] can be specified
887 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
888 (ELF file) or @option{s19} (Motorola s19).
889 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
890 @cindex flash protect
891 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
892 <@var{last}> of @option{flash bank} <@var{num}>.
893 @item @b{flash auto_erase} <@var{on}|@var{off}>
894 @cindex flash auto_erase
895 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
896 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
900 @section Target Specific Commands
901 @cindex Target Specific Commands
903 @subsection AT91SAM7 specific commands
904 @cindex AT91SAM7 specific commands
905 The flash configuration is deduced from the chip identification register. The flash
906 controller handles erases automatically on a page (128/265 byte) basis so erase is
907 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
908 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
909 that can be erased separatly.Only an EraseAll command is supported by the controller
910 for each flash plane and this is called with
912 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
913 bulk erase flash planes first_plane to last_plane.
914 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
915 @cindex at91sam7 gpnvm
916 set or clear a gpnvm bit for the processor
919 @subsection STR9 specific commands
920 @cindex STR9 specific commands
921 These are flash specific commands when using the str9xpec driver.
923 @item @b{str9xpec enable_turbo} <@var{num}>
924 @cindex str9xpec enable_turbo
925 enable turbo mode, simply this will remove the str9 from the chain and talk
926 directly to the embedded flash controller.
927 @item @b{str9xpec disable_turbo} <@var{num}>
928 @cindex str9xpec disable_turbo
929 restore the str9 into jtag chain.
930 @item @b{str9xpec lock} <@var{num}>
931 @cindex str9xpec lock
932 lock str9 device. The str9 will only respond to an unlock command that will
934 @item @b{str9xpec unlock} <@var{num}>
935 @cindex str9xpec unlock
937 @item @b{str9xpec options_read} <@var{num}>
938 @cindex str9xpec options_read
939 read str9 option bytes.
940 @item @b{str9xpec options_write} <@var{num}>
941 @cindex str9xpec options_write
942 write str9 option bytes.
945 @subsection STR9 configuration
946 @cindex STR9 configuration
948 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
949 <@var{BBADR}> <@var{NBBADR}>
950 @cindex str9x flash_config
951 Configure str9 flash controller.
953 eg. str9x flash_config 0 4 2 0 0x80000
955 BBSR - Boot Bank Size register
956 NBBSR - Non Boot Bank Size register
957 BBADR - Boot Bank Start Address register
958 NBBADR - Boot Bank Start Address register
962 @subsection STR9 option byte configuration
963 @cindex STR9 option byte configuration
965 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
966 @cindex str9xpec options_cmap
967 configure str9 boot bank.
968 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
969 @cindex str9xpec options_lvdthd
970 configure str9 lvd threshold.
971 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
972 @cindex str9xpec options_lvdsel
973 configure str9 lvd source.
974 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
975 @cindex str9xpec options_lvdwarn
976 configure str9 lvd reset warning source.
979 @subsection STM32x specific commands
980 @cindex STM32x specific commands
982 These are flash specific commands when using the stm32x driver.
984 @item @b{stm32x lock} <@var{num}>
987 @item @b{stm32x unlock} <@var{num}>
988 @cindex stm32x unlock
990 @item @b{stm32x options_read} <@var{num}>
991 @cindex stm32x options_read
992 read stm32 option bytes.
993 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
994 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
995 @cindex stm32x options_write
996 write stm32 option bytes.
997 @item @b{stm32x mass_erase} <@var{num}>
998 @cindex stm32x mass_erase
999 mass erase flash memory.
1003 @section Architecture Specific Commands
1004 @cindex Architecture Specific Commands
1006 @subsection ARMV4/5 specific commands
1007 @cindex ARMV4/5 specific commands
1009 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1010 or Intel XScale (XScale isn't supported yet).
1012 @item @b{armv4_5 reg}
1014 Display a list of all banked core registers, fetching the current value from every
1015 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1017 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1018 @cindex armv4_5 core_mode
1019 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1020 The target is resumed in the currently set @option{core_mode}.
1023 @subsection ARM7/9 specific commands
1024 @cindex ARM7/9 specific commands
1026 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1027 ARM920t or ARM926EJ-S.
1029 @item @b{arm7_9 sw_bkpts} <@var{enable}|@var{disable}>
1030 @cindex arm7_9 sw_bkpts
1031 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
1032 one of the watchpoint registers to implement software breakpoints. Disabling
1033 SW Bkpts frees that register again.
1034 @item @b{arm7_9 force_hw_bkpts} <@var{enable}|@var{disable}>
1035 @cindex arm7_9 force_hw_bkpts
1036 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
1037 breakpoints are turned into hardware breakpoints.
1038 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1039 @cindex arm7_9 dbgrq
1040 Enable use of the DBGRQ bit to force entry into debug mode. This should be
1041 safe for all but ARM7TDMI--S cores (like Philips LPC).
1042 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1043 @cindex arm7_9 fast_memory_access
1044 Allow the OpenOCD to read and write memory without checking completion of
1045 the operation. This provides a huge speed increase, especially with USB JTAG
1046 cables (FT2232), but might be unsafe if used with targets running at a very low
1047 speed, like the 32kHz startup clock of an AT91RM9200.
1048 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1049 @cindex arm7_9 dcc_downloads
1050 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1051 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1052 unsafe, especially with targets running at a very low speed. This command was introduced
1053 with OpenOCD rev. 60.
1056 @subsection ARM720T specific commands
1057 @cindex ARM720T specific commands
1060 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1061 @cindex arm720t cp15
1062 display/modify cp15 register <@option{num}> [@option{value}].
1063 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1064 @cindex arm720t md<bhw>_phys
1065 Display memory at physical address addr.
1066 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1067 @cindex arm720t mw<bhw>_phys
1068 Write memory at physical address addr.
1069 @item @b{arm720t virt2phys} <@var{va}>
1070 @cindex arm720t virt2phys
1071 Translate a virtual address to a physical address.
1074 @subsection ARM9TDMI specific commands
1075 @cindex ARM9TDMI specific commands
1078 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1079 @cindex arm9tdmi vector_catch
1080 Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1081 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1082 @option{irq} @option{fiq}.
1084 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1087 @subsection ARM966E specific commands
1088 @cindex ARM966E specific commands
1091 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1092 @cindex arm966e cp15
1093 display/modify cp15 register <@option{num}> [@option{value}].
1096 @subsection ARM920T specific commands
1097 @cindex ARM920T specific commands
1100 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1101 @cindex arm920t cp15
1102 display/modify cp15 register <@option{num}> [@option{value}].
1103 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1104 @cindex arm920t cp15i
1105 display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1106 @item @b{arm920t cache_info}
1107 @cindex arm920t cache_info
1108 Print information about the caches found. This allows you to see if your target
1109 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1110 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1111 @cindex arm920t md<bhw>_phys
1112 Display memory at physical address addr.
1113 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1114 @cindex arm920t mw<bhw>_phys
1115 Write memory at physical address addr.
1116 @item @b{arm920t read_cache} <@var{filename}>
1117 @cindex arm920t read_cache
1118 Dump the content of ICache and DCache to a file.
1119 @item @b{arm920t read_mmu} <@var{filename}>
1120 @cindex arm920t read_mmu
1121 Dump the content of the ITLB and DTLB to a file.
1122 @item @b{arm920t virt2phys} <@var{va}>
1123 @cindex arm920t virt2phys
1124 Translate a virtual address to a physical address.
1127 @subsection ARM926EJS specific commands
1128 @cindex ARM926EJS specific commands
1131 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1132 @cindex arm926ejs cp15
1133 display/modify cp15 register <@option{num}> [@option{value}].
1134 @item @b{arm926ejs cache_info}
1135 @cindex arm926ejs cache_info
1136 Print information about the caches found.
1137 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1138 @cindex arm926ejs md<bhw>_phys
1139 Display memory at physical address addr.
1140 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1141 @cindex arm926ejs mw<bhw>_phys
1142 Write memory at physical address addr.
1143 @item @b{arm926ejs virt2phys} <@var{va}>
1144 @cindex arm926ejs virt2phys
1145 Translate a virtual address to a physical address.
1149 @section Debug commands
1150 @cindex Debug commands
1151 The following commands give direct access to the core, and are most likely
1152 only useful while debugging the OpenOCD.
1154 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1155 @cindex arm7_9 write_xpsr
1156 Immediately write either the current program status register (CPSR) or the saved
1157 program status register (SPSR), without changing the register cache (as displayed
1158 by the @option{reg} and @option{armv4_5 reg} commands).
1159 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1160 <@var{0=cpsr},@var{1=spsr}>
1161 @cindex arm7_9 write_xpsr_im8
1162 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1163 operation (similar to @option{write_xpsr}).
1164 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1165 @cindex arm7_9 write_core_reg
1166 Write a core register, without changing the register cache (as displayed by the
1167 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1168 encoding of the [M4:M0] bits of the PSR.
1172 @section JTAG commands
1173 @cindex JTAG commands
1175 @item @b{scan_chain}
1177 Print current scan chain configuration.
1178 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1181 @item @b{endstate} <@var{tap_state}>
1183 Finish JTAG operations in <@var{tap_state}>.
1184 @item @b{runtest} <@var{num_cycles}>
1186 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1187 @item @b{statemove} [@var{tap_state}]
1189 Move to current endstate or [@var{tap_state}]
1190 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1192 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1193 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1195 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1196 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1197 @cindex verify_ircapture
1198 Verify value captured during Capture-IR. Default is enabled.
1199 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1201 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1202 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1204 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1208 @section Target Requests
1209 @cindex Target Requests
1210 Openocd can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1211 See libdcc in the contrib dir for more details.
1213 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1214 @cindex target_request debugmsgs
1215 Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1218 @node Sample Scripts
1219 @chapter Sample Scripts
1222 This page will collect some script examples for different CPUs.
1224 The configuration script can be divided in the following section:
1226 @item daemon configuration
1228 @item jtag scan chain
1229 @item target configuration
1230 @item flash configuration
1233 Detailed information about each section can be found at OpenOCD configuration
1235 @section OMAP5912 Flash Debug
1236 @cindex OMAP5912 Flash Debug
1237 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1238 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1239 - (@uref{http://www.spectrumdigital.com}).
1240 @subsection Openocd config
1242 #daemon configuration
1249 parport_cable wiggler
1252 #use combined on interfaces or targets that can't set TRST/SRST separately
1253 reset_config trst_and_srst
1256 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1257 jtag_device 38 0x0 0x0 0x0
1258 jtag_device 4 0x1 0x0 0xe
1259 jtag_device 8 0x0 0x0 0x0
1261 #target configuration
1262 daemon_startup reset
1264 #target <type> <endianness> <reset mode> <chainpos> <variant>
1265 target arm926ejs little run_and_init 1 arm926ejs
1266 target_script 0 reset omap5912_osk.init
1267 run_and_halt_time 0 30
1269 # omap5912 lcd frame buffer as working area
1270 working_area 0 0x20000000 0x3e800 nobackup
1272 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1273 flash bank cfi 0x00000000 0x1000000 2 2 0
1276 @subsection Openocd init
1288 mww 0xfffec808 0x000000f5
1289 mww 0xfffec808 0x000000a0
1291 mww 0xfffeb048 0x0000aaaa
1293 mww 0xfffeb048 0x00005555
1302 @section STR71x Script
1303 @cindex STR71x Script
1304 The following script was used with an Amontec JTAGkey and a STR710 / STR711 CPU:
1306 #daemon configuration
1312 ft2232_device_desc "Amontec JTAGkey A"
1313 ft2232_layout jtagkey
1314 ft2232_vid_pid 0x0403 0xcff8
1317 #use combined on interfaces or targets that can't set TRST/SRST separately
1318 reset_config trst_and_srst srst_pulls_trst
1321 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1322 jtag_device 4 0x1 0xf 0xe
1324 #target configuration
1325 daemon_startup reset
1327 #target <type> <startup mode>
1328 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1329 target arm7tdmi little run_and_halt 0 arm7tdmi
1330 run_and_halt_time 0 30
1332 working_area 0 0x2000C000 0x4000 nobackup
1334 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1335 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1338 @section STR750 Script
1339 @cindex STR750 Script
1340 The following script was used with an Amontec JTAGkey and a STR750 CPU:
1342 #daemon configuration
1348 ft2232_device_desc "Amontec JTAGkey A"
1349 ft2232_layout jtagkey
1350 ft2232_vid_pid 0x0403 0xcff8
1353 #use combined on interfaces or targets that can't set TRST/SRST separately
1354 #reset_config trst_and_srst srst_pulls_trst
1355 reset_config trst_and_srst srst_pulls_trst
1358 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1359 jtag_device 4 0x1 0xf 0xe
1361 #jtag nTRST and nSRST delay
1362 jtag_nsrst_delay 500
1363 jtag_ntrst_delay 500
1365 #target configuration
1366 daemon_startup reset
1368 #target <type> <startup mode>
1369 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1370 target arm7tdmi little run_and_halt 0 arm7tdmi
1371 run_and_halt_time 0 30
1373 working_area 0 0x40000000 0x4000 nobackup
1375 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1376 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1379 @section STR912 Script
1380 @cindex STR912 Script
1381 The following script was used with an Amontec JTAGkey and a STR912 CPU:
1383 #daemon configuration
1389 ft2232_device_desc "Amontec JTAGkey A"
1390 ft2232_layout jtagkey
1393 #use combined on interfaces or targets that can't set TRST/SRST separately
1394 reset_config trst_and_srst
1397 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1398 jtag_device 8 0x1 0x1 0xfe
1399 jtag_device 4 0x1 0xf 0xe
1400 jtag_device 5 0x1 0x1 0x1e
1402 #target configuration
1403 daemon_startup reset
1405 #target <type> <startup mode>
1406 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1407 target arm966e little reset_halt 1 arm966e
1408 run_and_halt_time 0 30
1410 working_area 0 0x50000000 16384 nobackup
1412 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1413 flash bank str9x 0x00000000 0x00080000 0 0 0
1416 @section STR912 comstick
1417 @cindex STR912 comstick Script
1418 The following script was used with a Hitex STR9 Comstick:
1420 #daemon configuration
1426 ft2232_device_desc "STR9-comStick A"
1427 ft2232_layout comstick
1430 jtag_nsrst_delay 100
1431 jtag_ntrst_delay 100
1433 #use combined on interfaces or targets that can't set TRST/SRST separately
1434 reset_config trst_and_srst
1437 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1438 jtag_device 8 0x1 0x1 0xfe
1439 jtag_device 4 0x1 0xf 0xe
1440 jtag_device 5 0x1 0x1 0x1e
1442 #target configuration
1443 daemon_startup reset
1445 #target <type> <startup mode>
1446 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1447 target arm966e little reset_halt 1 arm966e
1448 run_and_halt_time 0 30
1450 working_area 0 0x50000000 16384 nobackup
1452 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1453 flash bank str9x 0x00000000 0x00080000 0 0 0
1456 @section STM32x Script
1457 @cindex STM32x Script
1458 The following script was used with an Amontec JTAGkey and a STM32x CPU:
1460 #daemon configuration
1466 ft2232_device_desc "Amontec JTAGkey A"
1467 ft2232_layout jtagkey
1470 jtag_nsrst_delay 100
1471 jtag_ntrst_delay 100
1473 #use combined on interfaces or targets that can't set TRST/SRST separately
1474 reset_config trst_and_srst
1477 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1478 jtag_device 4 0x1 0xf 0xe
1479 jtag_device 5 0x1 0x1 0x1e
1481 #target configuration
1482 daemon_startup reset
1484 #target <type> <startup mode>
1485 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1486 target cortex_m3 little run_and_halt 0
1487 run_and_halt_time 0 30
1489 working_area 0 0x20000000 16384 nobackup
1491 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1492 flash bank stm32x 0x08000000 0x00020000 0 0 0
1495 @section STM32x Performance Stick
1496 @cindex STM32x Performance Stick Script
1497 The following script was used with the Hitex STM32 Performance Stick
1499 #daemon configuration
1505 ft2232_device_desc "STM32-PerformanceStick A"
1506 ft2232_layout stm32stick
1509 jtag_nsrst_delay 100
1510 jtag_ntrst_delay 100
1512 #use combined on interfaces or targets that can't set TRST/SRST separately
1513 reset_config trst_and_srst
1516 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1517 jtag_device 4 0x1 0xf 0xe
1518 jtag_device 5 0x1 0x1 0x1e
1519 jtag_device 4 0x1 0xf 0xe
1521 #target configuration
1522 daemon_startup reset
1524 #target <type> <startup mode>
1525 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1526 target cortex_m3 little run_and_halt 0
1527 run_and_halt_time 0 30
1529 working_area 0 0x20000000 16384 nobackup
1531 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1532 flash bank stm32x 0x08000000 0x00020000 0 0 0
1535 @section LPC2129 Script
1536 @cindex LPC2129 Script
1537 The following script was used with an wiggler PP and a LPC-2129 CPU:
1539 #daemon configuration
1546 parport_cable wiggler
1549 #use combined on interfaces or targets that can't set TRST/SRST separately
1550 reset_config trst_and_srst srst_pulls_trst
1553 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1554 jtag_device 4 0x1 0xf 0xe
1556 #target configuration
1557 daemon_startup reset
1559 #target <type> <startup mode>
1560 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1561 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1562 run_and_halt_time 0 30
1564 working_area 0 0x40000000 0x4000 nobackup
1566 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1567 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1570 @section LPC2148 Script
1571 @cindex LPC2148 Script
1572 The following script was used with an Amontec JTAGkey and a LPC2148 CPU:
1574 #daemon configuration
1580 ft2232_device_desc "Amontec JTAGkey A"
1581 ft2232_layout jtagkey
1582 ft2232_vid_pid 0x0403 0xcff8
1585 #use combined on interfaces or targets that can't set TRST/SRST separately
1586 reset_config trst_and_srst srst_pulls_trst
1589 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1590 jtag_device 4 0x1 0xf 0xe
1592 #target configuration
1593 daemon_startup reset
1595 #target <type> <startup mode>
1596 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1597 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1598 run_and_halt_time 0 30
1600 working_area 0 0x40000000 0x8000 nobackup
1602 #flash configuration
1603 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1606 @section LPC2294 Script
1607 @cindex LPC2294 Script
1608 The following script was used with an Amontec JTAGkey and a LPC2294 CPU:
1610 #daemon configuration
1616 ft2232_device_desc "Amontec JTAGkey A"
1617 ft2232_layout jtagkey
1618 ft2232_vid_pid 0x0403 0xcff8
1621 #use combined on interfaces or targets that can't set TRST/SRST separately
1622 reset_config trst_and_srst srst_pulls_trst
1625 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1626 jtag_device 4 0x1 0xf 0xe
1628 #target configuration
1629 daemon_startup reset
1631 #target <type> <startup mode>
1632 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1633 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1634 run_and_halt_time 0 30
1636 working_area 0 0x40000000 0x4000 nobackup
1638 #flash configuration
1639 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1642 @section AT91R40008 Script
1643 @cindex AT91R40008 Script
1644 The following script was used with an Amontec JTAGkey and a AT91R40008 CPU:
1646 #daemon configuration
1652 ft2232_device_desc "Amontec JTAGkey A"
1653 ft2232_layout jtagkey
1654 ft2232_vid_pid 0x0403 0xcff8
1656 jtag_nsrst_delay 200
1657 jtag_ntrst_delay 200
1659 #use combined on interfaces or targets that can't set TRST/SRST separately
1660 reset_config srst_only srst_pulls_trst
1663 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1664 jtag_device 4 0x1 0xf 0xe
1666 #target configuration
1667 daemon_startup reset
1669 #target <type> <startup mode>
1670 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1671 target arm7tdmi little run_and_halt 0 arm7tdmi
1672 run_and_halt_time 0 30
1675 @section AT91SAM7s Script
1676 @cindex AT91SAM7s Script
1677 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 CPU:
1679 #daemon configuration
1685 ft2232_device_desc "Olimex OpenOCD JTAG A"
1686 ft2232_layout olimex-jtag
1687 ft2232_vid_pid 0x15BA 0x0003
1689 jtag_nsrst_delay 200
1690 jtag_ntrst_delay 200
1692 #use combined on interfaces or targets that can't set TRST/SRST separately
1693 reset_config srst_only srst_pulls_trst
1696 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1697 jtag_device 4 0x1 0xf 0xe
1699 #target configuration
1700 daemon_startup reset
1702 #target <type> <startup mode>
1703 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1704 target arm7tdmi little run_and_halt 0 arm7tdmi
1705 run_and_halt_time 0 30
1707 # flash-options AT91
1708 working_area 0 0x00200000 0x4000 nobackup
1709 flash bank at91sam7 0 0 0 0 0
1712 # erase command (telnet-interface) for complete flash:
1713 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1714 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1715 # set/clear NVM-Bits:
1716 # at91sam7 gpnvm <num> <bit> <set|clear>
1717 # disable locking from SAM-BA:
1718 # flash protect 0 0 1 off
1721 @section XSCALE IXP42x Script
1722 @cindex XSCALE IXP42x Script
1723 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x CPU:
1725 #daemon configuration
1731 ft2232_device_desc "Amontec JTAGkey A"
1732 ft2232_layout jtagkey
1733 ft2232_vid_pid 0x0403 0xcff8
1735 jtag_nsrst_delay 200
1736 jtag_ntrst_delay 200
1738 #use combined on interfaces or targets that can't set TRST/SRST separately
1739 reset_config srst_only srst_pulls_trst
1742 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1743 jtag_device 7 0x1 0x7f 0x7e
1745 #target configuration
1746 daemon_startup reset
1748 #target <type> <startup mode>
1749 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1750 target xscale big run_and_halt 0 IXP42x
1751 run_and_halt_time 0 30
1754 @section Cirrus Logic EP9301 Script
1755 @cindex Cirrus Logic EP9301 Script
1756 The following script was used with FT2232 based JTAG interfaces and a
1757 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1759 #daemon configuration
1767 #ft2232_device_desc "Olimex OpenOCD JTAG"
1768 #ft2232_layout olimex-jtag
1769 #ft2232_vid_pid 0x15ba 0x0003
1771 #Amontec JTAGkey (and JTAGkey-Tiny)
1772 #Serial is only necessary if more than one JTAGkey is connected
1773 ft2232_device_desc "Amontec JTAGkey A"
1774 #ft2232_serial AMTJKV31
1775 #ft2232_serial T1P3S2W8
1776 ft2232_layout jtagkey
1777 ft2232_vid_pid 0x0403 0xcff8
1779 #wiggler/parallel port interface
1782 #parport_cable wiggler
1785 reset_config trst_and_srst
1788 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1789 jtag_device 4 0x1 0xf 0xe
1791 jtag_nsrst_delay 100
1792 jtag_ntrst_delay 100
1794 #target configuration
1795 daemon_startup attach
1797 #target <type> <endianess> <reset mode>
1798 target arm920t little reset_halt 0
1799 working_area 0 0x80014000 0x1000 backup
1801 #flash configuration
1802 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1803 flash bank cfi 0x60000000 0x1000000 2 2 0
1806 @section Hilscher netX 100 / 500 Script
1807 @cindex Hilscher netX 100 / 500 Script
1808 The following script was used with an Amontec JTAGkey and a Hilscher
1811 #daemon configuration
1817 ft2232_device_desc "Amontec JTAGkey A"
1818 ft2232_layout jtagkey
1819 ft2232_vid_pid 0x0403 0xcff8
1822 #use combined on interfaces or targets that can't set TRST/SRST separately
1823 reset_config trst_and_srst
1826 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1827 jtag_device 4 0x1 0xf 0xe
1829 jtag_nsrst_delay 100
1830 jtag_ntrst_delay 100
1832 #target configuration
1833 daemon_startup reset
1835 #target <type> <endianness> <startup mode> <chainpos> <variant>
1836 target arm926ejs little run_and_halt 0 arm926ejs
1837 run_and_halt_time 0 500
1840 @section Marvell/Intel PXA270 Script
1841 @cindex Marvell/Intel PXA270 Script
1843 # config for Intel PXA270
1844 # not, as of 2007-06-22, openocd only works with the
1845 # libftd2xx library from ftdi. libftdi does not work.
1851 ft2232_layout olimex-jtag
1852 ft2232_vid_pid 0x15BA 0x0003
1853 ft2232_device_desc "Olimex OpenOCD JTAG"
1855 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1856 # the rest of the needed delays are built into the openocd program
1857 jtag_nsrst_delay 260
1858 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1859 # the rest of the needed delays are built into the openocd program
1862 #use combined on interfaces or targets that can't set TRST/SRST separately
1863 reset_config trst_and_srst separate
1866 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1867 jtag_device 7 0x1 0x7f 0x7e
1869 #target configuration
1870 daemon_startup reset
1872 target xscale little reset_halt 0 pxa27x
1874 # maps to PXA internal RAM. If you are using a PXA255
1875 # you must initialize SDRAM or leave this option off
1876 working_area 0 0x5c000000 0x10000 nobackup
1878 run_and_halt_time 0 30
1880 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1881 # works for P30 flash
1882 flash bank cfi 0x00000000 0x1000000 2 4 0
1885 @node GDB and Openocd
1886 @chapter GDB and Openocd
1887 @cindex GDB and Openocd
1888 Openocd complies with the remote gdbserver protocol, and as such can be used
1889 to debug remote targets.
1891 @section Connecting to gdb
1892 @cindex Connecting to gdb
1893 A connection is typically started as follows:
1895 target remote localhost:3333
1897 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1899 To see a list of available openocd commands type @option{monitor help} on the
1902 Openocd supports the gdb @option{qSupported} packet, this enables information
1903 to be sent by the gdb server (openocd) to gdb. Typical information includes
1904 packet size and device memory map.
1906 Previous versions of openocd required the following gdb options to increase
1907 the packet size and speed up gdb communication.
1909 set remote memory-write-packet-size 1024
1910 set remote memory-write-packet-size fixed
1911 set remote memory-read-packet-size 1024
1912 set remote memory-read-packet-size fixed
1914 This is now handled in the @option{qSupported} PacketSize.
1916 @section Programming using gdb
1917 @cindex Programming using gdb
1919 By default the target memory map is not sent to gdb, this can be enabled by
1920 the following openocd config option:
1922 gdb_memory_map enable
1924 For this to function correctly a valid flash config must also be configured
1925 in openocd. For speed also configure a valid working area.
1927 Informing gdb of the memory map of the target will enable gdb to protect any
1928 flash area of the target and use hardware breakpoints by default. This means
1929 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1932 To view the configured memory map in gdb, use the gdb command @option{info mem}
1933 All other unasigned addresses within gdb are treated as RAM.
1935 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1936 this can be changed to the old behaviour by using the following gdb command.
1938 set mem inaccessible-by-default off
1941 If @option{gdb_flash_program enable} is also used, gdb will be able to
1942 program any flash memory using the vFlash interface.
1944 gdb will look at the target memory map when a load command is given, if any
1945 areas to be programmed lie within the target flash area the vFlash packets
1948 Incase the target needs configuring before gdb programming, a script can be executed.
1950 target_script 0 gdb_program_config config.script
1953 To verify any flash programming the gdb command @option{compare-sections}
1957 @chapter Deprecated/Removed Commands
1958 @cindex Deprecated/Removed Commands
1959 Certain openocd commands have been deprecated/removed during the various revisions.
1962 @item @b{load_binary}
1964 use @option{load_image} command with same args
1965 @item @b{dump_binary}
1967 use @option{dump_image} command with same args
1968 @item @b{flash erase}
1970 use @option{flash erase_sector} command with same args
1971 @item @b{flash write}
1973 use @option{flash write_bank} command with same args
1974 @item @b{flash write_binary}
1975 @cindex flash write_binary
1976 use @option{flash write_bank} command with same args
1977 @item @b{arm7_9 fast_writes}
1978 @cindex arm7_9 fast_writes
1979 use @option{arm7_9 fast_memory_access} command with same args
1986 @item OpenOCD complains about a missing cygwin1.dll.
1988 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1989 claims to come with all the necessary dlls. When using Cygwin, try launching
1990 the OpenOCD from the Cygwin shell.
1992 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1993 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1994 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1996 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1997 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1998 software breakpoints consume one of the two available hardware breakpoints,
1999 and are therefore disabled by default. If your code is running from RAM, you
2000 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
2001 your code resides in Flash, you can't use software breakpoints, but you can force
2002 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
2004 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
2005 and works sometimes fine.
2007 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
2008 clock at the time you're programming the flash. If you've specified the crystal's
2009 frequency, make sure the PLL is disabled, if you've specified the full core speed
2010 (e.g. 60MHz), make sure the PLL is enabled.
2012 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
2013 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
2014 out while waiting for end of scan, rtck was disabled".
2016 Make sure your PC's parallel port operates in EPP mode. You might have to try several
2017 settings in your PC BIOS (ECP, EPP, and different versions of those).
2019 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
2020 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
2021 memory read caused data abort".
2023 The errors are non-fatal, and are the result of GDB trying to trace stack frames
2024 beyond the last valid frame. It might be possible to prevent this by setting up
2025 a proper "initial" stack frame, if you happen to know what exactly has to
2026 be done, feel free to add this here.
2028 @item I get the following message in the OpenOCD console (or log file):
2029 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
2031 This warning doesn't indicate any serious problem, as long as you don't want to
2032 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
2033 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
2034 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
2035 independently. With this setup, it's not possible to halt the core right out of
2036 reset, everything else should work fine.
2038 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
2039 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
2040 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
2041 quit with an error message. Is there a stability issue with OpenOCD?
2043 No, this is not a stability issue concerning OpenOCD. Most users have solved
2044 this issue by simply using a self-powered USB hub, which they connect their
2045 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
2046 supply stable enough for the Amontec JTAGkey to be operated.
2048 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
2049 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
2050 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
2051 What does that mean and what might be the reason for this?
2053 First of all, the reason might be the USB power supply. Try using a self-powered
2054 hub instead of a direct connection to your computer. Secondly, the error code 4
2055 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
2056 chip ran into some sort of error - this points us to a USB problem.
2058 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
2059 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
2060 What does that mean and what might be the reason for this?
2062 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
2063 has closed the connection to OpenOCD. This might be a GDB issue.
2065 @item In the configuration file in the section where flash device configurations
2066 are described, there is a parameter for specifying the clock frequency for
2067 LPC2000 internal flash devices (e.g.
2068 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
2069 which must be specified in kilohertz. However, I do have a quartz crystal of a
2070 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
2071 Is it possible to specify real numbers for the clock frequency?
2073 No. The clock frequency specified here must be given as an integral number.
2074 However, this clock frequency is used by the In-Application-Programming (IAP)
2075 routines of the LPC2000 family only, which seems to be very tolerant concerning
2076 the given clock frequency, so a slight difference between the specified clock
2077 frequency and the actual clock frequency will not cause any trouble.
2079 @item Do I have to keep a specific order for the commands in the configuration file?
2081 Well, yes and no. Commands can be given in arbitrary order, yet the devices
2082 listed for the JTAG scan chain must be given in the right order (jtag_device),
2083 with the device closest to the TDO-Pin being listed first. In general,
2084 whenever objects of the same type exist which require an index number, then
2085 these objects must be given in the right order (jtag_devices, targets and flash
2086 banks - a target references a jtag_device and a flash bank references a target).
2088 @item Sometimes my debugging session terminates with an error. When I look into the
2089 log file, I can see these error messages: Error: arm7_9_common.c:561
2090 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP