1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
8 * OpenOCD: (openocd). Open On-Chip Debugger.
17 @item Copyright @copyright{} 2008 The OpenOCD Project
18 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
19 @item Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
20 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
24 Permission is granted to copy, distribute and/or modify this document
25 under the terms of the GNU Free Documentation License, Version 1.2 or
26 any later version published by the Free Software Foundation; with no
27 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
28 Texts. A copy of the license is included in the section entitled ``GNU
29 Free Documentation License''.
34 @title Open On-Chip Debugger (OpenOCD)
35 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
36 @subtitle @value{UPDATED}
38 @vskip 0pt plus 1filll
45 @node Top, About, , (dir)
48 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
49 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
54 * About:: About OpenOCD.
55 * Developers:: OpenOCD developers
56 * Building:: Building OpenOCD
57 * JTAG Hardware Dongles:: JTAG Hardware Dongles
58 * Running:: Running OpenOCD
59 * Simple Configuration Files:: Simple Configuration Files
60 * Config File Guidelines:: Config File Guidelines
61 * About JIM-Tcl:: About JIM-Tcl
62 * Daemon Configuration:: Daemon Configuration
63 * Interface - Dongle Configuration:: Interface - Dongle Configuration
64 * Reset Configuration:: Reset Configuration
65 * Tap Creation:: Tap Creation
66 * Target Configuration:: Target Configuration
67 * Flash Configuration:: Flash Configuration
68 * General Commands:: General Commands
69 * JTAG Commands:: JTAG Commands
70 * Sample Scripts:: Sample Target Scripts
72 * GDB and OpenOCD:: Using GDB and OpenOCD
73 * TCL scripting API:: Tcl scripting API
74 * Upgrading:: Deprecated/Removed Commands
75 * Target library:: Target library
76 * FAQ:: Frequently Asked Questions
77 * TCL Crash Course:: TCL Crash Course
78 * License:: GNU Free Documentation License
79 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
80 @comment case issue with ``Index.html'' and ``index.html''
81 @comment Occurs when creating ``--html --no-split'' output
82 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
83 * OpenOCD Index:: Main index.
90 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
91 in-system programming and boundary-scan testing for embedded target
94 @b{JTAG:} OpenOCD uses a ``hardware interface dongle'' to communicate
95 with the JTAG (IEEE 1149.1) complient taps on your target board.
97 @b{Dongles:} OpenOCD currently many types of hardware dongles: USB
98 Based, Parallel Port Based, and other standalone boxes that run
99 OpenOCD internally. See the section titled: @xref{JTAG Hardware Dongles}.
101 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920t,
102 ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
103 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be
104 debugged via the GDB Protocol.
106 @b{Flash Programing:} Flash writing is supported for external CFI
107 compatible flashes (Intel and AMD/Spansion command set) and several
108 internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3 and
109 STM32x). Preliminary support for using the LPC3180's NAND flash
110 controller is included.
116 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
117 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
118 Others interested in improving the state of free and open debug and testing technology
119 are welcome to participate.
121 Other developers have contributed support for additional targets and flashes as well
122 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
124 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
128 @cindex building OpenOCD
130 If you are interested in getting actual work done rather than building
131 OpenOCD, then check if your interface supplier provides binaries for
132 you. Chances are that that binary is from some SVN version that is more
133 stable than SVN trunk where bleeding edge development takes place.
136 You can download the current SVN version with SVN client of your choice from the
137 following repositories:
139 (@uref{svn://svn.berlios.de/openocd/trunk})
143 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
145 Using the SVN command line client, you can use the following command to fetch the
146 latest version (make sure there is no (non-svn) directory called "openocd" in the
150 svn checkout svn://svn.berlios.de/openocd/trunk openocd
153 Building OpenOCD requires a recent version of the GNU autotools.
154 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
155 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
156 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
157 paths, resulting in obscure dependency errors (This is an observation I've gathered
158 from the logs of one user - correct me if I'm wrong).
160 You further need the appropriate driver files, if you want to build support for
161 a FTDI FT2232 based interface:
163 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
164 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
165 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
166 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
169 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
170 see contrib/libftdi for more details.
172 In general, the D2XX driver provides superior performance (several times as fast),
173 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
174 a kernel module, only a user space library.
176 To build OpenOCD (on both Linux and Cygwin), use the following commands:
180 Bootstrap generates the configure script, and prepares building on your system.
184 Configure generates the Makefiles used to build OpenOCD.
188 Make builds OpenOCD, and places the final executable in ./src/.
190 The configure script takes several options, specifying which JTAG interfaces
195 @option{--enable-parport}
197 @option{--enable-parport_ppdev}
199 @option{--enable-parport_giveio}
201 @option{--enable-amtjtagaccel}
203 @option{--enable-ft2232_ftd2xx}
204 @footnote{Using the latest D2XX drivers from FTDI and following their installation
205 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
208 @option{--enable-ft2232_libftdi}
210 @option{--with-ftd2xx=/path/to/d2xx/}
212 @option{--enable-gw16012}
214 @option{--enable-usbprog}
216 @option{--enable-presto_libftdi}
218 @option{--enable-presto_ftd2xx}
220 @option{--enable-jlink}
223 If you want to access the parallel port using the PPDEV interface you have to specify
224 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
225 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
226 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
228 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
229 absolute path containing no spaces.
231 Linux users should copy the various parts of the D2XX package to the appropriate
232 locations, i.e. /usr/include, /usr/lib.
234 Miscellaneous configure options
238 @option{--enable-gccwarnings} - enable extra gcc warnings during build
241 @node JTAG Hardware Dongles
242 @chapter JTAG Hardware Dongles
251 Defined: @b{dongle}: A small device that plugins into a computer and serves as
252 an adapter .... [snip]
254 In the OpenOCD case, this generally refers to @b{a small adapater} one
255 attaches to your computer via USB or the Parallel Printer Port. The
256 execption being the Zylin ZY1000 which is a small box you attach via
260 @section Choosing a Dongle
262 There are three things you should keep in mind when choosing a dongle.
265 @item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
266 @item @b{Connection} Printer Ports - Does your computer have one?
267 @item @b{Connection} Is that long printer bit-bang cable practical?
268 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
271 @section Stand alone Systems
273 @b{ZY1000} See: @url{http://www.zylin.com/zy1000.html} Technically, not a
274 dongle, but a standalone box.
276 @section USB FT2232 Based
278 There are many USB jtag dongles on the market, many of them are based
279 on a chip from ``Future Technology Devices International'' (FTDI)
280 known as the FTDI FT2232.
282 See: @url{http://www.ftdichip.com} or @url{http://www.ftdichip.com/Products/FT2232H.htm}
284 As of 28/Nov/2008, the following are supported:
288 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
290 @* See: @url{http://www.amontec.com/jtagkey.shtml}
292 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
294 @* See: @url{http://www.signalyzer.com}
295 @item @b{evb_lm3s811}
296 @* See: @url{http://www.luminarymicro.com} - The Luminary Micro Stellaris LM3S811 eval board has an FTD2232C chip built in.
297 @item @b{olimex-jtag}
298 @* See: @url{http://www.olimex.com}
300 @* See: @url{http://www.tincantools.com}
301 @item @b{turtelizer2}
302 @* See: @url{http://www.ethernut.de}, or @url{http://www.ethernut.de/en/hardware/turtelizer/index.html}
304 @* Link: @url{http://www.hitex.com/index.php?id=383}
306 @* Link @url{http://www.hitex.com/stm32-stick}
307 @item @b{axm0432_jtag}
308 @* Axiom AXM-0432 Link @url{http://www.axman.com}
311 @section USB JLINK based
312 There are several OEM versions of the Segger @b{JLINK} adapter. It is
313 an example of a micro controller based JTAG adapter, it uses an
314 AT91SAM764 internally.
317 @item @b{ATMEL SAMICE} Only works with ATMEL chips!
318 @* Link: @url{http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3892}
319 @item @b{SEGGER JLINK}
320 @* Link: @url{http://www.segger.com/jlink.html}
322 @* Link: @url{http://www.iar.com/website1/1.0.1.0/369/1/index.php}
328 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
330 @item @b{USB - Presto}
331 @* Link: @url{http://tools.asix.net/prg_presto.htm}
334 @section IBM PC Parallel Printer Port Based
336 The two well known ``JTAG Parallel Ports'' cables are the Xilnx DLC5
337 and the MacGraigor Wiggler. There are many clones and variations of
342 @item @b{Wiggler} - There are many clones of this.
343 @* Link: @url{http://www.macraigor.com/wiggler.htm}
345 @item @b{DLC5} - From XILINX - There are many clones of this
346 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
347 produced, PDF schematics are easily found and it is easy to make.
349 @item @b{Amontec - JTAG Accelerator}
350 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
353 @* Link: @url{http://www.gateworks.com/products/avila_accessories/gw16042.php}
356 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
358 @item @b{Wiggler_ntrst_inverted}
359 @* Yet another variation - See the source code, src/jtag/parport.c
361 @item @b{old_amt_wiggler}
362 @* Unknown - probably not on the market today
365 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
368 @* Link: @url{http://www.amontec.com/chameleon.shtml}
374 @* ispDownload from Lattice Semiconductor @url{http://www.latticesemi.com/lit/docs/devtools/dlcable.pdf}
377 @* From ST Microsystems, link:
378 @url{http://www.st.com/stonline/products/literature/um/7889.pdf}
379 Title: FlashLINK JTAG programing cable for PSD and uPSD
387 @* An EP93xx based linux machine using the GPIO pins directly.
390 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
396 @cindex running OpenOCD
398 @cindex --debug_level
402 The @option{--help} option shows:
406 --help | -h display this help
407 --version | -v display OpenOCD version
408 --file | -f use configuration file <name>
409 --search | -s dir to search for config files and scripts
410 --debug | -d set debug level <0-3>
411 --log_output | -l redirect log output to file <name>
412 --command | -c run <command>
413 --pipe | -p use pipes when talking to gdb
416 By default OpenOCD reads the file configuration file ``openocd.cfg''
417 in the current directory. To specify a different (or multiple)
418 configuration file, you can use the ``-f'' option. For example:
421 openocd -f config1.cfg -f config2.cfg -f config3.cfg
424 Once started, OpenOCD runs as a daemon, waiting for connections from
425 clients (Telnet, GDB, Other).
427 If you are having problems, you can enable internal debug messages via
430 Also it is possible to interleave commands w/config scripts using the
431 @option{-c} command line switch.
433 To enable debug output (when reporting problems or working on OpenOCD
434 itself), use the @option{-d} command line switch. This sets the
435 @option{debug_level} to "3", outputting the most information,
436 including debug messages. The default setting is "2", outputting only
437 informational messages, warnings and errors. You can also change this
438 setting from within a telnet or gdb session using @option{debug_level
439 <n>} @xref{debug_level}.
441 You can redirect all output from the daemon to a file using the
442 @option{-l <logfile>} switch.
444 Search paths for config/script files can be added to OpenOCD by using
445 the @option{-s <search>} switch. The current directory and the OpenOCD
446 target library is in the search path by default.
448 For details on the @option{-p} option. @xref{Connecting to GDB}.
449 Option @option{-p} is not currently supported under native win32.
451 Note! OpenOCD will launch the GDB & telnet server even if it can not
452 establish a connection with the target. In general, it is possible for
453 the JTAG controller to be unresponsive until the target is set up
454 correctly via e.g. GDB monitor commands in a GDB init script.
456 @node Simple Configuration Files
457 @chapter Simple Configuration Files
458 @cindex configuration
461 There are 4 basic ways of ``configurating'' OpenOCD to run, they are:
464 @item A small openocd.cfg file which ``sources'' other configuration files
465 @item A monolithic openocd.cfg file
466 @item Many -f filename options on the command line
467 @item Your Mixed Solution
470 @section Small configuration file method
472 This is the prefered method, it is simple and is works well for many
473 people. The developers of OpenOCD would encourage you to use this
474 method. If you create a new configuration please email new
475 configurations to the development list.
477 Here is an example of an openocd.cfg file for an ATMEL at91sam7x256
480 source [find interface/signalyzer.cfg]
482 # Change the default telnet port...
486 # GDB can also flash my flash!
487 gdb_memory_map enable
488 gdb_flash_program enable
490 source [find target/sam7x256.cfg]
493 There are many example configuration scripts you can work with. You
494 should look in the directory: @t{$(INSTALLDIR)/lib/openocd}. You
498 @item @b{board} - eval board level configurations
499 @item @b{interface} - specific dongle configurations
500 @item @b{target} - the target chips
501 @item @b{tcl} - helper scripts
502 @item @b{xscale} - things specific to the xscale.
505 Look first in the ``boards'' area, then the ``targets'' area. Often a board
506 configuration is a good example to work from.
508 @section Many -f filename options
509 Some believe this is a wonderful solution, others find it painful.
511 You can use a series of ``-f filename'' options on the command line,
512 OpenOCD will read each filename in sequence, for example:
515 openocd -f file1.cfg -f file2.cfg -f file2.cfg
518 You can also intermix various commands with the ``-c'' command line
521 @section Monolithic file
522 The ``Monolithic File'' dispenses with all ``source'' statements and
523 puts everything in one self contained (monolithic) file. This is not
526 Please try to ``source'' various files or use the multiple -f
529 @section Advice for you
530 Often, one uses a ``mixed approach''. Where possible, please try to
531 ``source'' common things, and if needed cut/paste parts of the
532 standard distribution configuration files as needed.
534 @b{REMEMBER:} The ``important parts'' of your configuration file are:
537 @item @b{Interface} - Defines the dongle
538 @item @b{Taps} - Defines the JTAG Taps
539 @item @b{GDB Targets} - What GDB talks to
540 @item @b{Flash Programing} - Very Helpful
543 Some key things you should look at and understand are:
546 @item The RESET configuration of your debug environment as a hole
547 @item Is there a ``work area'' that OpenOCD can use?
548 @* For ARM - work areas mean up to 10x faster downloads.
549 @item For MMU/MPU based ARM chips (ie: ARM9 and later) will that work area still be available?
550 @item For complex targets (multiple chips) the JTAG SPEED becomes an issue.
555 @node Config File Guidelines
556 @chapter Config File Guidelines
558 This section/chapter is aimed at developers and integrators of
559 OpenOCD. These are guidelines for creating new boards and new target
560 configurations as of 28/Nov/2008.
562 However, you the user of OpenOCD should be some what familiar with
563 this section as it should help explain some of the internals of what
564 you might be looking at.
566 The user should find under @t{$(INSTALLDIR)/lib/openocd} the
567 following directories:
571 @*Think JTAG Dongle. Files that configure the jtag dongle go here.
573 @* Thing Circuit Board, PWA, PCB, they go by many names. Board files
574 contain initialization items that are specific to a board - for
575 example: The SDRAM initialization sequence for the board, or the type
576 of external flash and what address it is found at. Any initialization
577 sequence to enable that external flash or sdram should be found in the
578 board file. Boards may also contain multiple targets, ie: Two cpus, or
579 a CPU and an FPGA or CPLD.
581 @* Think CHIP. The ``target'' directory represents a jtag tap (or
582 chip) OpenOCD should control, not a board. Two common types of targets
583 are ARM chips and FPGA or CPLD chips.
586 @b{If needed...} The user in their ``openocd.cfg'' file or the board
587 file might override a specific feature in any of the above files by
588 setting a variable or two before sourcing the target file. Or adding
589 various commands specific to their situation.
591 @section Interface Config Files
593 The user should be able to source one of these files via a command like this:
596 source [find interface/FOOBAR.cfg]
598 openocd -f interface/FOOBAR.cfg
601 A preconfigured interface file should exist for every interface in use
602 today, that said, perhaps some interfaces have only been used by the
603 sole developer who created it.
605 @b{FIXME/NOTE:} We need to add support for a variable like TCL variable
606 tcl_platform(platform), it should be called jim_platform (because it
607 is jim, not real tcl) and it should contain 1 of 3 words: ``linux'',
608 ``cygwin'' or ``mingw''
610 Interface files should be found in @t{$(INSTALLDIR)/lib/openocd/interface}
612 @section Board Config Files
614 @b{Note: BOARD directory NEW as of 28/nov/2008}
616 The user should be able to source one of these files via a command like this:
619 source [find board/FOOBAR.cfg]
621 openocd -f board/FOOBAR.cfg
625 The board file should contain one or more @t{source [find
626 target/FOO.cfg]} statements along with any board specific things.
628 In summery the board files should contain (if present)
631 @item External flash configuration (ie: the flash on CS0)
632 @item SDRAM configuration (size, speed, etc)
633 @item Board specific IO configuration (ie: GPIO pins might disable a 2nd flash)
634 @item Multiple TARGET source statements
635 @item All things that are not ``inside a chip''
636 @item Things inside a chip go in a 'target' file
639 @section Target Config Files
641 The user should be able to source one of these files via a command like this:
644 source [find target/FOOBAR.cfg]
646 openocd -f target/FOOBAR.cfg
649 In summery the target files should contain
654 @item Reset Configuration
656 @item CPU/Chip/CPU-Core Specific features
660 @subsection Important variable names
662 By default, the end user should never need to set these
663 variables. However, if the user needs to override a setting they only
664 need to set the variable in a simple way.
668 @* This gives a name to the overall chip, and is used as part of the
669 tap identifier dotted name.
671 @* By default little - unless the chip or board is not normally used that way.
673 @* When OpenOCD examines the JTAG chain, it will attempt to identify
674 every chip. If the @t{-expected-id} is nonzero, OpenOCD attempts
675 to verify the tap id number verses configuration file and may issue an
676 error or warning like this. The hope is this will help pin point
677 problem OpenOCD configurations.
680 Info: JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
681 Error: ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
682 Error: ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
683 Error: ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
686 @item @b{_TARGETNAME}
687 @* By convention, this variable is created by the target configuration
688 script. The board configuration file may make use of this variable to
689 configure things like a ``reset init'' script, or other things
690 specific to that board and that target.
692 If the chip has 2 targets, use the names @b{_TARGETNAME0},
693 @b{_TARGETNAME1}, ... etc.
695 @b{Remember:} The ``board file'' may include multiple targets.
697 At no time should the name ``target0'' (the default target name if
698 none was specified) be used. The name ``target0'' is a hard coded name
699 - the next target on the board will be some other number.
701 The user (or board file) should reasonably be able to:
704 source [find target/FOO.cfg]
705 $_TARGETNAME configure ... FOO specific parameters
707 source [find target/BAR.cfg]
708 $_TARGETNAME configure ... BAR specific parameters
713 @subsection TCL Variables Guide Line
714 The Full Tcl/Tk language supports ``namespaces'' - JIM-Tcl does not.
716 Thus the rule we follow in OpenOCD is this: Variables that begin with
717 a leading underscore are temporal in nature, and can be modified and
718 used at will within a ?TARGET? configuration file
720 @b{EXAMPLE:} The user should be able to do this:
724 # PXA270 #1 network side, big endian
725 # PXA270 #2 video side, little endian
729 source [find target/pxa270.cfg]
730 # variable: _TARGETNAME = network.cpu
731 # other commands can refer to the "network.cpu" tap.
732 $_TARGETNAME configure .... params for this cpu..
736 source [find target/pxa270.cfg]
737 # variable: _TARGETNAME = video.cpu
738 # other commands can refer to the "video.cpu" tap.
739 $_TARGETNAME configure .... params for this cpu..
743 source [find target/spartan3.cfg]
745 # Since $_TARGETNAME is temporal..
746 # these names still work!
747 network.cpu configure ... params
748 video.cpu configure ... params
752 @subsection Default Value Boiler Plate Code
754 All target configuration files should start with this (or a modified form)
758 if @{ [info exists CHIPNAME] @} @{
759 set _CHIPNAME $CHIPNAME
761 set _CHIPNAME sam7x256
764 if @{ [info exists ENDIAN] @} @{
770 if @{ [info exists CPUTAPID ] @} @{
771 set _CPUTAPID $CPUTAPID
773 set _CPUTAPID 0x3f0f0f0f
778 @subsection Creating Taps
779 After the ``defaults'' are choosen, [see above], the taps are created.
781 @b{SIMPLE example:} such as an Atmel AT91SAM7X256
785 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
786 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
791 This is an SNIP/example for an STR912 - which has 3 internal taps. Key features shown:
794 @item @b{Unform tap names} - See: Tap Naming Convention
795 @item @b{_TARGETNAME} is created at the end where used.
799 if @{ [info exists FLASHTAPID ] @} @{
800 set _FLASHTAPID $FLASHTAPID
802 set _FLASHTAPID 0x25966041
804 jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
806 if @{ [info exists CPUTAPID ] @} @{
807 set _CPUTAPID $CPUTAPID
809 set _CPUTAPID 0x25966041
811 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID
814 if @{ [info exists BSTAPID ] @} @{
815 set _BSTAPID $BSTAPID
817 set _BSTAPID 0x1457f041
819 jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
821 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
824 @b{Tap Naming Convention}
826 See the command ``jtag newtap'' for detail, but in breif the names you should use are:
834 @item @b{unknownN} - it happens :-(
837 @subsection Reset Configuration
839 Some chips have specific ways the TRST and SRST signals are
840 managed. If these are @b{CHIP SPECIFIC} they go here, if they are
841 @b{BOARD SPECIFIC} they go in the board file.
843 @subsection Work Areas
845 Work areas are small RAM areas used by OpenOCD to speed up downloads,
846 and to download small snippits of code to program flash chips.
848 If the chip includes an form of ``on-chip-ram'' - and many do - define
849 a reasonable work area and use the ``backup'' option.
851 @b{PROBLEMS:} On more complex chips, this ``work area'' may become
852 inaccessable if/when the application code enables or disables the MMU.
854 @subsection ARM Core Specific Hacks
856 If the chip has a DCC, enable it. If the chip is an arm9 with some
857 special high speed download - enable it.
859 If the chip has an ARM ``vector catch'' feature - by defeault enable
860 it for Undefined Instructions, Data Abort, and Prefetch Abort, if the
861 user is really writing a handler for those situations - they can
862 easily disable it. Experiance has shown the ``vector catch'' is
863 helpful - for common programing errors.
865 If present, the MMU, the MPU and the CACHE should be disabled.
867 @subsection Internal Flash Configuration
869 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
871 @b{Never ever} in the ``target configuration file'' define any type of
872 flash that is external to the chip. (For example the BOOT flash on
873 Chip Select 0). The BOOT flash information goes in a board file - not
874 the TARGET (chip) file.
878 @item at91sam7x256 - has 256K flash YES enable it.
879 @item str912 - has flash internal YES enable it.
880 @item imx27 - uses boot flash on CS0 - it goes in the board file.
881 @item pxa270 - again - CS0 flash - it goes in the board file.
885 @chapter About JIM-Tcl
889 OpenOCD includes a small ``TCL Interpreter'' known as JIM-TCL. You can
890 learn more about JIM here: @url{http://jim.berlios.de}
893 @item @b{JIM vrs TCL}
894 @* JIM-TCL is a stripped down version of the well known Tcl language,
895 which can be found here: @url{http://www.tcl.tk}. JIM-Tcl has far
896 fewer features. JIM-Tcl is a single .C file and a single .H file and
897 impliments the basic TCL command set along. In contrast: Tcl 8.6 is a
898 4.2MEG zip file containing 1540 files.
900 @item @b{Missing Features}
901 @* Our practice has been: Add/clone the Real TCL feature if/when
902 needed. We welcome JIM Tcl improvements, not bloat.
905 @* OpenOCD configuration scripts are JIM Tcl Scripts. OpenOCD's
906 command interpretor today (28/nov/2008) is a mixture of (newer)
907 JIM-Tcl commands, and (older) the orginal command interpretor.
910 @* At the OpenOCD telnet command line (or via the GDB mon command) one
911 can type a Tcl for() loop, set variables, etc.
913 @item @b{Historical Note}
914 @* JIM-Tcl was introduced to OpenOCD in Spring 2008.
916 @item @b{Need a Crash Course In TCL?}
917 @* See: @xref{TCL Crash Course}.
921 @node Daemon Configuration
922 @chapter Daemon Configuration
923 The commands here are commonly found in the openocd.cfg file and are
924 used to specify what TCP/IP ports are used, and how GDB should be
928 This command terminates the configuration stage and
929 enters the normal command mode. This can be useful to add commands to
930 the startup scripts and commands such as resetting the target,
931 programming flash, etc. To reset the CPU upon startup, add "init" and
932 "reset" at the end of the config script or at the end of the OpenOCD
933 command line using the @option{-c} command line switch.
935 If this command does not appear in any startup/configuration file
936 OpenOCD executes the command for you after processing all
937 configuration files and/or command line options.
939 @b{NOTE:} This command normally occurs at or near the end of your
940 openocd.cfg file to force OpenOCD to ``initialize'' and make the
941 targets ready. For example: If your openocd.cfg file needs to
942 read/write memory on your target - the init command must occur before
943 the memory read/write commands.
945 @section TCP/IP Ports
947 @item @b{telnet_port} <@var{number}>
949 @*Intended for a human. Port on which to listen for incoming telnet connections.
951 @item @b{tcl_port} <@var{number}>
953 @*Intended as a machine interface. Port on which to listen for
954 incoming TCL syntax. This port is intended as a simplified RPC
955 connection that can be used by clients to issue commands and get the
956 output from the TCL engine.
958 @item @b{gdb_port} <@var{number}>
960 @*First port on which to listen for incoming GDB connections. The GDB port for the
961 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
966 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
967 @cindex gdb_breakpoint_override
968 @anchor{gdb_breakpoint_override}
969 @*Force breakpoint type for gdb 'break' commands.
970 The raison d'etre for this option is to support GDB GUI's without
971 a hard/soft breakpoint concept where the default OpenOCD and
972 GDB behaviour is not sufficient. Note that GDB will use hardware
973 breakpoints if the memory map has been set up for flash regions.
975 This option replaces older arm7_9 target commands that addressed
978 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
980 @*Configures what OpenOCD will do when gdb detaches from the daeman.
981 Default behaviour is <@var{resume}>
983 @item @b{gdb_memory_map} <@var{enable|disable}>
984 @cindex gdb_memory_map
985 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
986 requested. gdb will then know when to set hardware breakpoints, and program flash
987 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
988 for flash programming to work.
989 Default behaviour is <@var{enable}>
990 @xref{gdb_flash_program}.
992 @item @b{gdb_flash_program} <@var{enable|disable}>
993 @cindex gdb_flash_program
994 @anchor{gdb_flash_program}
995 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
996 vFlash packet is received.
997 Default behaviour is <@var{enable}>
998 @comment END GDB Items
1001 @node Interface - Dongle Configuration
1002 @chapter Interface - Dongle Configuration
1003 Interface commands are normally found in an interface configuration
1004 file which is sourced by your openocd.cfg file. These commands tell
1005 OpenOCD what type of JTAG dongle you have and how to talk to it.
1006 @section Simple Complete Interface Examples
1007 @b{A Turtelizer FT2232 Based JTAG Dongle}
1011 ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A"
1012 ft2232_layout turtelizer2
1013 ft2232_vid_pid 0x0403 0xbdc8
1024 parport_cable wiggler
1027 @section Interface Conmmand
1029 The interface command tells OpenOCD what type of jtag dongle you are
1030 using. Depending upon the type of dongle, you may need to have one or
1031 more additional commands.
1035 @item @b{interface} <@var{name}>
1037 @*Use the interface driver <@var{name}> to connect to the
1038 target. Currently supported interfaces are
1043 @* PC parallel port bit-banging (Wigglers, PLD download cable, ...)
1045 @item @b{amt_jtagaccel}
1046 @* Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
1050 @* FTDI FT2232 (USB) based devices using either the open-source libftdi or the binary only
1051 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
1052 platform. The libftdi uses libusb, and should be portable to all systems that provide
1056 @*Cirrus Logic EP93xx based single-board computer bit-banging (in development)
1059 @* ASIX PRESTO USB JTAG programmer.
1062 @* usbprog is a freely programmable USB adapter.
1065 @* Gateworks GW16012 JTAG programmer.
1068 @* Segger jlink usb adapter
1069 @comment - End parameters
1071 @comment - End Interface
1073 @subsection parport options
1076 @item @b{parport_port} <@var{number}>
1077 @cindex parport_port
1078 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
1079 the @file{/dev/parport} device
1081 When using PPDEV to access the parallel port, use the number of the parallel port:
1082 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
1083 you may encounter a problem.
1084 @item @b{parport_cable} <@var{name}>
1085 @cindex parport_cable
1086 @*The layout of the parallel port cable used to connect to the target.
1087 Currently supported cables are
1091 The original Wiggler layout, also supported by several clones, such
1092 as the Olimex ARM-JTAG
1095 Same as original wiggler except an led is fitted on D5.
1096 @item @b{wiggler_ntrst_inverted}
1097 @cindex wiggler_ntrst_inverted
1098 Same as original wiggler except TRST is inverted.
1099 @item @b{old_amt_wiggler}
1100 @cindex old_amt_wiggler
1101 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
1102 version available from the website uses the original Wiggler layout ('@var{wiggler}')
1105 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
1106 program the Chameleon itself, not a connected target.
1109 The Xilinx Parallel cable III.
1112 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
1113 This is also the layout used by the HollyGates design
1114 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
1117 The ST Parallel cable.
1120 Same as original wiggler except SRST and TRST connections reversed and
1121 TRST is also inverted.
1124 Altium Universal JTAG cable.
1126 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
1127 @cindex parport_write_on_exit
1128 @*This will configure the parallel driver to write a known value to the parallel
1129 interface on exiting OpenOCD
1132 @subsection amt_jtagaccel options
1134 @item @b{parport_port} <@var{number}>
1135 @cindex parport_port
1136 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
1137 @file{/dev/parport} device
1139 @subsection ft2232 options
1142 @item @b{ft2232_device_desc} <@var{description}>
1143 @cindex ft2232_device_desc
1144 @*The USB device description of the FTDI FT2232 device. If not
1145 specified, the FTDI default value is used. This setting is only valid
1146 if compiled with FTD2XX support.
1148 @b{TODO:} Confirm the following: On windows the name needs to end with
1149 a ``space A''? Or not? It has to do with the FTD2xx driver. When must
1150 this be added and when must it not be added? Why can't the code in the
1151 interface or in OpenOCD automatically add this if needed? -- Duane.
1153 @item @b{ft2232_serial} <@var{serial-number}>
1154 @cindex ft2232_serial
1155 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
1157 @item @b{ft2232_layout} <@var{name}>
1158 @cindex ft2232_layout
1159 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
1160 signals. Valid layouts are
1163 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
1165 Amontec JTAGkey and JTAGkey-tiny
1166 @item @b{signalyzer}
1168 @item @b{olimex-jtag}
1171 American Microsystems M5960
1172 @item @b{evb_lm3s811}
1173 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
1174 SRST signals on external connector
1177 @item @b{stm32stick}
1178 Hitex STM32 Performance Stick
1179 @item @b{flyswatter}
1180 Tin Can Tools Flyswatter
1181 @item @b{turtelizer2}
1182 egnite Software turtelizer2
1185 @item @b{axm0432_jtag}
1189 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
1190 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
1191 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
1193 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
1195 @item @b{ft2232_latency} <@var{ms}>
1196 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
1197 ft2232_read() fails to return the expected number of bytes. This can be caused by
1198 USB communication delays and has proved hard to reproduce and debug. Setting the
1199 FT2232 latency timer to a larger value increases delays for short USB packages but it
1200 also reduces the risk of timeouts before receiving the expected number of bytes.
1201 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
1204 @subsection ep93xx options
1205 @cindex ep93xx options
1206 Currently, there are no options available for the ep93xx interface.
1210 @item @b{jtag_khz} <@var{reset speed kHz}>
1213 It is debatable if this command belongs here - or in a board
1214 configuration file. In fact, in some situations the jtag speed is
1215 changed during the target initialization process (ie: (1) slow at
1216 reset, (2) program the cpu clocks, (3) run fast)
1218 Speed 0 (khz) selects RTCK method. A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
1220 Not all interfaces support ``rtck''. If the interface device can not
1221 support the rate asked for, or can not translate from kHz to
1222 jtag_speed, then an error is returned.
1224 Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
1225 especially true for synthesized cores (-S). Also see RTCK.
1227 @b{NOTE: Script writers} If the target chip requires/uses RTCK -
1228 please use the command: 'jtag_rclk FREQ'. This TCL proc (in
1229 startup.tcl) attempts to enable RTCK, if that fails it falls back to
1230 the specified frequency.
1233 # Fall back to 3mhz if RCLK is not supported
1237 @item @b{DEPRICATED} @b{jtag_speed} - please use jtag_khz above.
1239 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
1240 speed. The actual effect of this option depends on the JTAG interface used.
1242 The speed used during reset can be adjusted using setting jtag_speed during
1243 pre_reset and post_reset events.
1246 @item wiggler: maximum speed / @var{number}
1247 @item ft2232: 6MHz / (@var{number}+1)
1248 @item amt jtagaccel: 8 / 2**@var{number}
1249 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
1250 @comment end speed list.
1253 @comment END command list
1256 @node Reset Configuration
1257 @chapter Reset Configuration
1258 @cindex reset configuration
1260 Every system configuration may require a different reset
1261 configuration. This can also be quite confusing. Please see the
1262 various board files for example.
1264 @section jtag_nsrst_delay <@var{ms}>
1265 @cindex jtag_nsrst_delay
1266 @*How long (in milliseconds) OpenOCD should wait after deasserting
1267 nSRST before starting new JTAG operations.
1269 @section jtag_ntrst_delay <@var{ms}>
1270 @cindex jtag_ntrst_delay
1271 @*Same @b{jtag_nsrst_delay}, but for nTRST
1273 The jtag_n[st]rst_delay options are useful if reset circuitry (like a
1274 big resistor/capacitor, reset supervisor, or on-chip features). This
1275 keeps the signal asserted for some time after the external reset got
1278 @section reset_config
1280 @b{Note:} To maintainer types and integrators. Where exactly the
1281 ``reset configuration'' goes is a good question. It touches several
1282 things at once. In the end, if you have a board file - the board file
1283 should define it and assume 100% that the DONGLE supports
1284 anything. However, that does not mean the target should not also make
1285 not of something the silicon vendor has done inside the
1286 chip. @i{Grr.... nothing is every pretty.}
1290 @item Every JTAG Dongle is slightly different, some dongles impliment reset differently.
1291 @item Every board is also slightly different; some boards tie TRST and SRST together.
1292 @item Every chip is slightly different; some chips internally tie the two signals together.
1293 @item Some may not impliment all of the signals the same way.
1294 @item Some signals might be push-pull, others open-drain/collector.
1296 @b{Best Case:} OpenOCD can hold the SRST (push-button-reset), then
1297 reset the TAP via TRST and send commands through the JTAG tap to halt
1298 the CPU at the reset vector before the 1st instruction is executed,
1299 and finally release the SRST signal.
1300 @*Depending upon your board vendor, your chip vendor, etc, these
1301 signals may have slightly different names.
1303 OpenOCD defines these signals in these terms:
1305 @item @b{TRST} - is Tap Reset - and should reset only the TAP.
1306 @item @b{SRST} - is System Reset - typically equal to a reset push button.
1312 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
1313 @cindex reset_config
1314 @* The @t{reset_config} command tells OpenOCD the reset configuration
1315 of your combination of Dongle, Board, and Chips.
1316 If the JTAG interface provides SRST, but the target doesn't connect
1317 that signal properly, then OpenOCD can't use it. <@var{signals}> can
1318 be @option{none}, @option{trst_only}, @option{srst_only} or
1319 @option{trst_and_srst}.
1321 [@var{combination}] is an optional value specifying broken reset
1322 signal implementations. @option{srst_pulls_trst} states that the
1323 testlogic is reset together with the reset of the system (e.g. Philips
1324 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
1325 the system is reset together with the test logic (only hypothetical, I
1326 haven't seen hardware with such a bug, and can be worked around).
1327 @option{combined} imples both @option{srst_pulls_trst} and
1328 @option{trst_pulls_srst}. The default behaviour if no option given is
1331 The [@var{trst_type}] and [@var{srst_type}] parameters allow the
1332 driver type of the reset lines to be specified. Possible values are
1333 @option{trst_push_pull} (default) and @option{trst_open_drain} for the
1334 test reset signal, and @option{srst_open_drain} (default) and
1335 @option{srst_push_pull} for the system reset. These values only affect
1336 JTAG interfaces with support for different drivers, like the Amontec
1337 JTAGkey and JTAGAccelerator.
1339 @comment - end command
1345 @chapter Tap Creation
1346 @cindex tap creation
1347 @cindex tap configuration
1349 In order for OpenOCD to control a target, a JTAG tap must be
1352 Commands to create taps are normally found in a configuration file and
1353 are not normally typed by a human.
1355 When a tap is created a @b{dotted.name} is created for the tap. Other
1356 commands use that dotted.name to manipulate or refer to the tap.
1360 @item @b{Debug Target} A tap can be used by a GDB debug target
1361 @item @b{Flash Programing} Some chips program the flash via JTAG
1362 @item @b{Boundry Scan} Some chips support boundry scan.
1366 @section jtag newtap
1367 @b{@t{jtag newtap CHIPNAME TAPNAME configparams ....}}
1372 @cindex tap geometry
1374 @comment START options
1377 @* is a symbolic name of the chip.
1379 @* is a symbol name of a tap present on the chip.
1380 @item @b{Required configparams}
1381 @* Every tap has 3 required configparams, and several ``optional
1382 parameters'', the required parameters are:
1383 @comment START REQUIRED
1385 @item @b{-irlen NUMBER} - the length in bits of the instruction register
1386 @item @b{-ircapture NUMBER} - the ID code capture command.
1387 @item @b{-irmask NUMBER} - the corrisponding mask for the ir register.
1388 @comment END REQUIRED
1390 An example of a FOOBAR Tap
1392 jtag newtap foobar tap -irlen 7 -ircapture 0x42 -irmask 0x55
1394 Creates the tap ``foobar.tap'' with the instruction register (IR) is 7
1395 bits long, during Capture-IR 0x42 is loaded into the IR, and bits
1396 [6,4,2,0] are checked.
1398 FIXME: The IDCODE - this was not used in the old code, it should be?
1400 @item @b{Optional configparams}
1401 @comment START Optional
1403 @item @b{-expected-id NUMBER}
1404 @* By default it is zero. If non-zero represents the
1405 expected tap ID used when the Jtag Chain is examined. See below.
1408 @* By default not specified the tap is enabled. Some chips have a
1409 jtag route controller (JRC) that is used to enable and/or disable
1410 specific jtag taps. You can later enable or disable any JTAG tap via
1411 the command @b{jtag tapenable DOTTED.NAME} or @b{jtag tapdisable
1413 @comment END Optional
1416 @comment END OPTIONS
1419 @comment START NOTES
1421 @item @b{Technically}
1422 @* newtap is a sub command of the ``jtag'' command
1423 @item @b{Big Picture Background}
1424 @*GDB Talks to OpenOCD using the GDB protocol via
1425 tcpip. OpenOCD then uses the JTAG interface (the dongle) to
1426 control the JTAG chain on your board. Your board has one or more chips
1427 in a @i{daisy chain configuration}. Each chip may have one or more
1428 jtag taps. GDB ends up talking via OpenOCD to one of the taps.
1429 @item @b{NAME Rules}
1430 @*Names follow ``C'' symbol name rules (start with alpha ...)
1431 @item @b{TAPNAME - Conventions}
1433 @item @b{tap} - should be used only FPGA or CPLD like devices with a single tap.
1434 @item @b{cpu} - the main cpu of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
1435 @item @b{flash} - if the chip has a flash tap, example: str912.flash
1436 @item @b{bs} - for boundary scan if this is a seperate tap.
1437 @item @b{jrc} - for jtag route controller (example: OMAP3530 found on Beagleboards)
1438 @item @b{unknownN} - where N is a number if you have no idea what the tap is for
1439 @item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
1440 @item @b{When in doubt} - use the chip makers name in their data sheet.
1442 @item @b{DOTTED.NAME}
1443 @* @b{CHIPNAME}.@b{TAPNAME} creates the tap name, aka: the
1444 @b{Dotted.Name} is the @b{CHIPNAME} and @b{TAPNAME} combined with a
1445 dot (period); for example: @b{xilinx.tap}, @b{str912.flash},
1446 @b{omap3530.jrc}, or @b{stm32.cpu} The @b{dotted.name} is used in
1447 numerous other places to refer to various taps.
1449 @* The order this command appears via the config files is
1451 @item @b{Multi Tap Example}
1452 @* This example is based on the ST Microsystems STR912. See the ST
1453 document titled: @b{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
1454 28/102, Figure 3: Jtag chaining inside the STR91xFA}.
1456 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}
1457 @*@b{checked: 28/nov/2008}
1459 The diagram shows the TDO pin connects to the flash tap, flash TDI
1460 connects to the CPU debug tap, CPU TDI connects to the boundary scan
1461 tap which then connects to the TDI pin.
1465 # create tap: 'str912.flash'
1466 jtag newtap str912 flash ... params ...
1467 # create tap: 'str912.cpu'
1468 jtag newtap str912 cpu ... params ...
1469 # create tap: 'str912.bs'
1470 jtag newtap str912 bs ... params ...
1473 @item @b{Note: Deprecated} - Index Numbers
1474 @* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
1475 feature is still present, however its use is highly discouraged and
1476 should not be counted upon.
1477 @item @b{Multiple chips}
1478 @* If your board has multiple chips, you should be
1479 able to @b{source} two configuration files, in the proper order, and
1480 have the taps created in the proper order.
1483 @comment at command level
1484 @comment DOCUMENT old command
1485 @section jtag_device - REMOVED
1487 @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
1491 @* @b{Removed: 28/nov/2008} This command has been removed and replaced
1492 by the ``jtag newtap'' command. The documentation remains here so that
1493 one can easily convert the old syntax to the new syntax. About the old
1494 syntax: The old syntax is positional, ie: The 4th parameter is the
1495 ``irmask''. The new syntax requires named prefixes, and supports
1496 additional options, for example ``-irmask 4''. Please refer to the
1497 @b{jtag newtap} command for details.
1499 OLD: jtag_device 8 0x01 0x0e3 0xfe
1500 NEW: jtag newtap CHIPNAME TAPNAME -irlen 8 -ircapture 0xe3 -irmask 0xfe
1503 @section Enable/Disable Taps
1504 @b{Note:} These commands are intended to be used as a machine/script
1505 interface. Humans might find the ``scan_chain'' command more helpful
1506 when querying the state of the JTAG taps.
1508 @b{By default, all taps are enabled}
1511 @item @b{jtag tapenable} @var{DOTTED.NAME}
1512 @item @b{jtag tapdisable} @var{DOTTED.NAME}
1513 @item @b{jtag tapisenabled} @var{DOTTED.NAME}
1518 @cindex route controller
1520 These commands are used when your target has a JTAG Route controller
1521 that effectively adds or removes a tap from the jtag chain in a
1524 The ``standard way'' to remove a tap would be to place the tap in
1525 bypass mode. But with the advent of modern chips, this is not always a
1526 good solution. Some taps operate slowly, others operate fast, and
1527 there are other JTAG clock syncronization problems one must face. To
1528 solve that problem, the JTAG Route controller was introduced. Rather
1529 then ``bypass'' the tap, the tap is completely removed from the
1530 circuit and skipped.
1533 From OpenOCD's view point, a JTAG TAP is in one of 3 states:
1536 @item @b{Enabled - Not In ByPass} and has a variable bit length
1537 @item @b{Enabled - In ByPass} and has a length of exactly 1 bit.
1538 @item @b{Disabled} and has a length of ZERO and is removed from the circuit.
1541 The IEEE JTAG definition has no concept of a ``disabled'' tap.
1542 @b{Historical note:} this feature was added 28/nov/2008
1544 @b{jtag tapisenabled DOTTED.NAME}
1546 This command returns 1 if the named tap is currently enabled, 0 if not.
1547 This command exists so that scripts that manipulate a JRC (like the
1548 Omap3530 has) can determine if OpenOCD thinks a tap is presently
1549 enabled, or disabled.
1552 @node Target Configuration
1553 @chapter Target Configuration
1555 This chapter discusses how to create a GDB Debug Target. Before
1556 creating a ``target'' a JTAG Tap DOTTED.NAME must exist first.
1558 @section targets [NAME]
1559 @b{Note:} This command name is PLURAL - not singular.
1561 With NO parameter, this plural @b{targets} command lists all known
1562 targets in a human friendly form.
1564 With a parameter, this pural @b{targets} command sets the current
1565 target to the given name. (ie: If there are multiple debug targets)
1570 CmdName Type Endian ChainPos State
1571 -- ---------- ---------- ---------- -------- ----------
1572 0: target0 arm7tdmi little 0 halted
1575 @section target COMMANDS
1576 @b{Note:} This command name is SINGULAR - not plural. It is used to
1577 manipulate specific targets, to create targets and other things.
1579 Once a target is created, a TARGETNAME (object) command is created;
1580 see below for details.
1582 The TARGET command accepts these sub-commands:
1584 @item @b{create} .. parameters ..
1585 @* creates a new target, See below for details.
1587 @* Lists all supported target types (perhaps some are not yet in this document).
1589 @* Lists all current debug target names, for example: 'str912.cpu' or 'pxa27.cpu' example usage:
1591 foreach t [target names] {
1592 puts [format "Target: %s\n" $t]
1596 @* Returns the current target. OpenOCD always has, or refers to the ``current target'' in some way.
1597 By default, commands like: ``mww'' (used to write memory) operate on the current target.
1598 @item @b{number} @b{NUMBER}
1599 @* Internally OpenOCD maintains a list of targets - in numerical index
1600 (0..N-1) this command returns the name of the target at index N.
1603 set thename [target number $x]
1604 puts [format "Target %d is: %s\n" $x $thename]
1607 @* Returns the number of targets known to OpenOCD (see number above)
1610 set c [target count]
1611 for { set x 0 } { $x < $c } { incr x } {
1612 # Assuming you have created this function
1613 print_target_details $x
1619 @section TARGETNAME (object) commands
1620 @b{Use:} Once a target is created, an ``object name'' that represents the
1621 target is created. By convention, the target name is identical to the
1622 tap name. In a multiple target system, one can preceed many common
1623 commands with a specific target name and effect only that target.
1625 str912.cpu mww 0x1234 0x42
1626 omap3530.cpu mww 0x5555 123
1629 @b{Model:} The Tcl/Tk language has the concept of object commands. A
1630 good example is a on screen button, once a button is created a button
1631 has a name (a path in TK terms) and that name is useable as a 1st
1632 class command. For example in TK, one can create a button and later
1633 configure it like this:
1637 button .foobar -background red -command @{ foo @}
1639 .foobar configure -foreground blue
1641 set x [.foobar cget -background]
1643 puts [format "The button is %s" $x]
1646 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
1647 button. Commands avaialble as a ``target object'' are:
1649 @comment START targetobj commands.
1651 @item @b{configure} - configure the target; see Target Config/Cget Options below
1652 @item @b{cget} - query the target configuration; see Target Config/Cget Options below
1653 @item @b{curstate} - current target state (running, halt, etc)
1655 @* Intended for a human to see/read the currently configure target events.
1656 @item @b{Various Memory Commands} See the ``mww'' command elsewhere.
1657 @comment start memory
1667 @item @b{Memory To Array, Array To Memory}
1668 @* These are aimed at a machine interface to memory
1670 @item @b{mem2array ARRAYNAME WIDTH ADDRESS COUNT}
1671 @item @b{array2mem ARRAYNAME WIDTH ADDRESS COUNT}
1673 @* @b{ARRAYNAME} is the name of an array variable
1674 @* @b{WIDTH} is 8/16/32 - indicating the memory access size
1675 @* @b{ADDRESS} is the target memory address
1676 @* @b{COUNT} is the number of elements to process
1678 @item @b{Used during ``reset''}
1679 @* These commands are used internally by the OpenOCD scripts to deal
1680 with odd reset situations and are not documented here.
1682 @item @b{arp_examine}
1686 @item @b{arp_waitstate}
1688 @item @b{invoke-event} @b{EVENT-NAME}
1689 @* Invokes the specific event manually for the target
1692 @section Target Events
1693 At various times, certain things can happen, or you want them to happen.
1697 @item What should happen when GDB connects? Should your target reset?
1698 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
1699 @item During reset, do you need to write to certain memory location to reconfigure the SDRAM?
1702 All of the above items are handled by target events.
1704 To specify an event action, either during target creation, or later
1705 via ``$_TARGETNAME configure'' see this example.
1707 Syntactially, the option is: ``-event NAME BODY'' where NAME is a
1708 target event name, and BODY is a tcl procedure or string of commands
1711 The programmers model is the ``-command'' option used in Tcl/Tk
1712 buttons and events. Below are two identical examples, the first
1713 creates and invokes small procedure. The second inlines the procedure.
1716 proc my_attach_proc @{ @} @{
1720 mychip.cpu configure -event gdb-attach my_attach_proc
1721 mychip.cpu configure -event gdb-attach @{ puts "Reset..." ; reset halt @}
1727 @item @b{debug-halted}
1728 @* The target has halted for debug reasons (ie: breakpoint)
1729 @item @b{debug-resumed}
1730 @* The target has resumed (ie: gdb said run)
1731 @item @b{early-halted}
1732 @* Occurs early in the halt process
1733 @item @b{examine-end}
1734 @* Currently not used (goal: when JTAG examine completes)
1735 @item @b{examine-start}
1736 @* Currently not used (goal: when JTAG examine starts)
1737 @item @b{gdb-attach}
1738 @* When GDB connects
1739 @item @b{gdb-detach}
1740 @* When GDB disconnects
1742 @* When the taret has halted and GDB is not doing anything (see early halt)
1743 @item @b{gdb-flash-erase-start}
1744 @* Before the GDB flash process tries to erase the flash
1745 @item @b{gdb-flash-erase-end}
1746 @* After the GDB flash process has finished erasing the flash
1747 @item @b{gdb-flash-write-start}
1748 @* Before GDB writes to the flash
1749 @item @b{gdb-flash-write-end}
1750 @* After GDB writes to the flash
1752 @* Before the taret steps, gdb is trying to start/resume the tarfget
1754 @* The target has halted
1755 @item @b{old-gdb_program_config}
1756 @* DO NOT USE THIS: Used internally
1757 @item @b{old-pre_resume}
1758 @* DO NOT USE THIS: Used internally
1759 @item @b{reset-assert-pre}
1760 @* Before reset is asserted on the tap.
1761 @item @b{reset-assert-post}
1762 @* Reset is now asserted on the tap.
1763 @item @b{reset-deassert-pre}
1764 @* Reset is about to be released on the tap
1765 @item @b{reset-deassert-post}
1766 @* Reset has been released on the tap
1768 @* Currently not used.
1769 @item @b{reset-halt-post}
1770 @* Currently not usd
1771 @item @b{reset-halt-pre}
1772 @* Currently not used
1773 @item @b{reset-init}
1774 @* Currently not used
1775 @item @b{reset-start}
1776 @* Currently not used
1777 @item @b{reset-wait-pos}
1778 @* Currently not used
1779 @item @b{reset-wait-pre}
1780 @* Currently not used
1781 @item @b{resume-start}
1782 @* Before any target is resumed
1783 @item @b{resume-end}
1784 @* After all targets have resumed
1788 @* Target has resumed
1792 @section target create
1794 @cindex target creation
1797 @b{target} @b{create} <@var{NAME}> <@var{TYPE}> <@var{PARAMS ...}>
1799 @*This command creates a GDB debug target that refers to a specific JTAG tap.
1800 @comment START params
1803 @* Is the name of the debug target. By convention it should be the tap
1804 DOTTED.NAME, this name is also used to create the target object
1807 @* Specifies the target type, ie: arm7tdmi, or cortexM3. Currently supported targes are:
1808 @comment START types
1825 @*PARAMs are various target configure parameters, the following are mandatory
1827 @comment START mandatory
1829 @item @b{-endian big|little}
1830 @item @b{-chain-position DOTTED.NAME}
1831 @comment end MANDATORY
1836 @section Target Config/Cget Options
1837 These options can be specified when the target is created, or later
1838 via the configure option or to query the target via cget.
1840 @item @b{-type} - returns the target type
1841 @item @b{-event NAME BODY} see Target events
1842 @item @b{-work-area-virt [ADDRESS]} specify/set the work area
1843 @item @b{-work-area-phys [ADDRESS]} specify/set the work area
1844 @item @b{-work-area-size [ADDRESS]} specify/set the work area
1845 @item @b{-work-area-backup [0|1]} does the work area get backed up
1846 @item @b{-endian [big|little]}
1847 @item @b{-variant [NAME]} some chips have varients OpenOCD needs to know about
1848 @item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
1852 for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
1853 set name [target number $x]
1854 set y [$name cget -endian]
1855 set z [$name cget -type]
1856 puts [format "Chip %d is %s, Endian: %s, type: %s" $x $y $z]
1860 @section Target Varients
1863 @* Unknown (please write me)
1865 @* Unknown (please write me) (simular to arm7tdmi)
1867 @* Varients: @option{arm920t}, @option{arm922t} and @option{arm940t}
1868 This enables the hardware single-stepping support found on these
1873 @* None (this is also used as the ARM946)
1875 @* use variant <@var{-variant lm3s}> when debugging luminary lm3s targets. This will cause
1876 OpenOCD to use a software reset rather than asserting SRST to avoid a issue with clearing
1877 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
1878 be detected and the normal reset behaviour used.
1880 @* Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},@option{pxa250}, @option{pxa255}, @option{pxa26x}.
1882 @* Supported variants are @option{arm1136}, @option{arm1156}, @option{arm1176}
1884 @* Use variant @option{ejtag_srst} when debugging targets that do not
1885 provide a functional SRST line on the EJTAG connector. This causes
1886 OpenOCD to instead use an EJTAG software reset command to reset the
1887 processor. You still need to enable @option{srst} on the reset
1888 configuration command to enable OpenOCD hardware reset functionality.
1889 @comment END varients
1891 @section working_area - Command Removed
1892 @cindex working_area
1893 @*@b{Please use the ``$_TARGETNAME configure -work-area-... parameters instead}
1894 @* This documentation remains because there are existing scripts that
1895 still use this that need to be converted.
1897 working_area target# address size backup| [virtualaddress]
1899 @* The target# is a the 0 based target numerical index.
1901 This command specifies a working area for the debugger to use. This
1902 may be used to speed-up downloads to target memory and flash
1903 operations, or to perform otherwise unavailable operations (some
1904 coprocessor operations on ARM7/9 systems, for example). The last
1905 parameter decides whether the memory should be preserved
1906 (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
1907 possible, use a working_area that doesn't need to be backed up, as
1908 performing a backup slows down operation.
1910 @node Flash Configuration
1911 @chapter Flash Programing
1912 @cindex Flash Configuration
1914 @b{Note:} As of 28/nov/2008 OpenOCD does not know how to program a SPI
1915 flash that a micro may boot from. Perhaps you the reader would like to
1916 contribute support for this.
1920 @item Configure via the command @b{flash bank}
1921 @* Normally this is done in a configuration file.
1922 @item Operate on the flash via @b{flash SOMECOMMAND}
1923 @* Often commands to manipulate the flash are typed by a human, or run
1924 via a script in some automated way. For example: To program the boot
1925 flash on your board.
1927 @* Flashing via GDB requires the flash be configured via ``flash
1928 bank'', and the GDB flash features be enabled. See the Daemon
1929 configuration section for more details.
1932 @section Flash commands
1933 @cindex Flash commands
1934 @subsection flash banks
1937 @*List configured flash banks
1938 @*@b{NOTE:} the singular form: 'flash bank' is used to configure the flash banks.
1939 @subsection flash info
1940 @b{flash info} <@var{num}>
1942 @*Print info about flash bank <@option{num}>
1943 @subsection flash probe
1944 @b{flash probe} <@var{num}>
1946 @*Identify the flash, or validate the parameters of the configured flash. Operation
1947 depends on the flash type.
1948 @subsection flash erase_check
1949 @b{flash erase_check} <@var{num}>
1950 @cindex flash erase_check
1951 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
1952 updates the erase state information displayed by @option{flash info}. That means you have
1953 to issue an @option{erase_check} command after erasing or programming the device to get
1954 updated information.
1955 @subsection flash protect_check
1956 @b{flash protect_check} <@var{num}>
1957 @cindex flash protect_check
1958 @*Check protection state of sectors in flash bank <num>.
1959 @option{flash erase_sector} using the same syntax.
1960 @subsection flash erase_sector
1961 @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
1962 @cindex flash erase_sector
1963 @anchor{flash erase_sector}
1964 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
1965 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
1966 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
1968 @subsection flash erase_address
1969 @b{flash erase_address} <@var{address}> <@var{length}>
1970 @cindex flash erase_address
1971 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
1972 @subsection flash write_bank
1973 @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
1974 @cindex flash write_bank
1975 @anchor{flash write_bank}
1976 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
1977 <@option{offset}> bytes from the beginning of the bank.
1978 @subsection flash write_image
1979 @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
1980 @cindex flash write_image
1981 @anchor{flash write_image}
1982 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
1983 [@var{offset}] can be specified and the file [@var{type}] can be specified
1984 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
1985 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
1986 if the @option{erase} parameter is given.
1987 @subsection flash protect
1988 @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
1989 @cindex flash protect
1990 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
1991 <@var{last}> of @option{flash bank} <@var{num}>.
1993 @subsection mFlash commands
1994 @cindex mFlash commands
1996 @item @b{mflash probe}
1997 @cindex mflash probe
1999 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
2000 @cindex mflash write
2001 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
2002 <@var{offset}> bytes from the beginning of the bank.
2003 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
2005 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
2009 @section flash bank command
2010 The @b{flash bank} command is used to configure one or more flash chips (or banks in OpenOCD terms)
2013 @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
2014 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
2017 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
2018 and <@var{bus_width}> bytes using the selected flash <driver>.
2020 @subsection External Flash - cfi options
2022 CFI flash are external flash chips - often they are connected to a
2023 specific chip select on the micro. By default at hard reset most
2024 micros have the ablity to ``boot'' from some flash chip - typically
2025 attached to the chips CS0 pin.
2027 For other chip selects: OpenOCD does not know how to configure, or
2028 access a specific chip select. Instead you the human might need to via
2029 other commands (like: mww) configure additional chip selects, or
2030 perhaps configure a GPIO pin that controls the ``write protect'' pin
2033 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
2034 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
2035 @*CFI flashes require the number of the target they're connected to as an additional
2036 argument. The CFI driver makes use of a working area (specified for the target)
2037 to significantly speed up operation.
2039 @var{chip_width} and @var{bus_width} are specified in bytes.
2041 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
2045 @subsection Internal Flash (Micro Controllers)
2046 @subsubsection lpc2000 options
2047 @cindex lpc2000 options
2049 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2050 <@var{clock}> [@var{calc_checksum}]
2051 @*LPC flashes don't require the chip and bus width to be specified. Additional
2052 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
2053 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
2054 of the target this flash belongs to (first is 0), the frequency at which the core
2055 is currently running (in kHz - must be an integral number), and the optional keyword
2056 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
2060 @subsubsection at91sam7 options
2061 @cindex at91sam7 options
2063 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
2064 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
2065 reading the chip-id and type.
2067 @subsubsection str7 options
2068 @cindex str7 options
2070 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
2071 @*variant can be either STR71x, STR73x or STR75x.
2073 @subsubsection str9 options
2074 @cindex str9 options
2076 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2077 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
2079 str9x flash_config 0 4 2 0 0x80000
2081 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
2083 @subsubsection str9 options (str9xpec driver)
2085 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2086 @*Before using the flash commands the turbo mode will need enabling using str9xpec
2087 @option{enable_turbo} <@var{num>.}
2089 Only use this driver for locking/unlocking the device or configuring the option bytes.
2090 Use the standard str9 driver for programming. @xref{STR9 specific commands}.
2092 @subsubsection stellaris (LM3Sxxx) options
2093 @cindex stellaris (LM3Sxxx) options
2095 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2096 @*stellaris flash plugin only require the @var{target#}.
2098 @subsubsection stm32x options
2099 @cindex stm32x options
2101 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2102 @*stm32x flash plugin only require the @var{target#}.
2104 @subsubsection aduc702x options
2105 @cindex aduc702x options
2107 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
2108 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
2110 @subsection mFlash configuration
2111 @cindex mFlash configuration
2112 @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
2113 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
2115 @*Configures a mflash for <@var{soc}> host bank at
2116 <@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
2117 order. Pin number format is dependent on host GPIO calling convention.
2118 If WP or DPD pin was not used, write -1. Currently, mflash bank
2119 support s3c2440 and pxa270.
2121 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
2123 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
2125 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
2127 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
2130 @section Micro Controller Specific Flash Commands
2132 @subsection AT91SAM7 specific commands
2133 @cindex AT91SAM7 specific commands
2134 The flash configuration is deduced from the chip identification register. The flash
2135 controller handles erases automatically on a page (128/265 byte) basis so erase is
2136 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
2137 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
2138 that can be erased separatly. Only an EraseAll command is supported by the controller
2139 for each flash plane and this is called with
2141 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
2142 @*bulk erase flash planes first_plane to last_plane.
2143 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
2144 @cindex at91sam7 gpnvm
2145 @*set or clear a gpnvm bit for the processor
2148 @subsection STR9 specific commands
2149 @cindex STR9 specific commands
2150 @anchor{STR9 specific commands}
2151 These are flash specific commands when using the str9xpec driver.
2153 @item @b{str9xpec enable_turbo} <@var{num}>
2154 @cindex str9xpec enable_turbo
2155 @*enable turbo mode, simply this will remove the str9 from the chain and talk
2156 directly to the embedded flash controller.
2157 @item @b{str9xpec disable_turbo} <@var{num}>
2158 @cindex str9xpec disable_turbo
2159 @*restore the str9 into jtag chain.
2160 @item @b{str9xpec lock} <@var{num}>
2161 @cindex str9xpec lock
2162 @*lock str9 device. The str9 will only respond to an unlock command that will
2164 @item @b{str9xpec unlock} <@var{num}>
2165 @cindex str9xpec unlock
2166 @*unlock str9 device.
2167 @item @b{str9xpec options_read} <@var{num}>
2168 @cindex str9xpec options_read
2169 @*read str9 option bytes.
2170 @item @b{str9xpec options_write} <@var{num}>
2171 @cindex str9xpec options_write
2172 @*write str9 option bytes.
2175 Note: Before using the str9xpec driver here is some background info to help
2176 you better understand how the drivers works. OpenOCD has two flash drivers for
2180 Standard driver @option{str9x} programmed via the str9 core. Normally used for
2181 flash programming as it is faster than the @option{str9xpec} driver.
2183 Direct programming @option{str9xpec} using the flash controller, this is
2184 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
2185 core does not need to be running to program using this flash driver. Typical use
2186 for this driver is locking/unlocking the target and programming the option bytes.
2189 Before we run any cmds using the @option{str9xpec} driver we must first disable
2190 the str9 core. This example assumes the @option{str9xpec} driver has been
2191 configured for flash bank 0.
2193 # assert srst, we do not want core running
2194 # while accessing str9xpec flash driver
2196 # turn off target polling
2199 str9xpec enable_turbo 0
2201 str9xpec options_read 0
2202 # re-enable str9 core
2203 str9xpec disable_turbo 0
2207 The above example will read the str9 option bytes.
2208 When performing a unlock remember that you will not be able to halt the str9 - it
2209 has been locked. Halting the core is not required for the @option{str9xpec} driver
2210 as mentioned above, just issue the cmds above manually or from a telnet prompt.
2212 @subsection STR9 configuration
2213 @cindex STR9 configuration
2215 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
2216 <@var{BBADR}> <@var{NBBADR}>
2217 @cindex str9x flash_config
2218 @*Configure str9 flash controller.
2220 eg. str9x flash_config 0 4 2 0 0x80000
2222 BBSR - Boot Bank Size register
2223 NBBSR - Non Boot Bank Size register
2224 BBADR - Boot Bank Start Address register
2225 NBBADR - Boot Bank Start Address register
2229 @subsection STR9 option byte configuration
2230 @cindex STR9 option byte configuration
2232 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
2233 @cindex str9xpec options_cmap
2234 @*configure str9 boot bank.
2235 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
2236 @cindex str9xpec options_lvdthd
2237 @*configure str9 lvd threshold.
2238 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
2239 @cindex str9xpec options_lvdsel
2240 @*configure str9 lvd source.
2241 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
2242 @cindex str9xpec options_lvdwarn
2243 @*configure str9 lvd reset warning source.
2246 @subsection STM32x specific commands
2247 @cindex STM32x specific commands
2249 These are flash specific commands when using the stm32x driver.
2251 @item @b{stm32x lock} <@var{num}>
2253 @*lock stm32 device.
2254 @item @b{stm32x unlock} <@var{num}>
2255 @cindex stm32x unlock
2256 @*unlock stm32 device.
2257 @item @b{stm32x options_read} <@var{num}>
2258 @cindex stm32x options_read
2259 @*read stm32 option bytes.
2260 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
2261 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
2262 @cindex stm32x options_write
2263 @*write stm32 option bytes.
2264 @item @b{stm32x mass_erase} <@var{num}>
2265 @cindex stm32x mass_erase
2266 @*mass erase flash memory.
2269 @subsection Stellaris specific commands
2270 @cindex Stellaris specific commands
2272 These are flash specific commands when using the Stellaris driver.
2274 @item @b{stellaris mass_erase} <@var{num}>
2275 @cindex stellaris mass_erase
2276 @*mass erase flash memory.
2280 @node General Commands
2281 @chapter General Commands
2284 The commands documented in this chapter here are common commands that
2285 you a human may want to type and see the output of. Configuration type
2286 commands are documented elsewhere.
2290 @item @b{Source Of Commands}
2291 @* OpenOCD commands can occur in a configuration script (discussed
2292 elsewhere) or typed manually by a human or supplied programatically,
2293 or via one of several Tcp/Ip Ports.
2295 @item @b{From the human}
2296 @* A human should interact with the Telnet interface (default port: 4444,
2297 or via GDB, default port 3333)
2299 To issue commands from within a GDB session, use the @option{monitor}
2300 command, e.g. use @option{monitor poll} to issue the @option{poll}
2301 command. All output is relayed through the GDB session.
2303 @item @b{Machine Interface}
2304 The TCL interface intent is to be a machine interface. The default TCL
2309 @section Daemon Commands
2312 @b{sleep} <@var{msec}>
2314 @*Wait for n milliseconds before resuming. Useful in connection with script files
2315 (@var{script} command and @var{target_script} configuration).
2320 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
2322 @subsection debug_level [@var{n}]
2324 @anchor{debug_level}
2325 @*Display or adjust debug level to n<0-3>
2327 @subsection fast [@var{enable|disable}]
2329 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
2330 downloads and fast memory access will work if the JTAG interface isn't too fast and
2331 the core doesn't run at a too low frequency. Note that this option only changes the default
2332 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
2335 The target specific "dangerous" optimisation tweaking options may come and go
2336 as more robust and user friendly ways are found to ensure maximum throughput
2337 and robustness with a minimum of configuration.
2339 Typically the "fast enable" is specified first on the command line:
2342 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
2345 @subsection log_output <@var{file}>
2347 @*Redirect logging to <file> (default: stderr)
2349 @subsection script <@var{file}>
2351 @*Execute commands from <file>
2352 Also see: ``source [find FILENAME]''
2354 @section Target state handling
2355 @subsection power <@var{on}|@var{off}>
2357 @*Turn power switch to target on/off.
2358 No arguments: print status.
2359 Not all interfaces support this.
2361 @subsection reg [@option{#}|@option{name}] [value]
2363 @*Access a single register by its number[@option{#}] or by its [@option{name}].
2364 No arguments: list all available registers for the current target.
2365 Number or name argument: display a register
2366 Number or name and value arguments: set register value
2368 @subsection poll [@option{on}|@option{off}]
2370 @*Poll the target for its current state. If the target is in debug mode, architecture
2371 specific information about the current state is printed. An optional parameter
2372 allows continuous polling to be enabled and disabled.
2374 @subsection halt [@option{ms}]
2376 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
2377 Default [@option{ms}] is 5 seconds if no arg given.
2378 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
2379 will stop OpenOCD from waiting.
2381 @subsection wait_halt [@option{ms}]
2383 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
2384 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
2387 @subsection resume [@var{address}]
2389 @*Resume the target at its current code position, or at an optional address.
2390 OpenOCD will wait 5 seconds for the target to resume.
2392 @subsection step [@var{address}]
2394 @*Single-step the target at its current code position, or at an optional address.
2396 @subsection reset [@option{run}|@option{halt}|@option{init}]
2398 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
2400 With no arguments a "reset run" is executed
2404 @*Let the target run.
2407 @*Immediately halt the target (works only with certain configurations).
2410 @*Immediately halt the target, and execute the reset script (works only with certain
2414 @subsection soft_reset_halt
2416 @*Requesting target halt and executing a soft reset. This often used
2417 when a target cannot be reset and halted. The target, after reset is
2418 released begins to execute code. OpenOCD attempts to stop the CPU and
2419 then sets the Program counter back at the reset vector. Unfortunatlly
2420 that code that was executed may have left hardware in an unknown
2424 @section Memory access commands
2426 display available ram memory.
2427 @subsection Memory Peek/Poke type commands
2428 These commands allow accesses of a specific size to the memory
2429 system. Often these are used to configure the current target in some
2430 special way. For example - one may need to write certian values to the
2431 SDRAM controller to enable SDRAM.
2434 @item To change the current target see the ``targets'' (plural) command
2435 @item In system level scripts these commands are depricated, please use the TARGET object versions.
2439 @item @b{mdw} <@var{addr}> [@var{count}]
2441 @*display memory words (32bit)
2442 @item @b{mdh} <@var{addr}> [@var{count}]
2444 @*display memory half-words (16bit)
2445 @item @b{mdb} <@var{addr}> [@var{count}]
2447 @*display memory bytes (8bit)
2448 @item @b{mww} <@var{addr}> <@var{value}>
2450 @*write memory word (32bit)
2451 @item @b{mwh} <@var{addr}> <@var{value}>
2453 @*write memory half-word (16bit)
2454 @item @b{mwb} <@var{addr}> <@var{value}>
2456 @*write memory byte (8bit)
2459 @section Image Loading Commands
2460 @subsection load_image
2461 @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2464 @*Load image <@var{file}> to target memory at <@var{address}>
2465 @subsection fast_load_image
2466 @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2467 @cindex fast_load_image
2468 @anchor{fast_load_image}
2469 @*Normally you should be using @b{load_image} or GDB load. However, for
2470 testing purposes or when IO overhead is significant(OpenOCD running on embedded
2471 host), then storing the image in memory and uploading the image to the target
2472 can be a way to upload e.g. multiple debug sessions when the binary does not change.
2473 Arguments as @b{load_image}, but image is stored in OpenOCD host
2474 memory, i.e. does not affect target. This approach is also useful when profiling
2475 target programming performance as IO and target programming can easily be profiled
2477 @subsection fast_load
2481 @*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
2482 @subsection dump_image
2483 @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
2486 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
2487 (binary) <@var{file}>.
2488 @subsection verify_image
2489 @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
2490 @cindex verify_image
2491 @*Verify <@var{file}> against target memory starting at <@var{address}>.
2492 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
2495 @section Breakpoint commands
2496 @cindex Breakpoint commands
2498 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
2500 @*set breakpoint <address> <length> [hw]
2501 @item @b{rbp} <@var{addr}>
2503 @*remove breakpoint <adress>
2504 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
2506 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
2507 @item @b{rwp} <@var{addr}>
2509 @*remove watchpoint <adress>
2512 @section Misc Commands
2513 @cindex Other Target Commands
2515 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
2517 Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
2520 @section Target Specific Commands
2521 @cindex Target Specific Commands
2525 @section Architecture Specific Commands
2526 @cindex Architecture Specific Commands
2528 @subsection ARMV4/5 specific commands
2529 @cindex ARMV4/5 specific commands
2531 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
2532 or Intel XScale (XScale isn't supported yet).
2534 @item @b{armv4_5 reg}
2536 @*Display a list of all banked core registers, fetching the current value from every
2537 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
2539 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
2540 @cindex armv4_5 core_mode
2541 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
2542 The target is resumed in the currently set @option{core_mode}.
2545 @subsection ARM7/9 specific commands
2546 @cindex ARM7/9 specific commands
2548 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
2549 ARM920t or ARM926EJ-S.
2551 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
2552 @cindex arm7_9 dbgrq
2553 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
2554 safe for all but ARM7TDMI--S cores (like Philips LPC).
2555 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
2556 @cindex arm7_9 fast_memory_access
2557 @anchor{arm7_9 fast_memory_access}
2558 @*Allow OpenOCD to read and write memory without checking completion of
2559 the operation. This provides a huge speed increase, especially with USB JTAG
2560 cables (FT2232), but might be unsafe if used with targets running at a very low
2561 speed, like the 32kHz startup clock of an AT91RM9200.
2562 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
2563 @cindex arm7_9 dcc_downloads
2564 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
2565 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
2566 unsafe, especially with targets running at a very low speed. This command was introduced
2567 with OpenOCD rev. 60.
2570 @subsection ARM720T specific commands
2571 @cindex ARM720T specific commands
2574 @item @b{arm720t cp15} <@var{num}> [@var{value}]
2575 @cindex arm720t cp15
2576 @*display/modify cp15 register <@option{num}> [@option{value}].
2577 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
2578 @cindex arm720t md<bhw>_phys
2579 @*Display memory at physical address addr.
2580 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
2581 @cindex arm720t mw<bhw>_phys
2582 @*Write memory at physical address addr.
2583 @item @b{arm720t virt2phys} <@var{va}>
2584 @cindex arm720t virt2phys
2585 @*Translate a virtual address to a physical address.
2588 @subsection ARM9TDMI specific commands
2589 @cindex ARM9TDMI specific commands
2592 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
2593 @cindex arm9tdmi vector_catch
2594 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
2595 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
2596 @option{irq} @option{fiq}.
2598 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
2601 @subsection ARM966E specific commands
2602 @cindex ARM966E specific commands
2605 @item @b{arm966e cp15} <@var{num}> [@var{value}]
2606 @cindex arm966e cp15
2607 @*display/modify cp15 register <@option{num}> [@option{value}].
2610 @subsection ARM920T specific commands
2611 @cindex ARM920T specific commands
2614 @item @b{arm920t cp15} <@var{num}> [@var{value}]
2615 @cindex arm920t cp15
2616 @*display/modify cp15 register <@option{num}> [@option{value}].
2617 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
2618 @cindex arm920t cp15i
2619 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
2620 @item @b{arm920t cache_info}
2621 @cindex arm920t cache_info
2622 @*Print information about the caches found. This allows you to see if your target
2623 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
2624 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
2625 @cindex arm920t md<bhw>_phys
2626 @*Display memory at physical address addr.
2627 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
2628 @cindex arm920t mw<bhw>_phys
2629 @*Write memory at physical address addr.
2630 @item @b{arm920t read_cache} <@var{filename}>
2631 @cindex arm920t read_cache
2632 @*Dump the content of ICache and DCache to a file.
2633 @item @b{arm920t read_mmu} <@var{filename}>
2634 @cindex arm920t read_mmu
2635 @*Dump the content of the ITLB and DTLB to a file.
2636 @item @b{arm920t virt2phys} <@var{va}>
2637 @cindex arm920t virt2phys
2638 @*Translate a virtual address to a physical address.
2641 @subsection ARM926EJS specific commands
2642 @cindex ARM926EJS specific commands
2645 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
2646 @cindex arm926ejs cp15
2647 @*display/modify cp15 register <@option{num}> [@option{value}].
2648 @item @b{arm926ejs cache_info}
2649 @cindex arm926ejs cache_info
2650 @*Print information about the caches found.
2651 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
2652 @cindex arm926ejs md<bhw>_phys
2653 @*Display memory at physical address addr.
2654 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
2655 @cindex arm926ejs mw<bhw>_phys
2656 @*Write memory at physical address addr.
2657 @item @b{arm926ejs virt2phys} <@var{va}>
2658 @cindex arm926ejs virt2phys
2659 @*Translate a virtual address to a physical address.
2662 @subsection CORTEX_M3 specific commands
2663 @cindex CORTEX_M3 specific commands
2666 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
2667 @cindex cortex_m3 maskisr
2668 @*Enable masking (disabling) interrupts during target step/resume.
2672 @section Debug commands
2673 @cindex Debug commands
2674 The following commands give direct access to the core, and are most likely
2675 only useful while debugging OpenOCD.
2677 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
2678 @cindex arm7_9 write_xpsr
2679 @*Immediately write either the current program status register (CPSR) or the saved
2680 program status register (SPSR), without changing the register cache (as displayed
2681 by the @option{reg} and @option{armv4_5 reg} commands).
2682 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
2683 <@var{0=cpsr},@var{1=spsr}>
2684 @cindex arm7_9 write_xpsr_im8
2685 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
2686 operation (similar to @option{write_xpsr}).
2687 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
2688 @cindex arm7_9 write_core_reg
2689 @*Write a core register, without changing the register cache (as displayed by the
2690 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
2691 encoding of the [M4:M0] bits of the PSR.
2694 @section Target Requests
2695 @cindex Target Requests
2696 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
2697 See libdcc in the contrib dir for more details.
2699 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
2700 @cindex target_request debugmsgs
2701 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
2705 @chapter JTAG Commands
2706 @cindex JTAG commands
2707 Generally most people will not use the bulk of these commands. They
2708 are mostly used by the OpenOCD developers or those who need to
2709 directly manipulate the JTAG taps.
2711 In general these commands control JTAG taps at a very low level. For
2712 example if you need to control a JTAG Route Controller (ie: the
2713 OMAP3530 on the Beagle Board has one) you might use these commands in
2714 a script or an event procedure.
2717 @item @b{scan_chain}
2719 @*Print current scan chain configuration.
2720 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
2722 @*Toggle reset lines.
2723 @item @b{endstate} <@var{tap_state}>
2725 @*Finish JTAG operations in <@var{tap_state}>.
2726 @item @b{runtest} <@var{num_cycles}>
2728 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
2729 @item @b{statemove} [@var{tap_state}]
2731 @*Move to current endstate or [@var{tap_state}]
2732 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2734 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
2735 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
2737 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
2738 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
2739 @cindex verify_ircapture
2740 @*Verify value captured during Capture-IR. Default is enabled.
2741 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2743 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
2744 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
2746 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
2753 If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
2754 be used to access files on PCs(either developer PC or some other PC).
2756 The way this works on the ZY1000 is to prefix a filename by
2757 "/tftp/ip/" and append the tftp path on the tftp
2758 server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf" will
2759 load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
2760 if the file was hosted on the embedded host.
2762 In order to achieve decent performance, you must choose a tftp server
2763 that supports a packet size bigger than the default packet size(512 bytes). There
2764 are numerous tftp servers out there(free and commercial) and you will have to do
2765 a bit of googling to find something that fits your requirements.
2767 @node Sample Scripts
2768 @chapter Sample Scripts
2771 This page shows how to use the target library.
2773 The configuration script can be divided in the following section:
2775 @item daemon configuration
2777 @item jtag scan chain
2778 @item target configuration
2779 @item flash configuration
2782 Detailed information about each section can be found at OpenOCD configuration.
2784 @section AT91R40008 example
2785 @cindex AT91R40008 example
2786 To start OpenOCD with a target script for the AT91R40008 CPU and reset
2787 the CPU upon startup of the OpenOCD daemon.
2789 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
2793 @node GDB and OpenOCD
2794 @chapter GDB and OpenOCD
2795 @cindex GDB and OpenOCD
2796 OpenOCD complies with the remote gdbserver protocol, and as such can be used
2797 to debug remote targets.
2799 @section Connecting to GDB
2800 @cindex Connecting to GDB
2801 @anchor{Connecting to GDB}
2802 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
2803 instance 6.3 has a known bug where it produces bogus memory access
2804 errors, which has since been fixed: look up 1836 in
2805 @url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
2807 @*OpenOCD can communicate with GDB in two ways:
2810 A socket (tcp) connection is typically started as follows:
2812 target remote localhost:3333
2814 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
2816 A pipe connection is typically started as follows:
2818 target remote openocd --pipe
2820 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
2821 Using this method has the advantage of GDB starting/stopping OpenOCD for debug session.
2824 @*To see a list of available OpenOCD commands type @option{monitor help} on the
2827 OpenOCD supports the gdb @option{qSupported} packet, this enables information
2828 to be sent by the gdb server (OpenOCD) to GDB. Typical information includes
2829 packet size and device memory map.
2831 Previous versions of OpenOCD required the following GDB options to increase
2832 the packet size and speed up GDB communication.
2834 set remote memory-write-packet-size 1024
2835 set remote memory-write-packet-size fixed
2836 set remote memory-read-packet-size 1024
2837 set remote memory-read-packet-size fixed
2839 This is now handled in the @option{qSupported} PacketSize and should not be required.
2841 @section Programming using GDB
2842 @cindex Programming using GDB
2844 By default the target memory map is sent to GDB, this can be disabled by
2845 the following OpenOCD config option:
2847 gdb_memory_map disable
2849 For this to function correctly a valid flash config must also be configured
2850 in OpenOCD. For faster performance you should also configure a valid
2853 Informing GDB of the memory map of the target will enable GDB to protect any
2854 flash area of the target and use hardware breakpoints by default. This means
2855 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
2856 using a memory map. @xref{gdb_breakpoint_override}.
2858 To view the configured memory map in GDB, use the gdb command @option{info mem}
2859 All other unasigned addresses within GDB are treated as RAM.
2861 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
2862 this can be changed to the old behaviour by using the following GDB command.
2864 set mem inaccessible-by-default off
2867 If @option{gdb_flash_program enable} is also used, GDB will be able to
2868 program any flash memory using the vFlash interface.
2870 GDB will look at the target memory map when a load command is given, if any
2871 areas to be programmed lie within the target flash area the vFlash packets
2874 If the target needs configuring before GDB programming, an event
2875 script can be executed.
2877 $_TARGETNAME configure -event EVENTNAME BODY
2880 To verify any flash programming the GDB command @option{compare-sections}
2883 @node TCL scripting API
2884 @chapter TCL scripting API
2885 @cindex TCL scripting API
2888 The commands are stateless. E.g. the telnet command line has a concept
2889 of currently active target, the Tcl API proc's take this sort of state
2890 information as an argument to each proc.
2892 There are three main types of return values: single value, name value
2893 pair list and lists.
2895 Name value pair. The proc 'foo' below returns a name/value pair
2901 > set foo(you) Oyvind
2902 > set foo(mouse) Micky
2903 > set foo(duck) Donald
2911 me Duane you Oyvind mouse Micky duck Donald
2913 Thus, to get the names of the associative array is easy:
2915 foreach { name value } [set foo] {
2916 puts "Name: $name, Value: $value"
2920 Lists returned must be relatively small. Otherwise a range
2921 should be passed in to the proc in question.
2923 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
2924 is the low level API upon which "flash banks" is implemented.
2927 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2929 Read memory and return as a TCL array for script processing
2930 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2932 Convert a TCL array to memory locations and write the values
2933 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
2935 Return information about the flash banks
2938 OpenOCD commands can consist of two words, e.g. "flash banks". The
2939 startup.tcl "unknown" proc will translate this into a tcl proc
2940 called "flash_banks".
2944 @chapter Deprecated/Removed Commands
2945 @cindex Deprecated/Removed Commands
2946 Certain OpenOCD commands have been deprecated/removed during the various revisions.
2949 @item @b{arm7_9 fast_writes}
2950 @cindex arm7_9 fast_writes
2951 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
2952 @item @b{arm7_9 force_hw_bkpts}
2953 @cindex arm7_9 force_hw_bkpts
2954 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
2955 for flash if the gdb memory map has been set up(default when flash is declared in
2956 target configuration). @xref{gdb_breakpoint_override}.
2957 @item @b{arm7_9 sw_bkpts}
2958 @cindex arm7_9 sw_bkpts
2959 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
2960 @item @b{daemon_startup}
2961 @cindex daemon_startup
2962 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
2963 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
2964 and @option{target cortex_m3 little reset_halt 0}.
2965 @item @b{dump_binary}
2967 @*use @option{dump_image} command with same args. @xref{dump_image}.
2968 @item @b{flash erase}
2970 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
2971 @item @b{flash write}
2973 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2974 @item @b{flash write_binary}
2975 @cindex flash write_binary
2976 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2977 @item @b{flash auto_erase}
2978 @cindex flash auto_erase
2979 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
2980 @item @b{load_binary}
2982 @*use @option{load_image} command with same args. @xref{load_image}.
2983 @item @b{run_and_halt_time}
2984 @cindex run_and_halt_time
2985 @*This command has been removed for simpler reset behaviour, it can be simulated with the
2992 @item @b{target} <@var{type}> <@var{endian}> <@var{jtag-position}>
2994 @*use the create subcommand of @option{target}.
2995 @item @b{target_script} <@var{target#}> <@var{eventname}> <@var{scriptname}>
2996 @cindex target_script
2997 @*use <@var{target_name}> configure -event <@var{eventname}> "script <@var{scriptname}>"
2998 @item @b{working_area}
2999 @cindex working_area
3000 @*use the @option{configure} subcommand of @option{target} to set the work-area-virt, work-area-phy, work-area-size, and work-area-backup properties of the target.
3007 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
3009 @cindex adaptive clocking
3012 In digital circuit design it is often refered to as ``clock
3013 syncronization'' the JTAG interface uses one clock (TCK or TCLK)
3014 operating at some speed, your target is operating at another. The two
3015 clocks are not syncronized, they are ``asynchronous''
3017 In order for the two to work together they must syncronize. Otherwise
3018 the two systems will get out of sync with each other and nothing will
3019 work. There are 2 basic options. @b{1.} use a special circuit or
3020 @b{2.} one clock must be some multile slower the the other.
3022 @b{Does this really matter?} For some chips and some situations, this
3023 is a non-issue (ie: A 500mhz ARM926) but for others - for example some
3024 ATMEL SAM7 and SAM9 chips start operation from reset at 32khz -
3025 program/enable the oscillators and eventually the main clock. It is in
3026 those critical times you must slow the jtag clock to sometimes 1 to
3029 Imagine debugging that 500mhz arm926 hand held battery powered device
3030 that ``deep sleeps'' at 32khz between every keystroke. It can be
3033 @b{Solution #1 - A special circuit}
3035 In order to make use of this your jtag dongle must support the RTCK
3036 feature. Not all dongles support this - keep reading!
3038 The RTCK signal often found in some ARM chips is used to help with
3039 this problem. ARM has a good description of the problem described at
3040 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
3041 28/nov/2008]. Link title: ``How does the jtag synchronisation logic
3042 work? / how does adaptive clocking working?''.
3044 The nice thing about adaptive clocking is that ``battery powered hand
3045 held device example'' - the adaptiveness works perfectly all the
3046 time. One can set a break point or halt the system in the deep power
3047 down code, slow step out until the system speeds up.
3049 @b{Solution #2 - Always works - but is slower}
3051 Often this is a perfectly acceptable solution.
3053 In the most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
3054 the target clock speed. But what is that ``magic division'' it varies
3055 depending upon the chips on your board. @b{ARM Rule of thumb} Most ARM
3056 based systems require an 8:1 division. @b{Xilinx Rule of thumb} is
3057 1/12 the clock speed.
3059 Note: Many FTDI2232C based JTAG dongles are limited to 6mhz.
3061 You can still debug the 'lower power' situations - you just need to
3062 manually adjust the clock speed at every step. While painful and
3063 teadious, it is not always practical.
3065 It is however easy to ``code your way around it'' - ie: Cheat a little
3066 have a special debug mode in your application that does a ``high power
3067 sleep''. If you are careful - 98% of your problems can be debugged
3070 To set the JTAG frequency use the command:
3078 @item @b{Win32 Pathnames} Why does not backslashes in paths under Windows doesn't work?
3080 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
3081 around Windows filenames.
3094 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
3096 Make sure you have Cygwin installed, or at least a version of OpenOCD that
3097 claims to come with all the necessary dlls. When using Cygwin, try launching
3098 OpenOCD from the Cygwin shell.
3100 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
3101 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
3102 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
3104 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
3105 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
3106 software breakpoints consume one of the two available hardware breakpoints.
3108 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
3109 and works sometimes fine.
3111 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
3112 clock at the time you're programming the flash. If you've specified the crystal's
3113 frequency, make sure the PLL is disabled, if you've specified the full core speed
3114 (e.g. 60MHz), make sure the PLL is enabled.
3116 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
3117 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
3118 out while waiting for end of scan, rtck was disabled".
3120 Make sure your PC's parallel port operates in EPP mode. You might have to try several
3121 settings in your PC BIOS (ECP, EPP, and different versions of those).
3123 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
3124 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
3125 memory read caused data abort".
3127 The errors are non-fatal, and are the result of GDB trying to trace stack frames
3128 beyond the last valid frame. It might be possible to prevent this by setting up
3129 a proper "initial" stack frame, if you happen to know what exactly has to
3130 be done, feel free to add this here.
3132 @b{Simple:} In your startup code - push 8 registers of ZEROs onto the
3133 stack before calling main(). What GDB is doing is ``climbing'' the run
3134 time stack by reading various values on the stack using the standard
3135 call frame for the target. GDB keeps going - until one of 2 things
3136 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
3137 stackframes have been processed. By pushing ZEROs on the stack, GDB
3140 @b{Debugging Interrupt Service Routines} - In your ISR before you call
3141 your C code, do the same, artifically push some zeros on to the stack,
3142 remember to pop them off when the ISR is done.
3144 @b{Also note:} If you have a multi-threaded operating system, they
3145 often do not @b{in the intrest of saving memory} waste these few
3149 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
3150 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
3152 This warning doesn't indicate any serious problem, as long as you don't want to
3153 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
3154 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
3155 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
3156 independently. With this setup, it's not possible to halt the core right out of
3157 reset, everything else should work fine.
3159 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
3160 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
3161 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
3162 quit with an error message. Is there a stability issue with OpenOCD?
3164 No, this is not a stability issue concerning OpenOCD. Most users have solved
3165 this issue by simply using a self-powered USB hub, which they connect their
3166 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
3167 supply stable enough for the Amontec JTAGkey to be operated.
3169 @b{Laptops running on battery have this problem too...}
3171 @item @b{USB Power} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
3172 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
3173 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
3174 What does that mean and what might be the reason for this?
3176 First of all, the reason might be the USB power supply. Try using a self-powered
3177 hub instead of a direct connection to your computer. Secondly, the error code 4
3178 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
3179 chip ran into some sort of error - this points us to a USB problem.
3181 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
3182 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
3183 What does that mean and what might be the reason for this?
3185 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
3186 has closed the connection to OpenOCD. This might be a GDB issue.
3188 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
3189 are described, there is a parameter for specifying the clock frequency
3190 for LPC2000 internal flash devices (e.g. @option{flash bank lpc2000
3191 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
3192 specified in kilohertz. However, I do have a quartz crystal of a
3193 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
3194 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
3197 No. The clock frequency specified here must be given as an integral number.
3198 However, this clock frequency is used by the In-Application-Programming (IAP)
3199 routines of the LPC2000 family only, which seems to be very tolerant concerning
3200 the given clock frequency, so a slight difference between the specified clock
3201 frequency and the actual clock frequency will not cause any trouble.
3203 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
3205 Well, yes and no. Commands can be given in arbitrary order, yet the
3206 devices listed for the JTAG scan chain must be given in the right
3207 order (jtag newdevice), with the device closest to the TDO-Pin being
3208 listed first. In general, whenever objects of the same type exist
3209 which require an index number, then these objects must be given in the
3210 right order (jtag newtap, targets and flash banks - a target
3211 references a jtag newtap and a flash bank references a target).
3213 You can use the ``scan_chain'' command to verify and display the tap order.
3215 @item @b{JTAG Tap Order} JTAG Tap Order - Command Order
3217 Many newer devices have multiple JTAG taps. For example: ST
3218 Microsystems STM32 chips have two taps, a ``boundary scan tap'' and
3219 ``cortexM3'' tap. Example: The STM32 reference manual, Document ID:
3220 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
3221 connected to the Boundary Scan Tap, which then connects to the
3222 CortexM3 Tap, which then connects to the TDO pin.
3224 Thus, the proper order for the STM32 chip is: (1) The CortexM3, then
3225 (2) The Boundary Scan Tap. If your board includes an additional JTAG
3226 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
3227 place it before or after the stm32 chip in the chain. For example:
3230 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
3231 @item STM32 BS TDO (output) -> STM32 CortexM3 TDI (input)
3232 @item STM32 CortexM3 TDO (output) -> SM32 TDO Pin
3233 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
3234 @item Xilinx TDO Pin -> OpenOCD TDO (input)
3237 The ``jtag device'' commands would thus be in the order shown below. Note
3240 @item jtag newtap Xilinx tap -irlen ...
3241 @item jtag newtap stm32 cpu -irlen ...
3242 @item jtag newtap stm32 bs -irlen ...
3243 @item # Create the debug target and say where it is
3244 @item target create stm32.cpu -chain-position stm32.cpu ...
3248 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
3249 log file, I can see these error messages: Error: arm7_9_common.c:561
3250 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
3256 @node TCL Crash Course
3257 @chapter TCL Crash Course
3260 Not everyone knows TCL - this is not intended to be a replacement for
3261 learning TCL, the intent of this chapter is to give you some idea of
3262 how the TCL Scripts work.
3264 This chapter is written with two audiences in mind. (1) OpenOCD users
3265 who need to understand a bit more of how JIM-Tcl works so they can do
3266 something useful, and (2) those that want to add a new command to
3269 @section TCL Rule #1
3270 There is a famous joke, it goes like this:
3272 @item Rule #1: The wife is always correct
3273 @item Rule #2: If you think otherwise, See Rule #1
3276 The TCL equal is this:
3279 @item Rule #1: Everything is a string
3280 @item Rule #2: If you think otherwise, See Rule #1
3283 As in the famous joke, the consequences of Rule #1 are profound. Once
3284 you understand Rule #1, you will understand TCL.
3286 @section TCL Rule #1b
3287 There is a second pair of rules.
3289 @item Rule #1: Control flow does not exist. Only commands
3290 @* For example: the classic FOR loop or IF statement is not a control
3291 flow item, they are commands, there is no such thing as control flow
3293 @item Rule #2: If you think otherwise, See Rule #1
3294 @* Actually what happens is this: There are commands that by
3295 convention, act like control flow key words in other languages. One of
3296 those commands is the word ``for'', another command is ``if''.
3299 @section Per Rule #1 - All Results are strings
3300 Every TCL command results in a string. The word ``result'' is used
3301 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
3302 Everything is a string}
3304 @section TCL Quoting Operators
3305 In life of a TCL script, there are two important periods of time, the
3306 difference is subtle.
3309 @item Evaluation Time
3312 The two key items here are how ``quoted things'' work in TCL. TCL has
3313 three primary quoting constructs, the [square-brackets] the
3314 @{curly-braces@} and ``double-quotes''
3316 By now you should know $VARIABLES always start with a $DOLLAR
3317 sign. BTW, to set a variable, you actually use the command ``set'', as
3318 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
3319 = 1'' statement, but without the equal sign.
3322 @item @b{[square-brackets]}
3323 @* @b{[square-brackets]} are command subsitution. It operates much
3324 like Unix Shell `back-ticks`. The result of a [square-bracket]
3325 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
3326 string}. These two statments are roughly identical.
3330 echo "The Date is: $X"
3333 puts "The Date is: $X"
3335 @item @b{``double-quoted-things''}
3336 @* @b{``double-quoted-things''} are just simply quoted
3337 text. $VARIABLES and [square-brackets] are expanded in place - the
3338 result however is exactly 1 string. @i{Remember Rule #1 - Everything
3342 puts "It is now \"[date]\", $x is in 1 hour"
3344 @item @b{@{Curly-Braces@}}
3345 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
3346 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
3347 'single-quote' operators in BASH shell scripts, with the added
3348 feature: @{curly-braces@} nest, single quotes can not. @{@{@{this is
3349 nested 3 times@}@}@} NOTE: [date] is perhaps a bad example, as of
3350 28/nov/2008, Jim/OpenOCD does not have a date command.
3353 @section Consequences of Rule 1/2/3/4
3355 The consequences of Rule 1 is profound.
3357 @subsection Tokenizing & Execution.
3359 Of course, whitespace, blank lines and #comment lines are handled in
3362 As a script is parsed, each (multi) line in the script file is
3363 tokenized and according to the quoting rules. After tokenizing, that
3364 line is immedatly executed.
3366 Multi line statements end with one or more ``still-open''
3367 @{curly-braces@} which - eventually - a few lines later closes.
3369 @subsection Command Execution
3371 Remember earlier: There is no such thing as ``control flow''
3372 statements in TCL. Instead there are COMMANDS that simpily act like
3373 control flow operators.
3375 Commands are executed like this:
3378 @item Parse the next line into (argc) and (argv[]).
3379 @item Look up (argv[0]) in a table and call its function.
3380 @item Repeat until End Of File.
3383 It sort of works like this:
3386 ReadAndParse( &argc, &argv );
3388 cmdPtr = LookupCommand( argv[0] );
3390 (*cmdPtr->Execute)( argc, argv );
3394 When the command ``proc'' is parsed (which creates a procedure
3395 function) it gets 3 parameters on the command line. @b{1} the name of
3396 the proc (function), @b{2} the list of parameters, and @b{3} the body
3397 of the function. Not the choice of words: LIST and BODY. The PROC
3398 command stores these items in a table somewhere so it can be found by
3401 @subsection The FOR Command
3403 The most interesting command to look at is the FOR command. In TCL,
3404 the FOR command is normally implimented in C. Remember, FOR is a
3405 command just like any other command.
3407 When the ascii text containing the FOR command is parsed, the parser
3408 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
3412 @item The ascii text 'for'
3413 @item The start text
3414 @item The test expression
3419 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
3420 Remember @i{Rule #1 - Everything is a string.} The key point is this:
3421 Often many of those parameters are in @{curly-braces@} - thus the
3422 variables inside are not expanded or replaced until later.
3424 Remember that every TCL command looks like the classic ``main( argc,
3425 argv )'' function in C. In JimTCL - they actually look like this:
3429 MyCommand( Jim_Interp *interp,
3431 Jim_Obj * const *argvs );
3434 Real TCL is nearly identical. Although the newer versions have
3435 introduced a byte-code parser and intepreter, but at the core, it
3436 still operates in the same basic way.
3438 @subsection FOR Command Implimentation
3440 To understand TCL it is perhaps most helpful to see the FOR
3441 command. Remember, it is a COMMAND not a control flow structure.
3443 In TCL there are two underying C helper functions.
3445 Remember Rule #1 - You are a string.
3447 The @b{first} helper parses and executes commands found in an ascii
3448 string. Commands can be seperated by semi-colons, or newlines. While
3449 parsing, variables are expanded per the quoting rules
3451 The @b{second} helper evaluates an ascii string as a numerical
3452 expression and returns a value.
3454 Here is an example of how the @b{FOR} command could be
3455 implimented. The pseudo code below does not show error handling.
3457 void Execute_AsciiString( void *interp, const char *string );
3459 int Evaluate_AsciiExpression( void *interp, const char *string );
3462 MyForCommand( void *interp,
3467 SetResult( interp, "WRONG number of parameters");
3471 // argv[0] = the ascii string just like C
3473 // Execute the start statement.
3474 Execute_AsciiString( interp, argv[1] );
3478 i = Evaluate_AsciiExpression(interp, argv[2]);
3483 Execute_AsciiString( interp, argv[3] );
3485 // Execute the LOOP part
3486 Execute_AsciiString( interp, argv[4] );
3490 SetResult( interp, "" );
3495 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
3496 in the same basic way.
3498 @section OpenOCD TCL Usage
3500 @subsection source and find commands
3501 @b{Where:} In many configuration files
3502 @* Example: @b{ source [find FILENAME] }
3503 @*Remember the parsing rules
3505 @item The FIND command is in square brackets.
3506 @* The FIND command is executed with the parameter FILENAME. It should
3507 find the full path to the named file. The RESULT is a string, which is
3508 subsituted on the orginal command line.
3509 @item The command source is executed with the resulting filename.
3510 @* SOURCE reads a file and executes as a script.
3512 @subsection format command
3513 @b{Where:} Generally occurs in numerous places.
3514 @* TCL no command like @b{printf()}, intead it has @b{format}, which is really more like
3520 puts [format "The answer: %d" [expr $x * $y]]
3523 @item The SET command creates 2 variables, X and Y.
3524 @item The double [nested] EXPR command performs math
3525 @* The EXPR command produces numerical result as a string.
3527 @item The format command is executed, producing a single string
3528 @* Refer to Rule #1.
3529 @item The PUTS command outputs the text.
3531 @subsection Body Or Inlined Text
3532 @b{Where:} Various TARGET scripts.
3535 proc someproc @{@} @{
3536 ... multiple lines of stuff ...
3538 $_TARGETNAME configure -event FOO someproc
3539 #2 Good - no variables
3540 $_TARGETNAME confgure -event foo "this ; that;"
3541 #3 Good Curly Braces
3542 $_TARGETNAME configure -event FOO @{
3545 #4 DANGER DANGER DANGER
3546 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
3549 @item The $_TARGETNAME is an OpenOCD variable convention.
3550 @*@b{$_TARGETNAME} represents the last target created, the value changes
3551 each time a new target is created. Remember the parsing rules. When
3552 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
3553 the name of the target which happens to be a TARGET (object)
3555 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
3556 @*There are 4 examples:
3558 @item The TCLBODY is a simple string that happens to be a proc name
3559 @item The TCLBODY is several simple commands semi-colon seperated
3560 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
3561 @item The TCLBODY is a string with variables that get expanded.
3564 In the end, when the target event FOO occurs the TCLBODY is
3565 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
3566 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
3568 Remember the parsing rules. In case #3, @{curly-braces@} mean the
3569 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
3570 and the text is evaluated. In case #4, they are replaced before the
3571 ``Target Object Command'' is executed. This occurs at the same time
3572 $_TARGETNAME is replaced. In case #4 the date will never
3573 change. @{BTW: [date] is perhaps a bad example, as of 28/nov/2008,
3574 Jim/OpenOCD does not have a date command@}
3576 @subsection Global Variables
3577 @b{Where:} You might discover this when writing your own procs @* In
3578 simple terms: Inside a PROC, if you need to access a global variable
3579 you must say so. Also see ``upvar''. Example:
3581 proc myproc @{ @} @{
3582 set y 0 #Local variable Y
3583 global x #Global variable X
3584 puts [format "X=%d, Y=%d" $x $y]
3587 @section Other Tcl Hacks
3588 @b{Dynamic Variable Creation}
3590 # Dynamically create a bunch of variables.
3591 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
3593 set vn [format "BIT%d" $x]
3597 set $vn [expr (1 << $x)]
3600 @b{Dynamic Proc/Command Creation}
3602 # One "X" function - 5 uart functions.
3603 foreach who @{A B C D E@}
3604 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
3608 @node Target library
3609 @chapter Target library
3610 @cindex Target library
3612 OpenOCD comes with a target configuration script library. These scripts can be
3613 used as-is or serve as a starting point.
3615 The target library is published together with the OpenOCD executable and
3616 the path to the target library is in the OpenOCD script search path.
3617 Similarly there are example scripts for configuring the JTAG interface.
3619 The command line below uses the example parport configuration scripts
3620 that ship with OpenOCD, then configures the str710.cfg target and
3621 finally issues the init and reset command. The communication speed
3622 is set to 10kHz for reset and 8MHz for post reset.
3626 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
3630 To list the target scripts available:
3633 $ ls /usr/local/lib/openocd/target
3635 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
3636 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
3637 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
3638 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
3646 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
3647 @comment case issue with ``Index.html'' and ``index.html''
3648 @comment Occurs when creating ``--html --no-split'' output
3649 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
3650 @unnumbered OpenOCD Index