1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
160 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 STMicroelectronics has an adapter called @b{ST-LINK}.
481 They only work with STMicroelectronics chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
491 @* This is available standalone and as part of some kits.
492 @* Link: @url{http://www.st.com/stlink-v3}
495 For info the original ST-LINK enumerates using the mass storage usb class; however,
496 its implementation is completely broken. The result is this causes issues under Linux.
497 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
499 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
500 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
503 @section USB TI/Stellaris ICDI based
504 Texas Instruments has an adapter called @b{ICDI}.
505 It is not to be confused with the FTDI based adapters that were originally fitted to their
506 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
508 @section USB CMSIS-DAP based
509 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
510 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
515 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
517 @item @b{USB - Presto}
518 @* Link: @url{http://tools.asix.net/prg_presto.htm}
520 @item @b{Versaloon-Link}
521 @* Link: @url{http://www.versaloon.com}
523 @item @b{ARM-JTAG-EW}
524 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
527 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
530 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
533 @* Link: @url{http://code.google.com/p/estick-jtag/}
535 @item @b{Keil ULINK v1}
536 @* Link: @url{http://www.keil.com/ulink1/}
538 @item @b{TI XDS110 Debug Probe}
539 @* The XDS110 is included as the embedded debug probe on many Texas Instruments
540 LaunchPad evaluation boards.
541 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
542 @* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
545 @section IBM PC Parallel Printer Port Based
547 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
548 and the Macraigor Wiggler. There are many clones and variations of
551 Note that parallel ports are becoming much less common, so if you
552 have the choice you should probably avoid these adapters in favor
557 @item @b{Wiggler} - There are many clones of this.
558 @* Link: @url{http://www.macraigor.com/wiggler.htm}
560 @item @b{DLC5} - From XILINX - There are many clones of this
561 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
562 produced, PDF schematics are easily found and it is easy to make.
564 @item @b{Amontec - JTAG Accelerator}
565 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
568 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
570 @item @b{Wiggler_ntrst_inverted}
571 @* Yet another variation - See the source code, src/jtag/parport.c
573 @item @b{old_amt_wiggler}
574 @* Unknown - probably not on the market today
577 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
580 @* Link: @url{http://www.amontec.com/chameleon.shtml}
586 @* ispDownload from Lattice Semiconductor
587 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
590 @* From STMicroelectronics;
591 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
599 @* An EP93xx based Linux machine using the GPIO pins directly.
602 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
604 @item @b{bcm2835gpio}
605 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
608 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
611 @* A JTAG driver acting as a client for the JTAG VPI server interface.
612 @* Link: @url{http://github.com/fjullien/jtag_vpi}
617 @chapter About Jim-Tcl
621 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
622 This programming language provides a simple and extensible
625 All commands presented in this Guide are extensions to Jim-Tcl.
626 You can use them as simple commands, without needing to learn
627 much of anything about Tcl.
628 Alternatively, you can write Tcl programs with them.
630 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
631 There is an active and responsive community, get on the mailing list
632 if you have any questions. Jim-Tcl maintainers also lurk on the
633 OpenOCD mailing list.
636 @item @b{Jim vs. Tcl}
637 @* Jim-Tcl is a stripped down version of the well known Tcl language,
638 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
639 fewer features. Jim-Tcl is several dozens of .C files and .H files and
640 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
641 4.2 MB .zip file containing 1540 files.
643 @item @b{Missing Features}
644 @* Our practice has been: Add/clone the real Tcl feature if/when
645 needed. We welcome Jim-Tcl improvements, not bloat. Also there
646 are a large number of optional Jim-Tcl features that are not
650 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
651 command interpreter today is a mixture of (newer)
652 Jim-Tcl commands, and the (older) original command interpreter.
655 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
656 can type a Tcl for() loop, set variables, etc.
657 Some of the commands documented in this guide are implemented
658 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
660 @item @b{Historical Note}
661 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
662 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
663 as a Git submodule, which greatly simplified upgrading Jim-Tcl
664 to benefit from new features and bugfixes in Jim-Tcl.
666 @item @b{Need a crash course in Tcl?}
667 @*@xref{Tcl Crash Course}.
672 @cindex command line options
674 @cindex directory search
676 Properly installing OpenOCD sets up your operating system to grant it access
677 to the debug adapters. On Linux, this usually involves installing a file
678 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
679 that works for many common adapters is shipped with OpenOCD in the
680 @file{contrib} directory. MS-Windows needs
681 complex and confusing driver configuration for every peripheral. Such issues
682 are unique to each operating system, and are not detailed in this User's Guide.
684 Then later you will invoke the OpenOCD server, with various options to
685 tell it how each debug session should work.
686 The @option{--help} option shows:
690 --help | -h display this help
691 --version | -v display OpenOCD version
692 --file | -f use configuration file <name>
693 --search | -s dir to search for config files and scripts
694 --debug | -d set debug level to 3
695 | -d<n> set debug level to <level>
696 --log_output | -l redirect log output to file <name>
697 --command | -c run <command>
700 If you don't give any @option{-f} or @option{-c} options,
701 OpenOCD tries to read the configuration file @file{openocd.cfg}.
702 To specify one or more different
703 configuration files, use @option{-f} options. For example:
706 openocd -f config1.cfg -f config2.cfg -f config3.cfg
709 Configuration files and scripts are searched for in
711 @item the current directory,
712 @item any search dir specified on the command line using the @option{-s} option,
713 @item any search dir specified using the @command{add_script_search_dir} command,
714 @item @file{$HOME/.openocd} (not on Windows),
715 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
716 @item the site wide script library @file{$pkgdatadir/site} and
717 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
719 The first found file with a matching file name will be used.
722 Don't try to use configuration script names or paths which
723 include the "#" character. That character begins Tcl comments.
726 @section Simple setup, no customization
728 In the best case, you can use two scripts from one of the script
729 libraries, hook up your JTAG adapter, and start the server ... and
730 your JTAG setup will just work "out of the box". Always try to
731 start by reusing those scripts, but assume you'll need more
732 customization even if this works. @xref{OpenOCD Project Setup}.
734 If you find a script for your JTAG adapter, and for your board or
735 target, you may be able to hook up your JTAG adapter then start
736 the server with some variation of one of the following:
739 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
740 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
743 You might also need to configure which reset signals are present,
744 using @option{-c 'reset_config trst_and_srst'} or something similar.
745 If all goes well you'll see output something like
748 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
749 For bug reports, read
750 http://openocd.org/doc/doxygen/bugs.html
751 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
752 (mfg: 0x23b, part: 0xba00, ver: 0x3)
755 Seeing that "tap/device found" message, and no warnings, means
756 the JTAG communication is working. That's a key milestone, but
757 you'll probably need more project-specific setup.
759 @section What OpenOCD does as it starts
761 OpenOCD starts by processing the configuration commands provided
762 on the command line or, if there were no @option{-c command} or
763 @option{-f file.cfg} options given, in @file{openocd.cfg}.
764 @xref{configurationstage,,Configuration Stage}.
765 At the end of the configuration stage it verifies the JTAG scan
766 chain defined using those commands; your configuration should
767 ensure that this always succeeds.
768 Normally, OpenOCD then starts running as a server.
769 Alternatively, commands may be used to terminate the configuration
770 stage early, perform work (such as updating some flash memory),
771 and then shut down without acting as a server.
773 Once OpenOCD starts running as a server, it waits for connections from
774 clients (Telnet, GDB, RPC) and processes the commands issued through
777 If you are having problems, you can enable internal debug messages via
778 the @option{-d} option.
780 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
781 @option{-c} command line switch.
783 To enable debug output (when reporting problems or working on OpenOCD
784 itself), use the @option{-d} command line switch. This sets the
785 @option{debug_level} to "3", outputting the most information,
786 including debug messages. The default setting is "2", outputting only
787 informational messages, warnings and errors. You can also change this
788 setting from within a telnet or gdb session using @command{debug_level<n>}
789 (@pxref{debuglevel,,debug_level}).
791 You can redirect all output from the server to a file using the
792 @option{-l <logfile>} switch.
794 Note! OpenOCD will launch the GDB & telnet server even if it can not
795 establish a connection with the target. In general, it is possible for
796 the JTAG controller to be unresponsive until the target is set up
797 correctly via e.g. GDB monitor commands in a GDB init script.
799 @node OpenOCD Project Setup
800 @chapter OpenOCD Project Setup
802 To use OpenOCD with your development projects, you need to do more than
803 just connect the JTAG adapter hardware (dongle) to your development board
804 and start the OpenOCD server.
805 You also need to configure your OpenOCD server so that it knows
806 about your adapter and board, and helps your work.
807 You may also want to connect OpenOCD to GDB, possibly
808 using Eclipse or some other GUI.
810 @section Hooking up the JTAG Adapter
812 Today's most common case is a dongle with a JTAG cable on one side
813 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
814 and a USB cable on the other.
815 Instead of USB, some cables use Ethernet;
816 older ones may use a PC parallel port, or even a serial port.
819 @item @emph{Start with power to your target board turned off},
820 and nothing connected to your JTAG adapter.
821 If you're particularly paranoid, unplug power to the board.
822 It's important to have the ground signal properly set up,
823 unless you are using a JTAG adapter which provides
824 galvanic isolation between the target board and the
827 @item @emph{Be sure it's the right kind of JTAG connector.}
828 If your dongle has a 20-pin ARM connector, you need some kind
829 of adapter (or octopus, see below) to hook it up to
830 boards using 14-pin or 10-pin connectors ... or to 20-pin
831 connectors which don't use ARM's pinout.
833 In the same vein, make sure the voltage levels are compatible.
834 Not all JTAG adapters have the level shifters needed to work
835 with 1.2 Volt boards.
837 @item @emph{Be certain the cable is properly oriented} or you might
838 damage your board. In most cases there are only two possible
839 ways to connect the cable.
840 Connect the JTAG cable from your adapter to the board.
841 Be sure it's firmly connected.
843 In the best case, the connector is keyed to physically
844 prevent you from inserting it wrong.
845 This is most often done using a slot on the board's male connector
846 housing, which must match a key on the JTAG cable's female connector.
847 If there's no housing, then you must look carefully and
848 make sure pin 1 on the cable hooks up to pin 1 on the board.
849 Ribbon cables are frequently all grey except for a wire on one
850 edge, which is red. The red wire is pin 1.
852 Sometimes dongles provide cables where one end is an ``octopus'' of
853 color coded single-wire connectors, instead of a connector block.
854 These are great when converting from one JTAG pinout to another,
855 but are tedious to set up.
856 Use these with connector pinout diagrams to help you match up the
857 adapter signals to the right board pins.
859 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
860 A USB, parallel, or serial port connector will go to the host which
861 you are using to run OpenOCD.
862 For Ethernet, consult the documentation and your network administrator.
864 For USB-based JTAG adapters you have an easy sanity check at this point:
865 does the host operating system see the JTAG adapter? If you're running
866 Linux, try the @command{lsusb} command. If that host is an
867 MS-Windows host, you'll need to install a driver before OpenOCD works.
869 @item @emph{Connect the adapter's power supply, if needed.}
870 This step is primarily for non-USB adapters,
871 but sometimes USB adapters need extra power.
873 @item @emph{Power up the target board.}
874 Unless you just let the magic smoke escape,
875 you're now ready to set up the OpenOCD server
876 so you can use JTAG to work with that board.
880 Talk with the OpenOCD server using
881 telnet (@code{telnet localhost 4444} on many systems) or GDB.
882 @xref{GDB and OpenOCD}.
884 @section Project Directory
886 There are many ways you can configure OpenOCD and start it up.
888 A simple way to organize them all involves keeping a
889 single directory for your work with a given board.
890 When you start OpenOCD from that directory,
891 it searches there first for configuration files, scripts,
892 files accessed through semihosting,
893 and for code you upload to the target board.
894 It is also the natural place to write files,
895 such as log files and data you download from the board.
897 @section Configuration Basics
899 There are two basic ways of configuring OpenOCD, and
900 a variety of ways you can mix them.
901 Think of the difference as just being how you start the server:
904 @item Many @option{-f file} or @option{-c command} options on the command line
905 @item No options, but a @dfn{user config file}
906 in the current directory named @file{openocd.cfg}
909 Here is an example @file{openocd.cfg} file for a setup
910 using a Signalyzer FT2232-based JTAG adapter to talk to
911 a board with an Atmel AT91SAM7X256 microcontroller:
914 source [find interface/ftdi/signalyzer.cfg]
916 # GDB can also flash my flash!
917 gdb_memory_map enable
918 gdb_flash_program enable
920 source [find target/sam7x256.cfg]
923 Here is the command line equivalent of that configuration:
926 openocd -f interface/ftdi/signalyzer.cfg \
927 -c "gdb_memory_map enable" \
928 -c "gdb_flash_program enable" \
929 -f target/sam7x256.cfg
932 You could wrap such long command lines in shell scripts,
933 each supporting a different development task.
934 One might re-flash the board with a specific firmware version.
935 Another might set up a particular debugging or run-time environment.
938 At this writing (October 2009) the command line method has
939 problems with how it treats variables.
940 For example, after @option{-c "set VAR value"}, or doing the
941 same in a script, the variable @var{VAR} will have no value
942 that can be tested in a later script.
945 Here we will focus on the simpler solution: one user config
946 file, including basic configuration plus any TCL procedures
947 to simplify your work.
949 @section User Config Files
950 @cindex config file, user
951 @cindex user config file
952 @cindex config file, overview
954 A user configuration file ties together all the parts of a project
956 One of the following will match your situation best:
959 @item Ideally almost everything comes from configuration files
960 provided by someone else.
961 For example, OpenOCD distributes a @file{scripts} directory
962 (probably in @file{/usr/share/openocd/scripts} on Linux).
963 Board and tool vendors can provide these too, as can individual
964 user sites; the @option{-s} command line option lets you say
965 where to find these files. (@xref{Running}.)
966 The AT91SAM7X256 example above works this way.
968 Three main types of non-user configuration file each have their
969 own subdirectory in the @file{scripts} directory:
972 @item @b{interface} -- one for each different debug adapter;
973 @item @b{board} -- one for each different board
974 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
977 Best case: include just two files, and they handle everything else.
978 The first is an interface config file.
979 The second is board-specific, and it sets up the JTAG TAPs and
980 their GDB targets (by deferring to some @file{target.cfg} file),
981 declares all flash memory, and leaves you nothing to do except
985 source [find interface/olimex-jtag-tiny.cfg]
986 source [find board/csb337.cfg]
989 Boards with a single microcontroller often won't need more
990 than the target config file, as in the AT91SAM7X256 example.
991 That's because there is no external memory (flash, DDR RAM), and
992 the board differences are encapsulated by application code.
994 @item Maybe you don't know yet what your board looks like to JTAG.
995 Once you know the @file{interface.cfg} file to use, you may
996 need help from OpenOCD to discover what's on the board.
997 Once you find the JTAG TAPs, you can just search for appropriate
999 configuration files ... or write your own, from the bottom up.
1000 @xref{autoprobing,,Autoprobing}.
1002 @item You can often reuse some standard config files but
1003 need to write a few new ones, probably a @file{board.cfg} file.
1004 You will be using commands described later in this User's Guide,
1005 and working with the guidelines in the next chapter.
1007 For example, there may be configuration files for your JTAG adapter
1008 and target chip, but you need a new board-specific config file
1009 giving access to your particular flash chips.
1010 Or you might need to write another target chip configuration file
1011 for a new chip built around the Cortex-M3 core.
1014 When you write new configuration files, please submit
1015 them for inclusion in the next OpenOCD release.
1016 For example, a @file{board/newboard.cfg} file will help the
1017 next users of that board, and a @file{target/newcpu.cfg}
1018 will help support users of any board using that chip.
1022 You may may need to write some C code.
1023 It may be as simple as supporting a new FT2232 or parport
1024 based adapter; a bit more involved, like a NAND or NOR flash
1025 controller driver; or a big piece of work like supporting
1026 a new chip architecture.
1029 Reuse the existing config files when you can.
1030 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1031 You may find a board configuration that's a good example to follow.
1033 When you write config files, separate the reusable parts
1034 (things every user of that interface, chip, or board needs)
1035 from ones specific to your environment and debugging approach.
1039 For example, a @code{gdb-attach} event handler that invokes
1040 the @command{reset init} command will interfere with debugging
1041 early boot code, which performs some of the same actions
1042 that the @code{reset-init} event handler does.
1045 Likewise, the @command{arm9 vector_catch} command (or
1046 @cindex vector_catch
1047 its siblings @command{xscale vector_catch}
1048 and @command{cortex_m vector_catch}) can be a time-saver
1049 during some debug sessions, but don't make everyone use that either.
1050 Keep those kinds of debugging aids in your user config file,
1051 along with messaging and tracing setup.
1052 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1055 You might need to override some defaults.
1056 For example, you might need to move, shrink, or back up the target's
1057 work area if your application needs much SRAM.
1060 TCP/IP port configuration is another example of something which
1061 is environment-specific, and should only appear in
1062 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1065 @section Project-Specific Utilities
1067 A few project-specific utility
1068 routines may well speed up your work.
1069 Write them, and keep them in your project's user config file.
1071 For example, if you are making a boot loader work on a
1072 board, it's nice to be able to debug the ``after it's
1073 loaded to RAM'' parts separately from the finicky early
1074 code which sets up the DDR RAM controller and clocks.
1075 A script like this one, or a more GDB-aware sibling,
1079 proc ramboot @{ @} @{
1080 # Reset, running the target's "reset-init" scripts
1081 # to initialize clocks and the DDR RAM controller.
1082 # Leave the CPU halted.
1085 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1086 load_image u-boot.bin 0x20000000
1093 Then once that code is working you will need to make it
1094 boot from NOR flash; a different utility would help.
1095 Alternatively, some developers write to flash using GDB.
1096 (You might use a similar script if you're working with a flash
1097 based microcontroller application instead of a boot loader.)
1100 proc newboot @{ @} @{
1101 # Reset, leaving the CPU halted. The "reset-init" event
1102 # proc gives faster access to the CPU and to NOR flash;
1103 # "reset halt" would be slower.
1106 # Write standard version of U-Boot into the first two
1107 # sectors of NOR flash ... the standard version should
1108 # do the same lowlevel init as "reset-init".
1109 flash protect 0 0 1 off
1110 flash erase_sector 0 0 1
1111 flash write_bank 0 u-boot.bin 0x0
1112 flash protect 0 0 1 on
1114 # Reboot from scratch using that new boot loader.
1119 You may need more complicated utility procedures when booting
1121 That often involves an extra bootloader stage,
1122 running from on-chip SRAM to perform DDR RAM setup so it can load
1123 the main bootloader code (which won't fit into that SRAM).
1125 Other helper scripts might be used to write production system images,
1126 involving considerably more than just a three stage bootloader.
1128 @section Target Software Changes
1130 Sometimes you may want to make some small changes to the software
1131 you're developing, to help make JTAG debugging work better.
1132 For example, in C or assembly language code you might
1133 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1134 handling issues like:
1138 @item @b{Watchdog Timers}...
1139 Watchdog timers are typically used to automatically reset systems if
1140 some application task doesn't periodically reset the timer. (The
1141 assumption is that the system has locked up if the task can't run.)
1142 When a JTAG debugger halts the system, that task won't be able to run
1143 and reset the timer ... potentially causing resets in the middle of
1144 your debug sessions.
1146 It's rarely a good idea to disable such watchdogs, since their usage
1147 needs to be debugged just like all other parts of your firmware.
1148 That might however be your only option.
1150 Look instead for chip-specific ways to stop the watchdog from counting
1151 while the system is in a debug halt state. It may be simplest to set
1152 that non-counting mode in your debugger startup scripts. You may however
1153 need a different approach when, for example, a motor could be physically
1154 damaged by firmware remaining inactive in a debug halt state. That might
1155 involve a type of firmware mode where that "non-counting" mode is disabled
1156 at the beginning then re-enabled at the end; a watchdog reset might fire
1157 and complicate the debug session, but hardware (or people) would be
1158 protected.@footnote{Note that many systems support a "monitor mode" debug
1159 that is a somewhat cleaner way to address such issues. You can think of
1160 it as only halting part of the system, maybe just one task,
1161 instead of the whole thing.
1162 At this writing, January 2010, OpenOCD based debugging does not support
1163 monitor mode debug, only "halt mode" debug.}
1165 @item @b{ARM Semihosting}...
1166 @cindex ARM semihosting
1167 When linked with a special runtime library provided with many
1168 toolchains@footnote{See chapter 8 "Semihosting" in
1169 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1170 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1171 The CodeSourcery EABI toolchain also includes a semihosting library.},
1172 your target code can use I/O facilities on the debug host. That library
1173 provides a small set of system calls which are handled by OpenOCD.
1174 It can let the debugger provide your system console and a file system,
1175 helping with early debugging or providing a more capable environment
1176 for sometimes-complex tasks like installing system firmware onto
1179 @item @b{ARM Wait-For-Interrupt}...
1180 Many ARM chips synchronize the JTAG clock using the core clock.
1181 Low power states which stop that core clock thus prevent JTAG access.
1182 Idle loops in tasking environments often enter those low power states
1183 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1185 You may want to @emph{disable that instruction} in source code,
1186 or otherwise prevent using that state,
1187 to ensure you can get JTAG access at any time.@footnote{As a more
1188 polite alternative, some processors have special debug-oriented
1189 registers which can be used to change various features including
1190 how the low power states are clocked while debugging.
1191 The STM32 DBGMCU_CR register is an example; at the cost of extra
1192 power consumption, JTAG can be used during low power states.}
1193 For example, the OpenOCD @command{halt} command may not
1194 work for an idle processor otherwise.
1196 @item @b{Delay after reset}...
1197 Not all chips have good support for debugger access
1198 right after reset; many LPC2xxx chips have issues here.
1199 Similarly, applications that reconfigure pins used for
1200 JTAG access as they start will also block debugger access.
1202 To work with boards like this, @emph{enable a short delay loop}
1203 the first thing after reset, before "real" startup activities.
1204 For example, one second's delay is usually more than enough
1205 time for a JTAG debugger to attach, so that
1206 early code execution can be debugged
1207 or firmware can be replaced.
1209 @item @b{Debug Communications Channel (DCC)}...
1210 Some processors include mechanisms to send messages over JTAG.
1211 Many ARM cores support these, as do some cores from other vendors.
1212 (OpenOCD may be able to use this DCC internally, speeding up some
1213 operations like writing to memory.)
1215 Your application may want to deliver various debugging messages
1216 over JTAG, by @emph{linking with a small library of code}
1217 provided with OpenOCD and using the utilities there to send
1218 various kinds of message.
1219 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1223 @section Target Hardware Setup
1225 Chip vendors often provide software development boards which
1226 are highly configurable, so that they can support all options
1227 that product boards may require. @emph{Make sure that any
1228 jumpers or switches match the system configuration you are
1231 Common issues include:
1235 @item @b{JTAG setup} ...
1236 Boards may support more than one JTAG configuration.
1237 Examples include jumpers controlling pullups versus pulldowns
1238 on the nTRST and/or nSRST signals, and choice of connectors
1239 (e.g. which of two headers on the base board,
1240 or one from a daughtercard).
1241 For some Texas Instruments boards, you may need to jumper the
1242 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1244 @item @b{Boot Modes} ...
1245 Complex chips often support multiple boot modes, controlled
1246 by external jumpers. Make sure this is set up correctly.
1247 For example many i.MX boards from NXP need to be jumpered
1248 to "ATX mode" to start booting using the on-chip ROM, when
1249 using second stage bootloader code stored in a NAND flash chip.
1251 Such explicit configuration is common, and not limited to
1252 booting from NAND. You might also need to set jumpers to
1253 start booting using code loaded from an MMC/SD card; external
1254 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1255 flash; some external host; or various other sources.
1258 @item @b{Memory Addressing} ...
1259 Boards which support multiple boot modes may also have jumpers
1260 to configure memory addressing. One board, for example, jumpers
1261 external chipselect 0 (used for booting) to address either
1262 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1263 or NAND flash. When it's jumpered to address NAND flash, that
1264 board must also be told to start booting from on-chip ROM.
1266 Your @file{board.cfg} file may also need to be told this jumper
1267 configuration, so that it can know whether to declare NOR flash
1268 using @command{flash bank} or instead declare NAND flash with
1269 @command{nand device}; and likewise which probe to perform in
1270 its @code{reset-init} handler.
1272 A closely related issue is bus width. Jumpers might need to
1273 distinguish between 8 bit or 16 bit bus access for the flash
1274 used to start booting.
1276 @item @b{Peripheral Access} ...
1277 Development boards generally provide access to every peripheral
1278 on the chip, sometimes in multiple modes (such as by providing
1279 multiple audio codec chips).
1280 This interacts with software
1281 configuration of pin multiplexing, where for example a
1282 given pin may be routed either to the MMC/SD controller
1283 or the GPIO controller. It also often interacts with
1284 configuration jumpers. One jumper may be used to route
1285 signals to an MMC/SD card slot or an expansion bus (which
1286 might in turn affect booting); others might control which
1287 audio or video codecs are used.
1291 Plus you should of course have @code{reset-init} event handlers
1292 which set up the hardware to match that jumper configuration.
1293 That includes in particular any oscillator or PLL used to clock
1294 the CPU, and any memory controllers needed to access external
1295 memory and peripherals. Without such handlers, you won't be
1296 able to access those resources without working target firmware
1297 which can do that setup ... this can be awkward when you're
1298 trying to debug that target firmware. Even if there's a ROM
1299 bootloader which handles a few issues, it rarely provides full
1300 access to all board-specific capabilities.
1303 @node Config File Guidelines
1304 @chapter Config File Guidelines
1306 This chapter is aimed at any user who needs to write a config file,
1307 including developers and integrators of OpenOCD and any user who
1308 needs to get a new board working smoothly.
1309 It provides guidelines for creating those files.
1311 You should find the following directories under
1312 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1313 them as-is where you can; or as models for new files.
1315 @item @file{interface} ...
1316 These are for debug adapters. Files that specify configuration to use
1317 specific JTAG, SWD and other adapters go here.
1318 @item @file{board} ...
1319 Think Circuit Board, PWA, PCB, they go by many names. Board files
1320 contain initialization items that are specific to a board.
1322 They reuse target configuration files, since the same
1323 microprocessor chips are used on many boards,
1324 but support for external parts varies widely. For
1325 example, the SDRAM initialization sequence for the board, or the type
1326 of external flash and what address it uses. Any initialization
1327 sequence to enable that external flash or SDRAM should be found in the
1328 board file. Boards may also contain multiple targets: two CPUs; or
1330 @item @file{target} ...
1331 Think chip. The ``target'' directory represents the JTAG TAPs
1333 which OpenOCD should control, not a board. Two common types of targets
1334 are ARM chips and FPGA or CPLD chips.
1335 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1336 the target config file defines all of them.
1337 @item @emph{more} ... browse for other library files which may be useful.
1338 For example, there are various generic and CPU-specific utilities.
1341 The @file{openocd.cfg} user config
1342 file may override features in any of the above files by
1343 setting variables before sourcing the target file, or by adding
1344 commands specific to their situation.
1346 @section Interface Config Files
1348 The user config file
1349 should be able to source one of these files with a command like this:
1352 source [find interface/FOOBAR.cfg]
1355 A preconfigured interface file should exist for every debug adapter
1356 in use today with OpenOCD.
1357 That said, perhaps some of these config files
1358 have only been used by the developer who created it.
1360 A separate chapter gives information about how to set these up.
1361 @xref{Debug Adapter Configuration}.
1362 Read the OpenOCD source code (and Developer's Guide)
1363 if you have a new kind of hardware interface
1364 and need to provide a driver for it.
1366 @section Board Config Files
1367 @cindex config file, board
1368 @cindex board config file
1370 The user config file
1371 should be able to source one of these files with a command like this:
1374 source [find board/FOOBAR.cfg]
1377 The point of a board config file is to package everything
1378 about a given board that user config files need to know.
1379 In summary the board files should contain (if present)
1382 @item One or more @command{source [find target/...cfg]} statements
1383 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1384 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1385 @item Target @code{reset} handlers for SDRAM and I/O configuration
1386 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1387 @item All things that are not ``inside a chip''
1390 Generic things inside target chips belong in target config files,
1391 not board config files. So for example a @code{reset-init} event
1392 handler should know board-specific oscillator and PLL parameters,
1393 which it passes to target-specific utility code.
1395 The most complex task of a board config file is creating such a
1396 @code{reset-init} event handler.
1397 Define those handlers last, after you verify the rest of the board
1398 configuration works.
1400 @subsection Communication Between Config files
1402 In addition to target-specific utility code, another way that
1403 board and target config files communicate is by following a
1404 convention on how to use certain variables.
1406 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1407 Thus the rule we follow in OpenOCD is this: Variables that begin with
1408 a leading underscore are temporary in nature, and can be modified and
1409 used at will within a target configuration file.
1411 Complex board config files can do the things like this,
1412 for a board with three chips:
1415 # Chip #1: PXA270 for network side, big endian
1416 set CHIPNAME network
1418 source [find target/pxa270.cfg]
1419 # on return: _TARGETNAME = network.cpu
1420 # other commands can refer to the "network.cpu" target.
1421 $_TARGETNAME configure .... events for this CPU..
1423 # Chip #2: PXA270 for video side, little endian
1426 source [find target/pxa270.cfg]
1427 # on return: _TARGETNAME = video.cpu
1428 # other commands can refer to the "video.cpu" target.
1429 $_TARGETNAME configure .... events for this CPU..
1431 # Chip #3: Xilinx FPGA for glue logic
1434 source [find target/spartan3.cfg]
1437 That example is oversimplified because it doesn't show any flash memory,
1438 or the @code{reset-init} event handlers to initialize external DRAM
1439 or (assuming it needs it) load a configuration into the FPGA.
1440 Such features are usually needed for low-level work with many boards,
1441 where ``low level'' implies that the board initialization software may
1442 not be working. (That's a common reason to need JTAG tools. Another
1443 is to enable working with microcontroller-based systems, which often
1444 have no debugging support except a JTAG connector.)
1446 Target config files may also export utility functions to board and user
1447 config files. Such functions should use name prefixes, to help avoid
1450 Board files could also accept input variables from user config files.
1451 For example, there might be a @code{J4_JUMPER} setting used to identify
1452 what kind of flash memory a development board is using, or how to set
1453 up other clocks and peripherals.
1455 @subsection Variable Naming Convention
1456 @cindex variable names
1458 Most boards have only one instance of a chip.
1459 However, it should be easy to create a board with more than
1460 one such chip (as shown above).
1461 Accordingly, we encourage these conventions for naming
1462 variables associated with different @file{target.cfg} files,
1463 to promote consistency and
1464 so that board files can override target defaults.
1466 Inputs to target config files include:
1469 @item @code{CHIPNAME} ...
1470 This gives a name to the overall chip, and is used as part of
1471 tap identifier dotted names.
1472 While the default is normally provided by the chip manufacturer,
1473 board files may need to distinguish between instances of a chip.
1474 @item @code{ENDIAN} ...
1475 By default @option{little} - although chips may hard-wire @option{big}.
1476 Chips that can't change endianess don't need to use this variable.
1477 @item @code{CPUTAPID} ...
1478 When OpenOCD examines the JTAG chain, it can be told verify the
1479 chips against the JTAG IDCODE register.
1480 The target file will hold one or more defaults, but sometimes the
1481 chip in a board will use a different ID (perhaps a newer revision).
1484 Outputs from target config files include:
1487 @item @code{_TARGETNAME} ...
1488 By convention, this variable is created by the target configuration
1489 script. The board configuration file may make use of this variable to
1490 configure things like a ``reset init'' script, or other things
1491 specific to that board and that target.
1492 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1493 @code{_TARGETNAME1}, ... etc.
1496 @subsection The reset-init Event Handler
1497 @cindex event, reset-init
1498 @cindex reset-init handler
1500 Board config files run in the OpenOCD configuration stage;
1501 they can't use TAPs or targets, since they haven't been
1503 This means you can't write memory or access chip registers;
1504 you can't even verify that a flash chip is present.
1505 That's done later in event handlers, of which the target @code{reset-init}
1506 handler is one of the most important.
1508 Except on microcontrollers, the basic job of @code{reset-init} event
1509 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1510 Microcontrollers rarely use boot loaders; they run right out of their
1511 on-chip flash and SRAM memory. But they may want to use one of these
1512 handlers too, if just for developer convenience.
1515 Because this is so very board-specific, and chip-specific, no examples
1517 Instead, look at the board config files distributed with OpenOCD.
1518 If you have a boot loader, its source code will help; so will
1519 configuration files for other JTAG tools
1520 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1523 Some of this code could probably be shared between different boards.
1524 For example, setting up a DRAM controller often doesn't differ by
1525 much except the bus width (16 bits or 32?) and memory timings, so a
1526 reusable TCL procedure loaded by the @file{target.cfg} file might take
1527 those as parameters.
1528 Similarly with oscillator, PLL, and clock setup;
1529 and disabling the watchdog.
1530 Structure the code cleanly, and provide comments to help
1531 the next developer doing such work.
1532 (@emph{You might be that next person} trying to reuse init code!)
1534 The last thing normally done in a @code{reset-init} handler is probing
1535 whatever flash memory was configured. For most chips that needs to be
1536 done while the associated target is halted, either because JTAG memory
1537 access uses the CPU or to prevent conflicting CPU access.
1539 @subsection JTAG Clock Rate
1541 Before your @code{reset-init} handler has set up
1542 the PLLs and clocking, you may need to run with
1543 a low JTAG clock rate.
1544 @xref{jtagspeed,,JTAG Speed}.
1545 Then you'd increase that rate after your handler has
1546 made it possible to use the faster JTAG clock.
1547 When the initial low speed is board-specific, for example
1548 because it depends on a board-specific oscillator speed, then
1549 you should probably set it up in the board config file;
1550 if it's target-specific, it belongs in the target config file.
1552 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1553 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1554 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1555 Consult chip documentation to determine the peak JTAG clock rate,
1556 which might be less than that.
1559 On most ARMs, JTAG clock detection is coupled to the core clock, so
1560 software using a @option{wait for interrupt} operation blocks JTAG access.
1561 Adaptive clocking provides a partial workaround, but a more complete
1562 solution just avoids using that instruction with JTAG debuggers.
1565 If both the chip and the board support adaptive clocking,
1566 use the @command{jtag_rclk}
1567 command, in case your board is used with JTAG adapter which
1568 also supports it. Otherwise use @command{adapter_khz}.
1569 Set the slow rate at the beginning of the reset sequence,
1570 and the faster rate as soon as the clocks are at full speed.
1572 @anchor{theinitboardprocedure}
1573 @subsection The init_board procedure
1574 @cindex init_board procedure
1576 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1577 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1578 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1579 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1580 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1581 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1582 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1583 Additionally ``linear'' board config file will most likely fail when target config file uses
1584 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1585 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1586 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1587 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1589 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1590 the original), allowing greater code reuse.
1593 ### board_file.cfg ###
1595 # source target file that does most of the config in init_targets
1596 source [find target/target.cfg]
1598 proc enable_fast_clock @{@} @{
1599 # enables fast on-board clock source
1600 # configures the chip to use it
1603 # initialize only board specifics - reset, clock, adapter frequency
1604 proc init_board @{@} @{
1605 reset_config trst_and_srst trst_pulls_srst
1607 $_TARGETNAME configure -event reset-start @{
1611 $_TARGETNAME configure -event reset-init @{
1618 @section Target Config Files
1619 @cindex config file, target
1620 @cindex target config file
1622 Board config files communicate with target config files using
1623 naming conventions as described above, and may source one or
1624 more target config files like this:
1627 source [find target/FOOBAR.cfg]
1630 The point of a target config file is to package everything
1631 about a given chip that board config files need to know.
1632 In summary the target files should contain
1636 @item Add TAPs to the scan chain
1637 @item Add CPU targets (includes GDB support)
1638 @item CPU/Chip/CPU-Core specific features
1642 As a rule of thumb, a target file sets up only one chip.
1643 For a microcontroller, that will often include a single TAP,
1644 which is a CPU needing a GDB target, and its on-chip flash.
1646 More complex chips may include multiple TAPs, and the target
1647 config file may need to define them all before OpenOCD
1648 can talk to the chip.
1649 For example, some phone chips have JTAG scan chains that include
1650 an ARM core for operating system use, a DSP,
1651 another ARM core embedded in an image processing engine,
1652 and other processing engines.
1654 @subsection Default Value Boiler Plate Code
1656 All target configuration files should start with code like this,
1657 letting board config files express environment-specific
1658 differences in how things should be set up.
1661 # Boards may override chip names, perhaps based on role,
1662 # but the default should match what the vendor uses
1663 if @{ [info exists CHIPNAME] @} @{
1664 set _CHIPNAME $CHIPNAME
1666 set _CHIPNAME sam7x256
1669 # ONLY use ENDIAN with targets that can change it.
1670 if @{ [info exists ENDIAN] @} @{
1676 # TAP identifiers may change as chips mature, for example with
1677 # new revision fields (the "3" here). Pick a good default; you
1678 # can pass several such identifiers to the "jtag newtap" command.
1679 if @{ [info exists CPUTAPID ] @} @{
1680 set _CPUTAPID $CPUTAPID
1682 set _CPUTAPID 0x3f0f0f0f
1685 @c but 0x3f0f0f0f is for an str73x part ...
1687 @emph{Remember:} Board config files may include multiple target
1688 config files, or the same target file multiple times
1689 (changing at least @code{CHIPNAME}).
1691 Likewise, the target configuration file should define
1692 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1693 use it later on when defining debug targets:
1696 set _TARGETNAME $_CHIPNAME.cpu
1697 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1700 @subsection Adding TAPs to the Scan Chain
1701 After the ``defaults'' are set up,
1702 add the TAPs on each chip to the JTAG scan chain.
1703 @xref{TAP Declaration}, and the naming convention
1706 In the simplest case the chip has only one TAP,
1707 probably for a CPU or FPGA.
1708 The config file for the Atmel AT91SAM7X256
1709 looks (in part) like this:
1712 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1715 A board with two such at91sam7 chips would be able
1716 to source such a config file twice, with different
1717 values for @code{CHIPNAME}, so
1718 it adds a different TAP each time.
1720 If there are nonzero @option{-expected-id} values,
1721 OpenOCD attempts to verify the actual tap id against those values.
1722 It will issue error messages if there is mismatch, which
1723 can help to pinpoint problems in OpenOCD configurations.
1726 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1727 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1728 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1729 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1730 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1733 There are more complex examples too, with chips that have
1734 multiple TAPs. Ones worth looking at include:
1737 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1738 plus a JRC to enable them
1739 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1740 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1741 is not currently used)
1744 @subsection Add CPU targets
1746 After adding a TAP for a CPU, you should set it up so that
1747 GDB and other commands can use it.
1748 @xref{CPU Configuration}.
1749 For the at91sam7 example above, the command can look like this;
1750 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1751 to little endian, and this chip doesn't support changing that.
1754 set _TARGETNAME $_CHIPNAME.cpu
1755 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1758 Work areas are small RAM areas associated with CPU targets.
1759 They are used by OpenOCD to speed up downloads,
1760 and to download small snippets of code to program flash chips.
1761 If the chip includes a form of ``on-chip-ram'' - and many do - define
1762 a work area if you can.
1763 Again using the at91sam7 as an example, this can look like:
1766 $_TARGETNAME configure -work-area-phys 0x00200000 \
1767 -work-area-size 0x4000 -work-area-backup 0
1770 @anchor{definecputargetsworkinginsmp}
1771 @subsection Define CPU targets working in SMP
1773 After setting targets, you can define a list of targets working in SMP.
1776 set _TARGETNAME_1 $_CHIPNAME.cpu1
1777 set _TARGETNAME_2 $_CHIPNAME.cpu2
1778 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1779 -coreid 0 -dbgbase $_DAP_DBG1
1780 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1781 -coreid 1 -dbgbase $_DAP_DBG2
1782 #define 2 targets working in smp.
1783 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1785 In the above example on cortex_a, 2 cpus are working in SMP.
1786 In SMP only one GDB instance is created and :
1788 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1789 @item halt command triggers the halt of all targets in the list.
1790 @item resume command triggers the write context and the restart of all targets in the list.
1791 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1792 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1793 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1796 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1797 command have been implemented.
1799 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1800 @item cortex_a smp_off : disable SMP mode, the current target is the one
1801 displayed in the GDB session, only this target is now controlled by GDB
1802 session. This behaviour is useful during system boot up.
1803 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1810 #0 : coreid 0 is displayed to GDB ,
1811 #-> -1 : next resume triggers a real resume
1812 > cortex_a smp_gdb 1
1814 #0 :coreid 0 is displayed to GDB ,
1815 #->1 : next resume displays coreid 1 to GDB
1819 #1 :coreid 1 is displayed to GDB ,
1820 #->1 : next resume displays coreid 1 to GDB
1821 > cortex_a smp_gdb -1
1823 #1 :coreid 1 is displayed to GDB,
1824 #->-1 : next resume triggers a real resume
1828 @subsection Chip Reset Setup
1830 As a rule, you should put the @command{reset_config} command
1831 into the board file. Most things you think you know about a
1832 chip can be tweaked by the board.
1834 Some chips have specific ways the TRST and SRST signals are
1835 managed. In the unusual case that these are @emph{chip specific}
1836 and can never be changed by board wiring, they could go here.
1837 For example, some chips can't support JTAG debugging without
1840 Provide a @code{reset-assert} event handler if you can.
1841 Such a handler uses JTAG operations to reset the target,
1842 letting this target config be used in systems which don't
1843 provide the optional SRST signal, or on systems where you
1844 don't want to reset all targets at once.
1845 Such a handler might write to chip registers to force a reset,
1846 use a JRC to do that (preferable -- the target may be wedged!),
1847 or force a watchdog timer to trigger.
1848 (For Cortex-M targets, this is not necessary. The target
1849 driver knows how to use trigger an NVIC reset when SRST is
1852 Some chips need special attention during reset handling if
1853 they're going to be used with JTAG.
1854 An example might be needing to send some commands right
1855 after the target's TAP has been reset, providing a
1856 @code{reset-deassert-post} event handler that writes a chip
1857 register to report that JTAG debugging is being done.
1858 Another would be reconfiguring the watchdog so that it stops
1859 counting while the core is halted in the debugger.
1861 JTAG clocking constraints often change during reset, and in
1862 some cases target config files (rather than board config files)
1863 are the right places to handle some of those issues.
1864 For example, immediately after reset most chips run using a
1865 slower clock than they will use later.
1866 That means that after reset (and potentially, as OpenOCD
1867 first starts up) they must use a slower JTAG clock rate
1868 than they will use later.
1869 @xref{jtagspeed,,JTAG Speed}.
1871 @quotation Important
1872 When you are debugging code that runs right after chip
1873 reset, getting these issues right is critical.
1874 In particular, if you see intermittent failures when
1875 OpenOCD verifies the scan chain after reset,
1876 look at how you are setting up JTAG clocking.
1879 @anchor{theinittargetsprocedure}
1880 @subsection The init_targets procedure
1881 @cindex init_targets procedure
1883 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1884 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1885 procedure called @code{init_targets}, which will be executed when entering run stage
1886 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1887 Such procedure can be overridden by ``next level'' script (which sources the original).
1888 This concept facilitates code reuse when basic target config files provide generic configuration
1889 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1890 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1891 because sourcing them executes every initialization commands they provide.
1894 ### generic_file.cfg ###
1896 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1897 # basic initialization procedure ...
1900 proc init_targets @{@} @{
1901 # initializes generic chip with 4kB of flash and 1kB of RAM
1902 setup_my_chip MY_GENERIC_CHIP 4096 1024
1905 ### specific_file.cfg ###
1907 source [find target/generic_file.cfg]
1909 proc init_targets @{@} @{
1910 # initializes specific chip with 128kB of flash and 64kB of RAM
1911 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1915 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1916 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1918 For an example of this scheme see LPC2000 target config files.
1920 The @code{init_boards} procedure is a similar concept concerning board config files
1921 (@xref{theinitboardprocedure,,The init_board procedure}.)
1923 @anchor{theinittargeteventsprocedure}
1924 @subsection The init_target_events procedure
1925 @cindex init_target_events procedure
1927 A special procedure called @code{init_target_events} is run just after
1928 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1929 procedure}.) and before @code{init_board}
1930 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1931 to set up default target events for the targets that do not have those
1932 events already assigned.
1934 @subsection ARM Core Specific Hacks
1936 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1937 special high speed download features - enable it.
1939 If present, the MMU, the MPU and the CACHE should be disabled.
1941 Some ARM cores are equipped with trace support, which permits
1942 examination of the instruction and data bus activity. Trace
1943 activity is controlled through an ``Embedded Trace Module'' (ETM)
1944 on one of the core's scan chains. The ETM emits voluminous data
1945 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1946 If you are using an external trace port,
1947 configure it in your board config file.
1948 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1949 configure it in your target config file.
1952 etm config $_TARGETNAME 16 normal full etb
1953 etb config $_TARGETNAME $_CHIPNAME.etb
1956 @subsection Internal Flash Configuration
1958 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1960 @b{Never ever} in the ``target configuration file'' define any type of
1961 flash that is external to the chip. (For example a BOOT flash on
1962 Chip Select 0.) Such flash information goes in a board file - not
1963 the TARGET (chip) file.
1967 @item at91sam7x256 - has 256K flash YES enable it.
1968 @item str912 - has flash internal YES enable it.
1969 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1970 @item pxa270 - again - CS0 flash - it goes in the board file.
1973 @anchor{translatingconfigurationfiles}
1974 @section Translating Configuration Files
1976 If you have a configuration file for another hardware debugger
1977 or toolset (Abatron, BDI2000, BDI3000, CCS,
1978 Lauterbach, SEGGER, Macraigor, etc.), translating
1979 it into OpenOCD syntax is often quite straightforward. The most tricky
1980 part of creating a configuration script is oftentimes the reset init
1981 sequence where e.g. PLLs, DRAM and the like is set up.
1983 One trick that you can use when translating is to write small
1984 Tcl procedures to translate the syntax into OpenOCD syntax. This
1985 can avoid manual translation errors and make it easier to
1986 convert other scripts later on.
1988 Example of transforming quirky arguments to a simple search and
1992 # Lauterbach syntax(?)
1994 # Data.Set c15:0x042f %long 0x40000015
1996 # OpenOCD syntax when using procedure below.
1998 # setc15 0x01 0x00050078
2000 proc setc15 @{regs value@} @{
2003 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2005 arm mcr 15 [expr ($regs>>12)&0x7] \
2006 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
2007 [expr ($regs>>8)&0x7] $value
2013 @node Server Configuration
2014 @chapter Server Configuration
2015 @cindex initialization
2016 The commands here are commonly found in the openocd.cfg file and are
2017 used to specify what TCP/IP ports are used, and how GDB should be
2020 @anchor{configurationstage}
2021 @section Configuration Stage
2022 @cindex configuration stage
2023 @cindex config command
2025 When the OpenOCD server process starts up, it enters a
2026 @emph{configuration stage} which is the only time that
2027 certain commands, @emph{configuration commands}, may be issued.
2028 Normally, configuration commands are only available
2029 inside startup scripts.
2031 In this manual, the definition of a configuration command is
2032 presented as a @emph{Config Command}, not as a @emph{Command}
2033 which may be issued interactively.
2034 The runtime @command{help} command also highlights configuration
2035 commands, and those which may be issued at any time.
2037 Those configuration commands include declaration of TAPs,
2039 the interface used for JTAG communication,
2040 and other basic setup.
2041 The server must leave the configuration stage before it
2042 may access or activate TAPs.
2043 After it leaves this stage, configuration commands may no
2046 @anchor{enteringtherunstage}
2047 @section Entering the Run Stage
2049 The first thing OpenOCD does after leaving the configuration
2050 stage is to verify that it can talk to the scan chain
2051 (list of TAPs) which has been configured.
2052 It will warn if it doesn't find TAPs it expects to find,
2053 or finds TAPs that aren't supposed to be there.
2054 You should see no errors at this point.
2055 If you see errors, resolve them by correcting the
2056 commands you used to configure the server.
2057 Common errors include using an initial JTAG speed that's too
2058 fast, and not providing the right IDCODE values for the TAPs
2061 Once OpenOCD has entered the run stage, a number of commands
2063 A number of these relate to the debug targets you may have declared.
2064 For example, the @command{mww} command will not be available until
2065 a target has been successfully instantiated.
2066 If you want to use those commands, you may need to force
2067 entry to the run stage.
2069 @deffn {Config Command} init
2070 This command terminates the configuration stage and
2071 enters the run stage. This helps when you need to have
2072 the startup scripts manage tasks such as resetting the target,
2073 programming flash, etc. To reset the CPU upon startup, add "init" and
2074 "reset" at the end of the config script or at the end of the OpenOCD
2075 command line using the @option{-c} command line switch.
2077 If this command does not appear in any startup/configuration file
2078 OpenOCD executes the command for you after processing all
2079 configuration files and/or command line options.
2081 @b{NOTE:} This command normally occurs at or near the end of your
2082 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2083 targets ready. For example: If your openocd.cfg file needs to
2084 read/write memory on your target, @command{init} must occur before
2085 the memory read/write commands. This includes @command{nand probe}.
2088 @deffn {Overridable Procedure} jtag_init
2089 This is invoked at server startup to verify that it can talk
2090 to the scan chain (list of TAPs) which has been configured.
2092 The default implementation first tries @command{jtag arp_init},
2093 which uses only a lightweight JTAG reset before examining the
2095 If that fails, it tries again, using a harder reset
2096 from the overridable procedure @command{init_reset}.
2098 Implementations must have verified the JTAG scan chain before
2100 This is done by calling @command{jtag arp_init}
2101 (or @command{jtag arp_init-reset}).
2105 @section TCP/IP Ports
2110 The OpenOCD server accepts remote commands in several syntaxes.
2111 Each syntax uses a different TCP/IP port, which you may specify
2112 only during configuration (before those ports are opened).
2114 For reasons including security, you may wish to prevent remote
2115 access using one or more of these ports.
2116 In such cases, just specify the relevant port number as "disabled".
2117 If you disable all access through TCP/IP, you will need to
2118 use the command line @option{-pipe} option.
2121 @deffn {Command} gdb_port [number]
2123 Normally gdb listens to a TCP/IP port, but GDB can also
2124 communicate via pipes(stdin/out or named pipes). The name
2125 "gdb_port" stuck because it covers probably more than 90% of
2126 the normal use cases.
2128 No arguments reports GDB port. "pipe" means listen to stdin
2129 output to stdout, an integer is base port number, "disabled"
2130 disables the gdb server.
2132 When using "pipe", also use log_output to redirect the log
2133 output to a file so as not to flood the stdin/out pipes.
2135 The -p/--pipe option is deprecated and a warning is printed
2136 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2138 Any other string is interpreted as named pipe to listen to.
2139 Output pipe is the same name as input pipe, but with 'o' appended,
2140 e.g. /var/gdb, /var/gdbo.
2142 The GDB port for the first target will be the base port, the
2143 second target will listen on gdb_port + 1, and so on.
2144 When not specified during the configuration stage,
2145 the port @var{number} defaults to 3333.
2146 When @var{number} is not a numeric value, incrementing it to compute
2147 the next port number does not work. In this case, specify the proper
2148 @var{number} for each target by using the option @code{-gdb-port} of the
2149 commands @command{target create} or @command{$target_name configure}.
2150 @xref{gdbportoverride,,option -gdb-port}.
2152 Note: when using "gdb_port pipe", increasing the default remote timeout in
2153 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2154 cause initialization to fail with "Unknown remote qXfer reply: OK".
2157 @deffn {Command} tcl_port [number]
2158 Specify or query the port used for a simplified RPC
2159 connection that can be used by clients to issue TCL commands and get the
2160 output from the Tcl engine.
2161 Intended as a machine interface.
2162 When not specified during the configuration stage,
2163 the port @var{number} defaults to 6666.
2164 When specified as "disabled", this service is not activated.
2167 @deffn {Command} telnet_port [number]
2168 Specify or query the
2169 port on which to listen for incoming telnet connections.
2170 This port is intended for interaction with one human through TCL commands.
2171 When not specified during the configuration stage,
2172 the port @var{number} defaults to 4444.
2173 When specified as "disabled", this service is not activated.
2176 @anchor{gdbconfiguration}
2177 @section GDB Configuration
2179 @cindex GDB configuration
2180 You can reconfigure some GDB behaviors if needed.
2181 The ones listed here are static and global.
2182 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2183 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2185 @anchor{gdbbreakpointoverride}
2186 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2187 Force breakpoint type for gdb @command{break} commands.
2188 This option supports GDB GUIs which don't
2189 distinguish hard versus soft breakpoints, if the default OpenOCD and
2190 GDB behaviour is not sufficient. GDB normally uses hardware
2191 breakpoints if the memory map has been set up for flash regions.
2194 @anchor{gdbflashprogram}
2195 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2196 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2197 vFlash packet is received.
2198 The default behaviour is @option{enable}.
2201 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2202 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2203 requested. GDB will then know when to set hardware breakpoints, and program flash
2204 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2205 for flash programming to work.
2206 Default behaviour is @option{enable}.
2207 @xref{gdbflashprogram,,gdb_flash_program}.
2210 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2211 Specifies whether data aborts cause an error to be reported
2212 by GDB memory read packets.
2213 The default behaviour is @option{disable};
2214 use @option{enable} see these errors reported.
2217 @deffn {Config Command} gdb_report_register_access_error (@option{enable}|@option{disable})
2218 Specifies whether register accesses requested by GDB register read/write
2219 packets report errors or not.
2220 The default behaviour is @option{disable};
2221 use @option{enable} see these errors reported.
2224 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2225 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2226 The default behaviour is @option{enable}.
2229 @deffn {Command} gdb_save_tdesc
2230 Saves the target description file to the local file system.
2232 The file name is @i{target_name}.xml.
2235 @anchor{eventpolling}
2236 @section Event Polling
2238 Hardware debuggers are parts of asynchronous systems,
2239 where significant events can happen at any time.
2240 The OpenOCD server needs to detect some of these events,
2241 so it can report them to through TCL command line
2244 Examples of such events include:
2247 @item One of the targets can stop running ... maybe it triggers
2248 a code breakpoint or data watchpoint, or halts itself.
2249 @item Messages may be sent over ``debug message'' channels ... many
2250 targets support such messages sent over JTAG,
2251 for receipt by the person debugging or tools.
2252 @item Loss of power ... some adapters can detect these events.
2253 @item Resets not issued through JTAG ... such reset sources
2254 can include button presses or other system hardware, sometimes
2255 including the target itself (perhaps through a watchdog).
2256 @item Debug instrumentation sometimes supports event triggering
2257 such as ``trace buffer full'' (so it can quickly be emptied)
2258 or other signals (to correlate with code behavior).
2261 None of those events are signaled through standard JTAG signals.
2262 However, most conventions for JTAG connectors include voltage
2263 level and system reset (SRST) signal detection.
2264 Some connectors also include instrumentation signals, which
2265 can imply events when those signals are inputs.
2267 In general, OpenOCD needs to periodically check for those events,
2268 either by looking at the status of signals on the JTAG connector
2269 or by sending synchronous ``tell me your status'' JTAG requests
2270 to the various active targets.
2271 There is a command to manage and monitor that polling,
2272 which is normally done in the background.
2274 @deffn Command poll [@option{on}|@option{off}]
2275 Poll the current target for its current state.
2276 (Also, @pxref{targetcurstate,,target curstate}.)
2277 If that target is in debug mode, architecture
2278 specific information about the current state is printed.
2279 An optional parameter
2280 allows background polling to be enabled and disabled.
2282 You could use this from the TCL command shell, or
2283 from GDB using @command{monitor poll} command.
2284 Leave background polling enabled while you're using GDB.
2287 background polling: on
2288 target state: halted
2289 target halted in ARM state due to debug-request, \
2290 current mode: Supervisor
2291 cpsr: 0x800000d3 pc: 0x11081bfc
2292 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2297 @node Debug Adapter Configuration
2298 @chapter Debug Adapter Configuration
2299 @cindex config file, interface
2300 @cindex interface config file
2302 Correctly installing OpenOCD includes making your operating system give
2303 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2304 are used to select which one is used, and to configure how it is used.
2307 Because OpenOCD started out with a focus purely on JTAG, you may find
2308 places where it wrongly presumes JTAG is the only transport protocol
2309 in use. Be aware that recent versions of OpenOCD are removing that
2310 limitation. JTAG remains more functional than most other transports.
2311 Other transports do not support boundary scan operations, or may be
2312 specific to a given chip vendor. Some might be usable only for
2313 programming flash memory, instead of also for debugging.
2316 Debug Adapters/Interfaces/Dongles are normally configured
2317 through commands in an interface configuration
2318 file which is sourced by your @file{openocd.cfg} file, or
2319 through a command line @option{-f interface/....cfg} option.
2322 source [find interface/olimex-jtag-tiny.cfg]
2326 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2327 A few cases are so simple that you only need to say what driver to use:
2334 Most adapters need a bit more configuration than that.
2337 @section Interface Configuration
2339 The interface command tells OpenOCD what type of debug adapter you are
2340 using. Depending on the type of adapter, you may need to use one or
2341 more additional commands to further identify or configure the adapter.
2343 @deffn {Config Command} {interface} name
2344 Use the interface driver @var{name} to connect to the
2348 @deffn Command {interface_list}
2349 List the debug adapter drivers that have been built into
2350 the running copy of OpenOCD.
2352 @deffn Command {interface transports} transport_name+
2353 Specifies the transports supported by this debug adapter.
2354 The adapter driver builds-in similar knowledge; use this only
2355 when external configuration (such as jumpering) changes what
2356 the hardware can support.
2361 @deffn Command {adapter_name}
2362 Returns the name of the debug adapter driver being used.
2365 @section Interface Drivers
2367 Each of the interface drivers listed here must be explicitly
2368 enabled when OpenOCD is configured, in order to be made
2369 available at run time.
2371 @deffn {Interface Driver} {amt_jtagaccel}
2372 Amontec Chameleon in its JTAG Accelerator configuration,
2373 connected to a PC's EPP mode parallel port.
2374 This defines some driver-specific commands:
2376 @deffn {Config Command} {parport_port} number
2377 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2378 the number of the @file{/dev/parport} device.
2381 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2382 Displays status of RTCK option.
2383 Optionally sets that option first.
2387 @deffn {Interface Driver} {arm-jtag-ew}
2388 Olimex ARM-JTAG-EW USB adapter
2389 This has one driver-specific command:
2391 @deffn Command {armjtagew_info}
2396 @deffn {Interface Driver} {at91rm9200}
2397 Supports bitbanged JTAG from the local system,
2398 presuming that system is an Atmel AT91rm9200
2399 and a specific set of GPIOs is used.
2400 @c command: at91rm9200_device NAME
2401 @c chooses among list of bit configs ... only one option
2404 @deffn {Interface Driver} {cmsis-dap}
2405 ARM CMSIS-DAP compliant based adapter.
2407 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2408 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2409 the driver will attempt to auto detect the CMSIS-DAP device.
2410 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2412 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2416 @deffn {Config Command} {cmsis_dap_serial} [serial]
2417 Specifies the @var{serial} of the CMSIS-DAP device to use.
2418 If not specified, serial numbers are not considered.
2421 @deffn {Command} {cmsis-dap info}
2422 Display various device information, like hardware version, firmware version, current bus status.
2426 @deffn {Interface Driver} {dummy}
2427 A dummy software-only driver for debugging.
2430 @deffn {Interface Driver} {ep93xx}
2431 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2434 @deffn {Interface Driver} {ftdi}
2435 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2436 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2438 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2439 bypassing intermediate libraries like libftdi or D2XX.
2441 Support for new FTDI based adapters can be added completely through
2442 configuration files, without the need to patch and rebuild OpenOCD.
2444 The driver uses a signal abstraction to enable Tcl configuration files to
2445 define outputs for one or several FTDI GPIO. These outputs can then be
2446 controlled using the @command{ftdi_set_signal} command. Special signal names
2447 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2448 will be used for their customary purpose. Inputs can be read using the
2449 @command{ftdi_get_signal} command.
2451 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2452 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2453 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2454 required by the protocol, to tell the adapter to drive the data output onto
2455 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2457 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2458 be controlled differently. In order to support tristateable signals such as
2459 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2460 signal. The following output buffer configurations are supported:
2463 @item Push-pull with one FTDI output as (non-)inverted data line
2464 @item Open drain with one FTDI output as (non-)inverted output-enable
2465 @item Tristate with one FTDI output as (non-)inverted data line and another
2466 FTDI output as (non-)inverted output-enable
2467 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2468 switching data and direction as necessary
2471 These interfaces have several commands, used to configure the driver
2472 before initializing the JTAG scan chain:
2474 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2475 The vendor ID and product ID of the adapter. Up to eight
2476 [@var{vid}, @var{pid}] pairs may be given, e.g.
2478 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2482 @deffn {Config Command} {ftdi_device_desc} description
2483 Provides the USB device description (the @emph{iProduct string})
2484 of the adapter. If not specified, the device description is ignored
2485 during device selection.
2488 @deffn {Config Command} {ftdi_serial} serial-number
2489 Specifies the @var{serial-number} of the adapter to use,
2490 in case the vendor provides unique IDs and more than one adapter
2491 is connected to the host.
2492 If not specified, serial numbers are not considered.
2493 (Note that USB serial numbers can be arbitrary Unicode strings,
2494 and are not restricted to containing only decimal digits.)
2497 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2498 Specifies the physical USB port of the adapter to use. The path
2499 roots at @var{bus} and walks down the physical ports, with each
2500 @var{port} option specifying a deeper level in the bus topology, the last
2501 @var{port} denoting where the target adapter is actually plugged.
2502 The USB bus topology can be queried with the command @emph{lsusb -t}.
2504 This command is only available if your libusb1 is at least version 1.0.16.
2507 @deffn {Config Command} {ftdi_channel} channel
2508 Selects the channel of the FTDI device to use for MPSSE operations. Most
2509 adapters use the default, channel 0, but there are exceptions.
2512 @deffn {Config Command} {ftdi_layout_init} data direction
2513 Specifies the initial values of the FTDI GPIO data and direction registers.
2514 Each value is a 16-bit number corresponding to the concatenation of the high
2515 and low FTDI GPIO registers. The values should be selected based on the
2516 schematics of the adapter, such that all signals are set to safe levels with
2517 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2518 and initially asserted reset signals.
2521 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2522 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2523 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2524 register bitmasks to tell the driver the connection and type of the output
2525 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2526 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2527 used with inverting data inputs and @option{-data} with non-inverting inputs.
2528 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2529 not-output-enable) input to the output buffer is connected. The options
2530 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2531 with the method @command{ftdi_get_signal}.
2533 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2534 simple open-collector transistor driver would be specified with @option{-oe}
2535 only. In that case the signal can only be set to drive low or to Hi-Z and the
2536 driver will complain if the signal is set to drive high. Which means that if
2537 it's a reset signal, @command{reset_config} must be specified as
2538 @option{srst_open_drain}, not @option{srst_push_pull}.
2540 A special case is provided when @option{-data} and @option{-oe} is set to the
2541 same bitmask. Then the FTDI pin is considered being connected straight to the
2542 target without any buffer. The FTDI pin is then switched between output and
2543 input as necessary to provide the full set of low, high and Hi-Z
2544 characteristics. In all other cases, the pins specified in a signal definition
2545 are always driven by the FTDI.
2547 If @option{-alias} or @option{-nalias} is used, the signal is created
2548 identical (or with data inverted) to an already specified signal
2552 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2553 Set a previously defined signal to the specified level.
2555 @item @option{0}, drive low
2556 @item @option{1}, drive high
2557 @item @option{z}, set to high-impedance
2561 @deffn {Command} {ftdi_get_signal} name
2562 Get the value of a previously defined signal.
2565 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2566 Configure TCK edge at which the adapter samples the value of the TDO signal
2568 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2569 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2570 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2571 stability at higher JTAG clocks.
2573 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2574 @item @option{falling}, sample TDO on falling edge of TCK
2578 For example adapter definitions, see the configuration files shipped in the
2579 @file{interface/ftdi} directory.
2583 @deffn {Interface Driver} {ft232r}
2584 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2585 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2586 It currently doesn't support using CBUS pins as GPIO.
2588 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2595 @item DCD(10) - SRST
2598 User can change default pinout by supplying configuration
2599 commands with GPIO numbers or RS232 signal names.
2600 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2601 They differ from physical pin numbers.
2602 For details see actual FTDI chip datasheets.
2603 Every JTAG line must be configured to unique GPIO number
2604 different than any other JTAG line, even those lines
2605 that are sometimes not used like TRST or SRST.
2619 These interfaces have several commands, used to configure the driver
2620 before initializing the JTAG scan chain:
2622 @deffn {Config Command} {ft232r_vid_pid} @var{vid} @var{pid}
2623 The vendor ID and product ID of the adapter. If not specified, default
2624 0x0403:0x6001 is used.
2627 @deffn {Config Command} {ft232r_serial_desc} @var{serial}
2628 Specifies the @var{serial} of the adapter to use, in case the
2629 vendor provides unique IDs and more than one adapter is connected to
2630 the host. If not specified, serial numbers are not considered.
2633 @deffn {Config Command} {ft232r_jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2634 Set four JTAG GPIO numbers at once.
2635 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2638 @deffn {Config Command} {ft232r_tck_num} @var{tck}
2639 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2642 @deffn {Config Command} {ft232r_tms_num} @var{tms}
2643 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2646 @deffn {Config Command} {ft232r_tdi_num} @var{tdi}
2647 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2650 @deffn {Config Command} {ft232r_tdo_num} @var{tdo}
2651 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2654 @deffn {Config Command} {ft232r_trst_num} @var{trst}
2655 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2658 @deffn {Config Command} {ft232r_srst_num} @var{srst}
2659 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2662 @deffn {Config Command} {ft232r_restore_serial} @var{word}
2663 Restore serial port after JTAG. This USB bitmode control word
2664 (16-bit) will be sent before quit. Lower byte should
2665 set GPIO direction register to a "sane" state:
2666 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2667 byte is usually 0 to disable bitbang mode.
2668 When kernel driver reattaches, serial port should continue to work.
2669 Value 0xFFFF disables sending control word and serial port,
2670 then kernel driver will not reattach.
2671 If not specified, default 0xFFFF is used.
2676 @deffn {Interface Driver} {remote_bitbang}
2677 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2678 with a remote process and sends ASCII encoded bitbang requests to that process
2679 instead of directly driving JTAG.
2681 The remote_bitbang driver is useful for debugging software running on
2682 processors which are being simulated.
2684 @deffn {Config Command} {remote_bitbang_port} number
2685 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2686 sockets instead of TCP.
2689 @deffn {Config Command} {remote_bitbang_host} hostname
2690 Specifies the hostname of the remote process to connect to using TCP, or the
2691 name of the UNIX socket to use if remote_bitbang_port is 0.
2694 For example, to connect remotely via TCP to the host foobar you might have
2698 interface remote_bitbang
2699 remote_bitbang_port 3335
2700 remote_bitbang_host foobar
2703 To connect to another process running locally via UNIX sockets with socket
2707 interface remote_bitbang
2708 remote_bitbang_port 0
2709 remote_bitbang_host mysocket
2713 @deffn {Interface Driver} {usb_blaster}
2714 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2715 for FTDI chips. These interfaces have several commands, used to
2716 configure the driver before initializing the JTAG scan chain:
2718 @deffn {Config Command} {usb_blaster_device_desc} description
2719 Provides the USB device description (the @emph{iProduct string})
2720 of the FTDI FT245 device. If not
2721 specified, the FTDI default value is used. This setting is only valid
2722 if compiled with FTD2XX support.
2725 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2726 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2727 default values are used.
2728 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2729 Altera USB-Blaster (default):
2731 usb_blaster_vid_pid 0x09FB 0x6001
2733 The following VID/PID is for Kolja Waschk's USB JTAG:
2735 usb_blaster_vid_pid 0x16C0 0x06AD
2739 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2740 Sets the state or function of the unused GPIO pins on USB-Blasters
2741 (pins 6 and 8 on the female JTAG header). These pins can be used as
2742 SRST and/or TRST provided the appropriate connections are made on the
2745 For example, to use pin 6 as SRST:
2747 usb_blaster_pin pin6 s
2748 reset_config srst_only
2752 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2753 Chooses the low level access method for the adapter. If not specified,
2754 @option{ftdi} is selected unless it wasn't enabled during the
2755 configure stage. USB-Blaster II needs @option{ublast2}.
2758 @deffn {Command} {usb_blaster_firmware} @var{path}
2759 This command specifies @var{path} to access USB-Blaster II firmware
2760 image. To be used with USB-Blaster II only.
2765 @deffn {Interface Driver} {gw16012}
2766 Gateworks GW16012 JTAG programmer.
2767 This has one driver-specific command:
2769 @deffn {Config Command} {parport_port} [port_number]
2770 Display either the address of the I/O port
2771 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2772 If a parameter is provided, first switch to use that port.
2773 This is a write-once setting.
2777 @deffn {Interface Driver} {jlink}
2778 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2781 @quotation Compatibility Note
2782 SEGGER released many firmware versions for the many hardware versions they
2783 produced. OpenOCD was extensively tested and intended to run on all of them,
2784 but some combinations were reported as incompatible. As a general
2785 recommendation, it is advisable to use the latest firmware version
2786 available for each hardware version. However the current V8 is a moving
2787 target, and SEGGER firmware versions released after the OpenOCD was
2788 released may not be compatible. In such cases it is recommended to
2789 revert to the last known functional version. For 0.5.0, this is from
2790 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2791 version is from "May 3 2012 18:36:22", packed with 4.46f.
2794 @deffn {Command} {jlink hwstatus}
2795 Display various hardware related information, for example target voltage and pin
2798 @deffn {Command} {jlink freemem}
2799 Display free device internal memory.
2801 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2802 Set the JTAG command version to be used. Without argument, show the actual JTAG
2805 @deffn {Command} {jlink config}
2806 Display the device configuration.
2808 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2809 Set the target power state on JTAG-pin 19. Without argument, show the target
2812 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2813 Set the MAC address of the device. Without argument, show the MAC address.
2815 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2816 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2817 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2820 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2821 Set the USB address of the device. This will also change the USB Product ID
2822 (PID) of the device. Without argument, show the USB address.
2824 @deffn {Command} {jlink config reset}
2825 Reset the current configuration.
2827 @deffn {Command} {jlink config write}
2828 Write the current configuration to the internal persistent storage.
2830 @deffn {Command} {jlink emucom write <channel> <data>}
2831 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2834 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2835 the EMUCOM channel 0x10:
2837 > jlink emucom write 0x10 aa0b23
2840 @deffn {Command} {jlink emucom read <channel> <length>}
2841 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2844 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2846 > jlink emucom read 0x0 4
2850 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2851 Set the USB address of the interface, in case more than one adapter is connected
2852 to the host. If not specified, USB addresses are not considered. Device
2853 selection via USB address is deprecated and the serial number should be used
2856 As a configuration command, it can be used only before 'init'.
2858 @deffn {Config} {jlink serial} <serial number>
2859 Set the serial number of the interface, in case more than one adapter is
2860 connected to the host. If not specified, serial numbers are not considered.
2862 As a configuration command, it can be used only before 'init'.
2866 @deffn {Interface Driver} {kitprog}
2867 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2868 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2869 families, but it is possible to use it with some other devices. If you are using
2870 this adapter with a PSoC or a PRoC, you may need to add
2871 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2872 configuration script.
2874 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2875 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2876 be used with this driver, and must either be used with the cmsis-dap driver or
2877 switched back to KitProg mode. See the Cypress KitProg User Guide for
2878 instructions on how to switch KitProg modes.
2882 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2884 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2885 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2886 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2887 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2888 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2889 SWD sequence must be sent after every target reset in order to re-establish
2890 communications with the target.
2891 @item Due in part to the limitation above, KitProg devices with firmware below
2892 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2893 communicate with PSoC 5LP devices. This is because, assuming debug is not
2894 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2895 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2896 could only be sent with an acquisition sequence.
2899 @deffn {Config Command} {kitprog_init_acquire_psoc}
2900 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2901 Please be aware that the acquisition sequence hard-resets the target.
2904 @deffn {Config Command} {kitprog_serial} serial
2905 Select a KitProg device by its @var{serial}. If left unspecified, the first
2906 device detected by OpenOCD will be used.
2909 @deffn {Command} {kitprog acquire_psoc}
2910 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2911 outside of the target-specific configuration scripts since it hard-resets the
2912 target as a side-effect.
2913 This is necessary for "reset halt" on some PSoC 4 series devices.
2916 @deffn {Command} {kitprog info}
2917 Display various adapter information, such as the hardware version, firmware
2918 version, and target voltage.
2922 @deffn {Interface Driver} {parport}
2923 Supports PC parallel port bit-banging cables:
2924 Wigglers, PLD download cable, and more.
2925 These interfaces have several commands, used to configure the driver
2926 before initializing the JTAG scan chain:
2928 @deffn {Config Command} {parport_cable} name
2929 Set the layout of the parallel port cable used to connect to the target.
2930 This is a write-once setting.
2931 Currently valid cable @var{name} values include:
2934 @item @b{altium} Altium Universal JTAG cable.
2935 @item @b{arm-jtag} Same as original wiggler except SRST and
2936 TRST connections reversed and TRST is also inverted.
2937 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2938 in configuration mode. This is only used to
2939 program the Chameleon itself, not a connected target.
2940 @item @b{dlc5} The Xilinx Parallel cable III.
2941 @item @b{flashlink} The ST Parallel cable.
2942 @item @b{lattice} Lattice ispDOWNLOAD Cable
2943 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2945 Amontec's Chameleon Programmer. The new version available from
2946 the website uses the original Wiggler layout ('@var{wiggler}')
2947 @item @b{triton} The parallel port adapter found on the
2948 ``Karo Triton 1 Development Board''.
2949 This is also the layout used by the HollyGates design
2950 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2951 @item @b{wiggler} The original Wiggler layout, also supported by
2952 several clones, such as the Olimex ARM-JTAG
2953 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2954 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2958 @deffn {Config Command} {parport_port} [port_number]
2959 Display either the address of the I/O port
2960 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2961 If a parameter is provided, first switch to use that port.
2962 This is a write-once setting.
2964 When using PPDEV to access the parallel port, use the number of the parallel port:
2965 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2966 you may encounter a problem.
2969 @deffn Command {parport_toggling_time} [nanoseconds]
2970 Displays how many nanoseconds the hardware needs to toggle TCK;
2971 the parport driver uses this value to obey the
2972 @command{adapter_khz} configuration.
2973 When the optional @var{nanoseconds} parameter is given,
2974 that setting is changed before displaying the current value.
2976 The default setting should work reasonably well on commodity PC hardware.
2977 However, you may want to calibrate for your specific hardware.
2979 To measure the toggling time with a logic analyzer or a digital storage
2980 oscilloscope, follow the procedure below:
2982 > parport_toggling_time 1000
2985 This sets the maximum JTAG clock speed of the hardware, but
2986 the actual speed probably deviates from the requested 500 kHz.
2987 Now, measure the time between the two closest spaced TCK transitions.
2988 You can use @command{runtest 1000} or something similar to generate a
2989 large set of samples.
2990 Update the setting to match your measurement:
2992 > parport_toggling_time <measured nanoseconds>
2994 Now the clock speed will be a better match for @command{adapter_khz rate}
2995 commands given in OpenOCD scripts and event handlers.
2997 You can do something similar with many digital multimeters, but note
2998 that you'll probably need to run the clock continuously for several
2999 seconds before it decides what clock rate to show. Adjust the
3000 toggling time up or down until the measured clock rate is a good
3001 match for the adapter_khz rate you specified; be conservative.
3005 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
3006 This will configure the parallel driver to write a known
3007 cable-specific value to the parallel interface on exiting OpenOCD.
3010 For example, the interface configuration file for a
3011 classic ``Wiggler'' cable on LPT2 might look something like this:
3016 parport_cable wiggler
3020 @deffn {Interface Driver} {presto}
3021 ASIX PRESTO USB JTAG programmer.
3022 @deffn {Config Command} {presto_serial} serial_string
3023 Configures the USB serial number of the Presto device to use.
3027 @deffn {Interface Driver} {rlink}
3028 Raisonance RLink USB adapter
3031 @deffn {Interface Driver} {usbprog}
3032 usbprog is a freely programmable USB adapter.
3035 @deffn {Interface Driver} {vsllink}
3036 vsllink is part of Versaloon which is a versatile USB programmer.
3039 This defines quite a few driver-specific commands,
3040 which are not currently documented here.
3044 @anchor{hla_interface}
3045 @deffn {Interface Driver} {hla}
3046 This is a driver that supports multiple High Level Adapters.
3047 This type of adapter does not expose some of the lower level api's
3048 that OpenOCD would normally use to access the target.
3050 Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
3051 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3052 versions of firmware where serial number is reset after first use. Suggest
3053 using ST firmware update utility to upgrade ST-LINK firmware even if current
3054 version reported is V2.J21.S4.
3056 @deffn {Config Command} {hla_device_desc} description
3057 Currently Not Supported.
3060 @deffn {Config Command} {hla_serial} serial
3061 Specifies the serial number of the adapter.
3064 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
3065 Specifies the adapter layout to use.
3068 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3069 Pairs of vendor IDs and product IDs of the device.
3072 @deffn {Command} {hla_command} command
3073 Execute a custom adapter-specific command. The @var{command} string is
3074 passed as is to the underlying adapter layout handler.
3078 @deffn {Interface Driver} {opendous}
3079 opendous-jtag is a freely programmable USB adapter.
3082 @deffn {Interface Driver} {ulink}
3083 This is the Keil ULINK v1 JTAG debugger.
3086 @deffn {Interface Driver} {ZY1000}
3087 This is the Zylin ZY1000 JTAG debugger.
3091 This defines some driver-specific commands,
3092 which are not currently documented here.
3095 @deffn Command power [@option{on}|@option{off}]
3096 Turn power switch to target on/off.
3097 No arguments: print status.
3100 @deffn {Interface Driver} {bcm2835gpio}
3101 This SoC is present in Raspberry Pi which is a cheap single-board computer
3102 exposing some GPIOs on its expansion header.
3104 The driver accesses memory-mapped GPIO peripheral registers directly
3105 for maximum performance, but the only possible race condition is for
3106 the pins' modes/muxing (which is highly unlikely), so it should be
3107 able to coexist nicely with both sysfs bitbanging and various
3108 peripherals' kernel drivers. The driver restores the previous
3109 configuration on exit.
3111 See @file{interface/raspberrypi-native.cfg} for a sample config and
3116 @deffn {Interface Driver} {imx_gpio}
3117 i.MX SoC is present in many community boards. Wandboard is an example
3118 of the one which is most popular.
3120 This driver is mostly the same as bcm2835gpio.
3122 See @file{interface/imx-native.cfg} for a sample config and
3128 @deffn {Interface Driver} {openjtag}
3129 OpenJTAG compatible USB adapter.
3130 This defines some driver-specific commands:
3132 @deffn {Config Command} {openjtag_variant} variant
3133 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3134 Currently valid @var{variant} values include:
3137 @item @b{standard} Standard variant (default).
3138 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3139 (see @uref{http://www.cypress.com/?rID=82870}).
3143 @deffn {Config Command} {openjtag_device_desc} string
3144 The USB device description string of the adapter.
3145 This value is only used with the standard variant.
3149 @section Transport Configuration
3151 As noted earlier, depending on the version of OpenOCD you use,
3152 and the debug adapter you are using,
3153 several transports may be available to
3154 communicate with debug targets (or perhaps to program flash memory).
3155 @deffn Command {transport list}
3156 displays the names of the transports supported by this
3160 @deffn Command {transport select} @option{transport_name}
3161 Select which of the supported transports to use in this OpenOCD session.
3163 When invoked with @option{transport_name}, attempts to select the named
3164 transport. The transport must be supported by the debug adapter
3165 hardware and by the version of OpenOCD you are using (including the
3168 If no transport has been selected and no @option{transport_name} is
3169 provided, @command{transport select} auto-selects the first transport
3170 supported by the debug adapter.
3172 @command{transport select} always returns the name of the session's selected
3176 @subsection JTAG Transport
3178 JTAG is the original transport supported by OpenOCD, and most
3179 of the OpenOCD commands support it.
3180 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3181 each of which must be explicitly declared.
3182 JTAG supports both debugging and boundary scan testing.
3183 Flash programming support is built on top of debug support.
3185 JTAG transport is selected with the command @command{transport select
3186 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3187 driver}, in which case the command is @command{transport select
3190 @subsection SWD Transport
3192 @cindex Serial Wire Debug
3193 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3194 Debug Access Point (DAP, which must be explicitly declared.
3195 (SWD uses fewer signal wires than JTAG.)
3196 SWD is debug-oriented, and does not support boundary scan testing.
3197 Flash programming support is built on top of debug support.
3198 (Some processors support both JTAG and SWD.)
3200 SWD transport is selected with the command @command{transport select
3201 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3202 driver}, in which case the command is @command{transport select
3205 @deffn Command {swd newdap} ...
3206 Declares a single DAP which uses SWD transport.
3207 Parameters are currently the same as "jtag newtap" but this is
3210 @deffn Command {swd wcr trn prescale}
3211 Updates TRN (turnaround delay) and prescaling.fields of the
3212 Wire Control Register (WCR).
3213 No parameters: displays current settings.
3216 @subsection SPI Transport
3218 @cindex Serial Peripheral Interface
3219 The Serial Peripheral Interface (SPI) is a general purpose transport
3220 which uses four wire signaling. Some processors use it as part of a
3221 solution for flash programming.
3225 JTAG clock setup is part of system setup.
3226 It @emph{does not belong with interface setup} since any interface
3227 only knows a few of the constraints for the JTAG clock speed.
3228 Sometimes the JTAG speed is
3229 changed during the target initialization process: (1) slow at
3230 reset, (2) program the CPU clocks, (3) run fast.
3231 Both the "slow" and "fast" clock rates are functions of the
3232 oscillators used, the chip, the board design, and sometimes
3233 power management software that may be active.
3235 The speed used during reset, and the scan chain verification which
3236 follows reset, can be adjusted using a @code{reset-start}
3237 target event handler.
3238 It can then be reconfigured to a faster speed by a
3239 @code{reset-init} target event handler after it reprograms those
3240 CPU clocks, or manually (if something else, such as a boot loader,
3241 sets up those clocks).
3242 @xref{targetevents,,Target Events}.
3243 When the initial low JTAG speed is a chip characteristic, perhaps
3244 because of a required oscillator speed, provide such a handler
3245 in the target config file.
3246 When that speed is a function of a board-specific characteristic
3247 such as which speed oscillator is used, it belongs in the board
3248 config file instead.
3249 In both cases it's safest to also set the initial JTAG clock rate
3250 to that same slow speed, so that OpenOCD never starts up using a
3251 clock speed that's faster than the scan chain can support.
3255 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3258 If your system supports adaptive clocking (RTCK), configuring
3259 JTAG to use that is probably the most robust approach.
3260 However, it introduces delays to synchronize clocks; so it
3261 may not be the fastest solution.
3263 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3264 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3265 which support adaptive clocking.
3267 @deffn {Command} adapter_khz max_speed_kHz
3268 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3269 JTAG interfaces usually support a limited number of
3270 speeds. The speed actually used won't be faster
3271 than the speed specified.
3273 Chip data sheets generally include a top JTAG clock rate.
3274 The actual rate is often a function of a CPU core clock,
3275 and is normally less than that peak rate.
3276 For example, most ARM cores accept at most one sixth of the CPU clock.
3278 Speed 0 (khz) selects RTCK method.
3279 @xref{faqrtck,,FAQ RTCK}.
3280 If your system uses RTCK, you won't need to change the
3281 JTAG clocking after setup.
3282 Not all interfaces, boards, or targets support ``rtck''.
3283 If the interface device can not
3284 support it, an error is returned when you try to use RTCK.
3287 @defun jtag_rclk fallback_speed_kHz
3288 @cindex adaptive clocking
3290 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3291 If that fails (maybe the interface, board, or target doesn't
3292 support it), falls back to the specified frequency.
3294 # Fall back to 3mhz if RTCK is not supported
3299 @node Reset Configuration
3300 @chapter Reset Configuration
3301 @cindex Reset Configuration
3303 Every system configuration may require a different reset
3304 configuration. This can also be quite confusing.
3305 Resets also interact with @var{reset-init} event handlers,
3306 which do things like setting up clocks and DRAM, and
3307 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3308 They can also interact with JTAG routers.
3309 Please see the various board files for examples.
3312 To maintainers and integrators:
3313 Reset configuration touches several things at once.
3314 Normally the board configuration file
3315 should define it and assume that the JTAG adapter supports
3316 everything that's wired up to the board's JTAG connector.
3318 However, the target configuration file could also make note
3319 of something the silicon vendor has done inside the chip,
3320 which will be true for most (or all) boards using that chip.
3321 And when the JTAG adapter doesn't support everything, the
3322 user configuration file will need to override parts of
3323 the reset configuration provided by other files.
3326 @section Types of Reset
3328 There are many kinds of reset possible through JTAG, but
3329 they may not all work with a given board and adapter.
3330 That's part of why reset configuration can be error prone.
3334 @emph{System Reset} ... the @emph{SRST} hardware signal
3335 resets all chips connected to the JTAG adapter, such as processors,
3336 power management chips, and I/O controllers. Normally resets triggered
3337 with this signal behave exactly like pressing a RESET button.
3339 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3340 just the TAP controllers connected to the JTAG adapter.
3341 Such resets should not be visible to the rest of the system; resetting a
3342 device's TAP controller just puts that controller into a known state.
3344 @emph{Emulation Reset} ... many devices can be reset through JTAG
3345 commands. These resets are often distinguishable from system
3346 resets, either explicitly (a "reset reason" register says so)
3347 or implicitly (not all parts of the chip get reset).
3349 @emph{Other Resets} ... system-on-chip devices often support
3350 several other types of reset.
3351 You may need to arrange that a watchdog timer stops
3352 while debugging, preventing a watchdog reset.
3353 There may be individual module resets.
3356 In the best case, OpenOCD can hold SRST, then reset
3357 the TAPs via TRST and send commands through JTAG to halt the
3358 CPU at the reset vector before the 1st instruction is executed.
3359 Then when it finally releases the SRST signal, the system is
3360 halted under debugger control before any code has executed.
3361 This is the behavior required to support the @command{reset halt}
3362 and @command{reset init} commands; after @command{reset init} a
3363 board-specific script might do things like setting up DRAM.
3364 (@xref{resetcommand,,Reset Command}.)
3366 @anchor{srstandtrstissues}
3367 @section SRST and TRST Issues
3369 Because SRST and TRST are hardware signals, they can have a
3370 variety of system-specific constraints. Some of the most
3375 @item @emph{Signal not available} ... Some boards don't wire
3376 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3377 support such signals even if they are wired up.
3378 Use the @command{reset_config} @var{signals} options to say
3379 when either of those signals is not connected.
3380 When SRST is not available, your code might not be able to rely
3381 on controllers having been fully reset during code startup.
3382 Missing TRST is not a problem, since JTAG-level resets can
3383 be triggered using with TMS signaling.
3385 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3386 adapter will connect SRST to TRST, instead of keeping them separate.
3387 Use the @command{reset_config} @var{combination} options to say
3388 when those signals aren't properly independent.
3390 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3391 delay circuit, reset supervisor, or on-chip features can extend
3392 the effect of a JTAG adapter's reset for some time after the adapter
3393 stops issuing the reset. For example, there may be chip or board
3394 requirements that all reset pulses last for at least a
3395 certain amount of time; and reset buttons commonly have
3396 hardware debouncing.
3397 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3398 commands to say when extra delays are needed.
3400 @item @emph{Drive type} ... Reset lines often have a pullup
3401 resistor, letting the JTAG interface treat them as open-drain
3402 signals. But that's not a requirement, so the adapter may need
3403 to use push/pull output drivers.
3404 Also, with weak pullups it may be advisable to drive
3405 signals to both levels (push/pull) to minimize rise times.
3406 Use the @command{reset_config} @var{trst_type} and
3407 @var{srst_type} parameters to say how to drive reset signals.
3409 @item @emph{Special initialization} ... Targets sometimes need
3410 special JTAG initialization sequences to handle chip-specific
3411 issues (not limited to errata).
3412 For example, certain JTAG commands might need to be issued while
3413 the system as a whole is in a reset state (SRST active)
3414 but the JTAG scan chain is usable (TRST inactive).
3415 Many systems treat combined assertion of SRST and TRST as a
3416 trigger for a harder reset than SRST alone.
3417 Such custom reset handling is discussed later in this chapter.
3420 There can also be other issues.
3421 Some devices don't fully conform to the JTAG specifications.
3422 Trivial system-specific differences are common, such as
3423 SRST and TRST using slightly different names.
3424 There are also vendors who distribute key JTAG documentation for
3425 their chips only to developers who have signed a Non-Disclosure
3428 Sometimes there are chip-specific extensions like a requirement to use
3429 the normally-optional TRST signal (precluding use of JTAG adapters which
3430 don't pass TRST through), or needing extra steps to complete a TAP reset.
3432 In short, SRST and especially TRST handling may be very finicky,
3433 needing to cope with both architecture and board specific constraints.
3435 @section Commands for Handling Resets
3437 @deffn {Command} adapter_nsrst_assert_width milliseconds
3438 Minimum amount of time (in milliseconds) OpenOCD should wait
3439 after asserting nSRST (active-low system reset) before
3440 allowing it to be deasserted.
3443 @deffn {Command} adapter_nsrst_delay milliseconds
3444 How long (in milliseconds) OpenOCD should wait after deasserting
3445 nSRST (active-low system reset) before starting new JTAG operations.
3446 When a board has a reset button connected to SRST line it will
3447 probably have hardware debouncing, implying you should use this.
3450 @deffn {Command} jtag_ntrst_assert_width milliseconds
3451 Minimum amount of time (in milliseconds) OpenOCD should wait
3452 after asserting nTRST (active-low JTAG TAP reset) before
3453 allowing it to be deasserted.
3456 @deffn {Command} jtag_ntrst_delay milliseconds
3457 How long (in milliseconds) OpenOCD should wait after deasserting
3458 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3461 @anchor {reset_config}
3462 @deffn {Command} reset_config mode_flag ...
3463 This command displays or modifies the reset configuration
3464 of your combination of JTAG board and target in target
3465 configuration scripts.
3467 Information earlier in this section describes the kind of problems
3468 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3469 As a rule this command belongs only in board config files,
3470 describing issues like @emph{board doesn't connect TRST};
3471 or in user config files, addressing limitations derived
3472 from a particular combination of interface and board.
3473 (An unlikely example would be using a TRST-only adapter
3474 with a board that only wires up SRST.)
3476 The @var{mode_flag} options can be specified in any order, but only one
3477 of each type -- @var{signals}, @var{combination}, @var{gates},
3478 @var{trst_type}, @var{srst_type} and @var{connect_type}
3479 -- may be specified at a time.
3480 If you don't provide a new value for a given type, its previous
3481 value (perhaps the default) is unchanged.
3482 For example, this means that you don't need to say anything at all about
3483 TRST just to declare that if the JTAG adapter should want to drive SRST,
3484 it must explicitly be driven high (@option{srst_push_pull}).
3488 @var{signals} can specify which of the reset signals are connected.
3489 For example, If the JTAG interface provides SRST, but the board doesn't
3490 connect that signal properly, then OpenOCD can't use it.
3491 Possible values are @option{none} (the default), @option{trst_only},
3492 @option{srst_only} and @option{trst_and_srst}.
3495 If your board provides SRST and/or TRST through the JTAG connector,
3496 you must declare that so those signals can be used.
3500 The @var{combination} is an optional value specifying broken reset
3501 signal implementations.
3502 The default behaviour if no option given is @option{separate},
3503 indicating everything behaves normally.
3504 @option{srst_pulls_trst} states that the
3505 test logic is reset together with the reset of the system (e.g. NXP
3506 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3507 the system is reset together with the test logic (only hypothetical, I
3508 haven't seen hardware with such a bug, and can be worked around).
3509 @option{combined} implies both @option{srst_pulls_trst} and
3510 @option{trst_pulls_srst}.
3513 The @var{gates} tokens control flags that describe some cases where
3514 JTAG may be unavailable during reset.
3515 @option{srst_gates_jtag} (default)
3516 indicates that asserting SRST gates the
3517 JTAG clock. This means that no communication can happen on JTAG
3518 while SRST is asserted.
3519 Its converse is @option{srst_nogate}, indicating that JTAG commands
3520 can safely be issued while SRST is active.
3523 The @var{connect_type} tokens control flags that describe some cases where
3524 SRST is asserted while connecting to the target. @option{srst_nogate}
3525 is required to use this option.
3526 @option{connect_deassert_srst} (default)
3527 indicates that SRST will not be asserted while connecting to the target.
3528 Its converse is @option{connect_assert_srst}, indicating that SRST will
3529 be asserted before any target connection.
3530 Only some targets support this feature, STM32 and STR9 are examples.
3531 This feature is useful if you are unable to connect to your target due
3532 to incorrect options byte config or illegal program execution.
3535 The optional @var{trst_type} and @var{srst_type} parameters allow the
3536 driver mode of each reset line to be specified. These values only affect
3537 JTAG interfaces with support for different driver modes, like the Amontec
3538 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3539 relevant signal (TRST or SRST) is not connected.
3543 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3544 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3545 Most boards connect this signal to a pulldown, so the JTAG TAPs
3546 never leave reset unless they are hooked up to a JTAG adapter.
3549 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3550 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3551 Most boards connect this signal to a pullup, and allow the
3552 signal to be pulled low by various events including system
3553 power-up and pressing a reset button.
3557 @section Custom Reset Handling
3560 OpenOCD has several ways to help support the various reset
3561 mechanisms provided by chip and board vendors.
3562 The commands shown in the previous section give standard parameters.
3563 There are also @emph{event handlers} associated with TAPs or Targets.
3564 Those handlers are Tcl procedures you can provide, which are invoked
3565 at particular points in the reset sequence.
3567 @emph{When SRST is not an option} you must set
3568 up a @code{reset-assert} event handler for your target.
3569 For example, some JTAG adapters don't include the SRST signal;
3570 and some boards have multiple targets, and you won't always
3571 want to reset everything at once.
3573 After configuring those mechanisms, you might still
3574 find your board doesn't start up or reset correctly.
3575 For example, maybe it needs a slightly different sequence
3576 of SRST and/or TRST manipulations, because of quirks that
3577 the @command{reset_config} mechanism doesn't address;
3578 or asserting both might trigger a stronger reset, which
3579 needs special attention.
3581 Experiment with lower level operations, such as @command{jtag_reset}
3582 and the @command{jtag arp_*} operations shown here,
3583 to find a sequence of operations that works.
3584 @xref{JTAG Commands}.
3585 When you find a working sequence, it can be used to override
3586 @command{jtag_init}, which fires during OpenOCD startup
3587 (@pxref{configurationstage,,Configuration Stage});
3588 or @command{init_reset}, which fires during reset processing.
3590 You might also want to provide some project-specific reset
3591 schemes. For example, on a multi-target board the standard
3592 @command{reset} command would reset all targets, but you
3593 may need the ability to reset only one target at time and
3594 thus want to avoid using the board-wide SRST signal.
3596 @deffn {Overridable Procedure} init_reset mode
3597 This is invoked near the beginning of the @command{reset} command,
3598 usually to provide as much of a cold (power-up) reset as practical.
3599 By default it is also invoked from @command{jtag_init} if
3600 the scan chain does not respond to pure JTAG operations.
3601 The @var{mode} parameter is the parameter given to the
3602 low level reset command (@option{halt},
3603 @option{init}, or @option{run}), @option{setup},
3604 or potentially some other value.
3606 The default implementation just invokes @command{jtag arp_init-reset}.
3607 Replacements will normally build on low level JTAG
3608 operations such as @command{jtag_reset}.
3609 Operations here must not address individual TAPs
3610 (or their associated targets)
3611 until the JTAG scan chain has first been verified to work.
3613 Implementations must have verified the JTAG scan chain before
3615 This is done by calling @command{jtag arp_init}
3616 (or @command{jtag arp_init-reset}).
3619 @deffn Command {jtag arp_init}
3620 This validates the scan chain using just the four
3621 standard JTAG signals (TMS, TCK, TDI, TDO).
3622 It starts by issuing a JTAG-only reset.
3623 Then it performs checks to verify that the scan chain configuration
3624 matches the TAPs it can observe.
3625 Those checks include checking IDCODE values for each active TAP,
3626 and verifying the length of their instruction registers using
3627 TAP @code{-ircapture} and @code{-irmask} values.
3628 If these tests all pass, TAP @code{setup} events are
3629 issued to all TAPs with handlers for that event.
3632 @deffn Command {jtag arp_init-reset}
3633 This uses TRST and SRST to try resetting
3634 everything on the JTAG scan chain
3635 (and anything else connected to SRST).
3636 It then invokes the logic of @command{jtag arp_init}.
3640 @node TAP Declaration
3641 @chapter TAP Declaration
3642 @cindex TAP declaration
3643 @cindex TAP configuration
3645 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3646 TAPs serve many roles, including:
3649 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3650 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3651 Others do it indirectly, making a CPU do it.
3652 @item @b{Program Download} Using the same CPU support GDB uses,
3653 you can initialize a DRAM controller, download code to DRAM, and then
3654 start running that code.
3655 @item @b{Boundary Scan} Most chips support boundary scan, which
3656 helps test for board assembly problems like solder bridges
3657 and missing connections.
3660 OpenOCD must know about the active TAPs on your board(s).
3661 Setting up the TAPs is the core task of your configuration files.
3662 Once those TAPs are set up, you can pass their names to code
3663 which sets up CPUs and exports them as GDB targets,
3664 probes flash memory, performs low-level JTAG operations, and more.
3666 @section Scan Chains
3669 TAPs are part of a hardware @dfn{scan chain},
3670 which is a daisy chain of TAPs.
3671 They also need to be added to
3672 OpenOCD's software mirror of that hardware list,
3673 giving each member a name and associating other data with it.
3674 Simple scan chains, with a single TAP, are common in
3675 systems with a single microcontroller or microprocessor.
3676 More complex chips may have several TAPs internally.
3677 Very complex scan chains might have a dozen or more TAPs:
3678 several in one chip, more in the next, and connecting
3679 to other boards with their own chips and TAPs.
3681 You can display the list with the @command{scan_chain} command.
3682 (Don't confuse this with the list displayed by the @command{targets}
3683 command, presented in the next chapter.
3684 That only displays TAPs for CPUs which are configured as
3686 Here's what the scan chain might look like for a chip more than one TAP:
3689 TapName Enabled IdCode Expected IrLen IrCap IrMask
3690 -- ------------------ ------- ---------- ---------- ----- ----- ------
3691 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3692 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3693 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3696 OpenOCD can detect some of that information, but not all
3697 of it. @xref{autoprobing,,Autoprobing}.
3698 Unfortunately, those TAPs can't always be autoconfigured,
3699 because not all devices provide good support for that.
3700 JTAG doesn't require supporting IDCODE instructions, and
3701 chips with JTAG routers may not link TAPs into the chain
3702 until they are told to do so.
3704 The configuration mechanism currently supported by OpenOCD
3705 requires explicit configuration of all TAP devices using
3706 @command{jtag newtap} commands, as detailed later in this chapter.
3707 A command like this would declare one tap and name it @code{chip1.cpu}:
3710 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3713 Each target configuration file lists the TAPs provided
3715 Board configuration files combine all the targets on a board,
3717 Note that @emph{the order in which TAPs are declared is very important.}
3718 That declaration order must match the order in the JTAG scan chain,
3719 both inside a single chip and between them.
3720 @xref{faqtaporder,,FAQ TAP Order}.
3722 For example, the STMicroelectronics STR912 chip has
3723 three separate TAPs@footnote{See the ST
3724 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3725 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3726 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3727 To configure those taps, @file{target/str912.cfg}
3728 includes commands something like this:
3731 jtag newtap str912 flash ... params ...
3732 jtag newtap str912 cpu ... params ...
3733 jtag newtap str912 bs ... params ...
3736 Actual config files typically use a variable such as @code{$_CHIPNAME}
3737 instead of literals like @option{str912}, to support more than one chip
3738 of each type. @xref{Config File Guidelines}.
3740 @deffn Command {jtag names}
3741 Returns the names of all current TAPs in the scan chain.
3742 Use @command{jtag cget} or @command{jtag tapisenabled}
3743 to examine attributes and state of each TAP.
3745 foreach t [jtag names] @{
3746 puts [format "TAP: %s\n" $t]
3751 @deffn Command {scan_chain}
3752 Displays the TAPs in the scan chain configuration,
3754 The set of TAPs listed by this command is fixed by
3755 exiting the OpenOCD configuration stage,
3756 but systems with a JTAG router can
3757 enable or disable TAPs dynamically.
3760 @c FIXME! "jtag cget" should be able to return all TAP
3761 @c attributes, like "$target_name cget" does for targets.
3763 @c Probably want "jtag eventlist", and a "tap-reset" event
3764 @c (on entry to RESET state).
3769 When TAP objects are declared with @command{jtag newtap},
3770 a @dfn{dotted.name} is created for the TAP, combining the
3771 name of a module (usually a chip) and a label for the TAP.
3772 For example: @code{xilinx.tap}, @code{str912.flash},
3773 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3774 Many other commands use that dotted.name to manipulate or
3775 refer to the TAP. For example, CPU configuration uses the
3776 name, as does declaration of NAND or NOR flash banks.
3778 The components of a dotted name should follow ``C'' symbol
3779 name rules: start with an alphabetic character, then numbers
3780 and underscores are OK; while others (including dots!) are not.
3782 @section TAP Declaration Commands
3784 @c shouldn't this be(come) a {Config Command}?
3785 @deffn Command {jtag newtap} chipname tapname configparams...
3786 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3787 and configured according to the various @var{configparams}.
3789 The @var{chipname} is a symbolic name for the chip.
3790 Conventionally target config files use @code{$_CHIPNAME},
3791 defaulting to the model name given by the chip vendor but
3794 @cindex TAP naming convention
3795 The @var{tapname} reflects the role of that TAP,
3796 and should follow this convention:
3799 @item @code{bs} -- For boundary scan if this is a separate TAP;
3800 @item @code{cpu} -- The main CPU of the chip, alternatively
3801 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3802 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3803 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3804 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3805 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3806 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3807 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3809 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3810 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3811 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3812 a JTAG TAP; that TAP should be named @code{sdma}.
3815 Every TAP requires at least the following @var{configparams}:
3818 @item @code{-irlen} @var{NUMBER}
3819 @*The length in bits of the
3820 instruction register, such as 4 or 5 bits.
3823 A TAP may also provide optional @var{configparams}:
3826 @item @code{-disable} (or @code{-enable})
3827 @*Use the @code{-disable} parameter to flag a TAP which is not
3828 linked into the scan chain after a reset using either TRST
3829 or the JTAG state machine's @sc{reset} state.
3830 You may use @code{-enable} to highlight the default state
3831 (the TAP is linked in).
3832 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3833 @item @code{-expected-id} @var{NUMBER}
3834 @*A non-zero @var{number} represents a 32-bit IDCODE
3835 which you expect to find when the scan chain is examined.
3836 These codes are not required by all JTAG devices.
3837 @emph{Repeat the option} as many times as required if more than one
3838 ID code could appear (for example, multiple versions).
3839 Specify @var{number} as zero to suppress warnings about IDCODE
3840 values that were found but not included in the list.
3842 Provide this value if at all possible, since it lets OpenOCD
3843 tell when the scan chain it sees isn't right. These values
3844 are provided in vendors' chip documentation, usually a technical
3845 reference manual. Sometimes you may need to probe the JTAG
3846 hardware to find these values.
3847 @xref{autoprobing,,Autoprobing}.
3848 @item @code{-ignore-version}
3849 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3850 option. When vendors put out multiple versions of a chip, or use the same
3851 JTAG-level ID for several largely-compatible chips, it may be more practical
3852 to ignore the version field than to update config files to handle all of
3853 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3854 @item @code{-ircapture} @var{NUMBER}
3855 @*The bit pattern loaded by the TAP into the JTAG shift register
3856 on entry to the @sc{ircapture} state, such as 0x01.
3857 JTAG requires the two LSBs of this value to be 01.
3858 By default, @code{-ircapture} and @code{-irmask} are set
3859 up to verify that two-bit value. You may provide
3860 additional bits if you know them, or indicate that
3861 a TAP doesn't conform to the JTAG specification.
3862 @item @code{-irmask} @var{NUMBER}
3863 @*A mask used with @code{-ircapture}
3864 to verify that instruction scans work correctly.
3865 Such scans are not used by OpenOCD except to verify that
3866 there seems to be no problems with JTAG scan chain operations.
3867 @item @code{-ignore-syspwrupack}
3868 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
3869 register during initial examination and when checking the sticky error bit.
3870 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
3871 devices do not set the ack bit until sometime later.
3875 @section Other TAP commands
3877 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3878 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3879 At this writing this TAP attribute
3880 mechanism is used only for event handling.
3881 (It is not a direct analogue of the @code{cget}/@code{configure}
3882 mechanism for debugger targets.)
3883 See the next section for information about the available events.
3885 The @code{configure} subcommand assigns an event handler,
3886 a TCL string which is evaluated when the event is triggered.
3887 The @code{cget} subcommand returns that handler.
3894 OpenOCD includes two event mechanisms.
3895 The one presented here applies to all JTAG TAPs.
3896 The other applies to debugger targets,
3897 which are associated with certain TAPs.
3899 The TAP events currently defined are:
3902 @item @b{post-reset}
3903 @* The TAP has just completed a JTAG reset.
3904 The tap may still be in the JTAG @sc{reset} state.
3905 Handlers for these events might perform initialization sequences
3906 such as issuing TCK cycles, TMS sequences to ensure
3907 exit from the ARM SWD mode, and more.
3909 Because the scan chain has not yet been verified, handlers for these events
3910 @emph{should not issue commands which scan the JTAG IR or DR registers}
3911 of any particular target.
3912 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3914 @* The scan chain has been reset and verified.
3915 This handler may enable TAPs as needed.
3916 @item @b{tap-disable}
3917 @* The TAP needs to be disabled. This handler should
3918 implement @command{jtag tapdisable}
3919 by issuing the relevant JTAG commands.
3920 @item @b{tap-enable}
3921 @* The TAP needs to be enabled. This handler should
3922 implement @command{jtag tapenable}
3923 by issuing the relevant JTAG commands.
3926 If you need some action after each JTAG reset which isn't actually
3927 specific to any TAP (since you can't yet trust the scan chain's
3928 contents to be accurate), you might:
3931 jtag configure CHIP.jrc -event post-reset @{
3932 echo "JTAG Reset done"
3933 ... non-scan jtag operations to be done after reset
3938 @anchor{enablinganddisablingtaps}
3939 @section Enabling and Disabling TAPs
3940 @cindex JTAG Route Controller
3943 In some systems, a @dfn{JTAG Route Controller} (JRC)
3944 is used to enable and/or disable specific JTAG TAPs.
3945 Many ARM-based chips from Texas Instruments include
3946 an ``ICEPick'' module, which is a JRC.
3947 Such chips include DaVinci and OMAP3 processors.
3949 A given TAP may not be visible until the JRC has been
3950 told to link it into the scan chain; and if the JRC
3951 has been told to unlink that TAP, it will no longer
3953 Such routers address problems that JTAG ``bypass mode''
3957 @item The scan chain can only go as fast as its slowest TAP.
3958 @item Having many TAPs slows instruction scans, since all
3959 TAPs receive new instructions.
3960 @item TAPs in the scan chain must be powered up, which wastes
3961 power and prevents debugging some power management mechanisms.
3964 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3965 as implied by the existence of JTAG routers.
3966 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3967 does include a kind of JTAG router functionality.
3969 @c (a) currently the event handlers don't seem to be able to
3970 @c fail in a way that could lead to no-change-of-state.
3972 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3973 shown below, and is implemented using TAP event handlers.
3974 So for example, when defining a TAP for a CPU connected to
3975 a JTAG router, your @file{target.cfg} file
3976 should define TAP event handlers using
3977 code that looks something like this:
3980 jtag configure CHIP.cpu -event tap-enable @{
3981 ... jtag operations using CHIP.jrc
3983 jtag configure CHIP.cpu -event tap-disable @{
3984 ... jtag operations using CHIP.jrc
3988 Then you might want that CPU's TAP enabled almost all the time:
3991 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3994 Note how that particular setup event handler declaration
3995 uses quotes to evaluate @code{$CHIP} when the event is configured.
3996 Using brackets @{ @} would cause it to be evaluated later,
3997 at runtime, when it might have a different value.
3999 @deffn Command {jtag tapdisable} dotted.name
4000 If necessary, disables the tap
4001 by sending it a @option{tap-disable} event.
4002 Returns the string "1" if the tap
4003 specified by @var{dotted.name} is enabled,
4004 and "0" if it is disabled.
4007 @deffn Command {jtag tapenable} dotted.name
4008 If necessary, enables the tap
4009 by sending it a @option{tap-enable} event.
4010 Returns the string "1" if the tap
4011 specified by @var{dotted.name} is enabled,
4012 and "0" if it is disabled.
4015 @deffn Command {jtag tapisenabled} dotted.name
4016 Returns the string "1" if the tap
4017 specified by @var{dotted.name} is enabled,
4018 and "0" if it is disabled.
4021 Humans will find the @command{scan_chain} command more helpful
4022 for querying the state of the JTAG taps.
4026 @anchor{autoprobing}
4027 @section Autoprobing
4029 @cindex JTAG autoprobe
4031 TAP configuration is the first thing that needs to be done
4032 after interface and reset configuration. Sometimes it's
4033 hard finding out what TAPs exist, or how they are identified.
4034 Vendor documentation is not always easy to find and use.
4036 To help you get past such problems, OpenOCD has a limited
4037 @emph{autoprobing} ability to look at the scan chain, doing
4038 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4039 To use this mechanism, start the OpenOCD server with only data
4040 that configures your JTAG interface, and arranges to come up
4041 with a slow clock (many devices don't support fast JTAG clocks
4042 right when they come out of reset).
4044 For example, your @file{openocd.cfg} file might have:
4047 source [find interface/olimex-arm-usb-tiny-h.cfg]
4048 reset_config trst_and_srst
4052 When you start the server without any TAPs configured, it will
4053 attempt to autoconfigure the TAPs. There are two parts to this:
4056 @item @emph{TAP discovery} ...
4057 After a JTAG reset (sometimes a system reset may be needed too),
4058 each TAP's data registers will hold the contents of either the
4059 IDCODE or BYPASS register.
4060 If JTAG communication is working, OpenOCD will see each TAP,
4061 and report what @option{-expected-id} to use with it.
4062 @item @emph{IR Length discovery} ...
4063 Unfortunately JTAG does not provide a reliable way to find out
4064 the value of the @option{-irlen} parameter to use with a TAP
4066 If OpenOCD can discover the length of a TAP's instruction
4067 register, it will report it.
4068 Otherwise you may need to consult vendor documentation, such
4069 as chip data sheets or BSDL files.
4072 In many cases your board will have a simple scan chain with just
4073 a single device. Here's what OpenOCD reported with one board
4074 that's a bit more complex:
4078 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4079 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4080 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4081 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4082 AUTO auto0.tap - use "... -irlen 4"
4083 AUTO auto1.tap - use "... -irlen 4"
4084 AUTO auto2.tap - use "... -irlen 6"
4085 no gdb ports allocated as no target has been specified
4088 Given that information, you should be able to either find some existing
4089 config files to use, or create your own. If you create your own, you
4090 would configure from the bottom up: first a @file{target.cfg} file
4091 with these TAPs, any targets associated with them, and any on-chip
4092 resources; then a @file{board.cfg} with off-chip resources, clocking,
4095 @anchor{dapdeclaration}
4096 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4097 @cindex DAP declaration
4099 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4100 no longer implicitly created together with the target. It must be
4101 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4102 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4103 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4105 The @command{dap} command group supports the following sub-commands:
4107 @deffn Command {dap create} dap_name @option{-chain-position} dotted.name configparams...
4108 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4109 @var{dotted.name}. This also creates a new command (@command{dap_name})
4110 which is used for various purposes including additional configuration.
4111 There can only be one DAP for each JTAG tap in the system.
4113 A DAP may also provide optional @var{configparams}:
4116 @item @code{-ignore-syspwrupack}
4117 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4118 register during initial examination and when checking the sticky error bit.
4119 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4120 devices do not set the ack bit until sometime later.
4124 @deffn Command {dap names}
4125 This command returns a list of all registered DAP objects. It it useful mainly
4129 @deffn Command {dap info} [num]
4130 Displays the ROM table for MEM-AP @var{num},
4131 defaulting to the currently selected AP of the currently selected target.
4134 @deffn Command {dap init}
4135 Initialize all registered DAPs. This command is used internally
4136 during initialization. It can be issued at any time after the
4137 initialization, too.
4140 The following commands exist as subcommands of DAP instances:
4142 @deffn Command {$dap_name info} [num]
4143 Displays the ROM table for MEM-AP @var{num},
4144 defaulting to the currently selected AP.
4147 @deffn Command {$dap_name apid} [num]
4148 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4151 @anchor{DAP subcommand apreg}
4152 @deffn Command {$dap_name apreg} ap_num reg [value]
4153 Displays content of a register @var{reg} from AP @var{ap_num}
4154 or set a new value @var{value}.
4155 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4158 @deffn Command {$dap_name apsel} [num]
4159 Select AP @var{num}, defaulting to 0.
4162 @deffn Command {$dap_name dpreg} reg [value]
4163 Displays the content of DP register at address @var{reg}, or set it to a new
4166 In case of SWD, @var{reg} is a value in packed format
4167 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4168 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4170 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4171 background activity by OpenOCD while you are operating at such low-level.
4174 @deffn Command {$dap_name baseaddr} [num]
4175 Displays debug base address from MEM-AP @var{num},
4176 defaulting to the currently selected AP.
4179 @deffn Command {$dap_name memaccess} [value]
4180 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4181 memory bus access [0-255], giving additional time to respond to reads.
4182 If @var{value} is defined, first assigns that.
4185 @deffn Command {$dap_name apcsw} [value [mask]]
4186 Displays or changes CSW bit pattern for MEM-AP transfers.
4188 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4189 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4190 and the result is written to the real CSW register. All bits except dynamically
4191 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4192 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4195 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4196 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4199 kx.dap apcsw 0x2000000
4202 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4203 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4204 and leaves the rest of the pattern intact. It configures memory access through
4205 DCache on Cortex-M7.
4207 set CSW_HPROT3_CACHEABLE [expr 1 << 27]
4208 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4211 Another example clears SPROT bit and leaves the rest of pattern intact:
4213 set CSW_SPROT [expr 1 << 30]
4214 samv.dap apcsw 0 $CSW_SPROT
4217 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4218 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4220 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4221 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4222 example with a proper dap name:
4224 xxx.dap apcsw default
4228 @deffn Command {$dap_name ti_be_32_quirks} [@option{enable}]
4229 Set/get quirks mode for TI TMS450/TMS570 processors
4234 @node CPU Configuration
4235 @chapter CPU Configuration
4238 This chapter discusses how to set up GDB debug targets for CPUs.
4239 You can also access these targets without GDB
4240 (@pxref{Architecture and Core Commands},
4241 and @ref{targetstatehandling,,Target State handling}) and
4242 through various kinds of NAND and NOR flash commands.
4243 If you have multiple CPUs you can have multiple such targets.
4245 We'll start by looking at how to examine the targets you have,
4246 then look at how to add one more target and how to configure it.
4248 @section Target List
4249 @cindex target, current
4250 @cindex target, list
4252 All targets that have been set up are part of a list,
4253 where each member has a name.
4254 That name should normally be the same as the TAP name.
4255 You can display the list with the @command{targets}
4257 This display often has only one CPU; here's what it might
4258 look like with more than one:
4260 TargetName Type Endian TapName State
4261 -- ------------------ ---------- ------ ------------------ ------------
4262 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4263 1 MyTarget cortex_m little mychip.foo tap-disabled
4266 One member of that list is the @dfn{current target}, which
4267 is implicitly referenced by many commands.
4268 It's the one marked with a @code{*} near the target name.
4269 In particular, memory addresses often refer to the address
4270 space seen by that current target.
4271 Commands like @command{mdw} (memory display words)
4272 and @command{flash erase_address} (erase NOR flash blocks)
4273 are examples; and there are many more.
4275 Several commands let you examine the list of targets:
4277 @deffn Command {target current}
4278 Returns the name of the current target.
4281 @deffn Command {target names}
4282 Lists the names of all current targets in the list.
4284 foreach t [target names] @{
4285 puts [format "Target: %s\n" $t]
4290 @c yep, "target list" would have been better.
4291 @c plus maybe "target setdefault".
4293 @deffn Command targets [name]
4294 @emph{Note: the name of this command is plural. Other target
4295 command names are singular.}
4297 With no parameter, this command displays a table of all known
4298 targets in a user friendly form.
4300 With a parameter, this command sets the current target to
4301 the given target with the given @var{name}; this is
4302 only relevant on boards which have more than one target.
4305 @section Target CPU Types
4309 Each target has a @dfn{CPU type}, as shown in the output of
4310 the @command{targets} command. You need to specify that type
4311 when calling @command{target create}.
4312 The CPU type indicates more than just the instruction set.
4313 It also indicates how that instruction set is implemented,
4314 what kind of debug support it integrates,
4315 whether it has an MMU (and if so, what kind),
4316 what core-specific commands may be available
4317 (@pxref{Architecture and Core Commands}),
4320 It's easy to see what target types are supported,
4321 since there's a command to list them.
4323 @anchor{targettypes}
4324 @deffn Command {target types}
4325 Lists all supported target types.
4326 At this writing, the supported CPU types are:
4329 @item @code{arm11} -- this is a generation of ARMv6 cores
4330 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4331 @item @code{arm7tdmi} -- this is an ARMv4 core
4332 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4333 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4334 @item @code{arm966e} -- this is an ARMv5 core
4335 @item @code{arm9tdmi} -- this is an ARMv4 core
4336 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4337 (Support for this is preliminary and incomplete.)
4338 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4339 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4340 compact Thumb2 instruction set.
4341 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4342 @item @code{dragonite} -- resembles arm966e
4343 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4344 (Support for this is still incomplete.)
4345 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4346 The current implementation supports eSi-32xx cores.
4347 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4348 @item @code{feroceon} -- resembles arm926
4349 @item @code{mips_m4k} -- a MIPS core
4350 @item @code{xscale} -- this is actually an architecture,
4351 not a CPU type. It is based on the ARMv5 architecture.
4352 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4353 The current implementation supports three JTAG TAP cores:
4354 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4355 allowing access to physical memory addresses independently of CPU cores.
4357 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4358 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4359 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4361 And two debug interfaces cores:
4363 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4364 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4369 To avoid being confused by the variety of ARM based cores, remember
4370 this key point: @emph{ARM is a technology licencing company}.
4371 (See: @url{http://www.arm.com}.)
4372 The CPU name used by OpenOCD will reflect the CPU design that was
4373 licensed, not a vendor brand which incorporates that design.
4374 Name prefixes like arm7, arm9, arm11, and cortex
4375 reflect design generations;
4376 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4377 reflect an architecture version implemented by a CPU design.
4379 @anchor{targetconfiguration}
4380 @section Target Configuration
4382 Before creating a ``target'', you must have added its TAP to the scan chain.
4383 When you've added that TAP, you will have a @code{dotted.name}
4384 which is used to set up the CPU support.
4385 The chip-specific configuration file will normally configure its CPU(s)
4386 right after it adds all of the chip's TAPs to the scan chain.
4388 Although you can set up a target in one step, it's often clearer if you
4389 use shorter commands and do it in two steps: create it, then configure
4391 All operations on the target after it's created will use a new
4392 command, created as part of target creation.
4394 The two main things to configure after target creation are
4395 a work area, which usually has target-specific defaults even
4396 if the board setup code overrides them later;
4397 and event handlers (@pxref{targetevents,,Target Events}), which tend
4398 to be much more board-specific.
4399 The key steps you use might look something like this
4402 dap create mychip.dap -chain-position mychip.cpu
4403 target create MyTarget cortex_m -dap mychip.dap
4404 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4405 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4406 MyTarget configure -event reset-init @{ myboard_reinit @}
4409 You should specify a working area if you can; typically it uses some
4411 Such a working area can speed up many things, including bulk
4412 writes to target memory;
4413 flash operations like checking to see if memory needs to be erased;
4414 GDB memory checksumming;
4418 On more complex chips, the work area can become
4419 inaccessible when application code
4420 (such as an operating system)
4421 enables or disables the MMU.
4422 For example, the particular MMU context used to access the virtual
4423 address will probably matter ... and that context might not have
4424 easy access to other addresses needed.
4425 At this writing, OpenOCD doesn't have much MMU intelligence.
4428 It's often very useful to define a @code{reset-init} event handler.
4429 For systems that are normally used with a boot loader,
4430 common tasks include updating clocks and initializing memory
4432 That may be needed to let you write the boot loader into flash,
4433 in order to ``de-brick'' your board; or to load programs into
4434 external DDR memory without having run the boot loader.
4436 @deffn Command {target create} target_name type configparams...
4437 This command creates a GDB debug target that refers to a specific JTAG tap.
4438 It enters that target into a list, and creates a new
4439 command (@command{@var{target_name}}) which is used for various
4440 purposes including additional configuration.
4443 @item @var{target_name} ... is the name of the debug target.
4444 By convention this should be the same as the @emph{dotted.name}
4445 of the TAP associated with this target, which must be specified here
4446 using the @code{-chain-position @var{dotted.name}} configparam.
4448 This name is also used to create the target object command,
4449 referred to here as @command{$target_name},
4450 and in other places the target needs to be identified.
4451 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4452 @item @var{configparams} ... all parameters accepted by
4453 @command{$target_name configure} are permitted.
4454 If the target is big-endian, set it here with @code{-endian big}.
4456 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
4457 @code{-dap @var{dap_name}} here.
4461 @deffn Command {$target_name configure} configparams...
4462 The options accepted by this command may also be
4463 specified as parameters to @command{target create}.
4464 Their values can later be queried one at a time by
4465 using the @command{$target_name cget} command.
4467 @emph{Warning:} changing some of these after setup is dangerous.
4468 For example, moving a target from one TAP to another;
4469 and changing its endianness.
4473 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4474 used to access this target.
4476 @item @code{-dap} @var{dap_name} -- names the DAP used to access
4477 this target. @xref{dapdeclaration,,DAP declaration}, on how to
4478 create and manage DAP instances.
4480 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4481 whether the CPU uses big or little endian conventions
4483 @item @code{-event} @var{event_name} @var{event_body} --
4484 @xref{targetevents,,Target Events}.
4485 Note that this updates a list of named event handlers.
4486 Calling this twice with two different event names assigns
4487 two different handlers, but calling it twice with the
4488 same event name assigns only one handler.
4490 Current target is temporarily overridden to the event issuing target
4491 before handler code starts and switched back after handler is done.
4493 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4494 whether the work area gets backed up; by default,
4495 @emph{it is not backed up.}
4496 When possible, use a working_area that doesn't need to be backed up,
4497 since performing a backup slows down operations.
4498 For example, the beginning of an SRAM block is likely to
4499 be used by most build systems, but the end is often unused.
4501 @item @code{-work-area-size} @var{size} -- specify work are size,
4502 in bytes. The same size applies regardless of whether its physical
4503 or virtual address is being used.
4505 @item @code{-work-area-phys} @var{address} -- set the work area
4506 base @var{address} to be used when no MMU is active.
4508 @item @code{-work-area-virt} @var{address} -- set the work area
4509 base @var{address} to be used when an MMU is active.
4510 @emph{Do not specify a value for this except on targets with an MMU.}
4511 The value should normally correspond to a static mapping for the
4512 @code{-work-area-phys} address, set up by the current operating system.
4515 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4516 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4517 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4518 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
4519 @xref{gdbrtossupport,,RTOS Support}.
4521 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4522 scan and after a reset. A manual call to arp_examine is required to
4523 access the target for debugging.
4525 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4526 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4527 Use this option with systems where multiple, independent cores are connected
4528 to separate access ports of the same DAP.
4530 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
4531 to the target. Currently, only the @code{aarch64} target makes use of this option,
4532 where it is a mandatory configuration for the target run control.
4533 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
4534 for instruction on how to declare and control a CTI instance.
4536 @anchor{gdbportoverride}
4537 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
4538 possible values of the parameter @var{number}, which are not only numeric values.
4539 Use this option to override, for this target only, the global parameter set with
4540 command @command{gdb_port}.
4541 @xref{gdb_port,,command gdb_port}.
4545 @section Other $target_name Commands
4546 @cindex object command
4548 The Tcl/Tk language has the concept of object commands,
4549 and OpenOCD adopts that same model for targets.
4551 A good Tk example is a on screen button.
4552 Once a button is created a button
4553 has a name (a path in Tk terms) and that name is useable as a first
4554 class command. For example in Tk, one can create a button and later
4555 configure it like this:
4559 button .foobar -background red -command @{ foo @}
4561 .foobar configure -foreground blue
4563 set x [.foobar cget -background]
4565 puts [format "The button is %s" $x]
4568 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4569 button, and its object commands are invoked the same way.
4572 str912.cpu mww 0x1234 0x42
4573 omap3530.cpu mww 0x5555 123
4576 The commands supported by OpenOCD target objects are:
4578 @deffn Command {$target_name arp_examine} @option{allow-defer}
4579 @deffnx Command {$target_name arp_halt}
4580 @deffnx Command {$target_name arp_poll}
4581 @deffnx Command {$target_name arp_reset}
4582 @deffnx Command {$target_name arp_waitstate}
4583 Internal OpenOCD scripts (most notably @file{startup.tcl})
4584 use these to deal with specific reset cases.
4585 They are not otherwise documented here.
4588 @deffn Command {$target_name array2mem} arrayname width address count
4589 @deffnx Command {$target_name mem2array} arrayname width address count
4590 These provide an efficient script-oriented interface to memory.
4591 The @code{array2mem} primitive writes bytes, halfwords, or words;
4592 while @code{mem2array} reads them.
4593 In both cases, the TCL side uses an array, and
4594 the target side uses raw memory.
4596 The efficiency comes from enabling the use of
4597 bulk JTAG data transfer operations.
4598 The script orientation comes from working with data
4599 values that are packaged for use by TCL scripts;
4600 @command{mdw} type primitives only print data they retrieve,
4601 and neither store nor return those values.
4604 @item @var{arrayname} ... is the name of an array variable
4605 @item @var{width} ... is 8/16/32 - indicating the memory access size
4606 @item @var{address} ... is the target memory address
4607 @item @var{count} ... is the number of elements to process
4611 @deffn Command {$target_name cget} queryparm
4612 Each configuration parameter accepted by
4613 @command{$target_name configure}
4614 can be individually queried, to return its current value.
4615 The @var{queryparm} is a parameter name
4616 accepted by that command, such as @code{-work-area-phys}.
4617 There are a few special cases:
4620 @item @code{-event} @var{event_name} -- returns the handler for the
4621 event named @var{event_name}.
4622 This is a special case because setting a handler requires
4624 @item @code{-type} -- returns the target type.
4625 This is a special case because this is set using
4626 @command{target create} and can't be changed
4627 using @command{$target_name configure}.
4630 For example, if you wanted to summarize information about
4631 all the targets you might use something like this:
4634 foreach name [target names] @{
4635 set y [$name cget -endian]
4636 set z [$name cget -type]
4637 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4643 @anchor{targetcurstate}
4644 @deffn Command {$target_name curstate}
4645 Displays the current target state:
4646 @code{debug-running},
4649 @code{running}, or @code{unknown}.
4650 (Also, @pxref{eventpolling,,Event Polling}.)
4653 @deffn Command {$target_name eventlist}
4654 Displays a table listing all event handlers
4655 currently associated with this target.
4656 @xref{targetevents,,Target Events}.
4659 @deffn Command {$target_name invoke-event} event_name
4660 Invokes the handler for the event named @var{event_name}.
4661 (This is primarily intended for use by OpenOCD framework
4662 code, for example by the reset code in @file{startup.tcl}.)
4665 @deffn Command {$target_name mdw} addr [count]
4666 @deffnx Command {$target_name mdh} addr [count]
4667 @deffnx Command {$target_name mdb} addr [count]
4668 Display contents of address @var{addr}, as
4669 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4670 or 8-bit bytes (@command{mdb}).
4671 If @var{count} is specified, displays that many units.
4672 (If you want to manipulate the data instead of displaying it,
4673 see the @code{mem2array} primitives.)
4676 @deffn Command {$target_name mww} addr word
4677 @deffnx Command {$target_name mwh} addr halfword
4678 @deffnx Command {$target_name mwb} addr byte
4679 Writes the specified @var{word} (32 bits),
4680 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4681 at the specified address @var{addr}.
4684 @anchor{targetevents}
4685 @section Target Events
4686 @cindex target events
4688 At various times, certain things can happen, or you want them to happen.
4691 @item What should happen when GDB connects? Should your target reset?
4692 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4693 @item Is using SRST appropriate (and possible) on your system?
4694 Or instead of that, do you need to issue JTAG commands to trigger reset?
4695 SRST usually resets everything on the scan chain, which can be inappropriate.
4696 @item During reset, do you need to write to certain memory locations
4697 to set up system clocks or
4698 to reconfigure the SDRAM?
4699 How about configuring the watchdog timer, or other peripherals,
4700 to stop running while you hold the core stopped for debugging?
4703 All of the above items can be addressed by target event handlers.
4704 These are set up by @command{$target_name configure -event} or
4705 @command{target create ... -event}.
4707 The programmer's model matches the @code{-command} option used in Tcl/Tk
4708 buttons and events. The two examples below act the same, but one creates
4709 and invokes a small procedure while the other inlines it.
4712 proc my_init_proc @{ @} @{
4713 echo "Disabling watchdog..."
4714 mww 0xfffffd44 0x00008000
4716 mychip.cpu configure -event reset-init my_init_proc
4717 mychip.cpu configure -event reset-init @{
4718 echo "Disabling watchdog..."
4719 mww 0xfffffd44 0x00008000
4723 The following target events are defined:
4726 @item @b{debug-halted}
4727 @* The target has halted for debug reasons (i.e.: breakpoint)
4728 @item @b{debug-resumed}
4729 @* The target has resumed (i.e.: GDB said run)
4730 @item @b{early-halted}
4731 @* Occurs early in the halt process
4732 @item @b{examine-start}
4733 @* Before target examine is called.
4734 @item @b{examine-end}
4735 @* After target examine is called with no errors.
4736 @item @b{gdb-attach}
4737 @* When GDB connects. Issued before any GDB communication with the target
4738 starts. GDB expects the target is halted during attachment.
4739 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
4740 connect GDB to running target.
4741 The event can be also used to set up the target so it is possible to probe flash.
4742 Probing flash is necessary during GDB connect if you want to use
4743 @pxref{programmingusinggdb,,programming using GDB}.
4744 Another use of the flash memory map is for GDB to automatically choose
4745 hardware or software breakpoints depending on whether the breakpoint
4746 is in RAM or read only memory.
4747 Default is @code{halt}
4748 @item @b{gdb-detach}
4749 @* When GDB disconnects
4751 @* When the target has halted and GDB is not doing anything (see early halt)
4752 @item @b{gdb-flash-erase-start}
4753 @* Before the GDB flash process tries to erase the flash (default is
4755 @item @b{gdb-flash-erase-end}
4756 @* After the GDB flash process has finished erasing the flash
4757 @item @b{gdb-flash-write-start}
4758 @* Before GDB writes to the flash
4759 @item @b{gdb-flash-write-end}
4760 @* After GDB writes to the flash (default is @code{reset halt})
4762 @* Before the target steps, GDB is trying to start/resume the target
4764 @* The target has halted
4765 @item @b{reset-assert-pre}
4766 @* Issued as part of @command{reset} processing
4767 after @command{reset-start} was triggered
4768 but before either SRST alone is asserted on the scan chain,
4769 or @code{reset-assert} is triggered.
4770 @item @b{reset-assert}
4771 @* Issued as part of @command{reset} processing
4772 after @command{reset-assert-pre} was triggered.
4773 When such a handler is present, cores which support this event will use
4774 it instead of asserting SRST.
4775 This support is essential for debugging with JTAG interfaces which
4776 don't include an SRST line (JTAG doesn't require SRST), and for
4777 selective reset on scan chains that have multiple targets.
4778 @item @b{reset-assert-post}
4779 @* Issued as part of @command{reset} processing
4780 after @code{reset-assert} has been triggered.
4781 or the target asserted SRST on the entire scan chain.
4782 @item @b{reset-deassert-pre}
4783 @* Issued as part of @command{reset} processing
4784 after @code{reset-assert-post} has been triggered.
4785 @item @b{reset-deassert-post}
4786 @* Issued as part of @command{reset} processing
4787 after @code{reset-deassert-pre} has been triggered
4788 and (if the target is using it) after SRST has been
4789 released on the scan chain.
4791 @* Issued as the final step in @command{reset} processing.
4792 @item @b{reset-init}
4793 @* Used by @b{reset init} command for board-specific initialization.
4794 This event fires after @emph{reset-deassert-post}.
4796 This is where you would configure PLLs and clocking, set up DRAM so
4797 you can download programs that don't fit in on-chip SRAM, set up pin
4798 multiplexing, and so on.
4799 (You may be able to switch to a fast JTAG clock rate here, after
4800 the target clocks are fully set up.)
4801 @item @b{reset-start}
4802 @* Issued as the first step in @command{reset} processing
4803 before @command{reset-assert-pre} is called.
4805 This is the most robust place to use @command{jtag_rclk}
4806 or @command{adapter_khz} to switch to a low JTAG clock rate,
4807 when reset disables PLLs needed to use a fast clock.
4808 @item @b{resume-start}
4809 @* Before any target is resumed
4810 @item @b{resume-end}
4811 @* After all targets have resumed
4813 @* Target has resumed
4814 @item @b{trace-config}
4815 @* After target hardware trace configuration was changed
4818 @node Flash Commands
4819 @chapter Flash Commands
4821 OpenOCD has different commands for NOR and NAND flash;
4822 the ``flash'' command works with NOR flash, while
4823 the ``nand'' command works with NAND flash.
4824 This partially reflects different hardware technologies:
4825 NOR flash usually supports direct CPU instruction and data bus access,
4826 while data from a NAND flash must be copied to memory before it can be
4827 used. (SPI flash must also be copied to memory before use.)
4828 However, the documentation also uses ``flash'' as a generic term;
4829 for example, ``Put flash configuration in board-specific files''.
4833 @item Configure via the command @command{flash bank}
4834 @* Do this in a board-specific configuration file,
4835 passing parameters as needed by the driver.
4836 @item Operate on the flash via @command{flash subcommand}
4837 @* Often commands to manipulate the flash are typed by a human, or run
4838 via a script in some automated way. Common tasks include writing a
4839 boot loader, operating system, or other data.
4841 @* Flashing via GDB requires the flash be configured via ``flash
4842 bank'', and the GDB flash features be enabled.
4843 @xref{gdbconfiguration,,GDB Configuration}.
4846 Many CPUs have the ability to ``boot'' from the first flash bank.
4847 This means that misprogramming that bank can ``brick'' a system,
4848 so that it can't boot.
4849 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4850 board by (re)installing working boot firmware.
4852 @anchor{norconfiguration}
4853 @section Flash Configuration Commands
4854 @cindex flash configuration
4856 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4857 Configures a flash bank which provides persistent storage
4858 for addresses from @math{base} to @math{base + size - 1}.
4859 These banks will often be visible to GDB through the target's memory map.
4860 In some cases, configuring a flash bank will activate extra commands;
4861 see the driver-specific documentation.
4864 @item @var{name} ... may be used to reference the flash bank
4865 in other flash commands. A number is also available.
4866 @item @var{driver} ... identifies the controller driver
4867 associated with the flash bank being declared.
4868 This is usually @code{cfi} for external flash, or else
4869 the name of a microcontroller with embedded flash memory.
4870 @xref{flashdriverlist,,Flash Driver List}.
4871 @item @var{base} ... Base address of the flash chip.
4872 @item @var{size} ... Size of the chip, in bytes.
4873 For some drivers, this value is detected from the hardware.
4874 @item @var{chip_width} ... Width of the flash chip, in bytes;
4875 ignored for most microcontroller drivers.
4876 @item @var{bus_width} ... Width of the data bus used to access the
4877 chip, in bytes; ignored for most microcontroller drivers.
4878 @item @var{target} ... Names the target used to issue
4879 commands to the flash controller.
4880 @comment Actually, it's currently a controller-specific parameter...
4881 @item @var{driver_options} ... drivers may support, or require,
4882 additional parameters. See the driver-specific documentation
4883 for more information.
4886 This command is not available after OpenOCD initialization has completed.
4887 Use it in board specific configuration files, not interactively.
4891 @comment the REAL name for this command is "ocd_flash_banks"
4892 @comment less confusing would be: "flash list" (like "nand list")
4893 @deffn Command {flash banks}
4894 Prints a one-line summary of each device that was
4895 declared using @command{flash bank}, numbered from zero.
4896 Note that this is the @emph{plural} form;
4897 the @emph{singular} form is a very different command.
4900 @deffn Command {flash list}
4901 Retrieves a list of associative arrays for each device that was
4902 declared using @command{flash bank}, numbered from zero.
4903 This returned list can be manipulated easily from within scripts.
4906 @deffn Command {flash probe} num
4907 Identify the flash, or validate the parameters of the configured flash. Operation
4908 depends on the flash type.
4909 The @var{num} parameter is a value shown by @command{flash banks}.
4910 Most flash commands will implicitly @emph{autoprobe} the bank;
4911 flash drivers can distinguish between probing and autoprobing,
4912 but most don't bother.
4915 @section Erasing, Reading, Writing to Flash
4916 @cindex flash erasing
4917 @cindex flash reading
4918 @cindex flash writing
4919 @cindex flash programming
4920 @anchor{flashprogrammingcommands}
4922 One feature distinguishing NOR flash from NAND or serial flash technologies
4923 is that for read access, it acts exactly like any other addressable memory.
4924 This means you can use normal memory read commands like @command{mdw} or
4925 @command{dump_image} with it, with no special @command{flash} subcommands.
4926 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4928 Write access works differently. Flash memory normally needs to be erased
4929 before it's written. Erasing a sector turns all of its bits to ones, and
4930 writing can turn ones into zeroes. This is why there are special commands
4931 for interactive erasing and writing, and why GDB needs to know which parts
4932 of the address space hold NOR flash memory.
4935 Most of these erase and write commands leverage the fact that NOR flash
4936 chips consume target address space. They implicitly refer to the current
4937 JTAG target, and map from an address in that target's address space
4938 back to a flash bank.
4939 @comment In May 2009, those mappings may fail if any bank associated
4940 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
4941 A few commands use abstract addressing based on bank and sector numbers,
4942 and don't depend on searching the current target and its address space.
4943 Avoid confusing the two command models.
4946 Some flash chips implement software protection against accidental writes,
4947 since such buggy writes could in some cases ``brick'' a system.
4948 For such systems, erasing and writing may require sector protection to be
4950 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4951 and AT91SAM7 on-chip flash.
4952 @xref{flashprotect,,flash protect}.
4954 @deffn Command {flash erase_sector} num first last
4955 Erase sectors in bank @var{num}, starting at sector @var{first}
4956 up to and including @var{last}.
4957 Sector numbering starts at 0.
4958 Providing a @var{last} sector of @option{last}
4959 specifies "to the end of the flash bank".
4960 The @var{num} parameter is a value shown by @command{flash banks}.
4963 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4964 Erase sectors starting at @var{address} for @var{length} bytes.
4965 Unless @option{pad} is specified, @math{address} must begin a
4966 flash sector, and @math{address + length - 1} must end a sector.
4967 Specifying @option{pad} erases extra data at the beginning and/or
4968 end of the specified region, as needed to erase only full sectors.
4969 The flash bank to use is inferred from the @var{address}, and
4970 the specified length must stay within that bank.
4971 As a special case, when @var{length} is zero and @var{address} is
4972 the start of the bank, the whole flash is erased.
4973 If @option{unlock} is specified, then the flash is unprotected
4974 before erase starts.
4977 @deffn Command {flash fillw} address word length
4978 @deffnx Command {flash fillh} address halfword length
4979 @deffnx Command {flash fillb} address byte length
4980 Fills flash memory with the specified @var{word} (32 bits),
4981 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4982 starting at @var{address} and continuing
4983 for @var{length} units (word/halfword/byte).
4984 No erasure is done before writing; when needed, that must be done
4985 before issuing this command.
4986 Writes are done in blocks of up to 1024 bytes, and each write is
4987 verified by reading back the data and comparing it to what was written.
4988 The flash bank to use is inferred from the @var{address} of
4989 each block, and the specified length must stay within that bank.
4991 @comment no current checks for errors if fill blocks touch multiple banks!
4993 @deffn Command {flash write_bank} num filename [offset]
4994 Write the binary @file{filename} to flash bank @var{num},
4995 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
4996 is omitted, start at the beginning of the flash bank.
4997 The @var{num} parameter is a value shown by @command{flash banks}.
5000 @deffn Command {flash read_bank} num filename [offset [length]]
5001 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5002 and write the contents to the binary @file{filename}. If @var{offset} is
5003 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5004 read the remaining bytes from the flash bank.
5005 The @var{num} parameter is a value shown by @command{flash banks}.
5008 @deffn Command {flash verify_bank} num filename [offset]
5009 Compare the contents of the binary file @var{filename} with the contents of the
5010 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5011 start at the beginning of the flash bank. Fail if the contents do not match.
5012 The @var{num} parameter is a value shown by @command{flash banks}.
5015 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
5016 Write the image @file{filename} to the current target's flash bank(s).
5017 Only loadable sections from the image are written.
5018 A relocation @var{offset} may be specified, in which case it is added
5019 to the base address for each section in the image.
5020 The file [@var{type}] can be specified
5021 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5022 @option{elf} (ELF file), @option{s19} (Motorola s19).
5023 @option{mem}, or @option{builder}.
5024 The relevant flash sectors will be erased prior to programming
5025 if the @option{erase} parameter is given. If @option{unlock} is
5026 provided, then the flash banks are unlocked before erase and
5027 program. The flash bank to use is inferred from the address of
5031 Be careful using the @option{erase} flag when the flash is holding
5032 data you want to preserve.
5033 Portions of the flash outside those described in the image's
5034 sections might be erased with no notice.
5037 When a section of the image being written does not fill out all the
5038 sectors it uses, the unwritten parts of those sectors are necessarily
5039 also erased, because sectors can't be partially erased.
5041 Data stored in sector "holes" between image sections are also affected.
5042 For example, "@command{flash write_image erase ...}" of an image with
5043 one byte at the beginning of a flash bank and one byte at the end
5044 erases the entire bank -- not just the two sectors being written.
5046 Also, when flash protection is important, you must re-apply it after
5047 it has been removed by the @option{unlock} flag.
5052 @section Other Flash commands
5053 @cindex flash protection
5055 @deffn Command {flash erase_check} num
5056 Check erase state of sectors in flash bank @var{num},
5057 and display that status.
5058 The @var{num} parameter is a value shown by @command{flash banks}.
5061 @deffn Command {flash info} num [sectors]
5062 Print info about flash bank @var{num}, a list of protection blocks
5063 and their status. Use @option{sectors} to show a list of sectors instead.
5065 The @var{num} parameter is a value shown by @command{flash banks}.
5066 This command will first query the hardware, it does not print cached
5067 and possibly stale information.
5070 @anchor{flashprotect}
5071 @deffn Command {flash protect} num first last (@option{on}|@option{off})
5072 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5073 in flash bank @var{num}, starting at protection block @var{first}
5074 and continuing up to and including @var{last}.
5075 Providing a @var{last} block of @option{last}
5076 specifies "to the end of the flash bank".
5077 The @var{num} parameter is a value shown by @command{flash banks}.
5078 The protection block is usually identical to a flash sector.
5079 Some devices may utilize a protection block distinct from flash sector.
5080 See @command{flash info} for a list of protection blocks.
5083 @deffn Command {flash padded_value} num value
5084 Sets the default value used for padding any image sections, This should
5085 normally match the flash bank erased value. If not specified by this
5086 command or the flash driver then it defaults to 0xff.
5090 @deffn Command {program} filename [verify] [reset] [exit] [offset]
5091 This is a helper script that simplifies using OpenOCD as a standalone
5092 programmer. The only required parameter is @option{filename}, the others are optional.
5093 @xref{Flash Programming}.
5096 @anchor{flashdriverlist}
5097 @section Flash Driver List
5098 As noted above, the @command{flash bank} command requires a driver name,
5099 and allows driver-specific options and behaviors.
5100 Some drivers also activate driver-specific commands.
5102 @deffn {Flash Driver} virtual
5103 This is a special driver that maps a previously defined bank to another
5104 address. All bank settings will be copied from the master physical bank.
5106 The @var{virtual} driver defines one mandatory parameters,
5109 @item @var{master_bank} The bank that this virtual address refers to.
5112 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5113 the flash bank defined at address 0x1fc00000. Any command executed on
5114 the virtual banks is actually performed on the physical banks.
5116 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5117 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5118 $_TARGETNAME $_FLASHNAME
5119 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5120 $_TARGETNAME $_FLASHNAME
5124 @subsection External Flash
5126 @deffn {Flash Driver} cfi
5127 @cindex Common Flash Interface
5129 The ``Common Flash Interface'' (CFI) is the main standard for
5130 external NOR flash chips, each of which connects to a
5131 specific external chip select on the CPU.
5132 Frequently the first such chip is used to boot the system.
5133 Your board's @code{reset-init} handler might need to
5134 configure additional chip selects using other commands (like: @command{mww} to
5135 configure a bus and its timings), or
5136 perhaps configure a GPIO pin that controls the ``write protect'' pin
5138 The CFI driver can use a target-specific working area to significantly
5141 The CFI driver can accept the following optional parameters, in any order:
5144 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5145 like AM29LV010 and similar types.
5146 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5147 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5148 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5149 swapped when writing data values (i.e. not CFI commands).
5152 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5153 wide on a sixteen bit bus:
5156 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5157 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5160 To configure one bank of 32 MBytes
5161 built from two sixteen bit (two byte) wide parts wired in parallel
5162 to create a thirty-two bit (four byte) bus with doubled throughput:
5165 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5168 @c "cfi part_id" disabled
5171 @deffn {Flash Driver} jtagspi
5172 @cindex Generic JTAG2SPI driver
5176 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5177 SPI flash connected to them. To access this flash from the host, the device
5178 is first programmed with a special proxy bitstream that
5179 exposes the SPI flash on the device's JTAG interface. The flash can then be
5180 accessed through JTAG.
5182 Since signaling between JTAG and SPI is compatible, all that is required for
5183 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5184 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5185 a bitstream for several Xilinx FPGAs can be found in
5186 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5187 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5189 This flash bank driver requires a target on a JTAG tap and will access that
5190 tap directly. Since no support from the target is needed, the target can be a
5191 "testee" dummy. Since the target does not expose the flash memory
5192 mapping, target commands that would otherwise be expected to access the flash
5193 will not work. These include all @command{*_image} and
5194 @command{$target_name m*} commands as well as @command{program}. Equivalent
5195 functionality is available through the @command{flash write_bank},
5196 @command{flash read_bank}, and @command{flash verify_bank} commands.
5199 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5200 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5201 @var{USER1} instruction.
5205 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5206 set _XILINX_USER1 0x02
5207 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5208 $_TARGETNAME $_XILINX_USER1
5212 @deffn {Flash Driver} xcf
5213 @cindex Xilinx Platform flash driver
5215 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5216 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5217 only difference is special registers controlling its FPGA specific behavior.
5218 They must be properly configured for successful FPGA loading using
5219 additional @var{xcf} driver command:
5221 @deffn Command {xcf ccb} <bank_id>
5222 command accepts additional parameters:
5224 @item @var{external|internal} ... selects clock source.
5225 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5226 @item @var{slave|master} ... selects slave of master mode for flash device.
5227 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5231 xcf ccb 0 external parallel slave 40
5233 All of them must be specified even if clock frequency is pointless
5234 in slave mode. If only bank id specified than command prints current
5235 CCB register value. Note: there is no need to write this register
5236 every time you erase/program data sectors because it stores in
5240 @deffn Command {xcf configure} <bank_id>
5241 Initiates FPGA loading procedure. Useful if your board has no "configure"
5248 Additional driver notes:
5250 @item Only single revision supported.
5251 @item Driver automatically detects need of bit reverse, but
5252 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
5253 (Intel hex) file types supported.
5254 @item For additional info check xapp972.pdf and ug380.pdf.
5258 @deffn {Flash Driver} lpcspifi
5259 @cindex NXP SPI Flash Interface
5262 NXP's LPC43xx and LPC18xx families include a proprietary SPI
5263 Flash Interface (SPIFI) peripheral that can drive and provide
5264 memory mapped access to external SPI flash devices.
5266 The lpcspifi driver initializes this interface and provides
5267 program and erase functionality for these serial flash devices.
5268 Use of this driver @b{requires} a working area of at least 1kB
5269 to be configured on the target device; more than this will
5270 significantly reduce flash programming times.
5272 The setup command only requires the @var{base} parameter. All
5273 other parameters are ignored, and the flash size and layout
5274 are configured by the driver.
5277 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
5282 @deffn {Flash Driver} stmsmi
5283 @cindex STMicroelectronics Serial Memory Interface
5286 Some devices from STMicroelectronics (e.g. STR75x MCU family,
5287 SPEAr MPU family) include a proprietary
5288 ``Serial Memory Interface'' (SMI) controller able to drive external
5290 Depending on specific device and board configuration, up to 4 external
5291 flash devices can be connected.
5293 SMI makes the flash content directly accessible in the CPU address
5294 space; each external device is mapped in a memory bank.
5295 CPU can directly read data, execute code and boot from SMI banks.
5296 Normal OpenOCD commands like @command{mdw} can be used to display
5299 The setup command only requires the @var{base} parameter in order
5300 to identify the memory bank.
5301 All other parameters are ignored. Additional information, like
5302 flash size, are detected automatically.
5305 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
5310 @deffn {Flash Driver} mrvlqspi
5311 This driver supports QSPI flash controller of Marvell's Wireless
5312 Microcontroller platform.
5314 The flash size is autodetected based on the table of known JEDEC IDs
5315 hardcoded in the OpenOCD sources.
5318 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5323 @deffn {Flash Driver} ath79
5324 @cindex Atheros ath79 SPI driver
5326 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5328 On reset a SPI flash connected to the first chip select (CS0) is made
5329 directly read-accessible in the CPU address space (up to 16MBytes)
5330 and is usually used to store the bootloader and operating system.
5331 Normal OpenOCD commands like @command{mdw} can be used to display
5332 the flash content while it is in memory-mapped mode (only the first
5333 4MBytes are accessible without additional configuration on reset).
5335 The setup command only requires the @var{base} parameter in order
5336 to identify the memory bank. The actual value for the base address
5337 is not otherwise used by the driver. However the mapping is passed
5338 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5339 address should be the actual memory mapped base address. For unmapped
5340 chipselects (CS1 and CS2) care should be taken to use a base address
5341 that does not overlap with real memory regions.
5342 Additional information, like flash size, are detected automatically.
5343 An optional additional parameter sets the chipselect for the bank,
5344 with the default CS0.
5345 CS1 and CS2 require additional GPIO setup before they can be used
5346 since the alternate function must be enabled on the GPIO pin
5347 CS1/CS2 is routed to on the given SoC.
5350 flash bank $_FLASHNAME ath79 0 0 0 0 $_TARGETNAME
5352 # When using multiple chipselects the base should be different for each,
5353 # otherwise the write_image command is not able to distinguish the
5355 flash bank flash0 ath79 0x00000000 0 0 0 $_TARGETNAME cs0
5356 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5357 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5362 @subsection Internal Flash (Microcontrollers)
5364 @deffn {Flash Driver} aduc702x
5365 The ADUC702x analog microcontrollers from Analog Devices
5366 include internal flash and use ARM7TDMI cores.
5367 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5368 The setup command only requires the @var{target} argument
5369 since all devices in this family have the same memory layout.
5372 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5376 @deffn {Flash Driver} ambiqmicro
5379 All members of the Apollo microcontroller family from
5380 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5381 The host connects over USB to an FTDI interface that communicates
5382 with the target using SWD.
5384 The @var{ambiqmicro} driver reads the Chip Information Register detect
5385 the device class of the MCU.
5386 The Flash and SRAM sizes directly follow device class, and are used
5387 to set up the flash banks.
5388 If this fails, the driver will use default values set to the minimum
5389 sizes of an Apollo chip.
5391 All Apollo chips have two flash banks of the same size.
5392 In all cases the first flash bank starts at location 0,
5393 and the second bank starts after the first.
5397 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5398 # Flash bank 1 - same size as bank0, starts after bank 0.
5399 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5403 Flash is programmed using custom entry points into the bootloader.
5404 This is the only way to program the flash as no flash control registers
5405 are available to the user.
5407 The @var{ambiqmicro} driver adds some additional commands:
5409 @deffn Command {ambiqmicro mass_erase} <bank>
5412 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5415 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5416 Program OTP is a one time operation to create write protected flash.
5417 The user writes sectors to SRAM starting at 0x10000010.
5418 Program OTP will write these sectors from SRAM to flash, and write protect
5424 @deffn {Flash Driver} at91samd
5426 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
5427 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5428 This driver uses the same command names/syntax as @xref{at91sam3}.
5430 @deffn Command {at91samd chip-erase}
5431 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5432 used to erase a chip back to its factory state and does not require the
5433 processor to be halted.
5436 @deffn Command {at91samd set-security}
5437 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5438 to the Flash and can only be undone by using the chip-erase command which
5439 erases the Flash contents and turns off the security bit. Warning: at this
5440 time, openocd will not be able to communicate with a secured chip and it is
5441 therefore not possible to chip-erase it without using another tool.
5444 at91samd set-security enable
5448 @deffn Command {at91samd eeprom}
5449 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5450 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5451 must be one of the permitted sizes according to the datasheet. Settings are
5452 written immediately but only take effect on MCU reset. EEPROM emulation
5453 requires additional firmware support and the minimum EEPROM size may not be
5454 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5455 in order to disable this feature.
5459 at91samd eeprom 1024
5463 @deffn Command {at91samd bootloader}
5464 Shows or sets the bootloader size configuration, stored in the User Row of the
5465 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5466 must be specified in bytes and it must be one of the permitted sizes according
5467 to the datasheet. Settings are written immediately but only take effect on
5468 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5472 at91samd bootloader 16384
5476 @deffn Command {at91samd dsu_reset_deassert}
5477 This command releases internal reset held by DSU
5478 and prepares reset vector catch in case of reset halt.
5479 Command is used internally in event event reset-deassert-post.
5482 @deffn Command {at91samd nvmuserrow}
5483 Writes or reads the entire 64 bit wide NVM user row register which is located at
5484 0x804000. This register includes various fuses lock-bits and factory calibration
5485 data. Reading the register is done by invoking this command without any
5486 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
5487 is the register value to be written and the second one is an optional changemask.
5488 Every bit which value in changemask is 0 will stay unchanged. The lock- and
5489 reserved-bits are masked out and cannot be changed.
5493 >at91samd nvmuserrow
5494 NVMUSERROW: 0xFFFFFC5DD8E0C788
5495 # Write 0xFFFFFC5DD8E0C788 to user row
5496 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
5497 # Write 0x12300 to user row but leave other bits and low byte unchanged
5498 >at91samd nvmuserrow 0x12345 0xFFF00
5505 @deffn {Flash Driver} at91sam3
5507 All members of the AT91SAM3 microcontroller family from
5508 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5509 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5510 that the driver was orginaly developed and tested using the
5511 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5512 the family was cribbed from the data sheet. @emph{Note to future
5513 readers/updaters: Please remove this worrisome comment after other
5514 chips are confirmed.}
5516 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5517 have one flash bank. In all cases the flash banks are at
5518 the following fixed locations:
5521 # Flash bank 0 - all chips
5522 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5523 # Flash bank 1 - only 256K chips
5524 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5527 Internally, the AT91SAM3 flash memory is organized as follows.
5528 Unlike the AT91SAM7 chips, these are not used as parameters
5529 to the @command{flash bank} command:
5532 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5533 @item @emph{Bank Size:} 128K/64K Per flash bank
5534 @item @emph{Sectors:} 16 or 8 per bank
5535 @item @emph{SectorSize:} 8K Per Sector
5536 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5539 The AT91SAM3 driver adds some additional commands:
5541 @deffn Command {at91sam3 gpnvm}
5542 @deffnx Command {at91sam3 gpnvm clear} number
5543 @deffnx Command {at91sam3 gpnvm set} number
5544 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5545 With no parameters, @command{show} or @command{show all},
5546 shows the status of all GPNVM bits.
5547 With @command{show} @var{number}, displays that bit.
5549 With @command{set} @var{number} or @command{clear} @var{number},
5550 modifies that GPNVM bit.
5553 @deffn Command {at91sam3 info}
5554 This command attempts to display information about the AT91SAM3
5555 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5556 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5557 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5558 various clock configuration registers and attempts to display how it
5559 believes the chip is configured. By default, the SLOWCLK is assumed to
5560 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5563 @deffn Command {at91sam3 slowclk} [value]
5564 This command shows/sets the slow clock frequency used in the
5565 @command{at91sam3 info} command calculations above.
5569 @deffn {Flash Driver} at91sam4
5571 All members of the AT91SAM4 microcontroller family from
5572 Atmel include internal flash and use ARM's Cortex-M4 core.
5573 This driver uses the same command names/syntax as @xref{at91sam3}.
5576 @deffn {Flash Driver} at91sam4l
5578 All members of the AT91SAM4L microcontroller family from
5579 Atmel include internal flash and use ARM's Cortex-M4 core.
5580 This driver uses the same command names/syntax as @xref{at91sam3}.
5582 The AT91SAM4L driver adds some additional commands:
5583 @deffn Command {at91sam4l smap_reset_deassert}
5584 This command releases internal reset held by SMAP
5585 and prepares reset vector catch in case of reset halt.
5586 Command is used internally in event event reset-deassert-post.
5590 @deffn {Flash Driver} atsamv
5592 All members of the ATSAMV, ATSAMS, and ATSAME families from
5593 Atmel include internal flash and use ARM's Cortex-M7 core.
5594 This driver uses the same command names/syntax as @xref{at91sam3}.
5597 @deffn {Flash Driver} at91sam7
5598 All members of the AT91SAM7 microcontroller family from Atmel include
5599 internal flash and use ARM7TDMI cores. The driver automatically
5600 recognizes a number of these chips using the chip identification
5601 register, and autoconfigures itself.
5604 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5607 For chips which are not recognized by the controller driver, you must
5608 provide additional parameters in the following order:
5611 @item @var{chip_model} ... label used with @command{flash info}
5613 @item @var{sectors_per_bank}
5614 @item @var{pages_per_sector}
5615 @item @var{pages_size}
5616 @item @var{num_nvm_bits}
5617 @item @var{freq_khz} ... required if an external clock is provided,
5618 optional (but recommended) when the oscillator frequency is known
5621 It is recommended that you provide zeroes for all of those values
5622 except the clock frequency, so that everything except that frequency
5623 will be autoconfigured.
5624 Knowing the frequency helps ensure correct timings for flash access.
5626 The flash controller handles erases automatically on a page (128/256 byte)
5627 basis, so explicit erase commands are not necessary for flash programming.
5628 However, there is an ``EraseAll`` command that can erase an entire flash
5629 plane (of up to 256KB), and it will be used automatically when you issue
5630 @command{flash erase_sector} or @command{flash erase_address} commands.
5632 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5633 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5634 bit for the processor. Each processor has a number of such bits,
5635 used for controlling features such as brownout detection (so they
5636 are not truly general purpose).
5638 This assumes that the first flash bank (number 0) is associated with
5639 the appropriate at91sam7 target.
5644 @deffn {Flash Driver} avr
5645 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5646 @emph{The current implementation is incomplete.}
5647 @comment - defines mass_erase ... pointless given flash_erase_address
5650 @deffn {Flash Driver} bluenrg-x
5651 STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
5652 The driver automatically recognizes these chips using
5653 the chip identification registers, and autoconfigures itself.
5656 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
5659 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
5660 each single sector one by one.
5663 flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
5667 flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
5670 Triggering a mass erase is also useful when users want to disable readout protection.
5673 @deffn {Flash Driver} cc26xx
5674 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
5675 Instruments include internal flash. The cc26xx flash driver supports both the
5676 CC13xx and CC26xx family of devices. The driver automatically recognizes the
5677 specific version's flash parameters and autoconfigures itself. The flash bank
5678 starts at address 0.
5681 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
5685 @deffn {Flash Driver} cc3220sf
5686 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
5687 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
5688 supports the internal flash. The serial flash on SimpleLink boards is
5689 programmed via the bootloader over a UART connection. Security features of
5690 the CC3220SF may erase the internal flash during power on reset. Refer to
5691 documentation at @url{www.ti.com/cc3220sf} for details on security features
5692 and programming the serial flash.
5695 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
5699 @deffn {Flash Driver} efm32
5700 All members of the EFM32 microcontroller family from Energy Micro include
5701 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5702 a number of these chips using the chip identification register, and
5703 autoconfigures itself.
5705 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5707 A special feature of efm32 controllers is that it is possible to completely disable the
5708 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5709 this via the following command:
5713 The @var{num} parameter is a value shown by @command{flash banks}.
5714 Note that in order for this command to take effect, the target needs to be reset.
5715 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5719 @deffn {Flash Driver} esirisc
5720 Members of the eSi-RISC family may optionally include internal flash programmed
5721 via the eSi-TSMC Flash interface. Additional parameters are required to
5722 configure the driver: @option{cfg_address} is the base address of the
5723 configuration register interface, @option{clock_hz} is the expected clock
5724 frequency, and @option{wait_states} is the number of configured read wait states.
5727 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
5728 $_TARGETNAME cfg_address clock_hz wait_states
5731 @deffn Command {esirisc flash mass_erase} bank_id
5732 Erase all pages in data memory for the bank identified by @option{bank_id}.
5735 @deffn Command {esirisc flash ref_erase} bank_id
5736 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
5737 is an uncommon operation.}
5741 @deffn {Flash Driver} fm3
5742 All members of the FM3 microcontroller family from Fujitsu
5743 include internal flash and use ARM Cortex-M3 cores.
5744 The @var{fm3} driver uses the @var{target} parameter to select the
5745 correct bank config, it can currently be one of the following:
5746 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5747 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5750 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5754 @deffn {Flash Driver} fm4
5755 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5756 include internal flash and use ARM Cortex-M4 cores.
5757 The @var{fm4} driver uses a @var{family} parameter to select the
5758 correct bank config, it can currently be one of the following:
5759 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5760 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5761 with @code{x} treated as wildcard and otherwise case (and any trailing
5762 characters) ignored.
5765 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5766 $_TARGETNAME S6E2CCAJ0A
5767 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5768 $_TARGETNAME S6E2CCAJ0A
5770 @emph{The current implementation is incomplete. Protection is not supported,
5771 nor is Chip Erase (only Sector Erase is implemented).}
5774 @deffn {Flash Driver} kinetis
5776 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5777 from NXP (former Freescale) include
5778 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5779 recognizes flash size and a number of flash banks (1-4) using the chip
5780 identification register, and autoconfigures itself.
5781 Use kinetis_ke driver for KE0x and KEAx devices.
5783 The @var{kinetis} driver defines option:
5785 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5789 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5792 @deffn Command {kinetis create_banks}
5793 Configuration command enables automatic creation of additional flash banks
5794 based on real flash layout of device. Banks are created during device probe.
5795 Use 'flash probe 0' to force probe.
5798 @deffn Command {kinetis fcf_source} [protection|write]
5799 Select what source is used when writing to a Flash Configuration Field.
5800 @option{protection} mode builds FCF content from protection bits previously
5801 set by 'flash protect' command.
5802 This mode is default. MCU is protected from unwanted locking by immediate
5803 writing FCF after erase of relevant sector.
5804 @option{write} mode enables direct write to FCF.
5805 Protection cannot be set by 'flash protect' command. FCF is written along
5806 with the rest of a flash image.
5807 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5810 @deffn Command {kinetis fopt} [num]
5811 Set value to write to FOPT byte of Flash Configuration Field.
5812 Used in kinetis 'fcf_source protection' mode only.
5815 @deffn Command {kinetis mdm check_security}
5816 Checks status of device security lock. Used internally in examine-end event.
5819 @deffn Command {kinetis mdm halt}
5820 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5821 loop when connecting to an unsecured target.
5824 @deffn Command {kinetis mdm mass_erase}
5825 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5826 back to its factory state, removing security. It does not require the processor
5827 to be halted, however the target will remain in a halted state after this
5831 @deffn Command {kinetis nvm_partition}
5832 For FlexNVM devices only (KxxDX and KxxFX).
5833 Command shows or sets data flash or EEPROM backup size in kilobytes,
5834 sets two EEPROM blocks sizes in bytes and enables/disables loading
5835 of EEPROM contents to FlexRAM during reset.
5837 For details see device reference manual, Flash Memory Module,
5838 Program Partition command.
5840 Setting is possible only once after mass_erase.
5841 Reset the device after partition setting.
5843 Show partition size:
5845 kinetis nvm_partition info
5848 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5849 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5851 kinetis nvm_partition dataflash 32 512 1536 on
5854 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5855 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5857 kinetis nvm_partition eebkp 16 1024 1024 off
5861 @deffn Command {kinetis mdm reset}
5862 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5863 RESET pin, which can be used to reset other hardware on board.
5866 @deffn Command {kinetis disable_wdog}
5867 For Kx devices only (KLx has different COP watchdog, it is not supported).
5868 Command disables watchdog timer.
5872 @deffn {Flash Driver} kinetis_ke
5874 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
5875 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5876 the KE0x sub-family using the chip identification register, and
5877 autoconfigures itself.
5878 Use kinetis (not kinetis_ke) driver for KE1x devices.
5881 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5884 @deffn Command {kinetis_ke mdm check_security}
5885 Checks status of device security lock. Used internally in examine-end event.
5888 @deffn Command {kinetis_ke mdm mass_erase}
5889 Issues a complete Flash erase via the MDM-AP.
5890 This can be used to erase a chip back to its factory state.
5891 Command removes security lock from a device (use of SRST highly recommended).
5892 It does not require the processor to be halted.
5895 @deffn Command {kinetis_ke disable_wdog}
5896 Command disables watchdog timer.
5900 @deffn {Flash Driver} lpc2000
5901 This is the driver to support internal flash of all members of the
5902 LPC11(x)00 and LPC1300 microcontroller families and most members of
5903 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
5904 LPC8Nxx and NHS31xx microcontroller families from NXP.
5907 There are LPC2000 devices which are not supported by the @var{lpc2000}
5909 The LPC2888 is supported by the @var{lpc288x} driver.
5910 The LPC29xx family is supported by the @var{lpc2900} driver.
5913 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5914 which must appear in the following order:
5917 @item @var{variant} ... required, may be
5918 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5919 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5920 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5921 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5923 @option{lpc800} (LPC8xx)
5924 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5925 @option{lpc1500} (LPC15xx)
5926 @option{lpc54100} (LPC541xx)
5927 @option{lpc4000} (LPC40xx)
5928 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5929 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
5930 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5931 at which the core is running
5932 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5933 telling the driver to calculate a valid checksum for the exception vector table.
5935 If you don't provide @option{calc_checksum} when you're writing the vector
5936 table, the boot ROM will almost certainly ignore your flash image.
5937 However, if you do provide it,
5938 with most tool chains @command{verify_image} will fail.
5942 LPC flashes don't require the chip and bus width to be specified.
5945 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5946 lpc2000_v2 14765 calc_checksum
5949 @deffn {Command} {lpc2000 part_id} bank
5950 Displays the four byte part identifier associated with
5951 the specified flash @var{bank}.
5955 @deffn {Flash Driver} lpc288x
5956 The LPC2888 microcontroller from NXP needs slightly different flash
5957 support from its lpc2000 siblings.
5958 The @var{lpc288x} driver defines one mandatory parameter,
5959 the programming clock rate in Hz.
5960 LPC flashes don't require the chip and bus width to be specified.
5963 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5967 @deffn {Flash Driver} lpc2900
5968 This driver supports the LPC29xx ARM968E based microcontroller family
5971 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5972 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5973 sector layout are auto-configured by the driver.
5974 The driver has one additional mandatory parameter: The CPU clock rate
5975 (in kHz) at the time the flash operations will take place. Most of the time this
5976 will not be the crystal frequency, but a higher PLL frequency. The
5977 @code{reset-init} event handler in the board script is usually the place where
5980 The driver rejects flashless devices (currently the LPC2930).
5982 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5983 It must be handled much more like NAND flash memory, and will therefore be
5984 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5986 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5987 sector needs to be erased or programmed, it is automatically unprotected.
5988 What is shown as protection status in the @code{flash info} command, is
5989 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5990 sector from ever being erased or programmed again. As this is an irreversible
5991 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5992 and not by the standard @code{flash protect} command.
5994 Example for a 125 MHz clock frequency:
5996 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5999 Some @code{lpc2900}-specific commands are defined. In the following command list,
6000 the @var{bank} parameter is the bank number as obtained by the
6001 @code{flash banks} command.
6003 @deffn Command {lpc2900 signature} bank
6004 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6005 content. This is a hardware feature of the flash block, hence the calculation is
6006 very fast. You may use this to verify the content of a programmed device against
6011 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6015 @deffn Command {lpc2900 read_custom} bank filename
6016 Reads the 912 bytes of customer information from the flash index sector, and
6017 saves it to a file in binary format.
6020 lpc2900 read_custom 0 /path_to/customer_info.bin
6024 The index sector of the flash is a @emph{write-only} sector. It cannot be
6025 erased! In order to guard against unintentional write access, all following
6026 commands need to be preceded by a successful call to the @code{password}
6029 @deffn Command {lpc2900 password} bank password
6030 You need to use this command right before each of the following commands:
6031 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
6032 @code{lpc2900 secure_jtag}.
6034 The password string is fixed to "I_know_what_I_am_doing".
6037 lpc2900 password 0 I_know_what_I_am_doing
6038 Potentially dangerous operation allowed in next command!
6042 @deffn Command {lpc2900 write_custom} bank filename type
6043 Writes the content of the file into the customer info space of the flash index
6044 sector. The filetype can be specified with the @var{type} field. Possible values
6045 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
6046 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
6047 contain a single section, and the contained data length must be exactly
6049 @quotation Attention
6050 This cannot be reverted! Be careful!
6054 lpc2900 write_custom 0 /path_to/customer_info.bin bin
6058 @deffn Command {lpc2900 secure_sector} bank first last
6059 Secures the sector range from @var{first} to @var{last} (including) against
6060 further program and erase operations. The sector security will be effective
6061 after the next power cycle.
6062 @quotation Attention
6063 This cannot be reverted! Be careful!
6065 Secured sectors appear as @emph{protected} in the @code{flash info} command.
6068 lpc2900 secure_sector 0 1 1
6070 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
6071 # 0: 0x00000000 (0x2000 8kB) not protected
6072 # 1: 0x00002000 (0x2000 8kB) protected
6073 # 2: 0x00004000 (0x2000 8kB) not protected
6077 @deffn Command {lpc2900 secure_jtag} bank
6078 Irreversibly disable the JTAG port. The new JTAG security setting will be
6079 effective after the next power cycle.
6080 @quotation Attention
6081 This cannot be reverted! Be careful!
6085 lpc2900 secure_jtag 0
6090 @deffn {Flash Driver} mdr
6091 This drivers handles the integrated NOR flash on Milandr Cortex-M
6092 based controllers. A known limitation is that the Info memory can't be
6093 read or verified as it's not memory mapped.
6096 flash bank <name> mdr <base> <size> \
6097 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
6101 @item @var{type} - 0 for main memory, 1 for info memory
6102 @item @var{page_count} - total number of pages
6103 @item @var{sec_count} - number of sector per page count
6108 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
6109 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
6110 0 0 $_TARGETNAME 1 1 4
6112 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
6113 0 0 $_TARGETNAME 0 32 4
6118 @deffn {Flash Driver} msp432
6119 All versions of the SimpleLink MSP432 microcontrollers from Texas
6120 Instruments include internal flash. The msp432 flash driver automatically
6121 recognizes the specific version's flash parameters and autoconfigures itself.
6122 Main program flash (starting at address 0) is flash bank 0. Information flash
6123 region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
6126 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
6129 @deffn Command {msp432 mass_erase} [main|all]
6130 Performs a complete erase of flash. By default, @command{mass_erase} will erase
6131 only the main program flash.
6133 On MSP432P4 versions, using @command{mass_erase all} will erase both the
6134 main program and information flash regions. To also erase the BSL in information
6135 flash, the user must first use the @command{bsl} command.
6138 @deffn Command {msp432 bsl} [unlock|lock]
6139 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
6140 region in information flash so that flash commands can erase or write the BSL.
6141 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
6143 To erase and program the BSL:
6146 flash erase_address 0x202000 0x2000
6147 flash write_image bsl.bin 0x202000
6153 @deffn {Flash Driver} niietcm4
6154 This drivers handles the integrated NOR flash on NIIET Cortex-M4
6155 based controllers. Flash size and sector layout are auto-configured by the driver.
6156 Main flash memory is called "Bootflash" and has main region and info region.
6157 Info region is NOT memory mapped by default,
6158 but it can replace first part of main region if needed.
6159 Full erase, single and block writes are supported for both main and info regions.
6160 There is additional not memory mapped flash called "Userflash", which
6161 also have division into regions: main and info.
6162 Purpose of userflash - to store system and user settings.
6163 Driver has special commands to perform operations with this memory.
6166 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
6169 Some niietcm4-specific commands are defined:
6171 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
6172 Read byte from main or info userflash region.
6175 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
6176 Write byte to main or info userflash region.
6179 @deffn Command {niietcm4 uflash_full_erase} bank
6180 Erase all userflash including info region.
6183 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
6184 Erase sectors of main or info userflash region, starting at sector first up to and including last.
6187 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
6188 Check sectors protect.
6191 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
6192 Protect sectors of main or info userflash region, starting at sector first up to and including last.
6195 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
6196 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
6199 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
6200 Configure external memory interface for boot.
6203 @deffn Command {niietcm4 service_mode_erase} bank
6204 Perform emergency erase of all flash (bootflash and userflash).
6207 @deffn Command {niietcm4 driver_info} bank
6208 Show information about flash driver.
6213 @deffn {Flash Driver} nrf5
6214 All members of the nRF51 microcontroller families from Nordic Semiconductor
6215 include internal flash and use ARM Cortex-M0 core.
6216 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
6217 internal flash and use an ARM Cortex-M4F core.
6220 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
6223 Some nrf5-specific commands are defined:
6225 @deffn Command {nrf5 mass_erase}
6226 Erases the contents of the code memory and user information
6227 configuration registers as well. It must be noted that this command
6228 works only for chips that do not have factory pre-programmed region 0
6234 @deffn {Flash Driver} ocl
6235 This driver is an implementation of the ``on chip flash loader''
6236 protocol proposed by Pavel Chromy.
6238 It is a minimalistic command-response protocol intended to be used
6239 over a DCC when communicating with an internal or external flash
6240 loader running from RAM. An example implementation for AT91SAM7x is
6241 available in @file{contrib/loaders/flash/at91sam7x/}.
6244 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
6248 @deffn {Flash Driver} pic32mx
6249 The PIC32MX microcontrollers are based on the MIPS 4K cores,
6250 and integrate flash memory.
6253 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
6254 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
6257 @comment numerous *disabled* commands are defined:
6258 @comment - chip_erase ... pointless given flash_erase_address
6259 @comment - lock, unlock ... pointless given protect on/off (yes?)
6260 @comment - pgm_word ... shouldn't bank be deduced from address??
6261 Some pic32mx-specific commands are defined:
6262 @deffn Command {pic32mx pgm_word} address value bank
6263 Programs the specified 32-bit @var{value} at the given @var{address}
6264 in the specified chip @var{bank}.
6266 @deffn Command {pic32mx unlock} bank
6267 Unlock and erase specified chip @var{bank}.
6268 This will remove any Code Protection.
6272 @deffn {Flash Driver} psoc4
6273 All members of the PSoC 41xx/42xx microcontroller family from Cypress
6274 include internal flash and use ARM Cortex-M0 cores.
6275 The driver automatically recognizes a number of these chips using
6276 the chip identification register, and autoconfigures itself.
6278 Note: Erased internal flash reads as 00.
6279 System ROM of PSoC 4 does not implement erase of a flash sector.
6282 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
6285 psoc4-specific commands
6286 @deffn Command {psoc4 flash_autoerase} num (on|off)
6287 Enables or disables autoerase mode for a flash bank.
6289 If flash_autoerase is off, use mass_erase before flash programming.
6290 Flash erase command fails if region to erase is not whole flash memory.
6292 If flash_autoerase is on, a sector is both erased and programmed in one
6293 system ROM call. Flash erase command is ignored.
6294 This mode is suitable for gdb load.
6296 The @var{num} parameter is a value shown by @command{flash banks}.
6299 @deffn Command {psoc4 mass_erase} num
6300 Erases the contents of the flash memory, protection and security lock.
6302 The @var{num} parameter is a value shown by @command{flash banks}.
6306 @deffn {Flash Driver} psoc5lp
6307 All members of the PSoC 5LP microcontroller family from Cypress
6308 include internal program flash and use ARM Cortex-M3 cores.
6309 The driver probes for a number of these chips and autoconfigures itself,
6310 apart from the base address.
6313 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
6316 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
6317 @quotation Attention
6318 If flash operations are performed in ECC-disabled mode, they will also affect
6319 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
6320 then also erase the corresponding 2k data bytes in the 0x48000000 area.
6321 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
6324 Commands defined in the @var{psoc5lp} driver:
6326 @deffn Command {psoc5lp mass_erase}
6327 Erases all flash data and ECC/configuration bytes, all flash protection rows,
6328 and all row latches in all flash arrays on the device.
6332 @deffn {Flash Driver} psoc5lp_eeprom
6333 All members of the PSoC 5LP microcontroller family from Cypress
6334 include internal EEPROM and use ARM Cortex-M3 cores.
6335 The driver probes for a number of these chips and autoconfigures itself,
6336 apart from the base address.
6339 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
6343 @deffn {Flash Driver} psoc5lp_nvl
6344 All members of the PSoC 5LP microcontroller family from Cypress
6345 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
6346 The driver probes for a number of these chips and autoconfigures itself.
6349 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
6352 PSoC 5LP chips have multiple NV Latches:
6355 @item Device Configuration NV Latch - 4 bytes
6356 @item Write Once (WO) NV Latch - 4 bytes
6359 @b{Note:} This driver only implements the Device Configuration NVL.
6361 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
6362 @quotation Attention
6363 Switching ECC mode via write to Device Configuration NVL will require a reset
6364 after successful write.
6368 @deffn {Flash Driver} psoc6
6369 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
6370 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6371 the same Flash/RAM/MMIO address space.
6373 Flash in PSoC6 is split into three regions:
6375 @item Main Flash - this is the main storage for user application.
6376 Total size varies among devices, sector size: 256 kBytes, row size:
6377 512 bytes. Supports erase operation on individual rows.
6378 @item Work Flash - intended to be used as storage for user data
6379 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
6380 row size: 512 bytes.
6381 @item Supervisory Flash - special region which contains device-specific
6382 service data. This region does not support erase operation. Only few rows can
6383 be programmed by the user, most of the rows are read only. Programming
6384 operation will erase row automatically.
6387 All three flash regions are supported by the driver. Flash geometry is detected
6388 automatically by parsing data in SPCIF_GEOMETRY register.
6390 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
6393 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm0
6394 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm0
6395 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm0
6396 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm0
6397 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm0
6398 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm0
6400 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 $@{TARGET@}.cm4
6401 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 $@{TARGET@}.cm4
6402 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 $@{TARGET@}.cm4
6403 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 $@{TARGET@}.cm4
6404 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 $@{TARGET@}.cm4
6405 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 $@{TARGET@}.cm4
6408 psoc6-specific commands
6409 @deffn Command {psoc6 reset_halt}
6410 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
6411 When invoked for CM0+ target, it will set break point at application entry point
6412 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
6413 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
6414 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
6417 @deffn Command {psoc6 mass_erase} num
6418 Erases the contents given flash bank. The @var{num} parameter is a value shown
6419 by @command{flash banks}.
6420 Note: only Main and Work flash regions support Erase operation.
6424 @deffn {Flash Driver} sim3x
6425 All members of the SiM3 microcontroller family from Silicon Laboratories
6426 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
6428 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
6429 If this fails, it will use the @var{size} parameter as the size of flash bank.
6432 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
6435 There are 2 commands defined in the @var{sim3x} driver:
6437 @deffn Command {sim3x mass_erase}
6438 Erases the complete flash. This is used to unlock the flash.
6439 And this command is only possible when using the SWD interface.
6442 @deffn Command {sim3x lock}
6443 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
6447 @deffn {Flash Driver} stellaris
6448 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
6449 families from Texas Instruments include internal flash. The driver
6450 automatically recognizes a number of these chips using the chip
6451 identification register, and autoconfigures itself.
6454 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
6457 @deffn Command {stellaris recover}
6458 Performs the @emph{Recovering a "Locked" Device} procedure to restore
6459 the flash and its associated nonvolatile registers to their factory
6460 default values (erased). This is the only way to remove flash
6461 protection or re-enable debugging if that capability has been
6464 Note that the final "power cycle the chip" step in this procedure
6465 must be performed by hand, since OpenOCD can't do it.
6467 if more than one Stellaris chip is connected, the procedure is
6468 applied to all of them.
6473 @deffn {Flash Driver} stm32f1x
6474 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
6475 from STMicroelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
6476 The driver automatically recognizes a number of these chips using
6477 the chip identification register, and autoconfigures itself.
6480 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
6483 Note that some devices have been found that have a flash size register that contains
6484 an invalid value, to workaround this issue you can override the probed value used by
6488 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
6491 If you have a target with dual flash banks then define the second bank
6492 as per the following example.
6494 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
6497 Some stm32f1x-specific commands are defined:
6499 @deffn Command {stm32f1x lock} num
6500 Locks the entire stm32 device against reading.
6501 The @var{num} parameter is a value shown by @command{flash banks}.
6504 @deffn Command {stm32f1x unlock} num
6505 Unlocks the entire stm32 device for reading. This command will cause
6506 a mass erase of the entire stm32 device if previously locked.
6507 The @var{num} parameter is a value shown by @command{flash banks}.
6510 @deffn Command {stm32f1x mass_erase} num
6511 Mass erases the entire stm32 device.
6512 The @var{num} parameter is a value shown by @command{flash banks}.
6515 @deffn Command {stm32f1x options_read} num
6516 Reads and displays active stm32 option bytes loaded during POR
6517 or upon executing the @command{stm32f1x options_load} command.
6518 The @var{num} parameter is a value shown by @command{flash banks}.
6521 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
6522 Writes the stm32 option byte with the specified values.
6523 The @var{num} parameter is a value shown by @command{flash banks}.
6526 @deffn Command {stm32f1x options_load} num
6527 Generates a special kind of reset to re-load the stm32 option bytes written
6528 by the @command{stm32f1x options_write} or @command{flash protect} commands
6529 without having to power cycle the target. Not applicable to stm32f1x devices.
6530 The @var{num} parameter is a value shown by @command{flash banks}.
6534 @deffn {Flash Driver} stm32f2x
6535 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
6536 include internal flash and use ARM Cortex-M3/M4/M7 cores.
6537 The driver automatically recognizes a number of these chips using
6538 the chip identification register, and autoconfigures itself.
6541 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
6544 Note that some devices have been found that have a flash size register that contains
6545 an invalid value, to workaround this issue you can override the probed value used by
6549 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
6552 Some stm32f2x-specific commands are defined:
6554 @deffn Command {stm32f2x lock} num
6555 Locks the entire stm32 device.
6556 The @var{num} parameter is a value shown by @command{flash banks}.
6559 @deffn Command {stm32f2x unlock} num
6560 Unlocks the entire stm32 device.
6561 The @var{num} parameter is a value shown by @command{flash banks}.
6564 @deffn Command {stm32f2x mass_erase} num
6565 Mass erases the entire stm32f2x device.
6566 The @var{num} parameter is a value shown by @command{flash banks}.
6569 @deffn Command {stm32f2x options_read} num
6570 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6571 The @var{num} parameter is a value shown by @command{flash banks}.
6574 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6575 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6576 Warning: The meaning of the various bits depends on the device, always check datasheet!
6577 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6578 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6579 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6582 @deffn Command {stm32f2x optcr2_write} num optcr2
6583 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6584 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6588 @deffn {Flash Driver} stm32h7x
6589 All members of the STM32H7 microcontroller families from STMicroelectronics
6590 include internal flash and use ARM Cortex-M7 core.
6591 The driver automatically recognizes a number of these chips using
6592 the chip identification register, and autoconfigures itself.
6595 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6598 Note that some devices have been found that have a flash size register that contains
6599 an invalid value, to workaround this issue you can override the probed value used by
6603 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6606 Some stm32h7x-specific commands are defined:
6608 @deffn Command {stm32h7x lock} num
6609 Locks the entire stm32 device.
6610 The @var{num} parameter is a value shown by @command{flash banks}.
6613 @deffn Command {stm32h7x unlock} num
6614 Unlocks the entire stm32 device.
6615 The @var{num} parameter is a value shown by @command{flash banks}.
6618 @deffn Command {stm32h7x mass_erase} num
6619 Mass erases the entire stm32h7x device.
6620 The @var{num} parameter is a value shown by @command{flash banks}.
6624 @deffn {Flash Driver} stm32lx
6625 All members of the STM32L microcontroller families from STMicroelectronics
6626 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6627 The driver automatically recognizes a number of these chips using
6628 the chip identification register, and autoconfigures itself.
6631 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6634 Note that some devices have been found that have a flash size register that contains
6635 an invalid value, to workaround this issue you can override the probed value used by
6636 the flash driver. If you use 0 as the bank base address, it tells the
6637 driver to autodetect the bank location assuming you're configuring the
6641 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6644 Some stm32lx-specific commands are defined:
6646 @deffn Command {stm32lx lock} num
6647 Locks the entire stm32 device.
6648 The @var{num} parameter is a value shown by @command{flash banks}.
6651 @deffn Command {stm32lx unlock} num
6652 Unlocks the entire stm32 device.
6653 The @var{num} parameter is a value shown by @command{flash banks}.
6656 @deffn Command {stm32lx mass_erase} num
6657 Mass erases the entire stm32lx device (all flash banks and EEPROM
6658 data). This is the only way to unlock a protected flash (unless RDP
6659 Level is 2 which can't be unlocked at all).
6660 The @var{num} parameter is a value shown by @command{flash banks}.
6664 @deffn {Flash Driver} stm32l4x
6665 All members of the STM32L4 microcontroller families from STMicroelectronics
6666 include internal flash and use ARM Cortex-M4 cores.
6667 The driver automatically recognizes a number of these chips using
6668 the chip identification register, and autoconfigures itself.
6671 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6674 Note that some devices have been found that have a flash size register that contains
6675 an invalid value, to workaround this issue you can override the probed value used by
6679 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6682 Some stm32l4x-specific commands are defined:
6684 @deffn Command {stm32l4x lock} num
6685 Locks the entire stm32 device.
6686 The @var{num} parameter is a value shown by @command{flash banks}.
6689 @deffn Command {stm32l4x unlock} num
6690 Unlocks the entire stm32 device.
6691 The @var{num} parameter is a value shown by @command{flash banks}.
6694 @deffn Command {stm32l4x mass_erase} num
6695 Mass erases the entire stm32l4x device.
6696 The @var{num} parameter is a value shown by @command{flash banks}.
6699 @deffn Command {stm32l4x option_read} num reg_offset
6700 Reads an option byte register from the stm32l4x device.
6701 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6702 is the register offset of the Option byte to read.
6704 For example to read the FLASH_OPTR register:
6706 stm32l4x option_read 0 0x20
6707 # Option Register: <0x40022020> = 0xffeff8aa
6710 The above example will read out the FLASH_OPTR register which contains the RDP
6711 option byte, Watchdog configuration, BOR level etc.
6714 @deffn Command {stm32l4x option_write} num reg_offset reg_mask
6715 Write an option byte register of the stm32l4x device.
6716 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
6717 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
6718 to apply when writing the register (only bits with a '1' will be touched).
6720 For example to write the WRP1AR option bytes:
6722 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
6725 The above example will write the WRP1AR option register configuring the Write protection
6726 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
6727 This will effectively write protect all sectors in flash bank 1.
6730 @deffn Command {stm32l4x option_load} num
6731 Forces a re-load of the option byte registers. Will cause a reset of the device.
6732 The @var{num} parameter is a value shown by @command{flash banks}.
6736 @deffn {Flash Driver} str7x
6737 All members of the STR7 microcontroller family from STMicroelectronics
6738 include internal flash and use ARM7TDMI cores.
6739 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6740 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6743 flash bank $_FLASHNAME str7x \
6744 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6747 @deffn Command {str7x disable_jtag} bank
6748 Activate the Debug/Readout protection mechanism
6749 for the specified flash bank.
6753 @deffn {Flash Driver} str9x
6754 Most members of the STR9 microcontroller family from STMicroelectronics
6755 include internal flash and use ARM966E cores.
6756 The str9 needs the flash controller to be configured using
6757 the @command{str9x flash_config} command prior to Flash programming.
6760 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6761 str9x flash_config 0 4 2 0 0x80000
6764 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6765 Configures the str9 flash controller.
6766 The @var{num} parameter is a value shown by @command{flash banks}.
6769 @item @var{bbsr} - Boot Bank Size register
6770 @item @var{nbbsr} - Non Boot Bank Size register
6771 @item @var{bbadr} - Boot Bank Start Address register
6772 @item @var{nbbadr} - Boot Bank Start Address register
6778 @deffn {Flash Driver} str9xpec
6781 Only use this driver for locking/unlocking the device or configuring the option bytes.
6782 Use the standard str9 driver for programming.
6783 Before using the flash commands the turbo mode must be enabled using the
6784 @command{str9xpec enable_turbo} command.
6786 Here is some background info to help
6787 you better understand how this driver works. OpenOCD has two flash drivers for
6791 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6792 flash programming as it is faster than the @option{str9xpec} driver.
6794 Direct programming @option{str9xpec} using the flash controller. This is an
6795 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
6796 core does not need to be running to program using this flash driver. Typical use
6797 for this driver is locking/unlocking the target and programming the option bytes.
6800 Before we run any commands using the @option{str9xpec} driver we must first disable
6801 the str9 core. This example assumes the @option{str9xpec} driver has been
6802 configured for flash bank 0.
6804 # assert srst, we do not want core running
6805 # while accessing str9xpec flash driver
6807 # turn off target polling
6810 str9xpec enable_turbo 0
6812 str9xpec options_read 0
6813 # re-enable str9 core
6814 str9xpec disable_turbo 0
6818 The above example will read the str9 option bytes.
6819 When performing a unlock remember that you will not be able to halt the str9 - it
6820 has been locked. Halting the core is not required for the @option{str9xpec} driver
6821 as mentioned above, just issue the commands above manually or from a telnet prompt.
6823 Several str9xpec-specific commands are defined:
6825 @deffn Command {str9xpec disable_turbo} num
6826 Restore the str9 into JTAG chain.
6829 @deffn Command {str9xpec enable_turbo} num
6830 Enable turbo mode, will simply remove the str9 from the chain and talk
6831 directly to the embedded flash controller.
6834 @deffn Command {str9xpec lock} num
6835 Lock str9 device. The str9 will only respond to an unlock command that will
6839 @deffn Command {str9xpec part_id} num
6840 Prints the part identifier for bank @var{num}.
6843 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6844 Configure str9 boot bank.
6847 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6848 Configure str9 lvd source.
6851 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6852 Configure str9 lvd threshold.
6855 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6856 Configure str9 lvd reset warning source.
6859 @deffn Command {str9xpec options_read} num
6860 Read str9 option bytes.
6863 @deffn Command {str9xpec options_write} num
6864 Write str9 option bytes.
6867 @deffn Command {str9xpec unlock} num
6873 @deffn {Flash Driver} tms470
6874 Most members of the TMS470 microcontroller family from Texas Instruments
6875 include internal flash and use ARM7TDMI cores.
6876 This driver doesn't require the chip and bus width to be specified.
6878 Some tms470-specific commands are defined:
6880 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6881 Saves programming keys in a register, to enable flash erase and write commands.
6884 @deffn Command {tms470 osc_mhz} clock_mhz
6885 Reports the clock speed, which is used to calculate timings.
6888 @deffn Command {tms470 plldis} (0|1)
6889 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
6894 @deffn {Flash Driver} w600
6895 W60x series Wi-Fi SoC from WinnerMicro
6896 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
6897 The @var{w600} driver uses the @var{target} parameter to select the
6898 correct bank config.
6901 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
6905 @deffn {Flash Driver} xmc1xxx
6906 All members of the XMC1xxx microcontroller family from Infineon.
6907 This driver does not require the chip and bus width to be specified.
6910 @deffn {Flash Driver} xmc4xxx
6911 All members of the XMC4xxx microcontroller family from Infineon.
6912 This driver does not require the chip and bus width to be specified.
6914 Some xmc4xxx-specific commands are defined:
6916 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
6917 Saves flash protection passwords which are used to lock the user flash
6920 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
6921 Removes Flash write protection from the selected user bank
6926 @section NAND Flash Commands
6929 Compared to NOR or SPI flash, NAND devices are inexpensive
6930 and high density. Today's NAND chips, and multi-chip modules,
6931 commonly hold multiple GigaBytes of data.
6933 NAND chips consist of a number of ``erase blocks'' of a given
6934 size (such as 128 KBytes), each of which is divided into a
6935 number of pages (of perhaps 512 or 2048 bytes each). Each
6936 page of a NAND flash has an ``out of band'' (OOB) area to hold
6937 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6938 of OOB for every 512 bytes of page data.
6940 One key characteristic of NAND flash is that its error rate
6941 is higher than that of NOR flash. In normal operation, that
6942 ECC is used to correct and detect errors. However, NAND
6943 blocks can also wear out and become unusable; those blocks
6944 are then marked "bad". NAND chips are even shipped from the
6945 manufacturer with a few bad blocks. The highest density chips
6946 use a technology (MLC) that wears out more quickly, so ECC
6947 support is increasingly important as a way to detect blocks
6948 that have begun to fail, and help to preserve data integrity
6949 with techniques such as wear leveling.
6951 Software is used to manage the ECC. Some controllers don't
6952 support ECC directly; in those cases, software ECC is used.
6953 Other controllers speed up the ECC calculations with hardware.
6954 Single-bit error correction hardware is routine. Controllers
6955 geared for newer MLC chips may correct 4 or more errors for
6956 every 512 bytes of data.
6958 You will need to make sure that any data you write using
6959 OpenOCD includes the appropriate kind of ECC. For example,
6960 that may mean passing the @code{oob_softecc} flag when
6961 writing NAND data, or ensuring that the correct hardware
6964 The basic steps for using NAND devices include:
6966 @item Declare via the command @command{nand device}
6967 @* Do this in a board-specific configuration file,
6968 passing parameters as needed by the controller.
6969 @item Configure each device using @command{nand probe}.
6970 @* Do this only after the associated target is set up,
6971 such as in its reset-init script or in procures defined
6972 to access that device.
6973 @item Operate on the flash via @command{nand subcommand}
6974 @* Often commands to manipulate the flash are typed by a human, or run
6975 via a script in some automated way. Common task include writing a
6976 boot loader, operating system, or other data needed to initialize or
6980 @b{NOTE:} At the time this text was written, the largest NAND
6981 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6982 This is because the variables used to hold offsets and lengths
6983 are only 32 bits wide.
6984 (Larger chips may work in some cases, unless an offset or length
6985 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6986 Some larger devices will work, since they are actually multi-chip
6987 modules with two smaller chips and individual chipselect lines.
6989 @anchor{nandconfiguration}
6990 @subsection NAND Configuration Commands
6991 @cindex NAND configuration
6993 NAND chips must be declared in configuration scripts,
6994 plus some additional configuration that's done after
6995 OpenOCD has initialized.
6997 @deffn {Config Command} {nand device} name driver target [configparams...]
6998 Declares a NAND device, which can be read and written to
6999 after it has been configured through @command{nand probe}.
7000 In OpenOCD, devices are single chips; this is unlike some
7001 operating systems, which may manage multiple chips as if
7002 they were a single (larger) device.
7003 In some cases, configuring a device will activate extra
7004 commands; see the controller-specific documentation.
7006 @b{NOTE:} This command is not available after OpenOCD
7007 initialization has completed. Use it in board specific
7008 configuration files, not interactively.
7011 @item @var{name} ... may be used to reference the NAND bank
7012 in most other NAND commands. A number is also available.
7013 @item @var{driver} ... identifies the NAND controller driver
7014 associated with the NAND device being declared.
7015 @xref{nanddriverlist,,NAND Driver List}.
7016 @item @var{target} ... names the target used when issuing
7017 commands to the NAND controller.
7018 @comment Actually, it's currently a controller-specific parameter...
7019 @item @var{configparams} ... controllers may support, or require,
7020 additional parameters. See the controller-specific documentation
7021 for more information.
7025 @deffn Command {nand list}
7026 Prints a summary of each device declared
7027 using @command{nand device}, numbered from zero.
7028 Note that un-probed devices show no details.
7031 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7032 blocksize: 131072, blocks: 8192
7033 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
7034 blocksize: 131072, blocks: 8192
7039 @deffn Command {nand probe} num
7040 Probes the specified device to determine key characteristics
7041 like its page and block sizes, and how many blocks it has.
7042 The @var{num} parameter is the value shown by @command{nand list}.
7043 You must (successfully) probe a device before you can use
7044 it with most other NAND commands.
7047 @subsection Erasing, Reading, Writing to NAND Flash
7049 @deffn Command {nand dump} num filename offset length [oob_option]
7050 @cindex NAND reading
7051 Reads binary data from the NAND device and writes it to the file,
7052 starting at the specified offset.
7053 The @var{num} parameter is the value shown by @command{nand list}.
7055 Use a complete path name for @var{filename}, so you don't depend
7056 on the directory used to start the OpenOCD server.
7058 The @var{offset} and @var{length} must be exact multiples of the
7059 device's page size. They describe a data region; the OOB data
7060 associated with each such page may also be accessed.
7062 @b{NOTE:} At the time this text was written, no error correction
7063 was done on the data that's read, unless raw access was disabled
7064 and the underlying NAND controller driver had a @code{read_page}
7065 method which handled that error correction.
7067 By default, only page data is saved to the specified file.
7068 Use an @var{oob_option} parameter to save OOB data:
7070 @item no oob_* parameter
7071 @*Output file holds only page data; OOB is discarded.
7072 @item @code{oob_raw}
7073 @*Output file interleaves page data and OOB data;
7074 the file will be longer than "length" by the size of the
7075 spare areas associated with each data page.
7076 Note that this kind of "raw" access is different from
7077 what's implied by @command{nand raw_access}, which just
7078 controls whether a hardware-aware access method is used.
7079 @item @code{oob_only}
7080 @*Output file has only raw OOB data, and will
7081 be smaller than "length" since it will contain only the
7082 spare areas associated with each data page.
7086 @deffn Command {nand erase} num [offset length]
7087 @cindex NAND erasing
7088 @cindex NAND programming
7089 Erases blocks on the specified NAND device, starting at the
7090 specified @var{offset} and continuing for @var{length} bytes.
7091 Both of those values must be exact multiples of the device's
7092 block size, and the region they specify must fit entirely in the chip.
7093 If those parameters are not specified,
7094 the whole NAND chip will be erased.
7095 The @var{num} parameter is the value shown by @command{nand list}.
7097 @b{NOTE:} This command will try to erase bad blocks, when told
7098 to do so, which will probably invalidate the manufacturer's bad
7100 For the remainder of the current server session, @command{nand info}
7101 will still report that the block ``is'' bad.
7104 @deffn Command {nand write} num filename offset [option...]
7105 @cindex NAND writing
7106 @cindex NAND programming
7107 Writes binary data from the file into the specified NAND device,
7108 starting at the specified offset. Those pages should already
7109 have been erased; you can't change zero bits to one bits.
7110 The @var{num} parameter is the value shown by @command{nand list}.
7112 Use a complete path name for @var{filename}, so you don't depend
7113 on the directory used to start the OpenOCD server.
7115 The @var{offset} must be an exact multiple of the device's page size.
7116 All data in the file will be written, assuming it doesn't run
7117 past the end of the device.
7118 Only full pages are written, and any extra space in the last
7119 page will be filled with 0xff bytes. (That includes OOB data,
7120 if that's being written.)
7122 @b{NOTE:} At the time this text was written, bad blocks are
7123 ignored. That is, this routine will not skip bad blocks,
7124 but will instead try to write them. This can cause problems.
7126 Provide at most one @var{option} parameter. With some
7127 NAND drivers, the meanings of these parameters may change
7128 if @command{nand raw_access} was used to disable hardware ECC.
7130 @item no oob_* parameter
7131 @*File has only page data, which is written.
7132 If raw access is in use, the OOB area will not be written.
7133 Otherwise, if the underlying NAND controller driver has
7134 a @code{write_page} routine, that routine may write the OOB
7135 with hardware-computed ECC data.
7136 @item @code{oob_only}
7137 @*File has only raw OOB data, which is written to the OOB area.
7138 Each page's data area stays untouched. @i{This can be a dangerous
7139 option}, since it can invalidate the ECC data.
7140 You may need to force raw access to use this mode.
7141 @item @code{oob_raw}
7142 @*File interleaves data and OOB data, both of which are written
7143 If raw access is enabled, the data is written first, then the
7145 Otherwise, if the underlying NAND controller driver has
7146 a @code{write_page} routine, that routine may modify the OOB
7147 before it's written, to include hardware-computed ECC data.
7148 @item @code{oob_softecc}
7149 @*File has only page data, which is written.
7150 The OOB area is filled with 0xff, except for a standard 1-bit
7151 software ECC code stored in conventional locations.
7152 You might need to force raw access to use this mode, to prevent
7153 the underlying driver from applying hardware ECC.
7154 @item @code{oob_softecc_kw}
7155 @*File has only page data, which is written.
7156 The OOB area is filled with 0xff, except for a 4-bit software ECC
7157 specific to the boot ROM in Marvell Kirkwood SoCs.
7158 You might need to force raw access to use this mode, to prevent
7159 the underlying driver from applying hardware ECC.
7163 @deffn Command {nand verify} num filename offset [option...]
7164 @cindex NAND verification
7165 @cindex NAND programming
7166 Verify the binary data in the file has been programmed to the
7167 specified NAND device, starting at the specified offset.
7168 The @var{num} parameter is the value shown by @command{nand list}.
7170 Use a complete path name for @var{filename}, so you don't depend
7171 on the directory used to start the OpenOCD server.
7173 The @var{offset} must be an exact multiple of the device's page size.
7174 All data in the file will be read and compared to the contents of the
7175 flash, assuming it doesn't run past the end of the device.
7176 As with @command{nand write}, only full pages are verified, so any extra
7177 space in the last page will be filled with 0xff bytes.
7179 The same @var{options} accepted by @command{nand write},
7180 and the file will be processed similarly to produce the buffers that
7181 can be compared against the contents produced from @command{nand dump}.
7183 @b{NOTE:} This will not work when the underlying NAND controller
7184 driver's @code{write_page} routine must update the OOB with a
7185 hardware-computed ECC before the data is written. This limitation may
7186 be removed in a future release.
7189 @subsection Other NAND commands
7190 @cindex NAND other commands
7192 @deffn Command {nand check_bad_blocks} num [offset length]
7193 Checks for manufacturer bad block markers on the specified NAND
7194 device. If no parameters are provided, checks the whole
7195 device; otherwise, starts at the specified @var{offset} and
7196 continues for @var{length} bytes.
7197 Both of those values must be exact multiples of the device's
7198 block size, and the region they specify must fit entirely in the chip.
7199 The @var{num} parameter is the value shown by @command{nand list}.
7201 @b{NOTE:} Before using this command you should force raw access
7202 with @command{nand raw_access enable} to ensure that the underlying
7203 driver will not try to apply hardware ECC.
7206 @deffn Command {nand info} num
7207 The @var{num} parameter is the value shown by @command{nand list}.
7208 This prints the one-line summary from "nand list", plus for
7209 devices which have been probed this also prints any known
7210 status for each block.
7213 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
7214 Sets or clears an flag affecting how page I/O is done.
7215 The @var{num} parameter is the value shown by @command{nand list}.
7217 This flag is cleared (disabled) by default, but changing that
7218 value won't affect all NAND devices. The key factor is whether
7219 the underlying driver provides @code{read_page} or @code{write_page}
7220 methods. If it doesn't provide those methods, the setting of
7221 this flag is irrelevant; all access is effectively ``raw''.
7223 When those methods exist, they are normally used when reading
7224 data (@command{nand dump} or reading bad block markers) or
7225 writing it (@command{nand write}). However, enabling
7226 raw access (setting the flag) prevents use of those methods,
7227 bypassing hardware ECC logic.
7228 @i{This can be a dangerous option}, since writing blocks
7229 with the wrong ECC data can cause them to be marked as bad.
7232 @anchor{nanddriverlist}
7233 @subsection NAND Driver List
7234 As noted above, the @command{nand device} command allows
7235 driver-specific options and behaviors.
7236 Some controllers also activate controller-specific commands.
7238 @deffn {NAND Driver} at91sam9
7239 This driver handles the NAND controllers found on AT91SAM9 family chips from
7240 Atmel. It takes two extra parameters: address of the NAND chip;
7241 address of the ECC controller.
7243 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
7245 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
7246 @code{read_page} methods are used to utilize the ECC hardware unless they are
7247 disabled by using the @command{nand raw_access} command. There are four
7248 additional commands that are needed to fully configure the AT91SAM9 NAND
7249 controller. Two are optional; most boards use the same wiring for ALE/CLE:
7250 @deffn Command {at91sam9 cle} num addr_line
7251 Configure the address line used for latching commands. The @var{num}
7252 parameter is the value shown by @command{nand list}.
7254 @deffn Command {at91sam9 ale} num addr_line
7255 Configure the address line used for latching addresses. The @var{num}
7256 parameter is the value shown by @command{nand list}.
7259 For the next two commands, it is assumed that the pins have already been
7260 properly configured for input or output.
7261 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
7262 Configure the RDY/nBUSY input from the NAND device. The @var{num}
7263 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7264 is the base address of the PIO controller and @var{pin} is the pin number.
7266 @deffn Command {at91sam9 ce} num pio_base_addr pin
7267 Configure the chip enable input to the NAND device. The @var{num}
7268 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
7269 is the base address of the PIO controller and @var{pin} is the pin number.
7273 @deffn {NAND Driver} davinci
7274 This driver handles the NAND controllers found on DaVinci family
7275 chips from Texas Instruments.
7276 It takes three extra parameters:
7277 address of the NAND chip;
7278 hardware ECC mode to use (@option{hwecc1},
7279 @option{hwecc4}, @option{hwecc4_infix});
7280 address of the AEMIF controller on this processor.
7282 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
7284 All DaVinci processors support the single-bit ECC hardware,
7285 and newer ones also support the four-bit ECC hardware.
7286 The @code{write_page} and @code{read_page} methods are used
7287 to implement those ECC modes, unless they are disabled using
7288 the @command{nand raw_access} command.
7291 @deffn {NAND Driver} lpc3180
7292 These controllers require an extra @command{nand device}
7293 parameter: the clock rate used by the controller.
7294 @deffn Command {lpc3180 select} num [mlc|slc]
7295 Configures use of the MLC or SLC controller mode.
7296 MLC implies use of hardware ECC.
7297 The @var{num} parameter is the value shown by @command{nand list}.
7300 At this writing, this driver includes @code{write_page}
7301 and @code{read_page} methods. Using @command{nand raw_access}
7302 to disable those methods will prevent use of hardware ECC
7303 in the MLC controller mode, but won't change SLC behavior.
7305 @comment current lpc3180 code won't issue 5-byte address cycles
7307 @deffn {NAND Driver} mx3
7308 This driver handles the NAND controller in i.MX31. The mxc driver
7309 should work for this chip as well.
7312 @deffn {NAND Driver} mxc
7313 This driver handles the NAND controller found in Freescale i.MX
7314 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
7315 The driver takes 3 extra arguments, chip (@option{mx27},
7316 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
7317 and optionally if bad block information should be swapped between
7318 main area and spare area (@option{biswap}), defaults to off.
7320 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
7322 @deffn Command {mxc biswap} bank_num [enable|disable]
7323 Turns on/off bad block information swapping from main area,
7324 without parameter query status.
7328 @deffn {NAND Driver} orion
7329 These controllers require an extra @command{nand device}
7330 parameter: the address of the controller.
7332 nand device orion 0xd8000000
7334 These controllers don't define any specialized commands.
7335 At this writing, their drivers don't include @code{write_page}
7336 or @code{read_page} methods, so @command{nand raw_access} won't
7337 change any behavior.
7340 @deffn {NAND Driver} s3c2410
7341 @deffnx {NAND Driver} s3c2412
7342 @deffnx {NAND Driver} s3c2440
7343 @deffnx {NAND Driver} s3c2443
7344 @deffnx {NAND Driver} s3c6400
7345 These S3C family controllers don't have any special
7346 @command{nand device} options, and don't define any
7347 specialized commands.
7348 At this writing, their drivers don't include @code{write_page}
7349 or @code{read_page} methods, so @command{nand raw_access} won't
7350 change any behavior.
7355 @subsection mFlash Configuration
7356 @cindex mFlash Configuration
7358 @deffn {Config Command} {mflash bank} soc base RST_pin target
7359 Configures a mflash for @var{soc} host bank at
7361 The pin number format depends on the host GPIO naming convention.
7362 Currently, the mflash driver supports s3c2440 and pxa270.
7364 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
7367 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
7370 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
7373 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
7377 @subsection mFlash commands
7378 @cindex mFlash commands
7380 @deffn Command {mflash config pll} frequency
7381 Configure mflash PLL.
7382 The @var{frequency} is the mflash input frequency, in Hz.
7383 Issuing this command will erase mflash's whole internal nand and write new pll.
7384 After this command, mflash needs power-on-reset for normal operation.
7385 If pll was newly configured, storage and boot(optional) info also need to be update.
7388 @deffn Command {mflash config boot}
7389 Configure bootable option.
7390 If bootable option is set, mflash offer the first 8 sectors
7394 @deffn Command {mflash config storage}
7395 Configure storage information.
7396 For the normal storage operation, this information must be
7400 @deffn Command {mflash dump} num filename offset size
7401 Dump @var{size} bytes, starting at @var{offset} bytes from the
7402 beginning of the bank @var{num}, to the file named @var{filename}.
7405 @deffn Command {mflash probe}
7409 @deffn Command {mflash write} num filename offset
7410 Write the binary file @var{filename} to mflash bank @var{num}, starting at
7411 @var{offset} bytes from the beginning of the bank.
7414 @node Flash Programming
7415 @chapter Flash Programming
7417 OpenOCD implements numerous ways to program the target flash, whether internal or external.
7418 Programming can be achieved by either using GDB @ref{programmingusinggdb,,Programming using GDB},
7419 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
7421 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
7422 OpenOCD will program/verify/reset the target and optionally shutdown.
7424 The script is executed as follows and by default the following actions will be performed.
7426 @item 'init' is executed.
7427 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
7428 @item @code{flash write_image} is called to erase and write any flash using the filename given.
7429 @item @code{verify_image} is called if @option{verify} parameter is given.
7430 @item @code{reset run} is called if @option{reset} parameter is given.
7431 @item OpenOCD is shutdown if @option{exit} parameter is given.
7434 An example of usage is given below. @xref{program}.
7437 # program and verify using elf/hex/s19. verify and reset
7438 # are optional parameters
7439 openocd -f board/stm32f3discovery.cfg \
7440 -c "program filename.elf verify reset exit"
7442 # binary files need the flash address passing
7443 openocd -f board/stm32f3discovery.cfg \
7444 -c "program filename.bin exit 0x08000000"
7447 @node PLD/FPGA Commands
7448 @chapter PLD/FPGA Commands
7452 Programmable Logic Devices (PLDs) and the more flexible
7453 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
7454 OpenOCD can support programming them.
7455 Although PLDs are generally restrictive (cells are less functional, and
7456 there are no special purpose cells for memory or computational tasks),
7457 they share the same OpenOCD infrastructure.
7458 Accordingly, both are called PLDs here.
7460 @section PLD/FPGA Configuration and Commands
7462 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
7463 OpenOCD maintains a list of PLDs available for use in various commands.
7464 Also, each such PLD requires a driver.
7466 They are referenced by the number shown by the @command{pld devices} command,
7467 and new PLDs are defined by @command{pld device driver_name}.
7469 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
7470 Defines a new PLD device, supported by driver @var{driver_name},
7471 using the TAP named @var{tap_name}.
7472 The driver may make use of any @var{driver_options} to configure its
7476 @deffn {Command} {pld devices}
7477 Lists the PLDs and their numbers.
7480 @deffn {Command} {pld load} num filename
7481 Loads the file @file{filename} into the PLD identified by @var{num}.
7482 The file format must be inferred by the driver.
7485 @section PLD/FPGA Drivers, Options, and Commands
7487 Drivers may support PLD-specific options to the @command{pld device}
7488 definition command, and may also define commands usable only with
7489 that particular type of PLD.
7491 @deffn {FPGA Driver} virtex2 [no_jstart]
7492 Virtex-II is a family of FPGAs sold by Xilinx.
7493 It supports the IEEE 1532 standard for In-System Configuration (ISC).
7495 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
7496 loading the bitstream. While required for Series2, Series3, and Series6, it
7497 breaks bitstream loading on Series7.
7499 @deffn {Command} {virtex2 read_stat} num
7500 Reads and displays the Virtex-II status register (STAT)
7505 @node General Commands
7506 @chapter General Commands
7509 The commands documented in this chapter here are common commands that
7510 you, as a human, may want to type and see the output of. Configuration type
7511 commands are documented elsewhere.
7515 @item @b{Source Of Commands}
7516 @* OpenOCD commands can occur in a configuration script (discussed
7517 elsewhere) or typed manually by a human or supplied programmatically,
7518 or via one of several TCP/IP Ports.
7520 @item @b{From the human}
7521 @* A human should interact with the telnet interface (default port: 4444)
7522 or via GDB (default port 3333).
7524 To issue commands from within a GDB session, use the @option{monitor}
7525 command, e.g. use @option{monitor poll} to issue the @option{poll}
7526 command. All output is relayed through the GDB session.
7528 @item @b{Machine Interface}
7529 The Tcl interface's intent is to be a machine interface. The default Tcl
7534 @section Server Commands
7536 @deffn {Command} exit
7537 Exits the current telnet session.
7540 @deffn {Command} help [string]
7541 With no parameters, prints help text for all commands.
7542 Otherwise, prints each helptext containing @var{string}.
7543 Not every command provides helptext.
7545 Configuration commands, and commands valid at any time, are
7546 explicitly noted in parenthesis.
7547 In most cases, no such restriction is listed; this indicates commands
7548 which are only available after the configuration stage has completed.
7551 @deffn Command sleep msec [@option{busy}]
7552 Wait for at least @var{msec} milliseconds before resuming.
7553 If @option{busy} is passed, busy-wait instead of sleeping.
7554 (This option is strongly discouraged.)
7555 Useful in connection with script files
7556 (@command{script} command and @command{target_name} configuration).
7559 @deffn Command shutdown [@option{error}]
7560 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
7561 other). If option @option{error} is used, OpenOCD will return a
7562 non-zero exit code to the parent process.
7564 Like any TCL commands, also @command{shutdown} can be redefined, e.g.:
7567 rename shutdown original_shutdown
7568 proc shutdown @{@} @{
7569 puts "This is my implementation of shutdown"
7570 # my own stuff before exit OpenOCD
7574 If user types CTRL-C or kills OpenOCD, either the command @command{shutdown}
7575 or its replacement will be automatically executed before OpenOCD exits.
7579 @deffn Command debug_level [n]
7580 @cindex message level
7581 Display debug level.
7582 If @var{n} (from 0..4) is provided, then set it to that level.
7583 This affects the kind of messages sent to the server log.
7584 Level 0 is error messages only;
7585 level 1 adds warnings;
7586 level 2 adds informational messages;
7587 level 3 adds debugging messages;
7588 and level 4 adds verbose low-level debug messages.
7589 The default is level 2, but that can be overridden on
7590 the command line along with the location of that log
7591 file (which is normally the server's standard output).
7595 @deffn Command echo [-n] message
7596 Logs a message at "user" priority.
7597 Output @var{message} to stdout.
7598 Option "-n" suppresses trailing newline.
7600 echo "Downloading kernel -- please wait"
7604 @deffn Command log_output [filename]
7605 Redirect logging to @var{filename};
7606 the initial log output channel is stderr.
7609 @deffn Command add_script_search_dir [directory]
7610 Add @var{directory} to the file/script search path.
7613 @deffn Command bindto [@var{name}]
7614 Specify hostname or IPv4 address on which to listen for incoming
7615 TCP/IP connections. By default, OpenOCD will listen on the loopback
7616 interface only. If your network environment is safe, @code{bindto
7617 0.0.0.0} can be used to cover all available interfaces.
7620 @anchor{targetstatehandling}
7621 @section Target State handling
7624 @cindex target initialization
7626 In this section ``target'' refers to a CPU configured as
7627 shown earlier (@pxref{CPU Configuration}).
7628 These commands, like many, implicitly refer to
7629 a current target which is used to perform the
7630 various operations. The current target may be changed
7631 by using @command{targets} command with the name of the
7632 target which should become current.
7634 @deffn Command reg [(number|name) [(value|'force')]]
7635 Access a single register by @var{number} or by its @var{name}.
7636 The target must generally be halted before access to CPU core
7637 registers is allowed. Depending on the hardware, some other
7638 registers may be accessible while the target is running.
7640 @emph{With no arguments}:
7641 list all available registers for the current target,
7642 showing number, name, size, value, and cache status.
7643 For valid entries, a value is shown; valid entries
7644 which are also dirty (and will be written back later)
7645 are flagged as such.
7647 @emph{With number/name}: display that register's value.
7648 Use @var{force} argument to read directly from the target,
7649 bypassing any internal cache.
7651 @emph{With both number/name and value}: set register's value.
7652 Writes may be held in a writeback cache internal to OpenOCD,
7653 so that setting the value marks the register as dirty instead
7654 of immediately flushing that value. Resuming CPU execution
7655 (including by single stepping) or otherwise activating the
7656 relevant module will flush such values.
7658 Cores may have surprisingly many registers in their
7659 Debug and trace infrastructure:
7664 (0) r0 (/32): 0x0000D3C2 (dirty)
7665 (1) r1 (/32): 0xFD61F31C
7668 (164) ETM_contextid_comparator_mask (/32)
7673 @deffn Command halt [ms]
7674 @deffnx Command wait_halt [ms]
7675 The @command{halt} command first sends a halt request to the target,
7676 which @command{wait_halt} doesn't.
7677 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7678 or 5 seconds if there is no parameter, for the target to halt
7679 (and enter debug mode).
7680 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7683 On ARM cores, software using the @emph{wait for interrupt} operation
7684 often blocks the JTAG access needed by a @command{halt} command.
7685 This is because that operation also puts the core into a low
7686 power mode by gating the core clock;
7687 but the core clock is needed to detect JTAG clock transitions.
7689 One partial workaround uses adaptive clocking: when the core is
7690 interrupted the operation completes, then JTAG clocks are accepted
7691 at least until the interrupt handler completes.
7692 However, this workaround is often unusable since the processor, board,
7693 and JTAG adapter must all support adaptive JTAG clocking.
7694 Also, it can't work until an interrupt is issued.
7696 A more complete workaround is to not use that operation while you
7697 work with a JTAG debugger.
7698 Tasking environments generally have idle loops where the body is the
7699 @emph{wait for interrupt} operation.
7700 (On older cores, it is a coprocessor action;
7701 newer cores have a @option{wfi} instruction.)
7702 Such loops can just remove that operation, at the cost of higher
7703 power consumption (because the CPU is needlessly clocked).
7708 @deffn Command resume [address]
7709 Resume the target at its current code position,
7710 or the optional @var{address} if it is provided.
7711 OpenOCD will wait 5 seconds for the target to resume.
7714 @deffn Command step [address]
7715 Single-step the target at its current code position,
7716 or the optional @var{address} if it is provided.
7719 @anchor{resetcommand}
7720 @deffn Command reset
7721 @deffnx Command {reset run}
7722 @deffnx Command {reset halt}
7723 @deffnx Command {reset init}
7724 Perform as hard a reset as possible, using SRST if possible.
7725 @emph{All defined targets will be reset, and target
7726 events will fire during the reset sequence.}
7728 The optional parameter specifies what should
7729 happen after the reset.
7730 If there is no parameter, a @command{reset run} is executed.
7731 The other options will not work on all systems.
7732 @xref{Reset Configuration}.
7735 @item @b{run} Let the target run
7736 @item @b{halt} Immediately halt the target
7737 @item @b{init} Immediately halt the target, and execute the reset-init script
7741 @deffn Command soft_reset_halt
7742 Requesting target halt and executing a soft reset. This is often used
7743 when a target cannot be reset and halted. The target, after reset is
7744 released begins to execute code. OpenOCD attempts to stop the CPU and
7745 then sets the program counter back to the reset vector. Unfortunately
7746 the code that was executed may have left the hardware in an unknown
7750 @section I/O Utilities
7752 These commands are available when
7753 OpenOCD is built with @option{--enable-ioutil}.
7754 They are mainly useful on embedded targets,
7756 Hosts with operating systems have complementary tools.
7758 @emph{Note:} there are several more such commands.
7760 @deffn Command append_file filename [string]*
7761 Appends the @var{string} parameters to
7762 the text file @file{filename}.
7763 Each string except the last one is followed by one space.
7764 The last string is followed by a newline.
7767 @deffn Command cat filename
7768 Reads and displays the text file @file{filename}.
7771 @deffn Command cp src_filename dest_filename
7772 Copies contents from the file @file{src_filename}
7773 into @file{dest_filename}.
7777 @emph{No description provided.}
7781 @emph{No description provided.}
7785 @emph{No description provided.}
7788 @deffn Command meminfo
7789 Display available RAM memory on OpenOCD host.
7790 Used in OpenOCD regression testing scripts.
7794 @emph{No description provided.}
7798 @emph{No description provided.}
7801 @deffn Command rm filename
7802 @c "rm" has both normal and Jim-level versions??
7803 Unlinks the file @file{filename}.
7806 @deffn Command trunc filename
7807 Removes all data in the file @file{filename}.
7810 @anchor{memoryaccess}
7811 @section Memory access commands
7812 @cindex memory access
7814 These commands allow accesses of a specific size to the memory
7815 system. Often these are used to configure the current target in some
7816 special way. For example - one may need to write certain values to the
7817 SDRAM controller to enable SDRAM.
7820 @item Use the @command{targets} (plural) command
7821 to change the current target.
7822 @item In system level scripts these commands are deprecated.
7823 Please use their TARGET object siblings to avoid making assumptions
7824 about what TAP is the current target, or about MMU configuration.
7827 @deffn Command mdw [phys] addr [count]
7828 @deffnx Command mdh [phys] addr [count]
7829 @deffnx Command mdb [phys] addr [count]
7830 Display contents of address @var{addr}, as
7831 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7832 or 8-bit bytes (@command{mdb}).
7833 When the current target has an MMU which is present and active,
7834 @var{addr} is interpreted as a virtual address.
7835 Otherwise, or if the optional @var{phys} flag is specified,
7836 @var{addr} is interpreted as a physical address.
7837 If @var{count} is specified, displays that many units.
7838 (If you want to manipulate the data instead of displaying it,
7839 see the @code{mem2array} primitives.)
7842 @deffn Command mww [phys] addr word
7843 @deffnx Command mwh [phys] addr halfword
7844 @deffnx Command mwb [phys] addr byte
7845 Writes the specified @var{word} (32 bits),
7846 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7847 at the specified address @var{addr}.
7848 When the current target has an MMU which is present and active,
7849 @var{addr} is interpreted as a virtual address.
7850 Otherwise, or if the optional @var{phys} flag is specified,
7851 @var{addr} is interpreted as a physical address.
7854 @anchor{imageaccess}
7855 @section Image loading commands
7856 @cindex image loading
7857 @cindex image dumping
7859 @deffn Command {dump_image} filename address size
7860 Dump @var{size} bytes of target memory starting at @var{address} to the
7861 binary file named @var{filename}.
7864 @deffn Command {fast_load}
7865 Loads an image stored in memory by @command{fast_load_image} to the
7866 current target. Must be preceded by fast_load_image.
7869 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7870 Normally you should be using @command{load_image} or GDB load. However, for
7871 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7872 host), storing the image in memory and uploading the image to the target
7873 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7874 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7875 memory, i.e. does not affect target. This approach is also useful when profiling
7876 target programming performance as I/O and target programming can easily be profiled
7880 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7881 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7882 The file format may optionally be specified
7883 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7884 In addition the following arguments may be specified:
7885 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
7886 @var{max_length} - maximum number of bytes to load.
7888 proc load_image_bin @{fname foffset address length @} @{
7889 # Load data from fname filename at foffset offset to
7890 # target at address. Load at most length bytes.
7891 load_image $fname [expr $address - $foffset] bin \
7897 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
7898 Displays image section sizes and addresses
7899 as if @var{filename} were loaded into target memory
7900 starting at @var{address} (defaults to zero).
7901 The file format may optionally be specified
7902 (@option{bin}, @option{ihex}, or @option{elf})
7905 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
7906 Verify @var{filename} against target memory starting at @var{address}.
7907 The file format may optionally be specified
7908 (@option{bin}, @option{ihex}, or @option{elf})
7909 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
7912 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
7913 Verify @var{filename} against target memory starting at @var{address}.
7914 The file format may optionally be specified
7915 (@option{bin}, @option{ihex}, or @option{elf})
7916 This perform a comparison using a CRC checksum only
7920 @section Breakpoint and Watchpoint commands
7924 CPUs often make debug modules accessible through JTAG, with
7925 hardware support for a handful of code breakpoints and data
7927 In addition, CPUs almost always support software breakpoints.
7929 @deffn Command {bp} [address len [@option{hw}]]
7930 With no parameters, lists all active breakpoints.
7931 Else sets a breakpoint on code execution starting
7932 at @var{address} for @var{length} bytes.
7933 This is a software breakpoint, unless @option{hw} is specified
7934 in which case it will be a hardware breakpoint.
7936 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
7937 for similar mechanisms that do not consume hardware breakpoints.)
7940 @deffn Command {rbp} address
7941 Remove the breakpoint at @var{address}.
7944 @deffn Command {rwp} address
7945 Remove data watchpoint on @var{address}
7948 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
7949 With no parameters, lists all active watchpoints.
7950 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7951 The watch point is an "access" watchpoint unless
7952 the @option{r} or @option{w} parameter is provided,
7953 defining it as respectively a read or write watchpoint.
7954 If a @var{value} is provided, that value is used when determining if
7955 the watchpoint should trigger. The value may be first be masked
7956 using @var{mask} to mark ``don't care'' fields.
7959 @section Misc Commands
7962 @deffn Command {profile} seconds filename [start end]
7963 Profiling samples the CPU's program counter as quickly as possible,
7964 which is useful for non-intrusive stochastic profiling.
7965 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7966 format. Optional @option{start} and @option{end} parameters allow to
7967 limit the address range.
7970 @deffn Command {version}
7971 Displays a string identifying the version of this OpenOCD server.
7974 @deffn Command {virt2phys} virtual_address
7975 Requests the current target to map the specified @var{virtual_address}
7976 to its corresponding physical address, and displays the result.
7979 @node Architecture and Core Commands
7980 @chapter Architecture and Core Commands
7981 @cindex Architecture Specific Commands
7982 @cindex Core Specific Commands
7984 Most CPUs have specialized JTAG operations to support debugging.
7985 OpenOCD packages most such operations in its standard command framework.
7986 Some of those operations don't fit well in that framework, so they are
7987 exposed here as architecture or implementation (core) specific commands.
7989 @anchor{armhardwaretracing}
7990 @section ARM Hardware Tracing
7995 CPUs based on ARM cores may include standard tracing interfaces,
7996 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7997 address and data bus trace records to a ``Trace Port''.
8001 Development-oriented boards will sometimes provide a high speed
8002 trace connector for collecting that data, when the particular CPU
8003 supports such an interface.
8004 (The standard connector is a 38-pin Mictor, with both JTAG
8005 and trace port support.)
8006 Those trace connectors are supported by higher end JTAG adapters
8007 and some logic analyzer modules; frequently those modules can
8008 buffer several megabytes of trace data.
8009 Configuring an ETM coupled to such an external trace port belongs
8010 in the board-specific configuration file.
8012 If the CPU doesn't provide an external interface, it probably
8013 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
8014 dedicated SRAM. 4KBytes is one common ETB size.
8015 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
8016 (target) configuration file, since it works the same on all boards.
8019 ETM support in OpenOCD doesn't seem to be widely used yet.
8022 ETM support may be buggy, and at least some @command{etm config}
8023 parameters should be detected by asking the ETM for them.
8025 ETM trigger events could also implement a kind of complex
8026 hardware breakpoint, much more powerful than the simple
8027 watchpoint hardware exported by EmbeddedICE modules.
8028 @emph{Such breakpoints can be triggered even when using the
8029 dummy trace port driver}.
8031 It seems like a GDB hookup should be possible,
8032 as well as tracing only during specific states
8033 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
8035 There should be GUI tools to manipulate saved trace data and help
8036 analyse it in conjunction with the source code.
8037 It's unclear how much of a common interface is shared
8038 with the current XScale trace support, or should be
8039 shared with eventual Nexus-style trace module support.
8041 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
8042 for ETM modules is available. The code should be able to
8043 work with some newer cores; but not all of them support
8044 this original style of JTAG access.
8047 @subsection ETM Configuration
8048 ETM setup is coupled with the trace port driver configuration.
8050 @deffn {Config Command} {etm config} target width mode clocking driver
8051 Declares the ETM associated with @var{target}, and associates it
8052 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
8054 Several of the parameters must reflect the trace port capabilities,
8055 which are a function of silicon capabilities (exposed later
8056 using @command{etm info}) and of what hardware is connected to
8057 that port (such as an external pod, or ETB).
8058 The @var{width} must be either 4, 8, or 16,
8059 except with ETMv3.0 and newer modules which may also
8060 support 1, 2, 24, 32, 48, and 64 bit widths.
8061 (With those versions, @command{etm info} also shows whether
8062 the selected port width and mode are supported.)
8064 The @var{mode} must be @option{normal}, @option{multiplexed},
8065 or @option{demultiplexed}.
8066 The @var{clocking} must be @option{half} or @option{full}.
8069 With ETMv3.0 and newer, the bits set with the @var{mode} and
8070 @var{clocking} parameters both control the mode.
8071 This modified mode does not map to the values supported by
8072 previous ETM modules, so this syntax is subject to change.
8076 You can see the ETM registers using the @command{reg} command.
8077 Not all possible registers are present in every ETM.
8078 Most of the registers are write-only, and are used to configure
8079 what CPU activities are traced.
8083 @deffn Command {etm info}
8084 Displays information about the current target's ETM.
8085 This includes resource counts from the @code{ETM_CONFIG} register,
8086 as well as silicon capabilities (except on rather old modules).
8087 from the @code{ETM_SYS_CONFIG} register.
8090 @deffn Command {etm status}
8091 Displays status of the current target's ETM and trace port driver:
8092 is the ETM idle, or is it collecting data?
8093 Did trace data overflow?
8097 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
8098 Displays what data that ETM will collect.
8099 If arguments are provided, first configures that data.
8100 When the configuration changes, tracing is stopped
8101 and any buffered trace data is invalidated.
8104 @item @var{type} ... describing how data accesses are traced,
8105 when they pass any ViewData filtering that that was set up.
8107 @option{none} (save nothing),
8108 @option{data} (save data),
8109 @option{address} (save addresses),
8110 @option{all} (save data and addresses)
8111 @item @var{context_id_bits} ... 0, 8, 16, or 32
8112 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
8113 cycle-accurate instruction tracing.
8114 Before ETMv3, enabling this causes much extra data to be recorded.
8115 @item @var{branch_output} ... @option{enable} or @option{disable}.
8116 Disable this unless you need to try reconstructing the instruction
8117 trace stream without an image of the code.
8121 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
8122 Displays whether ETM triggering debug entry (like a breakpoint) is
8123 enabled or disabled, after optionally modifying that configuration.
8124 The default behaviour is @option{disable}.
8125 Any change takes effect after the next @command{etm start}.
8127 By using script commands to configure ETM registers, you can make the
8128 processor enter debug state automatically when certain conditions,
8129 more complex than supported by the breakpoint hardware, happen.
8132 @subsection ETM Trace Operation
8134 After setting up the ETM, you can use it to collect data.
8135 That data can be exported to files for later analysis.
8136 It can also be parsed with OpenOCD, for basic sanity checking.
8138 To configure what is being traced, you will need to write
8139 various trace registers using @command{reg ETM_*} commands.
8140 For the definitions of these registers, read ARM publication
8141 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
8142 Be aware that most of the relevant registers are write-only,
8143 and that ETM resources are limited. There are only a handful
8144 of address comparators, data comparators, counters, and so on.
8146 Examples of scenarios you might arrange to trace include:
8149 @item Code flow within a function, @emph{excluding} subroutines
8150 it calls. Use address range comparators to enable tracing
8151 for instruction access within that function's body.
8152 @item Code flow within a function, @emph{including} subroutines
8153 it calls. Use the sequencer and address comparators to activate
8154 tracing on an ``entered function'' state, then deactivate it by
8155 exiting that state when the function's exit code is invoked.
8156 @item Code flow starting at the fifth invocation of a function,
8157 combining one of the above models with a counter.
8158 @item CPU data accesses to the registers for a particular device,
8159 using address range comparators and the ViewData logic.
8160 @item Such data accesses only during IRQ handling, combining the above
8161 model with sequencer triggers which on entry and exit to the IRQ handler.
8162 @item @emph{... more}
8165 At this writing, September 2009, there are no Tcl utility
8166 procedures to help set up any common tracing scenarios.
8168 @deffn Command {etm analyze}
8169 Reads trace data into memory, if it wasn't already present.
8170 Decodes and prints the data that was collected.
8173 @deffn Command {etm dump} filename
8174 Stores the captured trace data in @file{filename}.
8177 @deffn Command {etm image} filename [base_address] [type]
8178 Opens an image file.
8181 @deffn Command {etm load} filename
8182 Loads captured trace data from @file{filename}.
8185 @deffn Command {etm start}
8186 Starts trace data collection.
8189 @deffn Command {etm stop}
8190 Stops trace data collection.
8193 @anchor{traceportdrivers}
8194 @subsection Trace Port Drivers
8196 To use an ETM trace port it must be associated with a driver.
8198 @deffn {Trace Port Driver} dummy
8199 Use the @option{dummy} driver if you are configuring an ETM that's
8200 not connected to anything (on-chip ETB or off-chip trace connector).
8201 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
8202 any trace data collection.}
8203 @deffn {Config Command} {etm_dummy config} target
8204 Associates the ETM for @var{target} with a dummy driver.
8208 @deffn {Trace Port Driver} etb
8209 Use the @option{etb} driver if you are configuring an ETM
8210 to use on-chip ETB memory.
8211 @deffn {Config Command} {etb config} target etb_tap
8212 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
8213 You can see the ETB registers using the @command{reg} command.
8215 @deffn Command {etb trigger_percent} [percent]
8216 This displays, or optionally changes, ETB behavior after the
8217 ETM's configured @emph{trigger} event fires.
8218 It controls how much more trace data is saved after the (single)
8219 trace trigger becomes active.
8222 @item The default corresponds to @emph{trace around} usage,
8223 recording 50 percent data before the event and the rest
8225 @item The minimum value of @var{percent} is 2 percent,
8226 recording almost exclusively data before the trigger.
8227 Such extreme @emph{trace before} usage can help figure out
8228 what caused that event to happen.
8229 @item The maximum value of @var{percent} is 100 percent,
8230 recording data almost exclusively after the event.
8231 This extreme @emph{trace after} usage might help sort out
8232 how the event caused trouble.
8234 @c REVISIT allow "break" too -- enter debug mode.
8239 @deffn {Trace Port Driver} oocd_trace
8240 This driver isn't available unless OpenOCD was explicitly configured
8241 with the @option{--enable-oocd_trace} option. You probably don't want
8242 to configure it unless you've built the appropriate prototype hardware;
8243 it's @emph{proof-of-concept} software.
8245 Use the @option{oocd_trace} driver if you are configuring an ETM that's
8246 connected to an off-chip trace connector.
8248 @deffn {Config Command} {oocd_trace config} target tty
8249 Associates the ETM for @var{target} with a trace driver which
8250 collects data through the serial port @var{tty}.
8253 @deffn Command {oocd_trace resync}
8254 Re-synchronizes with the capture clock.
8257 @deffn Command {oocd_trace status}
8258 Reports whether the capture clock is locked or not.
8262 @anchor{armcrosstrigger}
8263 @section ARM Cross-Trigger Interface
8266 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
8267 that connects event sources like tracing components or CPU cores with each
8268 other through a common trigger matrix (CTM). For ARMv8 architecture, a
8269 CTI is mandatory for core run control and each core has an individual
8270 CTI instance attached to it. OpenOCD has limited support for CTI using
8271 the @emph{cti} group of commands.
8273 @deffn Command {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-ctibase} base_address
8274 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
8275 @var{apn}. The @var{base_address} must match the base address of the CTI
8276 on the respective MEM-AP. All arguments are mandatory. This creates a
8277 new command @command{$cti_name} which is used for various purposes
8278 including additional configuration.
8281 @deffn Command {$cti_name enable} @option{on|off}
8282 Enable (@option{on}) or disable (@option{off}) the CTI.
8285 @deffn Command {$cti_name dump}
8286 Displays a register dump of the CTI.
8289 @deffn Command {$cti_name write } @var{reg_name} @var{value}
8290 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
8293 @deffn Command {$cti_name read} @var{reg_name}
8294 Print the value read from the CTI register with the symbolic name @var{reg_name}.
8297 @deffn Command {$cti_name testmode} @option{on|off}
8298 Enable (@option{on}) or disable (@option{off}) the integration test mode
8302 @deffn Command {cti names}
8303 Prints a list of names of all CTI objects created. This command is mainly
8304 useful in TCL scripting.
8307 @section Generic ARM
8310 These commands should be available on all ARM processors.
8311 They are available in addition to other core-specific
8312 commands that may be available.
8314 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
8315 Displays the core_state, optionally changing it to process
8316 either @option{arm} or @option{thumb} instructions.
8317 The target may later be resumed in the currently set core_state.
8318 (Processors may also support the Jazelle state, but
8319 that is not currently supported in OpenOCD.)
8322 @deffn Command {arm disassemble} address [count [@option{thumb}]]
8324 Disassembles @var{count} instructions starting at @var{address}.
8325 If @var{count} is not specified, a single instruction is disassembled.
8326 If @option{thumb} is specified, or the low bit of the address is set,
8327 Thumb2 (mixed 16/32-bit) instructions are used;
8328 else ARM (32-bit) instructions are used.
8329 (Processors may also support the Jazelle state, but
8330 those instructions are not currently understood by OpenOCD.)
8332 Note that all Thumb instructions are Thumb2 instructions,
8333 so older processors (without Thumb2 support) will still
8334 see correct disassembly of Thumb code.
8335 Also, ThumbEE opcodes are the same as Thumb2,
8336 with a handful of exceptions.
8337 ThumbEE disassembly currently has no explicit support.
8340 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
8341 Write @var{value} to a coprocessor @var{pX} register
8342 passing parameters @var{CRn},
8343 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8344 and using the MCR instruction.
8345 (Parameter sequence matches the ARM instruction, but omits
8349 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
8350 Read a coprocessor @var{pX} register passing parameters @var{CRn},
8351 @var{CRm}, opcodes @var{opc1} and @var{opc2},
8352 and the MRC instruction.
8353 Returns the result so it can be manipulated by Jim scripts.
8354 (Parameter sequence matches the ARM instruction, but omits
8358 @deffn Command {arm reg}
8359 Display a table of all banked core registers, fetching the current value from every
8360 core mode if necessary.
8363 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
8364 @cindex ARM semihosting
8365 Display status of semihosting, after optionally changing that status.
8367 Semihosting allows for code executing on an ARM target to use the
8368 I/O facilities on the host computer i.e. the system where OpenOCD
8369 is running. The target application must be linked against a library
8370 implementing the ARM semihosting convention that forwards operation
8371 requests by using a special SVC instruction that is trapped at the
8372 Supervisor Call vector by OpenOCD.
8375 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
8376 @cindex ARM semihosting
8377 Set the command line to be passed to the debugger.
8380 arm semihosting_cmdline argv0 argv1 argv2 ...
8383 This option lets one set the command line arguments to be passed to
8384 the program. The first argument (argv0) is the program name in a
8385 standard C environment (argv[0]). Depending on the program (not much
8386 programs look at argv[0]), argv0 is ignored and can be any string.
8389 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
8390 @cindex ARM semihosting
8391 Display status of semihosting fileio, after optionally changing that
8394 Enabling this option forwards semihosting I/O to GDB process using the
8395 File-I/O remote protocol extension. This is especially useful for
8396 interacting with remote files or displaying console messages in the
8400 @deffn Command {arm semihosting_resexit} [@option{enable}|@option{disable}]
8401 @cindex ARM semihosting
8402 Enable resumable SEMIHOSTING_SYS_EXIT.
8404 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
8405 things are simple, the openocd process calls exit() and passes
8406 the value returned by the target.
8408 When SEMIHOSTING_SYS_EXIT is called during a debug session,
8409 by default execution returns to the debugger, leaving the
8410 debugger in a HALT state, similar to the state entered when
8411 encountering a break.
8413 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
8414 return normally, as any semihosting call, and do not break
8416 The standard allows this to happen, but the condition
8417 to trigger it is a bit obscure ("by performing an RDI_Execute
8418 request or equivalent").
8420 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
8421 this option (default: disabled).
8424 @section ARMv4 and ARMv5 Architecture
8428 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
8429 and introduced core parts of the instruction set in use today.
8430 That includes the Thumb instruction set, introduced in the ARMv4T
8433 @subsection ARM7 and ARM9 specific commands
8437 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
8438 ARM9TDMI, ARM920T or ARM926EJ-S.
8439 They are available in addition to the ARM commands,
8440 and any other core-specific commands that may be available.
8442 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
8443 Displays the value of the flag controlling use of the
8444 the EmbeddedIce DBGRQ signal to force entry into debug mode,
8445 instead of breakpoints.
8446 If a boolean parameter is provided, first assigns that flag.
8449 safe for all but ARM7TDMI-S cores (like NXP LPC).
8450 This feature is enabled by default on most ARM9 cores,
8451 including ARM9TDMI, ARM920T, and ARM926EJ-S.
8454 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
8456 Displays the value of the flag controlling use of the debug communications
8457 channel (DCC) to write larger (>128 byte) amounts of memory.
8458 If a boolean parameter is provided, first assigns that flag.
8460 DCC downloads offer a huge speed increase, but might be
8461 unsafe, especially with targets running at very low speeds. This command was introduced
8462 with OpenOCD rev. 60, and requires a few bytes of working area.
8465 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
8466 Displays the value of the flag controlling use of memory writes and reads
8467 that don't check completion of the operation.
8468 If a boolean parameter is provided, first assigns that flag.
8470 This provides a huge speed increase, especially with USB JTAG
8471 cables (FT2232), but might be unsafe if used with targets running at very low
8472 speeds, like the 32kHz startup clock of an AT91RM9200.
8475 @subsection ARM720T specific commands
8478 These commands are available to ARM720T based CPUs,
8479 which are implementations of the ARMv4T architecture
8480 based on the ARM7TDMI-S integer core.
8481 They are available in addition to the ARM and ARM7/ARM9 commands.
8483 @deffn Command {arm720t cp15} opcode [value]
8484 @emph{DEPRECATED -- avoid using this.
8485 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8487 Display cp15 register returned by the ARM instruction @var{opcode};
8488 else if a @var{value} is provided, that value is written to that register.
8489 The @var{opcode} should be the value of either an MRC or MCR instruction.
8492 @subsection ARM9 specific commands
8495 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
8497 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
8499 @c 9-june-2009: tried this on arm920t, it didn't work.
8500 @c no-params always lists nothing caught, and that's how it acts.
8501 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
8502 @c versions have different rules about when they commit writes.
8504 @anchor{arm9vectorcatch}
8505 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
8506 @cindex vector_catch
8507 Vector Catch hardware provides a sort of dedicated breakpoint
8508 for hardware events such as reset, interrupt, and abort.
8509 You can use this to conserve normal breakpoint resources,
8510 so long as you're not concerned with code that branches directly
8511 to those hardware vectors.
8513 This always finishes by listing the current configuration.
8514 If parameters are provided, it first reconfigures the
8515 vector catch hardware to intercept
8516 @option{all} of the hardware vectors,
8517 @option{none} of them,
8518 or a list with one or more of the following:
8519 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
8520 @option{irq} @option{fiq}.
8523 @subsection ARM920T specific commands
8526 These commands are available to ARM920T based CPUs,
8527 which are implementations of the ARMv4T architecture
8528 built using the ARM9TDMI integer core.
8529 They are available in addition to the ARM, ARM7/ARM9,
8532 @deffn Command {arm920t cache_info}
8533 Print information about the caches found. This allows to see whether your target
8534 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
8537 @deffn Command {arm920t cp15} regnum [value]
8538 Display cp15 register @var{regnum};
8539 else if a @var{value} is provided, that value is written to that register.
8540 This uses "physical access" and the register number is as
8541 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
8542 (Not all registers can be written.)
8545 @deffn Command {arm920t cp15i} opcode [value [address]]
8546 @emph{DEPRECATED -- avoid using this.
8547 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
8549 Interpreted access using ARM instruction @var{opcode}, which should
8550 be the value of either an MRC or MCR instruction
8551 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
8552 If no @var{value} is provided, the result is displayed.
8553 Else if that value is written using the specified @var{address},
8554 or using zero if no other address is provided.
8557 @deffn Command {arm920t read_cache} filename
8558 Dump the content of ICache and DCache to a file named @file{filename}.
8561 @deffn Command {arm920t read_mmu} filename
8562 Dump the content of the ITLB and DTLB to a file named @file{filename}.
8565 @subsection ARM926ej-s specific commands
8568 These commands are available to ARM926ej-s based CPUs,
8569 which are implementations of the ARMv5TEJ architecture
8570 based on the ARM9EJ-S integer core.
8571 They are available in addition to the ARM, ARM7/ARM9,
8574 The Feroceon cores also support these commands, although
8575 they are not built from ARM926ej-s designs.
8577 @deffn Command {arm926ejs cache_info}
8578 Print information about the caches found.
8581 @subsection ARM966E specific commands
8584 These commands are available to ARM966 based CPUs,
8585 which are implementations of the ARMv5TE architecture.
8586 They are available in addition to the ARM, ARM7/ARM9,
8589 @deffn Command {arm966e cp15} regnum [value]
8590 Display cp15 register @var{regnum};
8591 else if a @var{value} is provided, that value is written to that register.
8592 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
8594 There is no current control over bits 31..30 from that table,
8595 as required for BIST support.
8598 @subsection XScale specific commands
8601 Some notes about the debug implementation on the XScale CPUs:
8603 The XScale CPU provides a special debug-only mini-instruction cache
8604 (mini-IC) in which exception vectors and target-resident debug handler
8605 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
8606 must point vector 0 (the reset vector) to the entry of the debug
8607 handler. However, this means that the complete first cacheline in the
8608 mini-IC is marked valid, which makes the CPU fetch all exception
8609 handlers from the mini-IC, ignoring the code in RAM.
8611 To address this situation, OpenOCD provides the @code{xscale
8612 vector_table} command, which allows the user to explicitly write
8613 individual entries to either the high or low vector table stored in
8616 It is recommended to place a pc-relative indirect branch in the vector
8617 table, and put the branch destination somewhere in memory. Doing so
8618 makes sure the code in the vector table stays constant regardless of
8619 code layout in memory:
8622 ldr pc,[pc,#0x100-8]
8623 ldr pc,[pc,#0x100-8]
8624 ldr pc,[pc,#0x100-8]
8625 ldr pc,[pc,#0x100-8]
8626 ldr pc,[pc,#0x100-8]
8627 ldr pc,[pc,#0x100-8]
8628 ldr pc,[pc,#0x100-8]
8629 ldr pc,[pc,#0x100-8]
8631 .long real_reset_vector
8632 .long real_ui_handler
8633 .long real_swi_handler
8635 .long real_data_abort
8636 .long 0 /* unused */
8637 .long real_irq_handler
8638 .long real_fiq_handler
8641 Alternatively, you may choose to keep some or all of the mini-IC
8642 vector table entries synced with those written to memory by your
8643 system software. The mini-IC can not be modified while the processor
8644 is executing, but for each vector table entry not previously defined
8645 using the @code{xscale vector_table} command, OpenOCD will copy the
8646 value from memory to the mini-IC every time execution resumes from a
8647 halt. This is done for both high and low vector tables (although the
8648 table not in use may not be mapped to valid memory, and in this case
8649 that copy operation will silently fail). This means that you will
8650 need to briefly halt execution at some strategic point during system
8651 start-up; e.g., after the software has initialized the vector table,
8652 but before exceptions are enabled. A breakpoint can be used to
8653 accomplish this once the appropriate location in the start-up code has
8654 been identified. A watchpoint over the vector table region is helpful
8655 in finding the location if you're not sure. Note that the same
8656 situation exists any time the vector table is modified by the system
8659 The debug handler must be placed somewhere in the address space using
8660 the @code{xscale debug_handler} command. The allowed locations for the
8661 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
8662 0xfffff800). The default value is 0xfe000800.
8664 XScale has resources to support two hardware breakpoints and two
8665 watchpoints. However, the following restrictions on watchpoint
8666 functionality apply: (1) the value and mask arguments to the @code{wp}
8667 command are not supported, (2) the watchpoint length must be a
8668 power of two and not less than four, and can not be greater than the
8669 watchpoint address, and (3) a watchpoint with a length greater than
8670 four consumes all the watchpoint hardware resources. This means that
8671 at any one time, you can have enabled either two watchpoints with a
8672 length of four, or one watchpoint with a length greater than four.
8674 These commands are available to XScale based CPUs,
8675 which are implementations of the ARMv5TE architecture.
8677 @deffn Command {xscale analyze_trace}
8678 Displays the contents of the trace buffer.
8681 @deffn Command {xscale cache_clean_address} address
8682 Changes the address used when cleaning the data cache.
8685 @deffn Command {xscale cache_info}
8686 Displays information about the CPU caches.
8689 @deffn Command {xscale cp15} regnum [value]
8690 Display cp15 register @var{regnum};
8691 else if a @var{value} is provided, that value is written to that register.
8694 @deffn Command {xscale debug_handler} target address
8695 Changes the address used for the specified target's debug handler.
8698 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8699 Enables or disable the CPU's data cache.
8702 @deffn Command {xscale dump_trace} filename
8703 Dumps the raw contents of the trace buffer to @file{filename}.
8706 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8707 Enables or disable the CPU's instruction cache.
8710 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8711 Enables or disable the CPU's memory management unit.
8714 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8715 Displays the trace buffer status, after optionally
8716 enabling or disabling the trace buffer
8717 and modifying how it is emptied.
8720 @deffn Command {xscale trace_image} filename [offset [type]]
8721 Opens a trace image from @file{filename}, optionally rebasing
8722 its segment addresses by @var{offset}.
8723 The image @var{type} may be one of
8724 @option{bin} (binary), @option{ihex} (Intel hex),
8725 @option{elf} (ELF file), @option{s19} (Motorola s19),
8726 @option{mem}, or @option{builder}.
8729 @anchor{xscalevectorcatch}
8730 @deffn Command {xscale vector_catch} [mask]
8731 @cindex vector_catch
8732 Display a bitmask showing the hardware vectors to catch.
8733 If the optional parameter is provided, first set the bitmask to that value.
8735 The mask bits correspond with bit 16..23 in the DCSR:
8738 0x02 Trap Undefined Instructions
8739 0x04 Trap Software Interrupt
8740 0x08 Trap Prefetch Abort
8741 0x10 Trap Data Abort
8748 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8749 @cindex vector_table
8751 Set an entry in the mini-IC vector table. There are two tables: one for
8752 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8753 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8754 points to the debug handler entry and can not be overwritten.
8755 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8757 Without arguments, the current settings are displayed.
8761 @section ARMv6 Architecture
8764 @subsection ARM11 specific commands
8767 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
8768 Displays the value of the memwrite burst-enable flag,
8769 which is enabled by default.
8770 If a boolean parameter is provided, first assigns that flag.
8771 Burst writes are only used for memory writes larger than 1 word.
8772 They improve performance by assuming that the CPU has read each data
8773 word over JTAG and completed its write before the next word arrives,
8774 instead of polling for a status flag to verify that completion.
8775 This is usually safe, because JTAG runs much slower than the CPU.
8778 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
8779 Displays the value of the memwrite error_fatal flag,
8780 which is enabled by default.
8781 If a boolean parameter is provided, first assigns that flag.
8782 When set, certain memory write errors cause earlier transfer termination.
8785 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
8786 Displays the value of the flag controlling whether
8787 IRQs are enabled during single stepping;
8788 they are disabled by default.
8789 If a boolean parameter is provided, first assigns that.
8792 @deffn Command {arm11 vcr} [value]
8793 @cindex vector_catch
8794 Displays the value of the @emph{Vector Catch Register (VCR)},
8795 coprocessor 14 register 7.
8796 If @var{value} is defined, first assigns that.
8798 Vector Catch hardware provides dedicated breakpoints
8799 for certain hardware events.
8800 The specific bit values are core-specific (as in fact is using
8801 coprocessor 14 register 7 itself) but all current ARM11
8802 cores @emph{except the ARM1176} use the same six bits.
8805 @section ARMv7 and ARMv8 Architecture
8809 @subsection ARMv7-A specific commands
8812 @deffn Command {cortex_a cache_info}
8813 display information about target caches
8816 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8817 Work around issues with software breakpoints when the program text is
8818 mapped read-only by the operating system. This option sets the CP15 DACR
8819 to "all-manager" to bypass MMU permission checks on memory access.
8823 @deffn Command {cortex_a dbginit}
8824 Initialize core debug
8825 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8828 @deffn Command {cortex_a smp_off}
8832 @deffn Command {cortex_a smp_on}
8836 @deffn Command {cortex_a smp_gdb} [core_id]
8837 Display/set the current core displayed in GDB
8840 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8841 Selects whether interrupts will be processed when single stepping
8844 @deffn Command {cache_config l2x} [base way]
8848 @deffn Command {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
8849 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
8850 memory location @var{address}. When dumping the table from @var{address}, print at most
8851 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
8852 possible (4096) entries are printed.
8855 @subsection ARMv7-R specific commands
8858 @deffn Command {cortex_r dbginit}
8859 Initialize core debug
8860 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8863 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8864 Selects whether interrupts will be processed when single stepping
8868 @subsection ARMv7-M specific commands
8876 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8877 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8878 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8880 ARMv7-M architecture provides several modules to generate debugging
8881 information internally (ITM, DWT and ETM). Their output is directed
8882 through TPIU to be captured externally either on an SWO pin (this
8883 configuration is called SWV) or on a synchronous parallel trace port.
8885 This command configures the TPIU module of the target and, if internal
8886 capture mode is selected, starts to capture trace output by using the
8887 debugger adapter features.
8889 Some targets require additional actions to be performed in the
8890 @b{trace-config} handler for trace port to be activated.
8894 @item @option{disable} disable TPIU handling;
8895 @item @option{external} configure TPIU to let user capture trace
8896 output externally (with an additional UART or logic analyzer hardware);
8897 @item @option{internal @var{filename}} configure TPIU and debug adapter to
8898 gather trace data and append it to @var{filename} (which can be
8899 either a regular file or a named pipe);
8900 @item @option{internal -} configure TPIU and debug adapter to
8901 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
8902 @item @option{sync @var{port_width}} use synchronous parallel trace output
8903 mode, and set port width to @var{port_width};
8904 @item @option{manchester} use asynchronous SWO mode with Manchester
8906 @item @option{uart} use asynchronous SWO mode with NRZ (same as
8907 regular UART 8N1) coding;
8908 @item @var{formatter_enable} is @option{on} or @option{off} to enable
8909 or disable TPIU formatter which needs to be used when both ITM and ETM
8910 data is to be output via SWO;
8911 @item @var{TRACECLKIN_freq} this should be specified to match target's
8912 current TRACECLKIN frequency (usually the same as HCLK);
8913 @item @var{trace_freq} trace port frequency. Can be omitted in
8914 internal mode to let the adapter driver select the maximum supported
8920 @item STM32L152 board is programmed with an application that configures
8921 PLL to provide core clock with 24MHz frequency; to use ITM output it's
8924 #include <libopencm3/cm3/itm.h>
8929 (the most obvious way is to use the first stimulus port for printf,
8930 for that this ITM_STIM8 assignment can be used inside _write(); to make it
8931 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
8932 ITM_STIM_FIFOREADY));});
8933 @item An FT2232H UART is connected to the SWO pin of the board;
8934 @item Commands to configure UART for 12MHz baud rate:
8936 $ setserial /dev/ttyUSB1 spd_cust divisor 5
8937 $ stty -F /dev/ttyUSB1 38400
8939 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
8940 baud with our custom divisor to get 12MHz)
8941 @item @code{itmdump -f /dev/ttyUSB1 -d1}
8942 @item OpenOCD invocation line:
8944 openocd -f interface/stlink.cfg \
8945 -c "transport select hla_swd" \
8946 -f target/stm32l1.cfg \
8947 -c "tpiu config external uart off 24000000 12000000"
8952 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
8953 Enable or disable trace output for ITM stimulus @var{port} (counting
8954 from 0). Port 0 is enabled on target creation automatically.
8957 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
8958 Enable or disable trace output for all ITM stimulus ports.
8961 @subsection Cortex-M specific commands
8964 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
8965 Control masking (disabling) interrupts during target step/resume.
8967 The @option{auto} option handles interrupts during stepping in a way that they
8968 get served but don't disturb the program flow. The step command first allows
8969 pending interrupt handlers to execute, then disables interrupts and steps over
8970 the next instruction where the core was halted. After the step interrupts
8971 are enabled again. If the interrupt handlers don't complete within 500ms,
8972 the step command leaves with the core running.
8974 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
8975 option. If no breakpoint is available at the time of the step, then the step
8976 is taken with interrupts enabled, i.e. the same way the @option{off} option
8979 Default is @option{auto}.
8982 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
8983 @cindex vector_catch
8984 Vector Catch hardware provides dedicated breakpoints
8985 for certain hardware events.
8987 Parameters request interception of
8988 @option{all} of these hardware event vectors,
8989 @option{none} of them,
8990 or one or more of the following:
8991 @option{hard_err} for a HardFault exception;
8992 @option{mm_err} for a MemManage exception;
8993 @option{bus_err} for a BusFault exception;
8996 @option{chk_err}, or
8997 @option{nocp_err} for various UsageFault exceptions; or
8999 If NVIC setup code does not enable them,
9000 MemManage, BusFault, and UsageFault exceptions
9001 are mapped to HardFault.
9002 UsageFault checks for
9003 divide-by-zero and unaligned access
9004 must also be explicitly enabled.
9006 This finishes by listing the current vector catch configuration.
9009 @deffn Command {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
9010 Control reset handling if hardware srst is not fitted
9011 @xref{reset_config,,reset_config}.
9014 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
9015 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
9018 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
9019 This however has the disadvantage of only resetting the core, all peripherals
9020 are unaffected. A solution would be to use a @code{reset-init} event handler
9021 to manually reset the peripherals.
9022 @xref{targetevents,,Target Events}.
9024 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
9028 @subsection ARMv8-A specific commands
9032 @deffn Command {aarch64 cache_info}
9033 Display information about target caches
9036 @deffn Command {aarch64 dbginit}
9037 This command enables debugging by clearing the OS Lock and sticky power-down and reset
9038 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
9039 target code relies on. In a configuration file, the command would typically be called from a
9040 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
9041 However, normally it is not necessary to use the command at all.
9044 @deffn Command {aarch64 smp_on|smp_off}
9045 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
9046 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
9047 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
9048 group. With SMP handling disabled, all targets need to be treated individually.
9051 @deffn Command {aarch64 maskisr} [@option{on}|@option{off}]
9052 Selects whether interrupts will be processed when single stepping. The default configuration is
9056 @section EnSilica eSi-RISC Architecture
9058 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
9059 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
9061 @subsection eSi-RISC Configuration
9063 @deffn Command {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
9064 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
9065 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
9068 @deffn Command {esirisc hwdc} (@option{all}|@option{none}|mask ...)
9069 Configure hardware debug control. The HWDC register controls which exceptions return
9070 control back to the debugger. Possible masks are @option{all}, @option{none},
9071 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
9072 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
9075 @subsection eSi-RISC Operation
9077 @deffn Command {esirisc flush_caches}
9078 Flush instruction and data caches. This command requires that the target is halted
9079 when the command is issued and configured with an instruction or data cache.
9082 @subsection eSi-Trace Configuration
9084 eSi-RISC targets may be configured with support for instruction tracing. Trace
9085 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
9086 is typically employed to move trace data off-device using a high-speed
9087 peripheral (eg. SPI). Collected trace data is encoded in one of three different
9088 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
9089 fifo} must be issued along with @command{esirisc trace format} before trace data
9092 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
9093 needed, collected trace data can be dumped to a file and processed by external
9097 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
9098 for this issue is to configure DMA to copy trace data to an in-memory buffer,
9099 which can then be passed to the @command{esirisc trace analyze} and
9100 @command{esirisc trace dump} commands.
9102 It is possible to corrupt trace data when using a FIFO if the peripheral
9103 responsible for draining data from the FIFO is not fast enough. This can be
9104 managed by enabling flow control, however this can impact timing-sensitive
9105 software operation on the CPU.
9108 @deffn Command {esirisc trace buffer} address size [@option{wrap}]
9109 Configure trace buffer using the provided address and size. If the @option{wrap}
9110 option is specified, trace collection will continue once the end of the buffer
9111 is reached. By default, wrap is disabled.
9114 @deffn Command {esirisc trace fifo} address
9115 Configure trace FIFO using the provided address.
9118 @deffn Command {esirisc trace flow_control} (@option{enable}|@option{disable})
9119 Enable or disable stalling the CPU to collect trace data. By default, flow
9120 control is disabled.
9123 @deffn Command {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
9124 Configure trace format and number of PC bits to be captured. @option{pc_bits}
9125 must be within 1 and 31 as the LSB is not collected. If external tooling is used
9126 to analyze collected trace data, these values must match.
9128 Supported trace formats:
9130 @item @option{full} capture full trace data, allowing execution history and
9131 timing to be determined.
9132 @item @option{branch} capture taken branch instructions and branch target
9134 @item @option{icache} capture instruction cache misses.
9138 @deffn Command {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
9139 Configure trigger start condition using the provided start data and mask. A
9140 brief description of each condition is provided below; for more detail on how
9141 these values are used, see the eSi-RISC Architecture Manual.
9143 Supported conditions:
9145 @item @option{none} manual tracing (see @command{esirisc trace start}).
9146 @item @option{pc} start tracing if the PC matches start data and mask.
9147 @item @option{load} start tracing if the effective address of a load
9148 instruction matches start data and mask.
9149 @item @option{store} start tracing if the effective address of a store
9150 instruction matches start data and mask.
9151 @item @option{exception} start tracing if the EID of an exception matches start
9153 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
9154 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
9155 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
9156 @item @option{high} start tracing when an external signal is a logical high.
9157 @item @option{low} start tracing when an external signal is a logical low.
9161 @deffn Command {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
9162 Configure trigger stop condition using the provided stop data and mask. A brief
9163 description of each condition is provided below; for more detail on how these
9164 values are used, see the eSi-RISC Architecture Manual.
9166 Supported conditions:
9168 @item @option{none} manual tracing (see @command{esirisc trace stop}).
9169 @item @option{pc} stop tracing if the PC matches stop data and mask.
9170 @item @option{load} stop tracing if the effective address of a load
9171 instruction matches stop data and mask.
9172 @item @option{store} stop tracing if the effective address of a store
9173 instruction matches stop data and mask.
9174 @item @option{exception} stop tracing if the EID of an exception matches stop
9176 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
9177 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
9178 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
9182 @deffn Command {esirisc trace trigger delay} (@option{trigger}) [cycles]
9183 Configure trigger start/stop delay in clock cycles.
9187 @item @option{none} no delay to start or stop collection.
9188 @item @option{start} delay @option{cycles} after trigger to start collection.
9189 @item @option{stop} delay @option{cycles} after trigger to stop collection.
9190 @item @option{both} delay @option{cycles} after both triggers to start or stop
9195 @subsection eSi-Trace Operation
9197 @deffn Command {esirisc trace init}
9198 Initialize trace collection. This command must be called any time the
9199 configuration changes. If an trace buffer has been configured, the contents will
9200 be overwritten when trace collection starts.
9203 @deffn Command {esirisc trace info}
9204 Display trace configuration.
9207 @deffn Command {esirisc trace status}
9208 Display trace collection status.
9211 @deffn Command {esirisc trace start}
9212 Start manual trace collection.
9215 @deffn Command {esirisc trace stop}
9216 Stop manual trace collection.
9219 @deffn Command {esirisc trace analyze} [address size]
9220 Analyze collected trace data. This command may only be used if a trace buffer
9221 has been configured. If a trace FIFO has been configured, trace data must be
9222 copied to an in-memory buffer identified by the @option{address} and
9223 @option{size} options using DMA.
9226 @deffn Command {esirisc trace dump} [address size] @file{filename}
9227 Dump collected trace data to file. This command may only be used if a trace
9228 buffer has been configured. If a trace FIFO has been configured, trace data must
9229 be copied to an in-memory buffer identified by the @option{address} and
9230 @option{size} options using DMA.
9233 @section Intel Architecture
9235 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
9236 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
9237 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
9238 software debug and the CLTAP is used for SoC level operations.
9239 Useful docs are here: https://communities.intel.com/community/makers/documentation
9241 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
9242 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
9243 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
9246 @subsection x86 32-bit specific commands
9247 The three main address spaces for x86 are memory, I/O and configuration space.
9248 These commands allow a user to read and write to the 64Kbyte I/O address space.
9250 @deffn Command {x86_32 idw} address
9251 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
9254 @deffn Command {x86_32 idh} address
9255 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
9258 @deffn Command {x86_32 idb} address
9259 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
9262 @deffn Command {x86_32 iww} address
9263 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
9266 @deffn Command {x86_32 iwh} address
9267 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
9270 @deffn Command {x86_32 iwb} address
9271 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
9274 @section OpenRISC Architecture
9276 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
9277 configured with any of the TAP / Debug Unit available.
9279 @subsection TAP and Debug Unit selection commands
9280 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
9281 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
9283 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
9284 Select between the Advanced Debug Interface and the classic one.
9286 An option can be passed as a second argument to the debug unit.
9288 When using the Advanced Debug Interface, option = 1 means the RTL core is
9289 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
9290 between bytes while doing read or write bursts.
9293 @subsection Registers commands
9294 @deffn Command {addreg} [name] [address] [feature] [reg_group]
9295 Add a new register in the cpu register list. This register will be
9296 included in the generated target descriptor file.
9298 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
9300 @strong{[reg_group]} can be anything. The default register list defines "system",
9301 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
9306 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
9311 @deffn Command {readgroup} (@option{group})
9312 Display all registers in @emph{group}.
9314 @emph{group} can be "system",
9315 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
9316 "timer" or any new group created with addreg command.
9319 @section RISC-V Architecture
9321 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
9322 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
9323 harts. (It's possible to increase this limit to 1024 by changing
9324 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
9325 Debug Specification, but there is also support for legacy targets that
9326 implement version 0.11.
9328 @subsection RISC-V Terminology
9330 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
9331 another hart, or may be a separate core. RISC-V treats those the same, and
9332 OpenOCD exposes each hart as a separate core.
9334 @subsection RISC-V Debug Configuration Commands
9336 @deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]...
9337 Configure a list of inclusive ranges for CSRs to expose in addition to the
9338 standard ones. This must be executed before `init`.
9340 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
9341 and then only if the corresponding extension appears to be implemented. This
9342 command can be used if OpenOCD gets this wrong, or a target implements custom
9346 @deffn Command {riscv set_command_timeout_sec} [seconds]
9347 Set the wall-clock timeout (in seconds) for individual commands. The default
9348 should work fine for all but the slowest targets (eg. simulators).
9351 @deffn Command {riscv set_reset_timeout_sec} [seconds]
9352 Set the maximum time to wait for a hart to come out of reset after reset is
9356 @deffn Command {riscv set_scratch_ram} none|[address]
9357 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
9358 This is used to access 64-bit floating point registers on 32-bit targets.
9361 @deffn Command {riscv set_prefer_sba} on|off
9362 When on, prefer to use System Bus Access to access memory. When off, prefer to
9363 use the Program Buffer to access memory.
9366 @subsection RISC-V Authentication Commands
9368 The following commands can be used to authenticate to a RISC-V system. Eg. a
9369 trivial challenge-response protocol could be implemented as follows in a
9370 configuration file, immediately following @command{init}:
9372 set challenge [ocd_riscv authdata_read]
9373 riscv authdata_write [expr $challenge + 1]
9376 @deffn Command {riscv authdata_read}
9377 Return the 32-bit value read from authdata. Note that to get read value back in
9378 a TCL script, it needs to be invoked as @command{ocd_riscv authdata_read}.
9381 @deffn Command {riscv authdata_write} value
9382 Write the 32-bit value to authdata.
9385 @subsection RISC-V DMI Commands
9387 The following commands allow direct access to the Debug Module Interface, which
9388 can be used to interact with custom debug features.
9390 @deffn Command {riscv dmi_read}
9391 Perform a 32-bit DMI read at address, returning the value. Note that to get
9392 read value back in a TCL script, it needs to be invoked as @command{ocd_riscv
9396 @deffn Command {riscv dmi_write} address value
9397 Perform a 32-bit DMI write of value at address.
9400 @anchor{softwaredebugmessagesandtracing}
9401 @section Software Debug Messages and Tracing
9402 @cindex Linux-ARM DCC support
9406 OpenOCD can process certain requests from target software, when
9407 the target uses appropriate libraries.
9408 The most powerful mechanism is semihosting, but there is also
9409 a lighter weight mechanism using only the DCC channel.
9411 Currently @command{target_request debugmsgs}
9412 is supported only for @option{arm7_9} and @option{cortex_m} cores.
9413 These messages are received as part of target polling, so
9414 you need to have @command{poll on} active to receive them.
9415 They are intrusive in that they will affect program execution
9416 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
9418 See @file{libdcc} in the contrib dir for more details.
9419 In addition to sending strings, characters, and
9420 arrays of various size integers from the target,
9421 @file{libdcc} also exports a software trace point mechanism.
9422 The target being debugged may
9423 issue trace messages which include a 24-bit @dfn{trace point} number.
9424 Trace point support includes two distinct mechanisms,
9425 each supported by a command:
9428 @item @emph{History} ... A circular buffer of trace points
9429 can be set up, and then displayed at any time.
9430 This tracks where code has been, which can be invaluable in
9431 finding out how some fault was triggered.
9433 The buffer may overflow, since it collects records continuously.
9434 It may be useful to use some of the 24 bits to represent a
9435 particular event, and other bits to hold data.
9437 @item @emph{Counting} ... An array of counters can be set up,
9438 and then displayed at any time.
9439 This can help establish code coverage and identify hot spots.
9441 The array of counters is directly indexed by the trace point
9442 number, so trace points with higher numbers are not counted.
9445 Linux-ARM kernels have a ``Kernel low-level debugging
9446 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
9447 depends on CONFIG_DEBUG_LL) which uses this mechanism to
9448 deliver messages before a serial console can be activated.
9449 This is not the same format used by @file{libdcc}.
9450 Other software, such as the U-Boot boot loader, sometimes
9451 does the same thing.
9453 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
9454 Displays current handling of target DCC message requests.
9455 These messages may be sent to the debugger while the target is running.
9456 The optional @option{enable} and @option{charmsg} parameters
9457 both enable the messages, while @option{disable} disables them.
9459 With @option{charmsg} the DCC words each contain one character,
9460 as used by Linux with CONFIG_DEBUG_ICEDCC;
9461 otherwise the libdcc format is used.
9464 @deffn Command {trace history} [@option{clear}|count]
9465 With no parameter, displays all the trace points that have triggered
9466 in the order they triggered.
9467 With the parameter @option{clear}, erases all current trace history records.
9468 With a @var{count} parameter, allocates space for that many
9472 @deffn Command {trace point} [@option{clear}|identifier]
9473 With no parameter, displays all trace point identifiers and how many times
9474 they have been triggered.
9475 With the parameter @option{clear}, erases all current trace point counters.
9476 With a numeric @var{identifier} parameter, creates a new a trace point counter
9477 and associates it with that identifier.
9479 @emph{Important:} The identifier and the trace point number
9480 are not related except by this command.
9481 These trace point numbers always start at zero (from server startup,
9482 or after @command{trace point clear}) and count up from there.
9487 @chapter JTAG Commands
9488 @cindex JTAG Commands
9489 Most general purpose JTAG commands have been presented earlier.
9490 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
9491 Lower level JTAG commands, as presented here,
9492 may be needed to work with targets which require special
9493 attention during operations such as reset or initialization.
9495 To use these commands you will need to understand some
9496 of the basics of JTAG, including:
9499 @item A JTAG scan chain consists of a sequence of individual TAP
9500 devices such as a CPUs.
9501 @item Control operations involve moving each TAP through the same
9502 standard state machine (in parallel)
9503 using their shared TMS and clock signals.
9504 @item Data transfer involves shifting data through the chain of
9505 instruction or data registers of each TAP, writing new register values
9506 while the reading previous ones.
9507 @item Data register sizes are a function of the instruction active in
9508 a given TAP, while instruction register sizes are fixed for each TAP.
9509 All TAPs support a BYPASS instruction with a single bit data register.
9510 @item The way OpenOCD differentiates between TAP devices is by
9511 shifting different instructions into (and out of) their instruction
9515 @section Low Level JTAG Commands
9517 These commands are used by developers who need to access
9518 JTAG instruction or data registers, possibly controlling
9519 the order of TAP state transitions.
9520 If you're not debugging OpenOCD internals, or bringing up a
9521 new JTAG adapter or a new type of TAP device (like a CPU or
9522 JTAG router), you probably won't need to use these commands.
9523 In a debug session that doesn't use JTAG for its transport protocol,
9524 these commands are not available.
9526 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
9527 Loads the data register of @var{tap} with a series of bit fields
9528 that specify the entire register.
9529 Each field is @var{numbits} bits long with
9530 a numeric @var{value} (hexadecimal encouraged).
9531 The return value holds the original value of each
9534 For example, a 38 bit number might be specified as one
9535 field of 32 bits then one of 6 bits.
9536 @emph{For portability, never pass fields which are more
9537 than 32 bits long. Many OpenOCD implementations do not
9538 support 64-bit (or larger) integer values.}
9540 All TAPs other than @var{tap} must be in BYPASS mode.
9541 The single bit in their data registers does not matter.
9543 When @var{tap_state} is specified, the JTAG state machine is left
9545 For example @sc{drpause} might be specified, so that more
9546 instructions can be issued before re-entering the @sc{run/idle} state.
9547 If the end state is not specified, the @sc{run/idle} state is entered.
9550 OpenOCD does not record information about data register lengths,
9551 so @emph{it is important that you get the bit field lengths right}.
9552 Remember that different JTAG instructions refer to different
9553 data registers, which may have different lengths.
9554 Moreover, those lengths may not be fixed;
9555 the SCAN_N instruction can change the length of
9556 the register accessed by the INTEST instruction
9557 (by connecting a different scan chain).
9561 @deffn Command {flush_count}
9562 Returns the number of times the JTAG queue has been flushed.
9563 This may be used for performance tuning.
9565 For example, flushing a queue over USB involves a
9566 minimum latency, often several milliseconds, which does
9567 not change with the amount of data which is written.
9568 You may be able to identify performance problems by finding
9569 tasks which waste bandwidth by flushing small transfers too often,
9570 instead of batching them into larger operations.
9573 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
9574 For each @var{tap} listed, loads the instruction register
9575 with its associated numeric @var{instruction}.
9576 (The number of bits in that instruction may be displayed
9577 using the @command{scan_chain} command.)
9578 For other TAPs, a BYPASS instruction is loaded.
9580 When @var{tap_state} is specified, the JTAG state machine is left
9582 For example @sc{irpause} might be specified, so the data register
9583 can be loaded before re-entering the @sc{run/idle} state.
9584 If the end state is not specified, the @sc{run/idle} state is entered.
9587 OpenOCD currently supports only a single field for instruction
9588 register values, unlike data register values.
9589 For TAPs where the instruction register length is more than 32 bits,
9590 portable scripts currently must issue only BYPASS instructions.
9594 @deffn Command {jtag_reset} trst srst
9595 Set values of reset signals.
9596 The @var{trst} and @var{srst} parameter values may be
9597 @option{0}, indicating that reset is inactive (pulled or driven high),
9598 or @option{1}, indicating it is active (pulled or driven low).
9599 The @command{reset_config} command should already have been used
9600 to configure how the board and JTAG adapter treat these two
9601 signals, and to say if either signal is even present.
9602 @xref{Reset Configuration}.
9604 Note that TRST is specially handled.
9605 It actually signifies JTAG's @sc{reset} state.
9606 So if the board doesn't support the optional TRST signal,
9607 or it doesn't support it along with the specified SRST value,
9608 JTAG reset is triggered with TMS and TCK signals
9609 instead of the TRST signal.
9610 And no matter how that JTAG reset is triggered, once
9611 the scan chain enters @sc{reset} with TRST inactive,
9612 TAP @code{post-reset} events are delivered to all TAPs
9613 with handlers for that event.
9616 @deffn Command {pathmove} start_state [next_state ...]
9617 Start by moving to @var{start_state}, which
9618 must be one of the @emph{stable} states.
9619 Unless it is the only state given, this will often be the
9620 current state, so that no TCK transitions are needed.
9621 Then, in a series of single state transitions
9622 (conforming to the JTAG state machine) shift to
9623 each @var{next_state} in sequence, one per TCK cycle.
9624 The final state must also be stable.
9627 @deffn Command {runtest} @var{num_cycles}
9628 Move to the @sc{run/idle} state, and execute at least
9629 @var{num_cycles} of the JTAG clock (TCK).
9630 Instructions often need some time
9631 to execute before they take effect.
9634 @c tms_sequence (short|long)
9635 @c ... temporary, debug-only, other than USBprog bug workaround...
9637 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
9638 Verify values captured during @sc{ircapture} and returned
9639 during IR scans. Default is enabled, but this can be
9640 overridden by @command{verify_jtag}.
9641 This flag is ignored when validating JTAG chain configuration.
9644 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
9645 Enables verification of DR and IR scans, to help detect
9646 programming errors. For IR scans, @command{verify_ircapture}
9647 must also be enabled.
9651 @section TAP state names
9652 @cindex TAP state names
9654 The @var{tap_state} names used by OpenOCD in the @command{drscan},
9655 @command{irscan}, and @command{pathmove} commands are the same
9656 as those used in SVF boundary scan documents, except that
9657 SVF uses @sc{idle} instead of @sc{run/idle}.
9660 @item @b{RESET} ... @emph{stable} (with TMS high);
9661 acts as if TRST were pulsed
9662 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
9665 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
9666 through the data register
9668 @item @b{DRPAUSE} ... @emph{stable}; data register ready
9669 for update or more shifting
9674 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
9675 through the instruction register
9677 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
9678 for update or more shifting
9683 Note that only six of those states are fully ``stable'' in the
9684 face of TMS fixed (low except for @sc{reset})
9685 and a free-running JTAG clock. For all the
9686 others, the next TCK transition changes to a new state.
9689 @item From @sc{drshift} and @sc{irshift}, clock transitions will
9690 produce side effects by changing register contents. The values
9691 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
9692 may not be as expected.
9693 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
9694 choices after @command{drscan} or @command{irscan} commands,
9695 since they are free of JTAG side effects.
9696 @item @sc{run/idle} may have side effects that appear at non-JTAG
9697 levels, such as advancing the ARM9E-S instruction pipeline.
9698 Consult the documentation for the TAP(s) you are working with.
9701 @node Boundary Scan Commands
9702 @chapter Boundary Scan Commands
9704 One of the original purposes of JTAG was to support
9705 boundary scan based hardware testing.
9706 Although its primary focus is to support On-Chip Debugging,
9707 OpenOCD also includes some boundary scan commands.
9709 @section SVF: Serial Vector Format
9710 @cindex Serial Vector Format
9713 The Serial Vector Format, better known as @dfn{SVF}, is a
9714 way to represent JTAG test patterns in text files.
9715 In a debug session using JTAG for its transport protocol,
9716 OpenOCD supports running such test files.
9718 @deffn Command {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
9719 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
9720 This issues a JTAG reset (Test-Logic-Reset) and then
9721 runs the SVF script from @file{filename}.
9723 Arguments can be specified in any order; the optional dash doesn't
9724 affect their semantics.
9728 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
9729 specified by the SVF file with HIR, TIR, HDR and TDR commands;
9730 instead, calculate them automatically according to the current JTAG
9731 chain configuration, targeting @var{tapname};
9732 @item @option{[-]quiet} do not log every command before execution;
9733 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
9734 on the real interface;
9735 @item @option{[-]progress} enable progress indication;
9736 @item @option{[-]ignore_error} continue execution despite TDO check
9741 @section XSVF: Xilinx Serial Vector Format
9742 @cindex Xilinx Serial Vector Format
9745 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
9746 binary representation of SVF which is optimized for use with
9748 In a debug session using JTAG for its transport protocol,
9749 OpenOCD supports running such test files.
9751 @quotation Important
9752 Not all XSVF commands are supported.
9755 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
9756 This issues a JTAG reset (Test-Logic-Reset) and then
9757 runs the XSVF script from @file{filename}.
9758 When a @var{tapname} is specified, the commands are directed at
9760 When @option{virt2} is specified, the @sc{xruntest} command counts
9761 are interpreted as TCK cycles instead of microseconds.
9762 Unless the @option{quiet} option is specified,
9763 messages are logged for comments and some retries.
9766 The OpenOCD sources also include two utility scripts
9767 for working with XSVF; they are not currently installed
9768 after building the software.
9769 You may find them useful:
9772 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
9773 syntax understood by the @command{xsvf} command; see notes below.
9774 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
9775 understands the OpenOCD extensions.
9778 The input format accepts a handful of non-standard extensions.
9779 These include three opcodes corresponding to SVF extensions
9780 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
9781 two opcodes supporting a more accurate translation of SVF
9782 (XTRST, XWAITSTATE).
9783 If @emph{xsvfdump} shows a file is using those opcodes, it
9784 probably will not be usable with other XSVF tools.
9787 @node Utility Commands
9788 @chapter Utility Commands
9789 @cindex Utility Commands
9791 @section RAM testing
9794 There is often a need to stress-test random access memory (RAM) for
9795 errors. OpenOCD comes with a Tcl implementation of well-known memory
9796 testing procedures allowing the detection of all sorts of issues with
9797 electrical wiring, defective chips, PCB layout and other common
9800 To use them, you usually need to initialise your RAM controller first;
9801 consult your SoC's documentation to get the recommended list of
9802 register operations and translate them to the corresponding
9803 @command{mww}/@command{mwb} commands.
9805 Load the memory testing functions with
9808 source [find tools/memtest.tcl]
9811 to get access to the following facilities:
9813 @deffn Command {memTestDataBus} address
9814 Test the data bus wiring in a memory region by performing a walking
9815 1's test at a fixed address within that region.
9818 @deffn Command {memTestAddressBus} baseaddress size
9819 Perform a walking 1's test on the relevant bits of the address and
9820 check for aliasing. This test will find single-bit address failures
9821 such as stuck-high, stuck-low, and shorted pins.
9824 @deffn Command {memTestDevice} baseaddress size
9825 Test the integrity of a physical memory device by performing an
9826 increment/decrement test over the entire region. In the process every
9827 storage bit in the device is tested as zero and as one.
9830 @deffn Command {runAllMemTests} baseaddress size
9831 Run all of the above tests over a specified memory region.
9834 @section Firmware recovery helpers
9835 @cindex Firmware recovery
9837 OpenOCD includes an easy-to-use script to facilitate mass-market
9838 devices recovery with JTAG.
9840 For quickstart instructions run:
9842 openocd -f tools/firmware-recovery.tcl -c firmware_help
9848 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
9849 be used to access files on PCs (either the developer's PC or some other PC).
9851 The way this works on the ZY1000 is to prefix a filename by
9852 "/tftp/ip/" and append the TFTP path on the TFTP
9853 server (tftpd). For example,
9856 load_image /tftp/10.0.0.96/c:\temp\abc.elf
9859 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
9860 if the file was hosted on the embedded host.
9862 In order to achieve decent performance, you must choose a TFTP server
9863 that supports a packet size bigger than the default packet size (512 bytes). There
9864 are numerous TFTP servers out there (free and commercial) and you will have to do
9865 a bit of googling to find something that fits your requirements.
9867 @node GDB and OpenOCD
9868 @chapter GDB and OpenOCD
9870 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
9871 to debug remote targets.
9872 Setting up GDB to work with OpenOCD can involve several components:
9875 @item The OpenOCD server support for GDB may need to be configured.
9876 @xref{gdbconfiguration,,GDB Configuration}.
9877 @item GDB's support for OpenOCD may need configuration,
9878 as shown in this chapter.
9879 @item If you have a GUI environment like Eclipse,
9880 that also will probably need to be configured.
9883 Of course, the version of GDB you use will need to be one which has
9884 been built to know about the target CPU you're using. It's probably
9885 part of the tool chain you're using. For example, if you are doing
9886 cross-development for ARM on an x86 PC, instead of using the native
9887 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
9888 if that's the tool chain used to compile your code.
9890 @section Connecting to GDB
9891 @cindex Connecting to GDB
9892 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
9893 instance GDB 6.3 has a known bug that produces bogus memory access
9894 errors, which has since been fixed; see
9895 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
9897 OpenOCD can communicate with GDB in two ways:
9901 A socket (TCP/IP) connection is typically started as follows:
9903 target remote localhost:3333
9905 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
9907 It is also possible to use the GDB extended remote protocol as follows:
9909 target extended-remote localhost:3333
9912 A pipe connection is typically started as follows:
9914 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
9916 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
9917 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
9918 session. log_output sends the log output to a file to ensure that the pipe is
9919 not saturated when using higher debug level outputs.
9922 To list the available OpenOCD commands type @command{monitor help} on the
9925 @section Sample GDB session startup
9927 With the remote protocol, GDB sessions start a little differently
9928 than they do when you're debugging locally.
9929 Here's an example showing how to start a debug session with a
9931 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
9932 Most programs would be written into flash (address 0) and run from there.
9935 $ arm-none-eabi-gdb example.elf
9936 (gdb) target remote localhost:3333
9937 Remote debugging using localhost:3333
9939 (gdb) monitor reset halt
9942 Loading section .vectors, size 0x100 lma 0x20000000
9943 Loading section .text, size 0x5a0 lma 0x20000100
9944 Loading section .data, size 0x18 lma 0x200006a0
9945 Start address 0x2000061c, load size 1720
9946 Transfer rate: 22 KB/sec, 573 bytes/write.
9952 You could then interrupt the GDB session to make the program break,
9953 type @command{where} to show the stack, @command{list} to show the
9954 code around the program counter, @command{step} through code,
9955 set breakpoints or watchpoints, and so on.
9957 @section Configuring GDB for OpenOCD
9959 OpenOCD supports the gdb @option{qSupported} packet, this enables information
9960 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
9961 packet size and the device's memory map.
9962 You do not need to configure the packet size by hand,
9963 and the relevant parts of the memory map should be automatically
9964 set up when you declare (NOR) flash banks.
9966 However, there are other things which GDB can't currently query.
9967 You may need to set those up by hand.
9968 As OpenOCD starts up, you will often see a line reporting
9972 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
9975 You can pass that information to GDB with these commands:
9978 set remote hardware-breakpoint-limit 6
9979 set remote hardware-watchpoint-limit 4
9982 With that particular hardware (Cortex-M3) the hardware breakpoints
9983 only work for code running from flash memory. Most other ARM systems
9984 do not have such restrictions.
9986 Rather than typing such commands interactively, you may prefer to
9987 save them in a file and have GDB execute them as it starts, perhaps
9988 using a @file{.gdbinit} in your project directory or starting GDB
9989 using @command{gdb -x filename}.
9991 @section Programming using GDB
9992 @cindex Programming using GDB
9993 @anchor{programmingusinggdb}
9995 By default the target memory map is sent to GDB. This can be disabled by
9996 the following OpenOCD configuration option:
9998 gdb_memory_map disable
10000 For this to function correctly a valid flash configuration must also be set
10001 in OpenOCD. For faster performance you should also configure a valid
10004 Informing GDB of the memory map of the target will enable GDB to protect any
10005 flash areas of the target and use hardware breakpoints by default. This means
10006 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
10007 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
10009 To view the configured memory map in GDB, use the GDB command @option{info mem}.
10010 All other unassigned addresses within GDB are treated as RAM.
10012 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
10013 This can be changed to the old behaviour by using the following GDB command
10015 set mem inaccessible-by-default off
10018 If @command{gdb_flash_program enable} is also used, GDB will be able to
10019 program any flash memory using the vFlash interface.
10021 GDB will look at the target memory map when a load command is given, if any
10022 areas to be programmed lie within the target flash area the vFlash packets
10025 If the target needs configuring before GDB programming, set target
10026 event gdb-flash-erase-start:
10028 $_TARGETNAME configure -event gdb-flash-erase-start BODY
10030 @xref{targetevents,,Target Events}, for other GDB programming related events.
10032 To verify any flash programming the GDB command @option{compare-sections}
10035 @section Using GDB as a non-intrusive memory inspector
10036 @cindex Using GDB as a non-intrusive memory inspector
10037 @anchor{gdbmeminspect}
10039 If your project controls more than a blinking LED, let's say a heavy industrial
10040 robot or an experimental nuclear reactor, stopping the controlling process
10041 just because you want to attach GDB is not a good option.
10043 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
10044 Though there is a possible setup where the target does not get stopped
10045 and GDB treats it as it were running.
10046 If the target supports background access to memory while it is running,
10047 you can use GDB in this mode to inspect memory (mainly global variables)
10048 without any intrusion of the target process.
10050 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
10051 Place following command after target configuration:
10053 $_TARGETNAME configure -event gdb-attach @{@}
10056 If any of installed flash banks does not support probe on running target,
10057 switch off gdb_memory_map:
10059 gdb_memory_map disable
10062 Ensure GDB is configured without interrupt-on-connect.
10063 Some GDB versions set it by default, some does not.
10065 set remote interrupt-on-connect off
10068 If you switched gdb_memory_map off, you may want to setup GDB memory map
10069 manually or issue @command{set mem inaccessible-by-default off}
10071 Now you can issue GDB command @command{target remote ...} and inspect memory
10072 of a running target. Do not use GDB commands @command{continue},
10073 @command{step} or @command{next} as they synchronize GDB with your target
10074 and GDB would require stopping the target to get the prompt back.
10076 Do not use this mode under an IDE like Eclipse as it caches values of
10077 previously shown varibles.
10079 @anchor{usingopenocdsmpwithgdb}
10080 @section Using OpenOCD SMP with GDB
10082 For SMP support following GDB serial protocol packet have been defined :
10084 @item j - smp status request
10085 @item J - smp set request
10088 OpenOCD implements :
10090 @item @option{jc} packet for reading core id displayed by
10091 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
10092 @option{E01} for target not smp.
10093 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
10094 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
10095 for target not smp or @option{OK} on success.
10098 Handling of this packet within GDB can be done :
10100 @item by the creation of an internal variable (i.e @option{_core}) by mean
10101 of function allocate_computed_value allowing following GDB command.
10104 #Jc01 packet is sent
10106 #jc packet is sent and result is affected in $
10109 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
10110 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
10113 # toggle0 : force display of coreid 0
10119 # toggle1 : force display of coreid 1
10128 @section RTOS Support
10129 @cindex RTOS Support
10130 @anchor{gdbrtossupport}
10132 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
10133 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
10135 @xref{Threads, Debugging Programs with Multiple Threads,
10136 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
10139 @* An example setup is below:
10142 $_TARGETNAME configure -rtos auto
10145 This will attempt to auto detect the RTOS within your application.
10147 Currently supported rtos's include:
10149 @item @option{eCos}
10150 @item @option{ThreadX}
10151 @item @option{FreeRTOS}
10152 @item @option{linux}
10153 @item @option{ChibiOS}
10154 @item @option{embKernel}
10156 @item @option{uCOS-III}
10157 @item @option{nuttx}
10161 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
10162 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
10167 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
10168 @item ThreadX symbols
10169 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
10170 @item FreeRTOS symbols
10171 @c The following is taken from recent texinfo to provide compatibility
10172 @c with ancient versions that do not support @raggedright
10175 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
10176 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
10177 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
10178 uxCurrentNumberOfTasks, uxTopUsedPriority.
10182 @item linux symbols
10184 @item ChibiOS symbols
10185 rlist, ch_debug, chSysInit.
10186 @item embKernel symbols
10187 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
10188 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
10190 _mqx_kernel_data, MQX_init_struct.
10191 @item uC/OS-III symbols
10192 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
10193 @item nuttx symbols
10194 g_readytorun, g_tasklisttable
10197 For most RTOS supported the above symbols will be exported by default. However for
10198 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
10200 These RTOSes may require additional OpenOCD-specific file to be linked
10201 along with the project:
10205 contrib/rtos-helpers/FreeRTOS-openocd.c
10207 contrib/rtos-helpers/uCOS-III-openocd.c
10210 @node Tcl Scripting API
10211 @chapter Tcl Scripting API
10212 @cindex Tcl Scripting API
10213 @cindex Tcl scripts
10216 Tcl commands are stateless; e.g. the @command{telnet} command has
10217 a concept of currently active target, the Tcl API proc's take this sort
10218 of state information as an argument to each proc.
10220 There are three main types of return values: single value, name value
10221 pair list and lists.
10223 Name value pair. The proc 'foo' below returns a name/value pair
10227 > set foo(me) Duane
10228 > set foo(you) Oyvind
10229 > set foo(mouse) Micky
10230 > set foo(duck) Donald
10242 me Duane you Oyvind mouse Micky duck Donald
10245 Thus, to get the names of the associative array is easy:
10248 foreach { name value } [set foo] {
10249 puts "Name: $name, Value: $value"
10253 Lists returned should be relatively small. Otherwise, a range
10254 should be passed in to the proc in question.
10256 @section Internal low-level Commands
10258 By "low-level," we mean commands that a human would typically not
10261 Some low-level commands need to be prefixed with "ocd_"; e.g.
10262 @command{ocd_flash_banks}
10263 is the low-level API upon which @command{flash banks} is implemented.
10266 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10268 Read memory and return as a Tcl array for script processing
10269 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
10271 Convert a Tcl array to memory locations and write the values
10272 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
10274 Return information about the flash banks
10276 @item @b{capture} <@var{command}>
10278 Run <@var{command}> and return full log output that was produced during
10279 its execution. Example:
10282 > capture "reset init"
10287 OpenOCD commands can consist of two words, e.g. "flash banks". The
10288 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
10289 called "flash_banks".
10291 @section OpenOCD specific Global Variables
10293 Real Tcl has ::tcl_platform(), and platform::identify, and many other
10294 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
10295 holds one of the following values:
10298 @item @b{cygwin} Running under Cygwin
10299 @item @b{darwin} Darwin (Mac-OS) is the underlying operating system.
10300 @item @b{freebsd} Running under FreeBSD
10301 @item @b{openbsd} Running under OpenBSD
10302 @item @b{netbsd} Running under NetBSD
10303 @item @b{linux} Linux is the underlying operating system
10304 @item @b{mingw32} Running under MingW32
10305 @item @b{winxx} Built using Microsoft Visual Studio
10306 @item @b{ecos} Running under eCos
10307 @item @b{other} Unknown, none of the above.
10310 Note: 'winxx' was chosen because today (March-2009) no distinction is made between Win32 and Win64.
10313 We should add support for a variable like Tcl variable
10314 @code{tcl_platform(platform)}, it should be called
10315 @code{jim_platform} (because it
10316 is jim, not real tcl).
10319 @section Tcl RPC server
10322 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
10323 commands and receive the results.
10325 To access it, your application needs to connect to a configured TCP port
10326 (see @command{tcl_port}). Then it can pass any string to the
10327 interpreter terminating it with @code{0x1a} and wait for the return
10328 value (it will be terminated with @code{0x1a} as well). This can be
10329 repeated as many times as desired without reopening the connection.
10331 Remember that most of the OpenOCD commands need to be prefixed with
10332 @code{ocd_} to get the results back. Sometimes you might also need the
10333 @command{capture} command.
10335 See @file{contrib/rpc_examples/} for specific client implementations.
10337 @section Tcl RPC server notifications
10338 @cindex RPC Notifications
10340 Notifications are sent asynchronously to other commands being executed over
10341 the RPC server, so the port must be polled continuously.
10343 Target event, state and reset notifications are emitted as Tcl associative arrays
10344 in the following format.
10347 type target_event event [event-name]
10348 type target_state state [state-name]
10349 type target_reset mode [reset-mode]
10352 @deffn {Command} tcl_notifications [on/off]
10353 Toggle output of target notifications to the current Tcl RPC server.
10354 Only available from the Tcl RPC server.
10359 @section Tcl RPC server trace output
10360 @cindex RPC trace output
10362 Trace data is sent asynchronously to other commands being executed over
10363 the RPC server, so the port must be polled continuously.
10365 Target trace data is emitted as a Tcl associative array in the following format.
10368 type target_trace data [trace-data-hex-encoded]
10371 @deffn {Command} tcl_trace [on/off]
10372 Toggle output of target trace data to the current Tcl RPC server.
10373 Only available from the Tcl RPC server.
10376 See an example application here:
10377 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
10386 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
10388 @cindex adaptive clocking
10391 In digital circuit design it is often referred to as ``clock
10392 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
10393 operating at some speed, your CPU target is operating at another.
10394 The two clocks are not synchronised, they are ``asynchronous''
10396 In order for the two to work together they must be synchronised
10397 well enough to work; JTAG can't go ten times faster than the CPU,
10398 for example. There are 2 basic options:
10401 Use a special "adaptive clocking" circuit to change the JTAG
10402 clock rate to match what the CPU currently supports.
10404 The JTAG clock must be fixed at some speed that's enough slower than
10405 the CPU clock that all TMS and TDI transitions can be detected.
10408 @b{Does this really matter?} For some chips and some situations, this
10409 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
10410 the CPU has no difficulty keeping up with JTAG.
10411 Startup sequences are often problematic though, as are other
10412 situations where the CPU clock rate changes (perhaps to save
10415 For example, Atmel AT91SAM chips start operation from reset with
10416 a 32kHz system clock. Boot firmware may activate the main oscillator
10417 and PLL before switching to a faster clock (perhaps that 500 MHz
10419 If you're using JTAG to debug that startup sequence, you must slow
10420 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
10421 JTAG can use a faster clock.
10423 Consider also debugging a 500MHz ARM926 hand held battery powered
10424 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
10425 clock, between keystrokes unless it has work to do. When would
10426 that 5 MHz JTAG clock be usable?
10428 @b{Solution #1 - A special circuit}
10430 In order to make use of this,
10431 your CPU, board, and JTAG adapter must all support the RTCK
10432 feature. Not all of them support this; keep reading!
10434 The RTCK ("Return TCK") signal in some ARM chips is used to help with
10435 this problem. ARM has a good description of the problem described at
10436 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
10437 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
10438 work? / how does adaptive clocking work?''.
10440 The nice thing about adaptive clocking is that ``battery powered hand
10441 held device example'' - the adaptiveness works perfectly all the
10442 time. One can set a break point or halt the system in the deep power
10443 down code, slow step out until the system speeds up.
10445 Note that adaptive clocking may also need to work at the board level,
10446 when a board-level scan chain has multiple chips.
10447 Parallel clock voting schemes are good way to implement this,
10448 both within and between chips, and can easily be implemented
10450 It's not difficult to have logic fan a module's input TCK signal out
10451 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
10452 back with the right polarity before changing the output RTCK signal.
10453 Texas Instruments makes some clock voting logic available
10454 for free (with no support) in VHDL form; see
10455 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
10457 @b{Solution #2 - Always works - but may be slower}
10459 Often this is a perfectly acceptable solution.
10461 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
10462 the target clock speed. But what that ``magic division'' is varies
10463 depending on the chips on your board.
10464 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
10465 ARM11 cores use an 8:1 division.
10466 @b{Xilinx rule of thumb} is 1/12 the clock speed.
10468 Note: most full speed FT2232 based JTAG adapters are limited to a
10469 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
10470 often support faster clock rates (and adaptive clocking).
10472 You can still debug the 'low power' situations - you just need to
10473 either use a fixed and very slow JTAG clock rate ... or else
10474 manually adjust the clock speed at every step. (Adjusting is painful
10475 and tedious, and is not always practical.)
10477 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
10478 have a special debug mode in your application that does a ``high power
10479 sleep''. If you are careful - 98% of your problems can be debugged
10482 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
10483 operation in your idle loops even if you don't otherwise change the CPU
10485 That operation gates the CPU clock, and thus the JTAG clock; which
10486 prevents JTAG access. One consequence is not being able to @command{halt}
10487 cores which are executing that @emph{wait for interrupt} operation.
10489 To set the JTAG frequency use the command:
10492 # Example: 1.234MHz
10497 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
10499 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
10500 around Windows filenames.
10513 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
10515 Make sure you have Cygwin installed, or at least a version of OpenOCD that
10516 claims to come with all the necessary DLLs. When using Cygwin, try launching
10517 OpenOCD from the Cygwin shell.
10519 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
10520 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
10521 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
10523 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
10524 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
10525 software breakpoints consume one of the two available hardware breakpoints.
10527 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
10529 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
10530 clock at the time you're programming the flash. If you've specified the crystal's
10531 frequency, make sure the PLL is disabled. If you've specified the full core speed
10532 (e.g. 60MHz), make sure the PLL is enabled.
10534 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
10535 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
10536 out while waiting for end of scan, rtck was disabled".
10538 Make sure your PC's parallel port operates in EPP mode. You might have to try several
10539 settings in your PC BIOS (ECP, EPP, and different versions of those).
10541 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
10542 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
10543 memory read caused data abort".
10545 The errors are non-fatal, and are the result of GDB trying to trace stack frames
10546 beyond the last valid frame. It might be possible to prevent this by setting up
10547 a proper "initial" stack frame, if you happen to know what exactly has to
10548 be done, feel free to add this here.
10550 @b{Simple:} In your startup code - push 8 registers of zeros onto the
10551 stack before calling main(). What GDB is doing is ``climbing'' the run
10552 time stack by reading various values on the stack using the standard
10553 call frame for the target. GDB keeps going - until one of 2 things
10554 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
10555 stackframes have been processed. By pushing zeros on the stack, GDB
10558 @b{Debugging Interrupt Service Routines} - In your ISR before you call
10559 your C code, do the same - artificially push some zeros onto the stack,
10560 remember to pop them off when the ISR is done.
10562 @b{Also note:} If you have a multi-threaded operating system, they
10563 often do not @b{in the intrest of saving memory} waste these few
10567 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
10568 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
10570 This warning doesn't indicate any serious problem, as long as you don't want to
10571 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
10572 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
10573 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
10574 independently. With this setup, it's not possible to halt the core right out of
10575 reset, everything else should work fine.
10577 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
10578 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
10579 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
10580 quit with an error message. Is there a stability issue with OpenOCD?
10582 No, this is not a stability issue concerning OpenOCD. Most users have solved
10583 this issue by simply using a self-powered USB hub, which they connect their
10584 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
10585 supply stable enough for the Amontec JTAGkey to be operated.
10587 @b{Laptops running on battery have this problem too...}
10589 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
10590 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
10591 What does that mean and what might be the reason for this?
10593 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
10594 has closed the connection to OpenOCD. This might be a GDB issue.
10596 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
10597 are described, there is a parameter for specifying the clock frequency
10598 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
10599 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
10600 specified in kilohertz. However, I do have a quartz crystal of a
10601 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
10602 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
10605 No. The clock frequency specified here must be given as an integral number.
10606 However, this clock frequency is used by the In-Application-Programming (IAP)
10607 routines of the LPC2000 family only, which seems to be very tolerant concerning
10608 the given clock frequency, so a slight difference between the specified clock
10609 frequency and the actual clock frequency will not cause any trouble.
10611 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
10613 Well, yes and no. Commands can be given in arbitrary order, yet the
10614 devices listed for the JTAG scan chain must be given in the right
10615 order (jtag newdevice), with the device closest to the TDO-Pin being
10616 listed first. In general, whenever objects of the same type exist
10617 which require an index number, then these objects must be given in the
10618 right order (jtag newtap, targets and flash banks - a target
10619 references a jtag newtap and a flash bank references a target).
10621 You can use the ``scan_chain'' command to verify and display the tap order.
10623 Also, some commands can't execute until after @command{init} has been
10624 processed. Such commands include @command{nand probe} and everything
10625 else that needs to write to controller registers, perhaps for setting
10626 up DRAM and loading it with code.
10628 @anchor{faqtaporder}
10629 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
10632 Yes; whenever you have more than one, you must declare them in
10633 the same order used by the hardware.
10635 Many newer devices have multiple JTAG TAPs. For example:
10636 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
10637 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
10638 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
10639 connected to the boundary scan TAP, which then connects to the
10640 Cortex-M3 TAP, which then connects to the TDO pin.
10642 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
10643 (2) The boundary scan TAP. If your board includes an additional JTAG
10644 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
10645 place it before or after the STM32 chip in the chain. For example:
10648 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
10649 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
10650 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
10651 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
10652 @item Xilinx TDO Pin -> OpenOCD TDO (input)
10655 The ``jtag device'' commands would thus be in the order shown below. Note:
10658 @item jtag newtap Xilinx tap -irlen ...
10659 @item jtag newtap stm32 cpu -irlen ...
10660 @item jtag newtap stm32 bs -irlen ...
10661 @item # Create the debug target and say where it is
10662 @item target create stm32.cpu -chain-position stm32.cpu ...
10666 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
10667 log file, I can see these error messages: Error: arm7_9_common.c:561
10668 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
10674 @node Tcl Crash Course
10675 @chapter Tcl Crash Course
10678 Not everyone knows Tcl - this is not intended to be a replacement for
10679 learning Tcl, the intent of this chapter is to give you some idea of
10680 how the Tcl scripts work.
10682 This chapter is written with two audiences in mind. (1) OpenOCD users
10683 who need to understand a bit more of how Jim-Tcl works so they can do
10684 something useful, and (2) those that want to add a new command to
10687 @section Tcl Rule #1
10688 There is a famous joke, it goes like this:
10690 @item Rule #1: The wife is always correct
10691 @item Rule #2: If you think otherwise, See Rule #1
10694 The Tcl equal is this:
10697 @item Rule #1: Everything is a string
10698 @item Rule #2: If you think otherwise, See Rule #1
10701 As in the famous joke, the consequences of Rule #1 are profound. Once
10702 you understand Rule #1, you will understand Tcl.
10704 @section Tcl Rule #1b
10705 There is a second pair of rules.
10707 @item Rule #1: Control flow does not exist. Only commands
10708 @* For example: the classic FOR loop or IF statement is not a control
10709 flow item, they are commands, there is no such thing as control flow
10711 @item Rule #2: If you think otherwise, See Rule #1
10712 @* Actually what happens is this: There are commands that by
10713 convention, act like control flow key words in other languages. One of
10714 those commands is the word ``for'', another command is ``if''.
10717 @section Per Rule #1 - All Results are strings
10718 Every Tcl command results in a string. The word ``result'' is used
10719 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
10720 Everything is a string}
10722 @section Tcl Quoting Operators
10723 In life of a Tcl script, there are two important periods of time, the
10724 difference is subtle.
10727 @item Evaluation Time
10730 The two key items here are how ``quoted things'' work in Tcl. Tcl has
10731 three primary quoting constructs, the [square-brackets] the
10732 @{curly-braces@} and ``double-quotes''
10734 By now you should know $VARIABLES always start with a $DOLLAR
10735 sign. BTW: To set a variable, you actually use the command ``set'', as
10736 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
10737 = 1'' statement, but without the equal sign.
10740 @item @b{[square-brackets]}
10741 @* @b{[square-brackets]} are command substitutions. It operates much
10742 like Unix Shell `back-ticks`. The result of a [square-bracket]
10743 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
10744 string}. These two statements are roughly identical:
10748 echo "The Date is: $X"
10751 puts "The Date is: $X"
10753 @item @b{``double-quoted-things''}
10754 @* @b{``double-quoted-things''} are just simply quoted
10755 text. $VARIABLES and [square-brackets] are expanded in place - the
10756 result however is exactly 1 string. @i{Remember Rule #1 - Everything
10760 puts "It is now \"[date]\", $x is in 1 hour"
10762 @item @b{@{Curly-Braces@}}
10763 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
10764 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
10765 'single-quote' operators in BASH shell scripts, with the added
10766 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
10767 nested 3 times@}@}@} NOTE: [date] is a bad example;
10768 at this writing, Jim/OpenOCD does not have a date command.
10771 @section Consequences of Rule 1/2/3/4
10773 The consequences of Rule 1 are profound.
10775 @subsection Tokenisation & Execution.
10777 Of course, whitespace, blank lines and #comment lines are handled in
10780 As a script is parsed, each (multi) line in the script file is
10781 tokenised and according to the quoting rules. After tokenisation, that
10782 line is immediately executed.
10784 Multi line statements end with one or more ``still-open''
10785 @{curly-braces@} which - eventually - closes a few lines later.
10787 @subsection Command Execution
10789 Remember earlier: There are no ``control flow''
10790 statements in Tcl. Instead there are COMMANDS that simply act like
10791 control flow operators.
10793 Commands are executed like this:
10796 @item Parse the next line into (argc) and (argv[]).
10797 @item Look up (argv[0]) in a table and call its function.
10798 @item Repeat until End Of File.
10801 It sort of works like this:
10804 ReadAndParse( &argc, &argv );
10806 cmdPtr = LookupCommand( argv[0] );
10808 (*cmdPtr->Execute)( argc, argv );
10812 When the command ``proc'' is parsed (which creates a procedure
10813 function) it gets 3 parameters on the command line. @b{1} the name of
10814 the proc (function), @b{2} the list of parameters, and @b{3} the body
10815 of the function. Not the choice of words: LIST and BODY. The PROC
10816 command stores these items in a table somewhere so it can be found by
10817 ``LookupCommand()''
10819 @subsection The FOR command
10821 The most interesting command to look at is the FOR command. In Tcl,
10822 the FOR command is normally implemented in C. Remember, FOR is a
10823 command just like any other command.
10825 When the ascii text containing the FOR command is parsed, the parser
10826 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
10830 @item The ascii text 'for'
10831 @item The start text
10832 @item The test expression
10833 @item The next text
10834 @item The body text
10837 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
10838 Remember @i{Rule #1 - Everything is a string.} The key point is this:
10839 Often many of those parameters are in @{curly-braces@} - thus the
10840 variables inside are not expanded or replaced until later.
10842 Remember that every Tcl command looks like the classic ``main( argc,
10843 argv )'' function in C. In JimTCL - they actually look like this:
10847 MyCommand( Jim_Interp *interp,
10849 Jim_Obj * const *argvs );
10852 Real Tcl is nearly identical. Although the newer versions have
10853 introduced a byte-code parser and interpreter, but at the core, it
10854 still operates in the same basic way.
10856 @subsection FOR command implementation
10858 To understand Tcl it is perhaps most helpful to see the FOR
10859 command. Remember, it is a COMMAND not a control flow structure.
10861 In Tcl there are two underlying C helper functions.
10863 Remember Rule #1 - You are a string.
10865 The @b{first} helper parses and executes commands found in an ascii
10866 string. Commands can be separated by semicolons, or newlines. While
10867 parsing, variables are expanded via the quoting rules.
10869 The @b{second} helper evaluates an ascii string as a numerical
10870 expression and returns a value.
10872 Here is an example of how the @b{FOR} command could be
10873 implemented. The pseudo code below does not show error handling.
10875 void Execute_AsciiString( void *interp, const char *string );
10877 int Evaluate_AsciiExpression( void *interp, const char *string );
10880 MyForCommand( void *interp,
10885 SetResult( interp, "WRONG number of parameters");
10889 // argv[0] = the ascii string just like C
10891 // Execute the start statement.
10892 Execute_AsciiString( interp, argv[1] );
10894 // Top of loop test
10896 i = Evaluate_AsciiExpression(interp, argv[2]);
10900 // Execute the body
10901 Execute_AsciiString( interp, argv[3] );
10903 // Execute the LOOP part
10904 Execute_AsciiString( interp, argv[4] );
10908 SetResult( interp, "" );
10913 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
10914 in the same basic way.
10916 @section OpenOCD Tcl Usage
10918 @subsection source and find commands
10919 @b{Where:} In many configuration files
10920 @* Example: @b{ source [find FILENAME] }
10921 @*Remember the parsing rules
10923 @item The @command{find} command is in square brackets,
10924 and is executed with the parameter FILENAME. It should find and return
10925 the full path to a file with that name; it uses an internal search path.
10926 The RESULT is a string, which is substituted into the command line in
10927 place of the bracketed @command{find} command.
10928 (Don't try to use a FILENAME which includes the "#" character.
10929 That character begins Tcl comments.)
10930 @item The @command{source} command is executed with the resulting filename;
10931 it reads a file and executes as a script.
10933 @subsection format command
10934 @b{Where:} Generally occurs in numerous places.
10935 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
10941 puts [format "The answer: %d" [expr $x * $y]]
10944 @item The SET command creates 2 variables, X and Y.
10945 @item The double [nested] EXPR command performs math
10946 @* The EXPR command produces numerical result as a string.
10947 @* Refer to Rule #1
10948 @item The format command is executed, producing a single string
10949 @* Refer to Rule #1.
10950 @item The PUTS command outputs the text.
10952 @subsection Body or Inlined Text
10953 @b{Where:} Various TARGET scripts.
10956 proc someproc @{@} @{
10957 ... multiple lines of stuff ...
10959 $_TARGETNAME configure -event FOO someproc
10960 #2 Good - no variables
10961 $_TARGETNAME configure -event foo "this ; that;"
10962 #3 Good Curly Braces
10963 $_TARGETNAME configure -event FOO @{
10964 puts "Time: [date]"
10966 #4 DANGER DANGER DANGER
10967 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
10970 @item The $_TARGETNAME is an OpenOCD variable convention.
10971 @*@b{$_TARGETNAME} represents the last target created, the value changes
10972 each time a new target is created. Remember the parsing rules. When
10973 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
10974 the name of the target which happens to be a TARGET (object)
10976 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
10977 @*There are 4 examples:
10979 @item The TCLBODY is a simple string that happens to be a proc name
10980 @item The TCLBODY is several simple commands separated by semicolons
10981 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
10982 @item The TCLBODY is a string with variables that get expanded.
10985 In the end, when the target event FOO occurs the TCLBODY is
10986 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
10987 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
10989 Remember the parsing rules. In case #3, @{curly-braces@} mean the
10990 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
10991 and the text is evaluated. In case #4, they are replaced before the
10992 ``Target Object Command'' is executed. This occurs at the same time
10993 $_TARGETNAME is replaced. In case #4 the date will never
10994 change. @{BTW: [date] is a bad example; at this writing,
10995 Jim/OpenOCD does not have a date command@}
10997 @subsection Global Variables
10998 @b{Where:} You might discover this when writing your own procs @* In
10999 simple terms: Inside a PROC, if you need to access a global variable
11000 you must say so. See also ``upvar''. Example:
11002 proc myproc @{ @} @{
11003 set y 0 #Local variable Y
11004 global x #Global variable X
11005 puts [format "X=%d, Y=%d" $x $y]
11008 @section Other Tcl Hacks
11009 @b{Dynamic variable creation}
11011 # Dynamically create a bunch of variables.
11012 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
11014 set vn [format "BIT%d" $x]
11018 set $vn [expr (1 << $x)]
11021 @b{Dynamic proc/command creation}
11023 # One "X" function - 5 uart functions.
11024 foreach who @{A B C D E@}
11025 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
11031 @node OpenOCD Concept Index
11032 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
11033 @comment case issue with ``Index.html'' and ``index.html''
11034 @comment Occurs when creating ``--html --no-split'' output
11035 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
11036 @unnumbered OpenOCD Concept Index
11040 @node Command and Driver Index
11041 @unnumbered Command and Driver Index