1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (OpenOCD)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}@*
15 Copyright @copyright{} 2008 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
17 Permission is granted to copy, distribute and/or modify this document
18 under the terms of the GNU Free Documentation License, Version 1.2 or
19 any later version published by the Free Software Foundation; with no
20 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
21 Texts. A copy of the license is included in the section entitled ``GNU
22 Free Documentation License''.
27 @title Open On-Chip Debugger (OpenOCD)
28 @subtitle Edition @value{EDITION} for OpenOCD version @value{VERSION}
29 @subtitle @value{UPDATED}
31 @vskip 0pt plus 1filll
37 @node Top, About, , (dir)
40 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
41 (OpenOCD) version @value{VERSION}, @value{UPDATED}.
46 * About:: About OpenOCD.
47 * Developers:: OpenOCD developers
48 * Building:: Building OpenOCD
49 * Running:: Running OpenOCD
50 * Configuration:: OpenOCD Configuration.
51 * Target library:: Target library
52 * Commands:: OpenOCD Commands
53 * Sample Scripts:: Sample Target Scripts
55 * GDB and OpenOCD:: Using GDB and OpenOCD
56 * TCL and OpenOCD:: Using TCL and OpenOCD
57 * TCL scripting API:: Tcl scripting API
58 * Upgrading:: Deprecated/Removed Commands
59 * FAQ:: Frequently Asked Questions
60 * License:: GNU Free Documentation License
68 The Open On-Chip Debugger (OpenOCD) aims to provide debugging, in-system programming
69 and boundary-scan testing for embedded target devices. The targets are interfaced
70 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
71 connection types in the future.
73 OpenOCD currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
74 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
75 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
76 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
78 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
79 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
80 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
86 OpenOCD was created by Dominic Rath as part of a diploma thesis written at the
87 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
88 Others interested in improving the state of free and open debug and testing technology
89 are welcome to participate.
91 Other developers have contributed support for additional targets and flashes as well
92 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
94 The main OpenOCD web site is available at @uref{http://openocd.berlios.de/web/}
98 @cindex building OpenOCD
100 If you are interested in getting actual work done rather than building
101 OpenOCD, then check if your interface supplier provides binaries for
102 you. Chances are that that binary is from some SVN version that is more
103 stable than SVN trunk where bleeding edge development takes place.
106 You can download the current SVN version with SVN client of your choice from the
107 following repositories:
109 (@uref{svn://svn.berlios.de/openocd/trunk})
113 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
115 Using the SVN command line client, you can use the following command to fetch the
116 latest version (make sure there is no (non-svn) directory called "openocd" in the
120 svn checkout svn://svn.berlios.de/openocd/trunk openocd
123 Building OpenOCD requires a recent version of the GNU autotools.
124 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
125 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
126 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
127 paths, resulting in obscure dependency errors (This is an observation I've gathered
128 from the logs of one user - correct me if I'm wrong).
130 You further need the appropriate driver files, if you want to build support for
131 a FTDI FT2232 based interface:
133 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
134 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
135 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
136 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
139 libftdi is supported under windows. Versions earlier than 0.13 will require patching.
140 see contrib/libftdi for more details.
142 In general, the D2XX driver provides superior performance (several times as fast),
143 but has the draw-back of being binary-only - though that isn't that bad, as it isn't
144 a kernel module, only a user space library.
146 To build OpenOCD (on both Linux and Cygwin), use the following commands:
150 Bootstrap generates the configure script, and prepares building on your system.
154 Configure generates the Makefiles used to build OpenOCD.
158 Make builds OpenOCD, and places the final executable in ./src/.
160 The configure script takes several options, specifying which JTAG interfaces
165 @option{--enable-parport}
167 @option{--enable-parport_ppdev}
169 @option{--enable-parport_giveio}
171 @option{--enable-amtjtagaccel}
173 @option{--enable-ft2232_ftd2xx}
174 @footnote{Using the latest D2XX drivers from FTDI and following their installation
175 instructions, I had to use @option{--enable-ft2232_libftd2xx} for OpenOCD to
178 @option{--enable-ft2232_libftdi}
180 @option{--with-ftd2xx=/path/to/d2xx/}
182 @option{--enable-gw16012}
184 @option{--enable-usbprog}
186 @option{--enable-presto_libftdi}
188 @option{--enable-presto_ftd2xx}
190 @option{--enable-jlink}
193 If you want to access the parallel port using the PPDEV interface you have to specify
194 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
195 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
196 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
198 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
199 absolute path containing no spaces.
201 Linux users should copy the various parts of the D2XX package to the appropriate
202 locations, i.e. /usr/include, /usr/lib.
204 Miscellaneous configure options
208 @option{--enable-gccwarnings} - enable extra gcc warnings during build
213 @cindex running OpenOCD
215 @cindex --debug_level
218 OpenOCD runs as a daemon, waiting for connections from clients (Telnet, GDB, Other).
219 Run with @option{--help} or @option{-h} to view the available command line switches.
221 It reads its configuration by default from the file openocd.cfg located in the current
222 working directory. This may be overwritten with the @option{-f <configfile>} command line
223 switch. The @option{-f} command line switch can be specified multiple times, in which case the config files
224 are executed in order.
226 Also it is possible to interleave commands w/config scripts using the @option{-c} command line switch.
228 To enable debug output (when reporting problems or working on OpenOCD itself), use
229 the @option{-d} command line switch. This sets the @option{debug_level} to "3", outputting
230 the most information, including debug messages. The default setting is "2", outputting
231 only informational messages, warnings and errors. You can also change this setting
232 from within a telnet or gdb session using @option{debug_level <n>} @xref{debug_level}.
234 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
236 Search paths for config/script files can be added to OpenOCD by using
237 the @option{-s <search>} switch. The current directory and the OpenOCD target library
238 is in the search path by default.
240 Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection
241 with the target. In general, it is possible for the JTAG controller to be unresponsive until
242 the target is set up correctly via e.g. GDB monitor commands in a GDB init script.
245 @chapter Configuration
246 @cindex configuration
247 OpenOCD runs as a daemon, and reads it current configuration
248 by default from the file openocd.cfg in the current directory. A different configuration
249 file can be specified with the @option{-f <conf.file>} command line switch specified when starting OpenOCD.
251 The configuration file is used to specify on which ports the daemon listens for new
252 connections, the JTAG interface used to connect to the target, the layout of the JTAG
253 chain, the targets that should be debugged, and connected flashes.
255 @section Daemon configuration
259 @*This command terminates the configuration stage and enters the normal
260 command mode. This can be useful to add commands to the startup scripts and commands
261 such as resetting the target, programming flash, etc. To reset the CPU upon startup,
262 add "init" and "reset" at the end of the config script or at the end of the
263 OpenOCD command line using the @option{-c} command line switch.
265 @item @b{telnet_port} <@var{number}>
267 @*Port on which to listen for incoming telnet connections
268 @item @b{tcl_port} <@var{number}>
270 @*Port on which to listen for incoming TCL syntax. This port is intended as
271 a simplified RPC connection that can be used by clients to issue commands
272 and get the output from the TCL engine.
273 @item @b{gdb_port} <@var{number}>
275 @*First port on which to listen for incoming GDB connections. The GDB port for the
276 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
277 @item @b{gdb_breakpoint_override} <@var{hard|soft|disabled}>
278 @cindex gdb_breakpoint_override
279 @anchor{gdb_breakpoint_override}
280 @*Force breakpoint type for gdb 'break' commands.
281 The raison d'etre for this option is to support GDB GUI's without
282 a hard/soft breakpoint concept where the default OpenOCD and
283 GDB behaviour is not sufficient. Note that GDB will use hardware
284 breakpoints if the memory map has been set up for flash regions.
286 This option replaces older arm7_9 target commands that addressed
288 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
290 @*Configures what OpenOCD will do when gdb detaches from the daeman.
291 Default behaviour is <@var{resume}>
292 @item @b{gdb_memory_map} <@var{enable|disable}>
293 @cindex gdb_memory_map
294 @*Set to <@var{enable}> to cause OpenOCD to send the memory configuration to gdb when
295 requested. gdb will then know when to set hardware breakpoints, and program flash
296 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
297 for flash programming to work.
298 Default behaviour is <@var{enable}>
299 @xref{gdb_flash_program}.
300 @item @b{gdb_flash_program} <@var{enable|disable}>
301 @cindex gdb_flash_program
302 @anchor{gdb_flash_program}
303 @*Set to <@var{enable}> to cause OpenOCD to program the flash memory when a
304 vFlash packet is received.
305 Default behaviour is <@var{enable}>
308 @section JTAG interface configuration
311 @item @b{interface} <@var{name}>
313 @*Use the interface driver <@var{name}> to connect to the target. Currently supported
317 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
320 @item @b{amt_jtagaccel}
321 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
326 FTDI FT2232 based devices using either the open-source libftdi or the binary only
327 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
328 platform. The libftdi uses libusb, and should be portable to all systems that provide
333 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
337 ASIX PRESTO USB JTAG programmer.
341 usbprog is a freely programmable USB adapter.
345 Gateworks GW16012 JTAG programmer.
349 Segger jlink usb adapter
354 @item @b{jtag_speed} <@var{reset speed}>
356 @*Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
357 speed. The actual effect of this option depends on the JTAG interface used.
359 The speed used during reset can be adjusted using setting jtag_speed during
360 pre_reset and post_reset events.
363 @item wiggler: maximum speed / @var{number}
364 @item ft2232: 6MHz / (@var{number}+1)
365 @item amt jtagaccel: 8 / 2**@var{number}
366 @item jlink: maximum speed in kHz (0-12000), 0 will use RTCK
369 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
370 especially true for synthesized cores (-S).
372 @item @b{jtag_khz} <@var{reset speed kHz}>
374 @*Same as jtag_speed, except that the speed is specified in maximum kHz. If
375 the device can not support the rate asked for, or can not translate from
376 kHz to jtag_speed, then an error is returned. 0 means RTCK. If RTCK
377 is not supported, then an error is reported.
379 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
381 @*The configuration of the reset signals available on the JTAG interface AND the target.
382 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
383 then OpenOCD can't use it. <@var{signals}> can be @option{none}, @option{trst_only},
384 @option{srst_only} or @option{trst_and_srst}.
386 [@var{combination}] is an optional value specifying broken reset signal implementations.
387 @option{srst_pulls_trst} states that the testlogic is reset together with the reset of
388 the system (e.g. Philips LPC2000, "broken" board layout), @option{trst_pulls_srst} says
389 that the system is reset together with the test logic (only hypothetical, I haven't
390 seen hardware with such a bug, and can be worked around).
391 @option{combined} imples both @option{srst_pulls_trst} and @option{trst_pulls_srst}.
392 The default behaviour if no option given is @option{separate}.
394 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
395 reset lines to be specified. Possible values are @option{trst_push_pull} (default)
396 and @option{trst_open_drain} for the test reset signal, and @option{srst_open_drain}
397 (default) and @option{srst_push_pull} for the system reset. These values only affect
398 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
400 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
402 @*Describes the devices that form the JTAG daisy chain, with the first device being
403 the one closest to TDO. The parameters are the length of the instruction register
404 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
405 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
406 The IDCODE instruction will in future be used to query devices for their JTAG
407 identification code. This line is the same for all ARM7 and ARM9 devices.
408 Other devices, like CPLDs, require different parameters. An example configuration
409 line for a Xilinx XC9500 CPLD would look like this:
411 jtag_device 8 0x01 0x0e3 0xfe
413 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
414 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
415 The IDCODE instruction is 0xfe.
417 @item @b{jtag_nsrst_delay} <@var{ms}>
418 @cindex jtag_nsrst_delay
419 @*How long (in milliseconds) OpenOCD should wait after deasserting nSRST before
420 starting new JTAG operations.
421 @item @b{jtag_ntrst_delay} <@var{ms}>
422 @cindex jtag_ntrst_delay
423 @*Same @b{jtag_nsrst_delay}, but for nTRST
425 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
426 or on-chip features) keep a reset line asserted for some time after the external reset
430 @section parport options
433 @item @b{parport_port} <@var{number}>
435 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of
436 the @file{/dev/parport} device
438 When using PPDEV to access the parallel port, use the number of the parallel port:
439 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
440 you may encounter a problem.
441 @item @b{parport_cable} <@var{name}>
442 @cindex parport_cable
443 @*The layout of the parallel port cable used to connect to the target.
444 Currently supported cables are
448 The original Wiggler layout, also supported by several clones, such
449 as the Olimex ARM-JTAG
452 Same as original wiggler except an led is fitted on D5.
453 @item @b{wiggler_ntrst_inverted}
454 @cindex wiggler_ntrst_inverted
455 Same as original wiggler except TRST is inverted.
456 @item @b{old_amt_wiggler}
457 @cindex old_amt_wiggler
458 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
459 version available from the website uses the original Wiggler layout ('@var{wiggler}')
462 The Amontec Chameleon's CPLD when operated in configuration mode. This is only used to
463 program the Chameleon itself, not a connected target.
466 The Xilinx Parallel cable III.
469 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
470 This is also the layout used by the HollyGates design
471 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
474 The ST Parallel cable.
477 Same as original wiggler except SRST and TRST connections reversed and
478 TRST is also inverted.
481 Altium Universal JTAG cable.
483 @item @b{parport_write_on_exit} <@var{on}|@var{off}>
484 @cindex parport_write_on_exit
485 @*This will configure the parallel driver to write a known value to the parallel
486 interface on exiting OpenOCD
489 @section amt_jtagaccel options
491 @item @b{parport_port} <@var{number}>
493 @*Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
494 @file{/dev/parport} device
496 @section ft2232 options
499 @item @b{ft2232_device_desc} <@var{description}>
500 @cindex ft2232_device_desc
501 @*The USB device description of the FTDI FT2232 device. If not specified, the FTDI
502 default value is used. This setting is only valid if compiled with FTD2XX support.
503 @item @b{ft2232_serial} <@var{serial-number}>
504 @cindex ft2232_serial
505 @*The serial number of the FTDI FT2232 device. If not specified, the FTDI default
507 @item @b{ft2232_layout} <@var{name}>
508 @cindex ft2232_layout
509 @*The layout of the FT2232 GPIO signals used to control output-enables and reset
510 signals. Valid layouts are
513 "USBJTAG-1" layout described in the original OpenOCD diploma thesis
515 Amontec JTAGkey and JTAGkey-tiny
518 @item @b{olimex-jtag}
521 American Microsystems M5960
522 @item @b{evb_lm3s811}
523 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
524 SRST signals on external connector
528 Hitex STM32 Performance Stick
530 Tin Can Tools Flyswatter
531 @item @b{turtelizer2}
532 egnite Software turtelizer2
537 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
538 @*The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
539 default values are used. Multiple <@var{vid}>, <@var{pid}> pairs may be given, eg.
541 ft2232_vid_pid 0x0403 0xcff8 0x15ba 0x0003
543 @item @b{ft2232_latency} <@var{ms}>
544 @*On some systems using ft2232 based JTAG interfaces the FT_Read function call in
545 ft2232_read() fails to return the expected number of bytes. This can be caused by
546 USB communication delays and has proved hard to reproduce and debug. Setting the
547 FT2232 latency timer to a larger value increases delays for short USB packages but it
548 also reduces the risk of timeouts before receiving the expected number of bytes.
549 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
552 @section ep93xx options
553 @cindex ep93xx options
554 Currently, there are no options available for the ep93xx interface.
557 @section Target configuration
560 @item @b{target} <@var{type}> <@var{endianess}> <@var{JTAG pos}>
563 @*Defines a target that should be debugged. Currently supported types are:
579 If you want to use a target board that is not on this list, see Adding a new
581 The @option{target types} command can be used to get the list of targets supported from within openocd.
583 Endianess may be @option{little} or @option{big}.
585 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
586 @cindex target_script
587 @*Event is one of the following:
588 @option{pre_reset}, @option{reset}, @option{post_reset}, @option{post_halt},
589 @option{pre_resume} or @option{gdb_program_config}.
590 @option{post_reset} and @option{reset} will produce the same results.
592 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}> <@var{backup}|@var{nobackup}> [@option{virtual address}]
594 @*Specifies a working area for the debugger to use. This may be used to speed-up
595 downloads to target memory and flash operations, or to perform otherwise unavailable
596 operations (some coprocessor operations on ARM7/9 systems, for example). The last
597 parameter decides whether the memory should be preserved (<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If possible, use
598 a working_area that doesn't need to be backed up, as performing a backup slows down operation.
601 @subsection arm7tdmi options
602 @cindex arm7tdmi options
603 target arm7tdmi <@var{endianess}> <@var{jtag#}>
604 @*The arm7tdmi target definition requires at least one additional argument, specifying
605 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
606 The optional [@var{variant}] parameter has been removed in recent versions.
607 The correct feature set is determined at runtime.
609 @subsection arm720t options
610 @cindex arm720t options
611 ARM720t options are similar to ARM7TDMI options.
613 @subsection arm9tdmi options
614 @cindex arm9tdmi options
615 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
616 @option{arm920t}, @option{arm922t} and @option{arm940t}.
617 This enables the hardware single-stepping support found on these cores.
619 @subsection arm920t options
620 @cindex arm920t options
621 ARM920t options are similar to ARM9TDMI options.
623 @subsection arm966e options
624 @cindex arm966e options
625 ARM966e options are similar to ARM9TDMI options.
627 @subsection cortex_m3 options
628 @cindex cortex_m3 options
629 use variant <@var{variant}> @option{lm3s} when debugging luminary lm3s targets. This will cause
630 openocd to use a software reset rather than asserting SRST to avoid a issue with clearing
631 the debug registers. This is fixed in Fury Rev B, DustDevil Rev B, Tempest, these revisions will
632 be detected and the normal reset behaviour used.
634 @subsection xscale options
635 @cindex xscale options
636 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
637 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
639 @subsection arm11 options
640 @cindex arm11 options
642 @subsection mips_m4k options
643 @cindex mips_m4k options
644 Use variant @option{ejtag_srst} when debugging targets that
645 do not provide a functional SRST line on the EJTAG connector.
646 This causes openocd to instead use an EJTAG software reset command to reset the processor.
647 You still need to enable @option{srst} on the reset configuration command to enable openocd hardware reset functionality.
649 @section Flash configuration
650 @cindex Flash configuration
653 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
654 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
656 @*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
657 and <@var{bus_width}> bytes using the selected flash <driver>.
660 @subsection lpc2000 options
661 @cindex lpc2000 options
663 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
664 <@var{clock}> [@var{calc_checksum}]
665 @*LPC flashes don't require the chip and bus width to be specified. Additional
666 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
667 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
668 of the target this flash belongs to (first is 0), the frequency at which the core
669 is currently running (in kHz - must be an integral number), and the optional keyword
670 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
673 @subsection cfi options
676 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
677 <@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
678 @*CFI flashes require the number of the target they're connected to as an additional
679 argument. The CFI driver makes use of a working area (specified for the target)
680 to significantly speed up operation.
682 @var{chip_width} and @var{bus_width} are specified in bytes.
684 The @var{jedec_probe} option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
688 @subsection at91sam7 options
689 @cindex at91sam7 options
691 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
692 @*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
693 reading the chip-id and type.
695 @subsection str7 options
698 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
699 @*variant can be either STR71x, STR73x or STR75x.
701 @subsection str9 options
704 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
705 @*The str9 needs the flash controller to be configured prior to Flash programming, eg.
707 str9x flash_config 0 4 2 0 0x80000
709 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
711 @subsection str9 options (str9xpec driver)
713 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
714 @*Before using the flash commands the turbo mode will need enabling using str9xpec
715 @option{enable_turbo} <@var{num>.}
717 Only use this driver for locking/unlocking the device or configuring the option bytes.
718 Use the standard str9 driver for programming.
720 @subsection stellaris (LM3Sxxx) options
721 @cindex stellaris (LM3Sxxx) options
723 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
724 @*stellaris flash plugin only require the @var{target#}.
726 @subsection stm32x options
727 @cindex stm32x options
729 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
730 @*stm32x flash plugin only require the @var{target#}.
732 @subsection aduc702x options
733 @cindex aduc702x options
735 @b{flash bank aduc702x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
736 @*aduc702x flash plugin require the flash @var{base}, @var{size} and @var{target#}.
738 @section mFlash configuration
739 @cindex mFlash configuration
742 @item @b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
743 <@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
745 @*Configures a mflash for <@var{soc}> host bank at <@var{base}>. <@var{chip_width}> and
746 <@var{bus_width}> are bytes order. Pin number format is dependent on host GPIO calling convention.
747 If WP or DPD pin was not used, write -1. Currently, mflash bank support s3c2440 and pxa270.
749 (ex. of s3c2440) mflash <@var{RST pin}> is GPIO B1, <@var{WP pin}> and <@var{DPD pin}> are not used.
751 mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
753 (ex. of pxa270) mflash <@var{RST pin}> is GPIO 43, <@var{DPD pin}> is not used and <@var{DPD pin}> is GPIO 51.
755 mflash bank pxa270 0x08000000 2 2 43 -1 51 0
759 @chapter Target library
760 @cindex Target library
762 OpenOCD comes with a target configuration script library. These scripts can be
763 used as-is or serve as a starting point.
765 The target library is published together with the openocd executable and
766 the path to the target library is in the OpenOCD script search path.
767 Similarly there are example scripts for configuring the JTAG interface.
769 The command line below uses the example parport configuration scripts
770 that ship with OpenOCD, then configures the str710.cfg target and
771 finally issues the init and reset command. The communication speed
772 is set to 10kHz for reset and 8MHz for post reset.
776 openocd -f interface/parport.cfg -f target/str710.cfg -c "init" -c "reset"
780 To list the target scripts available:
783 $ ls /usr/local/lib/openocd/target
785 arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
786 at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
787 at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
788 at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
796 OpenOCD allows user interaction through a GDB server (default: port 3333),
797 a telnet interface (default: port 4444), and a TCL interface (default: port 5555). The command line interpreter
798 is available from both the telnet interface and a GDB session. To issue commands to the
799 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
800 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
803 The TCL interface is used as a simplified RPC mechanism that feeds all the
804 input into the TCL interpreter and returns the output from the evaluation of
810 @item @b{sleep} <@var{msec}>
812 @*Wait for n milliseconds before resuming. Useful in connection with script files
813 (@var{script} command and @var{target_script} configuration).
817 @*Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet, Other).
819 @item @b{debug_level} [@var{n}]
822 @*Display or adjust debug level to n<0-3>
824 @item @b{fast} [@var{enable|disable}]
826 @*Default disabled. Set default behaviour of OpenOCD to be "fast and dangerous". For instance ARM7/9 DCC memory
827 downloads and fast memory access will work if the JTAG interface isn't too fast and
828 the core doesn't run at a too low frequency. Note that this option only changes the default
829 and that the indvidual options, like DCC memory downloads, can be enabled and disabled
832 The target specific "dangerous" optimisation tweaking options may come and go
833 as more robust and user friendly ways are found to ensure maximum throughput
834 and robustness with a minimum of configuration.
836 Typically the "fast enable" is specified first on the command line:
839 openocd -c "fast enable" -c "interface dummy" -f target/str710.cfg
842 @item @b{log_output} <@var{file}>
844 @*Redirect logging to <file> (default: stderr)
846 @item @b{script} <@var{file}>
848 @*Execute commands from <file>
852 @subsection Target state handling
854 @item @b{power} <@var{on}|@var{off}>
856 @*Turn power switch to target on/off.
857 No arguments: print status.
860 @item @b{reg} [@option{#}|@option{name}] [value]
862 @*Access a single register by its number[@option{#}] or by its [@option{name}].
863 No arguments: list all available registers for the current target.
864 Number or name argument: display a register
865 Number or name and value arguments: set register value
867 @item @b{poll} [@option{on}|@option{off}]
869 @*Poll the target for its current state. If the target is in debug mode, architecture
870 specific information about the current state is printed. An optional parameter
871 allows continuous polling to be enabled and disabled.
873 @item @b{halt} [@option{ms}]
875 @*Send a halt request to the target and wait for it to halt for up to [@option{ms}] milliseconds.
876 Default [@option{ms}] is 5 seconds if no arg given.
877 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
878 will stop OpenOCD from waiting.
880 @item @b{wait_halt} [@option{ms}]
882 @*Wait for the target to enter debug mode. Optional [@option{ms}] is
883 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
886 @item @b{resume} [@var{address}]
888 @*Resume the target at its current code position, or at an optional address.
889 OpenOCD will wait 5 seconds for the target to resume.
891 @item @b{step} [@var{address}]
893 @*Single-step the target at its current code position, or at an optional address.
895 @item @b{reset} [@option{run}|@option{halt}|@option{init}]
897 @*Perform a hard-reset. The optional parameter specifies what should happen after the reset.
899 With no arguments a "reset run" is executed
903 @*Let the target run.
906 @*Immediately halt the target (works only with certain configurations).
909 @*Immediately halt the target, and execute the reset script (works only with certain
913 @item @b{soft_reset_halt}
915 @*Requesting target halt and executing a soft reset.
918 @subsection Memory access commands
922 display available ram memory.
924 These commands allow accesses of a specific size to the memory system:
926 @item @b{mdw} <@var{addr}> [@var{count}]
928 @*display memory words
929 @item @b{mdh} <@var{addr}> [@var{count}]
931 @*display memory half-words
932 @item @b{mdb} <@var{addr}> [@var{count}]
934 @*display memory bytes
935 @item @b{mww} <@var{addr}> <@var{value}>
938 @item @b{mwh} <@var{addr}> <@var{value}>
940 @*write memory half-word
941 @item @b{mwb} <@var{addr}> <@var{value}>
945 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
948 @*Load image <@var{file}> to target memory at <@var{address}>
949 @item @b{fast_load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
950 @cindex fast_load_image
951 @anchor{fast_load_image}
952 @*Normally you should be using @b{load_image} or GDB load. However, for
953 testing purposes or when IO overhead is significant(OpenOCD running on embedded
954 host), then storing the image in memory and uploading the image to the target
955 can be a way to upload e.g. multiple debug sessions when the binary does not change.
956 Arguments as @b{load_image}, but image is stored in OpenOCD host
957 memory, i.e. does not affect target. This approach is also useful when profiling
958 target programming performance as IO and target programming can easily be profiled
963 @*Loads image stored in memory by @b{fast_load_image} to current target. Must be preceeded by fast_load_image.
964 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
967 @*Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
968 (binary) <@var{file}>.
969 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
971 @*Verify <@var{file}> against target memory starting at <@var{address}>.
972 This will first attempt comparison using a crc checksum, if this fails it will try a binary compare.
975 @subsection Breakpoint commands
976 @cindex Breakpoint commands
978 @item @b{bp} <@var{addr}> <@var{len}> [@var{hw}]
980 @*set breakpoint <address> <length> [hw]
981 @item @b{rbp} <@var{addr}>
983 @*remove breakpoint <adress>
984 @item @b{wp} <@var{addr}> <@var{len}> <@var{r}|@var{w}|@var{a}> [@var{value}] [@var{mask}]
986 @*set watchpoint <address> <length> <r/w/a> [value] [mask]
987 @item @b{rwp} <@var{addr}>
989 @*remove watchpoint <adress>
992 @subsection Flash commands
993 @cindex Flash commands
995 @item @b{flash banks}
997 @*List configured flash banks
998 @item @b{flash info} <@var{num}>
1000 @*Print info about flash bank <@option{num}>
1001 @item @b{flash probe} <@var{num}>
1003 @*Identify the flash, or validate the parameters of the configured flash. Operation
1004 depends on the flash type.
1005 @item @b{flash erase_check} <@var{num}>
1006 @cindex flash erase_check
1007 @*Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
1008 updates the erase state information displayed by @option{flash info}. That means you have
1009 to issue an @option{erase_check} command after erasing or programming the device to get
1010 updated information.
1011 @item @b{flash protect_check} <@var{num}>
1012 @cindex flash protect_check
1013 @*Check protection state of sectors in flash bank <num>.
1014 @option{flash erase_sector} using the same syntax.
1015 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
1016 @cindex flash erase_sector
1017 @anchor{flash erase_sector}
1018 @*Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
1019 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing may
1020 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
1022 @item @b{flash erase_address} <@var{address}> <@var{length}>
1023 @cindex flash erase_address
1024 @*Erase sectors starting at <@var{address}> for <@var{length}> bytes
1025 @item @b{flash write_bank} <@var{num}> <@var{file}> <@var{offset}>
1026 @cindex flash write_bank
1027 @anchor{flash write_bank}
1028 @*Write the binary <@var{file}> to flash bank <@var{num}>, starting at
1029 <@option{offset}> bytes from the beginning of the bank.
1030 @item @b{flash write_image} [@var{erase}] <@var{file}> [@var{offset}] [@var{type}]
1031 @cindex flash write_image
1032 @anchor{flash write_image}
1033 @*Write the image <@var{file}> to the current target's flash bank(s). A relocation
1034 [@var{offset}] can be specified and the file [@var{type}] can be specified
1035 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
1036 (ELF file) or @option{s19} (Motorola s19). Flash memory will be erased prior to programming
1037 if the @option{erase} parameter is given.
1038 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
1039 @cindex flash protect
1040 @*Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
1041 <@var{last}> of @option{flash bank} <@var{num}>.
1044 @subsection mFlash commands
1045 @cindex mFlash commands
1047 @item @b{mflash probe}
1048 @cindex mflash probe
1050 @item @b{mflash write} <@var{num}> <@var{file}> <@var{offset}>
1051 @cindex mflash write
1052 Write the binary <@var{file}> to mflash bank <@var{num}>, starting at
1053 <@var{offset}> bytes from the beginning of the bank.
1054 @item @b{mflash dump} <@var{num}> <@var{file}> <@var{offset}> <@var{size}>
1056 Dump <size> bytes, starting at <@var{offset}> bytes from the beginning of the <@var{num}> bank
1061 @section Target Commands
1062 @cindex Target Commands
1064 @subsection Overview
1066 Pre "TCL" - many commands in OpenOCD where implemented as C functions. Post "TCL"
1067 (Jim-Tcl to be more exact, June 2008) TCL became a bigger part of OpenOCD.
1069 One of the biggest changes is the introduction of 'target specific'
1070 commands. When every time you create a target, a special command name is
1071 created specifically for that target.
1072 For example - in TCL/TK - if you create a button (or any other screen object) you
1073 can specify various "button configuration parameters". One of those parameters is
1074 the "object cmd/name" [ In TK - this is referred to as the object path ]. Later
1075 you can use that 'path' as a command to modify the button, for example to make it
1076 "grey", or change the color. In effect, the "path" function is an 'object
1077 oriented command'. The TCL change in OpenOCD follows the same principle, you create
1078 a target, and a specific "targetname" command is created.
1080 There are two methods of creating a target:
1084 Using the old syntax (deprecated). Target names are autogenerated as:
1085 "target0", "target1", etc.;
1088 Using the new syntax, you can specify the name of the target.
1092 As most users will have a single JTAG target, and by default the command name will
1093 probably default to "target0", thus for reasons of simplicity the instructions below
1094 use the name "target0".
1096 @subsection Commands
1098 OpenOCD has the following 'target' or 'target-like' commands:
1102 @b{targets (plural)} - lists all known targets and a little bit of information about each
1103 target, most importantly the target *COMMAND*NAME* (it also lists the target number);
1106 @b{target (singular)} - used to create, configure list, etc the targets;
1109 @b{target0} - the command object for the first target. Unless you specified another name.
1113 @subsubsection Targets Command
1114 @cindex Targets Command
1115 The "targets" command has 2 functions:
1119 With a parameter, you can change the current command line target.
1121 NOTE: "with a parameter" is really only useful with 'multiple JTAG targets' not something
1122 you normally encounter (ie: If you had 2 arm chips - sharing the same JTAG chain).
1124 # using a target name.
1125 (gdb) mon targets target0
1126 # or a target by number.
1129 @cindex with a parameter
1131 Plain, without any parameter lists targets, for example:
1135 CmdName Type Endian ChainPos State
1136 -- ---------- ---------- ---------- -------- ----------
1137 0: target0 arm7tdmi little 0 halted
1143 in this example, a single target;
1145 target number 0 (1st column);
1147 the 'object name' is target0 (the default name);
1153 the position in the JTAG chain;
1155 and is currently halted.
1157 @cindex without any parameter
1160 @subsubsection Target Command
1161 @cindex Target Command
1163 The "target" command has the following options:
1169 target create CMDNAME TYPE ... config options ...
1172 argv[2] = the 'object command'
1173 (normally, target0, see (3) above)
1174 argv[3] = the target type, ie: arm7tdmi
1175 argv[4..N] = configuration parameters
1180 Lists all supported target types; ie: arm7tdmi, xscale, fericon, cortex-m3.
1181 The result TCL list of all known target types (and is human readable).
1185 Returns a TCL list of all known target commands (and is human readable).
1189 foreach t [target names] {
1190 puts [format "Target: %s\n" $t]
1196 Returns the TCL command name of the current target.
1200 set ct [target current]
1201 set t [$ct cget -type]
1203 puts "Current target name is: $ct, and is a: $t"
1206 target number <VALUE>
1208 Returns the TCL command name of the specified target.
1212 set thename [target number $x]
1213 puts [format "Target %d is: %s\n" $x $thename]
1215 For instance, assuming the defaults
1219 Would return 'target0' (or whatever you called it)
1223 Returns the larget+1 target number.
1227 set c [target count]
1228 for { set x 0 } { $x < $c } { incr x } {
1229 # Assuming you have this function..
1230 print_target_details $x
1235 @subsubsection Target0 Command
1236 @cindex Target0 Command
1237 The "target0" command (the "Target Object" command):
1239 Once a target is 'created' a command object by that targets name is created, for example
1241 target create BiGRed arm7tdmi -endian little -chain-position 3
1244 Would create a [case sensitive] "command" BiGRed
1246 If you use the old [deprecated] syntax, the name is automatically
1247 generated and is in the form:
1249 target0, target1, target2, target3, ... etc.
1252 @subsubsection Target CREATE, CONFIGURE and CGET Options Command
1253 @cindex Target CREATE, CONFIGURE and CGET Options Command
1256 target create CMDNAME TYPE [configure-options]
1257 CMDNAME configure [configure-options]
1258 CMDNAME cget [configure-options]
1262 In the 'create' case, one is creating the target and can specify any
1263 number of configuration parameters.
1265 In the 'CMDNAME configure' case, one can change the setting [Not all things can, or should be changed].
1267 In the 'CMDNAME cget' case, the goal is to query the target for a
1268 specific configuration option.
1271 In the above, the "default" name target0 is 'target0'.
1275 From the (gdb) prompt, one can type this:
1278 (gdb) mon target0 configure -endian big
1281 And change target0 to 'big-endian'. This is a contrived example,
1282 specifically for this document - don't expect changing endian
1283 'mid-operation' to work you should set the endian at creation.
1285 Known options [30/august/2008] are:
1288 [Mandatory 'create' Options]
1291 type arm7tdmi|arm720|etc ...
1293 chain-position NUMBER
1301 event EVENTNAME "tcl-action"
1311 work-area-backup BOOLEAN
1314 Hint: To get a list of available options, try this:
1316 (gdb) mon target0 cget -BLAHBLAHBLAH
1319 the above causes an error - and a helpful list of valid options.
1321 One can query any of the above options at run time, for example:
1323 (gdb) mon target0 cget -OPTION [param]
1329 # For all targets...
1330 set c [target count]
1331 for { set x 0 } { $x < $c } { incr x ] {
1332 set n [target number $x]
1333 set t [$n cget -type]
1334 set e [$n cget -endian]
1335 puts [format "%d: %s, %s, endian: %s\n" $x $n $t $n]
1342 0: pic32chip, mips_m4k, endain: little
1343 1: arm7, arm7tdmi, endian: big
1344 2: blackfin, bf534, endian: little
1347 Notice the above example is not target0, target1, target2 Why? Because in this contrived multi-target example -
1348 more human understandable target names might be helpful.
1350 For example these two are the same:
1353 (gdb) mon blackfin configure -event FOO {puts "Hi mom"}
1359 (gdb) mon [target number 2] configure -event FOO {puts "Hi mom"}
1362 In the second case, we use [] to get the command name of target #2, in this contrived example - it is "blackfin".
1364 Two important configuration options are:
1366 "-event" and "-reset"
1368 The "-reset" option specifies what should happen when the chip is reset, for example should it 'halt', 're-init',
1371 The "-event" option less you specify a TCL command to occur when a specific event occurs.
1373 @subsubsection Other Target Commands
1374 @cindex Other Target Commands
1376 @item @b{profile} <@var{seconds}> <@var{gmon.out}>
1378 Profiling samples the CPU PC as quickly as OpenOCD is able, which will be used as a random sampling of PC.
1381 @subsection Target Events
1382 @cindex Target Events
1384 @subsubsection Overview
1386 At various points in time - certain 'target' events happen. You can create a custom event action to occur at that time.
1387 For example - after reset, the PLLs and CLOCKs may need to be reconfigured, or perhaps the SDRAM needs to be re-initialized.
1388 Often the easiest way to do that is to create a simple script file containing the series of (mww [poke memory]) commands
1389 you would type by hand, to reconfigure the target clocks. You could specify the "event action" like this:
1392 (gdb) mon target0 configure -event reset-init "script cfg.clocks"
1395 In the above example, when the event "reset-init" occurs, the "action-string" will be evaluated as if you typed it at the
1398 @item @b{Option1} - The simple approach (above) is to create a script file with lots of "mww" (memory write word) commands
1399 to configure your targets clocks and/or external memory;
1400 @item @b{Option2} - You can instead create a fancy TCL procedure and invoke that procedure instead of sourcing a file [In fact,
1401 "script" is a TCL procedure that loads a file].
1404 @subsubsection Details
1406 There are many events one could use, to get a current list of events type the following invalid command, you'll get a helpful
1407 "runtime error" message, see below [list valid as of 30/august/2008]:
1410 (gdb) mon target0 cget -event FAFA
1411 Runtime error, file "../../../openocd23/src/helper/command.c", line 433:
1412 -event: Unknown: FAFA, try one of: old-pre_reset,
1413 old-gdb_program_config, old-post_reset, halted,
1414 resumed, resume-start, resume-end, reset-start,
1415 reset-assert-pre, reset-assert-post,
1416 reset-deassert-pre, reset-deassert-post,
1417 reset-halt-pre, reset-halt-post, reset-wait-pre,
1418 reset-wait-post, reset-init, reset-end,
1419 examine-start, examine-end, debug-halted,
1420 debug-resumed, gdb-attach, gdb-detach,
1421 gdb-flash-write-start, gdb-flash-write-end,
1422 gdb-flash-erase-start, gdb-flash-erase-end,
1423 resume-start, resume-ok, or resume-end
1426 NOTE: The event-names "old-*" are deprecated and exist only to help old scripts continue to function, and the old "target_script"
1427 command to work. Please do not rely on them.
1429 These are some other important names:
1431 @item gdb-flash-erase-start
1432 @item gdb-flash-erase-end
1433 @item gdb-flash-write-start
1434 @item gdb-flash-write-end
1437 These occur when GDB/OpenOCD attempts to erase & program the FLASH chip via GDB. For example - some PCBs may have a simple GPIO
1438 pin that acts like a "flash write protect" you might need to write a script that disables "write protect".
1440 To get a list of current 'event actions', type the following command:
1443 (gdb) mon target0 eventlist
1445 Event actions for target (0) target0
1448 ------------------------- | ----------------------------------------
1449 old-post_reset | script event/sam7x256_reset.script
1452 Here is a simple example for all targets:
1455 (gdb) mon foreach x [target names] { $x eventlist }
1458 The above uses some TCL tricks:
1460 @item foreach VARIABLE LIST BODY
1461 @item to generate the list, we use [target names]
1462 @item the BODY, contains $x - the loop variable and expands to the target specific name
1465 Recalling the earlier discussion - the "object command" there are other things you can
1466 do besides "configure" the target.
1468 Note: Many of these commands exist as "global" commands, and they also exist as target
1469 specific commands. For example, the "mww" (memory write word) operates on the current
1470 target if you have more then 1 target, you must switch. In contrast to the normal
1471 commands, these commands operate on the specific target. For example, the command "mww"
1472 writes data to the *current* command line target.
1474 Often, you have only a single target - but if you have multiple targets (ie: a PIC32
1475 and an at91sam7 - your reset-init scripts might get a bit more complicated, ie: you must
1476 specify which of the two chips you want to write to. Writing 'pic32' clock configuration
1477 to an at91sam7 does not work).
1479 The commands are [as of 30/august/2008]:
1481 TNAME mww ADDRESS VALUE
1482 TNAME mwh ADDRESS VALUE
1483 TNAME mwb ADDRESS VALUE
1484 Write(poke): 32, 16, 8bit values to memory.
1486 TNAME mdw ADDRESS VALUE
1487 TNAME mdh ADDRESS VALUE
1488 TNAME mdb ADDRESS VALUE
1489 Human 'hexdump' with ascii 32, 16, 8bit values
1491 TNAME mem2array [see mem2array command]
1492 TNAME array2mem [see array2mem command]
1495 Returns the current state of the target.
1498 See 'advanced target reset'
1500 See 'advanced target reset'
1502 See 'advanced target reset'
1503 TNAME reset deassert
1504 See 'advanced target reset'
1506 See 'advanced target reset'
1507 TNAME waitstate STATENAME
1508 See 'advanced target reset'
1512 @section Target Specific Commands
1513 @cindex Target Specific Commands
1515 @subsection AT91SAM7 specific commands
1516 @cindex AT91SAM7 specific commands
1517 The flash configuration is deduced from the chip identification register. The flash
1518 controller handles erases automatically on a page (128/265 byte) basis so erase is
1519 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
1520 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
1521 that can be erased separatly. Only an EraseAll command is supported by the controller
1522 for each flash plane and this is called with
1524 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
1525 @*bulk erase flash planes first_plane to last_plane.
1526 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
1527 @cindex at91sam7 gpnvm
1528 @*set or clear a gpnvm bit for the processor
1531 @subsection STR9 specific commands
1532 @cindex STR9 specific commands
1533 These are flash specific commands when using the str9xpec driver.
1535 @item @b{str9xpec enable_turbo} <@var{num}>
1536 @cindex str9xpec enable_turbo
1537 @*enable turbo mode, simply this will remove the str9 from the chain and talk
1538 directly to the embedded flash controller.
1539 @item @b{str9xpec disable_turbo} <@var{num}>
1540 @cindex str9xpec disable_turbo
1541 @*restore the str9 into jtag chain.
1542 @item @b{str9xpec lock} <@var{num}>
1543 @cindex str9xpec lock
1544 @*lock str9 device. The str9 will only respond to an unlock command that will
1546 @item @b{str9xpec unlock} <@var{num}>
1547 @cindex str9xpec unlock
1548 @*unlock str9 device.
1549 @item @b{str9xpec options_read} <@var{num}>
1550 @cindex str9xpec options_read
1551 @*read str9 option bytes.
1552 @item @b{str9xpec options_write} <@var{num}>
1553 @cindex str9xpec options_write
1554 @*write str9 option bytes.
1557 @subsection STR9 configuration
1558 @cindex STR9 configuration
1560 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
1561 <@var{BBADR}> <@var{NBBADR}>
1562 @cindex str9x flash_config
1563 @*Configure str9 flash controller.
1565 eg. str9x flash_config 0 4 2 0 0x80000
1567 BBSR - Boot Bank Size register
1568 NBBSR - Non Boot Bank Size register
1569 BBADR - Boot Bank Start Address register
1570 NBBADR - Boot Bank Start Address register
1574 @subsection STR9 option byte configuration
1575 @cindex STR9 option byte configuration
1577 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
1578 @cindex str9xpec options_cmap
1579 @*configure str9 boot bank.
1580 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
1581 @cindex str9xpec options_lvdthd
1582 @*configure str9 lvd threshold.
1583 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
1584 @cindex str9xpec options_lvdsel
1585 @*configure str9 lvd source.
1586 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
1587 @cindex str9xpec options_lvdwarn
1588 @*configure str9 lvd reset warning source.
1591 @subsection STM32x specific commands
1592 @cindex STM32x specific commands
1594 These are flash specific commands when using the stm32x driver.
1596 @item @b{stm32x lock} <@var{num}>
1598 @*lock stm32 device.
1599 @item @b{stm32x unlock} <@var{num}>
1600 @cindex stm32x unlock
1601 @*unlock stm32 device.
1602 @item @b{stm32x options_read} <@var{num}>
1603 @cindex stm32x options_read
1604 @*read stm32 option bytes.
1605 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
1606 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
1607 @cindex stm32x options_write
1608 @*write stm32 option bytes.
1609 @item @b{stm32x mass_erase} <@var{num}>
1610 @cindex stm32x mass_erase
1611 @*mass erase flash memory.
1614 @subsection Stellaris specific commands
1615 @cindex Stellaris specific commands
1617 These are flash specific commands when using the Stellaris driver.
1619 @item @b{stellaris mass_erase} <@var{num}>
1620 @cindex stellaris mass_erase
1621 @*mass erase flash memory.
1625 @section Architecture Specific Commands
1626 @cindex Architecture Specific Commands
1628 @subsection ARMV4/5 specific commands
1629 @cindex ARMV4/5 specific commands
1631 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
1632 or Intel XScale (XScale isn't supported yet).
1634 @item @b{armv4_5 reg}
1636 @*Display a list of all banked core registers, fetching the current value from every
1637 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
1639 @item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
1640 @cindex armv4_5 core_mode
1641 @*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
1642 The target is resumed in the currently set @option{core_mode}.
1645 @subsection ARM7/9 specific commands
1646 @cindex ARM7/9 specific commands
1648 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
1649 ARM920t or ARM926EJ-S.
1651 @item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
1652 @cindex arm7_9 dbgrq
1653 @*Enable use of the DBGRQ bit to force entry into debug mode. This should be
1654 safe for all but ARM7TDMI--S cores (like Philips LPC).
1655 @item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
1656 @cindex arm7_9 fast_memory_access
1657 @anchor{arm7_9 fast_memory_access}
1658 @*Allow OpenOCD to read and write memory without checking completion of
1659 the operation. This provides a huge speed increase, especially with USB JTAG
1660 cables (FT2232), but might be unsafe if used with targets running at a very low
1661 speed, like the 32kHz startup clock of an AT91RM9200.
1662 @item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
1663 @cindex arm7_9 dcc_downloads
1664 @*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
1665 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
1666 unsafe, especially with targets running at a very low speed. This command was introduced
1667 with OpenOCD rev. 60.
1670 @subsection ARM720T specific commands
1671 @cindex ARM720T specific commands
1674 @item @b{arm720t cp15} <@var{num}> [@var{value}]
1675 @cindex arm720t cp15
1676 @*display/modify cp15 register <@option{num}> [@option{value}].
1677 @item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
1678 @cindex arm720t md<bhw>_phys
1679 @*Display memory at physical address addr.
1680 @item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
1681 @cindex arm720t mw<bhw>_phys
1682 @*Write memory at physical address addr.
1683 @item @b{arm720t virt2phys} <@var{va}>
1684 @cindex arm720t virt2phys
1685 @*Translate a virtual address to a physical address.
1688 @subsection ARM9TDMI specific commands
1689 @cindex ARM9TDMI specific commands
1692 @item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
1693 @cindex arm9tdmi vector_catch
1694 @*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
1695 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
1696 @option{irq} @option{fiq}.
1698 Can also be used on other arm9 based cores, arm966, arm920t and arm926ejs.
1701 @subsection ARM966E specific commands
1702 @cindex ARM966E specific commands
1705 @item @b{arm966e cp15} <@var{num}> [@var{value}]
1706 @cindex arm966e cp15
1707 @*display/modify cp15 register <@option{num}> [@option{value}].
1710 @subsection ARM920T specific commands
1711 @cindex ARM920T specific commands
1714 @item @b{arm920t cp15} <@var{num}> [@var{value}]
1715 @cindex arm920t cp15
1716 @*display/modify cp15 register <@option{num}> [@option{value}].
1717 @item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
1718 @cindex arm920t cp15i
1719 @*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
1720 @item @b{arm920t cache_info}
1721 @cindex arm920t cache_info
1722 @*Print information about the caches found. This allows you to see if your target
1723 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1724 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1725 @cindex arm920t md<bhw>_phys
1726 @*Display memory at physical address addr.
1727 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1728 @cindex arm920t mw<bhw>_phys
1729 @*Write memory at physical address addr.
1730 @item @b{arm920t read_cache} <@var{filename}>
1731 @cindex arm920t read_cache
1732 @*Dump the content of ICache and DCache to a file.
1733 @item @b{arm920t read_mmu} <@var{filename}>
1734 @cindex arm920t read_mmu
1735 @*Dump the content of the ITLB and DTLB to a file.
1736 @item @b{arm920t virt2phys} <@var{va}>
1737 @cindex arm920t virt2phys
1738 @*Translate a virtual address to a physical address.
1741 @subsection ARM926EJS specific commands
1742 @cindex ARM926EJS specific commands
1745 @item @b{arm926ejs cp15} <@var{num}> [@var{value}]
1746 @cindex arm926ejs cp15
1747 @*display/modify cp15 register <@option{num}> [@option{value}].
1748 @item @b{arm926ejs cache_info}
1749 @cindex arm926ejs cache_info
1750 @*Print information about the caches found.
1751 @item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
1752 @cindex arm926ejs md<bhw>_phys
1753 @*Display memory at physical address addr.
1754 @item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
1755 @cindex arm926ejs mw<bhw>_phys
1756 @*Write memory at physical address addr.
1757 @item @b{arm926ejs virt2phys} <@var{va}>
1758 @cindex arm926ejs virt2phys
1759 @*Translate a virtual address to a physical address.
1762 @subsection CORTEX_M3 specific commands
1763 @cindex CORTEX_M3 specific commands
1766 @item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
1767 @cindex cortex_m3 maskisr
1768 @*Enable masking (disabling) interrupts during target step/resume.
1772 @section Debug commands
1773 @cindex Debug commands
1774 The following commands give direct access to the core, and are most likely
1775 only useful while debugging OpenOCD.
1777 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1778 @cindex arm7_9 write_xpsr
1779 @*Immediately write either the current program status register (CPSR) or the saved
1780 program status register (SPSR), without changing the register cache (as displayed
1781 by the @option{reg} and @option{armv4_5 reg} commands).
1782 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1783 <@var{0=cpsr},@var{1=spsr}>
1784 @cindex arm7_9 write_xpsr_im8
1785 @*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1786 operation (similar to @option{write_xpsr}).
1787 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1788 @cindex arm7_9 write_core_reg
1789 @*Write a core register, without changing the register cache (as displayed by the
1790 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1791 encoding of the [M4:M0] bits of the PSR.
1795 @section JTAG commands
1796 @cindex JTAG commands
1798 @item @b{scan_chain}
1800 @*Print current scan chain configuration.
1801 @item @b{jtag_reset} <@var{trst}> <@var{srst}>
1803 @*Toggle reset lines.
1804 @item @b{endstate} <@var{tap_state}>
1806 @*Finish JTAG operations in <@var{tap_state}>.
1807 @item @b{runtest} <@var{num_cycles}>
1809 @*Move to Run-Test/Idle, and execute <@var{num_cycles}>
1810 @item @b{statemove} [@var{tap_state}]
1812 @*Move to current endstate or [@var{tap_state}]
1813 @item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1815 @*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1816 @item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
1818 @*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1819 @item @b{verify_ircapture} <@option{enable}|@option{disable}>
1820 @cindex verify_ircapture
1821 @*Verify value captured during Capture-IR. Default is enabled.
1822 @item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1824 @*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1825 @item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1827 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
1831 @section Target Requests
1832 @cindex Target Requests
1833 OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
1834 See libdcc in the contrib dir for more details.
1836 @item @b{target_request debugmsgs} <@var{enable}|@var{disable}>
1837 @cindex target_request debugmsgs
1838 @*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running.
1844 If OpenOCD runs on an embedded host(as ZY1000 does), then tftp can
1845 be used to access files on PCs(either developer PC or some other PC).
1847 The way this works is to prefix a filename by "/tftp/ip/" and append
1848 the tftp path on the tftp server(tftpd). E.g. "load_image /tftp/10.0.0.96/c:\temp\abc.elf"
1849 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
1850 if the file was hosted on the embedded host.
1852 In order to achieve decent performance, you must choose a tftp server
1853 that supports a packet size bigger than the default packet size(512 bytes). There
1854 are numerous tftp servers out there(free and commercial) and you will have to do
1855 a bit of googling to find something that fits your requirements.
1857 @node Sample Scripts
1858 @chapter Sample Scripts
1861 This page shows how to use the target library.
1863 The configuration script can be divided in the following section:
1865 @item daemon configuration
1867 @item jtag scan chain
1868 @item target configuration
1869 @item flash configuration
1872 Detailed information about each section can be found at OpenOCD configuration.
1874 @section AT91R40008 example
1875 @cindex AT91R40008 example
1876 To start OpenOCD with a target script for the AT91R40008 CPU and reset
1877 the CPU upon startup of the OpenOCD daemon.
1879 openocd -f interface/parport.cfg -f target/at91r40008.cfg -c init -c reset
1883 @node GDB and OpenOCD
1884 @chapter GDB and OpenOCD
1885 @cindex GDB and OpenOCD
1886 OpenOCD complies with the remote gdbserver protocol, and as such can be used
1887 to debug remote targets.
1889 @section Connecting to gdb
1890 @cindex Connecting to gdb
1891 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For instance 6.3 has a
1892 known bug where it produces bogus memory access errors, which has since
1893 been fixed: look up 1836 in http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb
1896 A connection is typically started as follows:
1898 target remote localhost:3333
1900 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1902 To see a list of available OpenOCD commands type @option{monitor help} on the
1905 OpenOCD supports the gdb @option{qSupported} packet, this enables information
1906 to be sent by the gdb server (openocd) to gdb. Typical information includes
1907 packet size and device memory map.
1909 Previous versions of OpenOCD required the following gdb options to increase
1910 the packet size and speed up gdb communication.
1912 set remote memory-write-packet-size 1024
1913 set remote memory-write-packet-size fixed
1914 set remote memory-read-packet-size 1024
1915 set remote memory-read-packet-size fixed
1917 This is now handled in the @option{qSupported} PacketSize.
1919 @section Programming using gdb
1920 @cindex Programming using gdb
1922 By default the target memory map is sent to gdb, this can be disabled by
1923 the following OpenOCD config option:
1925 gdb_memory_map disable
1927 For this to function correctly a valid flash config must also be configured
1928 in OpenOCD. For faster performance you should also configure a valid
1931 Informing gdb of the memory map of the target will enable gdb to protect any
1932 flash area of the target and use hardware breakpoints by default. This means
1933 that the OpenOCD option @option{gdb_breakpoint_override} is not required when
1934 using a memory map. @xref{gdb_breakpoint_override}.
1936 To view the configured memory map in gdb, use the gdb command @option{info mem}
1937 All other unasigned addresses within gdb are treated as RAM.
1939 GDB 6.8 and higher set any memory area not in the memory map as inaccessible,
1940 this can be changed to the old behaviour by using the following gdb command.
1942 set mem inaccessible-by-default off
1945 If @option{gdb_flash_program enable} is also used, gdb will be able to
1946 program any flash memory using the vFlash interface.
1948 gdb will look at the target memory map when a load command is given, if any
1949 areas to be programmed lie within the target flash area the vFlash packets
1952 If the target needs configuring before gdb programming, a script can be executed.
1954 target_script 0 gdb_program_config config.script
1957 To verify any flash programming the gdb command @option{compare-sections}
1960 @node TCL and OpenOCD
1961 @chapter TCL and OpenOCD
1962 @cindex TCL and OpenOCD
1963 OpenOCD embeds a TCL interpreter (see JIM) for command parsing and scripting
1966 The TCL interpreter can be invoked from the interactive command line, files, and a network port.
1968 The command and file interfaces are fairly straightforward, while the network
1969 port is geared toward intergration with external clients. A small example
1970 of an external TCL script that can connect to openocd is shown below.
1973 # Simple tcl client to connect to openocd
1974 puts "Use empty line to exit"
1975 set fo [socket 127.0.0.1 6666]
1976 puts -nonewline stdout "> "
1978 while {[gets stdin line] >= 0} {
1979 if {$line eq {}} break
1984 puts -nonewline stdout "> "
1990 This script can easily be modified to front various GUIs or be a sub
1991 component of a larger framework for control and interaction.
1994 @node TCL scripting API
1995 @chapter TCL scripting API
1996 @cindex TCL scripting API
1999 The commands are stateless. E.g. the telnet command line has a concept
2000 of currently active target, the Tcl API proc's take this sort of state
2001 information as an argument to each proc.
2003 There are three main types of return values: single value, name value
2004 pair list and lists.
2006 Name value pair. The proc 'foo' below returns a name/value pair
2012 > set foo(you) Oyvind
2013 > set foo(mouse) Micky
2014 > set foo(duck) Donald
2022 me Duane you Oyvind mouse Micky duck Donald
2024 Thus, to get the names of the associative array is easy:
2026 foreach { name value } [set foo] {
2027 puts "Name: $name, Value: $value"
2031 Lists returned must be relatively small. Otherwise a range
2032 should be passed in to the proc in question.
2034 Low level commands are prefixed with "openocd_", e.g. openocd_flash_banks
2035 is the low level API upon which "flash banks" is implemented.
2038 @item @b{ocd_mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2040 Read memory and return as a TCL array for script processing
2041 @item @b{ocd_array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
2043 Convert a TCL array to memory locations and write the values
2044 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
2046 Return information about the flash banks
2049 OpenOCD commands can consist of two words, e.g. "flash banks". The
2050 startup.tcl "unknown" proc will translate this into a tcl proc
2051 called "flash_banks".
2055 @chapter Deprecated/Removed Commands
2056 @cindex Deprecated/Removed Commands
2057 Certain OpenOCD commands have been deprecated/removed during the various revisions.
2060 @item @b{load_binary}
2062 @*use @option{load_image} command with same args. @xref{load_image}.
2065 @*@option{target} no longer take the reset_init, reset_run, run_and_halt, run_and_init. The @option{reset} command
2066 always does a @option{reset run} when passed no arguments.
2067 @item @b{dump_binary}
2069 @*use @option{dump_image} command with same args. @xref{dump_image}.
2070 @item @b{flash erase}
2072 @*use @option{flash erase_sector} command with same args. @xref{flash erase_sector}.
2073 @item @b{flash write}
2075 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2076 @item @b{flash write_binary}
2077 @cindex flash write_binary
2078 @*use @option{flash write_bank} command with same args. @xref{flash write_bank}.
2079 @item @b{arm7_9 fast_writes}
2080 @cindex arm7_9 fast_writes
2081 @*use @option{arm7_9 fast_memory_access} command with same args. @xref{arm7_9 fast_memory_access}.
2082 @item @b{flash auto_erase}
2083 @cindex flash auto_erase
2084 @*use @option{flash write_image} command passing @option{erase} as the first parameter. @xref{flash write_image}.
2085 @item @b{daemon_startup}
2086 @cindex daemon_startup
2087 @*this config option has been removed, simply adding @option{init} and @option{reset halt} to
2088 the end of your config script will give the same behaviour as using @option{daemon_startup reset}
2089 and @option{target cortex_m3 little reset_halt 0}.
2090 @item @b{arm7_9 sw_bkpts}
2091 @cindex arm7_9 sw_bkpts
2092 @*On by default. See also @option{gdb_breakpoint_override}. @xref{gdb_breakpoint_override}.
2093 @item @b{arm7_9 force_hw_bkpts}
2094 @cindex arm7_9 force_hw_bkpts
2095 @*Use @option{gdb_breakpoint_override} instead. Note that GDB will use hardware breakpoints
2096 for flash if the gdb memory map has been set up(default when flash is declared in
2097 target configuration). @xref{gdb_breakpoint_override}.
2098 @item @b{run_and_halt_time}
2099 @cindex run_and_halt_time
2100 @*This command has been removed for simpler reset behaviour, it can be simulated with the
2113 @item Why does not backslashes in paths under Windows doesn't work?
2115 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
2116 around Windows filenames.
2129 @item OpenOCD complains about a missing cygwin1.dll.
2131 Make sure you have Cygwin installed, or at least a version of OpenOCD that
2132 claims to come with all the necessary dlls. When using Cygwin, try launching
2133 OpenOCD from the Cygwin shell.
2135 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
2136 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
2137 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
2139 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
2140 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
2141 software breakpoints consume one of the two available hardware breakpoints.
2143 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
2144 and works sometimes fine.
2146 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
2147 clock at the time you're programming the flash. If you've specified the crystal's
2148 frequency, make sure the PLL is disabled, if you've specified the full core speed
2149 (e.g. 60MHz), make sure the PLL is enabled.
2151 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
2152 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
2153 out while waiting for end of scan, rtck was disabled".
2155 Make sure your PC's parallel port operates in EPP mode. You might have to try several
2156 settings in your PC BIOS (ECP, EPP, and different versions of those).
2158 @item When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
2159 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
2160 memory read caused data abort".
2162 The errors are non-fatal, and are the result of GDB trying to trace stack frames
2163 beyond the last valid frame. It might be possible to prevent this by setting up
2164 a proper "initial" stack frame, if you happen to know what exactly has to
2165 be done, feel free to add this here.
2167 @item I get the following message in the OpenOCD console (or log file):
2168 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
2170 This warning doesn't indicate any serious problem, as long as you don't want to
2171 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
2172 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
2173 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
2174 independently. With this setup, it's not possible to halt the core right out of
2175 reset, everything else should work fine.
2177 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
2178 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
2179 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
2180 quit with an error message. Is there a stability issue with OpenOCD?
2182 No, this is not a stability issue concerning OpenOCD. Most users have solved
2183 this issue by simply using a self-powered USB hub, which they connect their
2184 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
2185 supply stable enough for the Amontec JTAGkey to be operated.
2187 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
2188 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
2189 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
2190 What does that mean and what might be the reason for this?
2192 First of all, the reason might be the USB power supply. Try using a self-powered
2193 hub instead of a direct connection to your computer. Secondly, the error code 4
2194 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
2195 chip ran into some sort of error - this points us to a USB problem.
2197 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
2198 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
2199 What does that mean and what might be the reason for this?
2201 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
2202 has closed the connection to OpenOCD. This might be a GDB issue.
2204 @item In the configuration file in the section where flash device configurations
2205 are described, there is a parameter for specifying the clock frequency for
2206 LPC2000 internal flash devices (e.g.
2207 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
2208 which must be specified in kilohertz. However, I do have a quartz crystal of a
2209 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
2210 Is it possible to specify real numbers for the clock frequency?
2212 No. The clock frequency specified here must be given as an integral number.
2213 However, this clock frequency is used by the In-Application-Programming (IAP)
2214 routines of the LPC2000 family only, which seems to be very tolerant concerning
2215 the given clock frequency, so a slight difference between the specified clock
2216 frequency and the actual clock frequency will not cause any trouble.
2218 @item Do I have to keep a specific order for the commands in the configuration file?
2220 Well, yes and no. Commands can be given in arbitrary order, yet the devices
2221 listed for the JTAG scan chain must be given in the right order (jtag_device),
2222 with the device closest to the TDO-Pin being listed first. In general,
2223 whenever objects of the same type exist which require an index number, then
2224 these objects must be given in the right order (jtag_devices, targets and flash
2225 banks - a target references a jtag_device and a flash bank references a target).
2227 @item Sometimes my debugging session terminates with an error. When I look into the
2228 log file, I can see these error messages: Error: arm7_9_common.c:561
2229 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP