1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
34 Texts. A copy of the license is included in the section entitled ``GNU
35 Free Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
83 * GDB and OpenOCD:: Using GDB and OpenOCD
84 * Tcl Scripting API:: Tcl Scripting API
85 * FAQ:: Frequently Asked Questions
86 * Tcl Crash Course:: Tcl Crash Course
87 * License:: GNU Free Documentation License
89 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
90 @comment case issue with ``Index.html'' and ``index.html''
91 @comment Occurs when creating ``--html --no-split'' output
92 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
93 * OpenOCD Concept Index:: Concept Index
94 * Command and Driver Index:: Command and Driver Index
101 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
102 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
103 Since that time, the project has grown into an active open-source project,
104 supported by a diverse community of software and hardware developers from
107 @section What is OpenOCD?
111 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
112 in-system programming and boundary-scan testing for embedded target
115 It does so with the assistance of a @dfn{debug adapter}, which is
116 a small hardware module which helps provide the right kind of
117 electrical signaling to the target being debugged. These are
118 required since the debug host (on which OpenOCD runs) won't
119 usually have native support for such signaling, or the connector
120 needed to hook up to the target.
122 Such debug adapters support one or more @dfn{transport} protocols,
123 each of which involves different electrical signaling (and uses
124 different messaging protocols on top of that signaling). There
125 are many types of debug adapter, and little uniformity in what
126 they are called. (There are also product naming differences.)
128 These adapters are sometimes packaged as discrete dongles, which
129 may generically be called @dfn{hardware interface dongles}.
130 Some development boards also integrate them directly, which may
131 let the development board connect directly to the debug
132 host over USB (and sometimes also to power it over USB).
134 For example, a @dfn{JTAG Adapter} supports JTAG
135 signaling, and is used to communicate
136 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
137 A @dfn{TAP} is a ``Test Access Port'', a module which processes
138 special instructions and data. TAPs are daisy-chained within and
139 between chips and boards. JTAG supports debugging and boundary
142 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
143 signaling to communicate with some newer ARM cores, as well as debug
144 adapters which support both JTAG and SWD transports. SWD supports only
145 debugging, whereas JTAG also supports boundary scan operations.
147 For some chips, there are also @dfn{Programming Adapters} supporting
148 special transports used only to write code to flash memory, without
149 support for on-chip debugging or boundary scan.
150 (At this writing, OpenOCD does not support such non-debug adapters.)
153 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
154 USB-based, parallel port-based, and other standalone boxes that run
155 OpenOCD internally. @xref{Debug Adapter Hardware}.
157 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
158 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
159 (Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
160 based cores to be debugged via the GDB protocol.
162 @b{Flash Programming:} Flash writing is supported for external
163 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
164 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
165 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
166 controllers (LPC3180, Orion, S3C24xx, more) is included.
168 @section OpenOCD Web Site
170 The OpenOCD web site provides the latest public news from the community:
172 @uref{http://openocd.org/}
174 @section Latest User's Guide:
176 The user's guide you are now reading may not be the latest one
177 available. A version for more recent code may be available.
178 Its HTML form is published regularly at:
180 @uref{http://openocd.org/doc/html/index.html}
182 PDF form is likewise published at:
184 @uref{http://openocd.org/doc/pdf/openocd.pdf}
186 @section OpenOCD User's Forum
188 There is an OpenOCD forum (phpBB) hosted by SparkFun,
189 which might be helpful to you. Note that if you want
190 anything to come to the attention of developers, you
191 should post it to the OpenOCD Developer Mailing List
192 instead of this forum.
194 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
196 @section OpenOCD User's Mailing List
198 The OpenOCD User Mailing List provides the primary means of
199 communication between users:
201 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
205 Support can also be found on irc:
206 @uref{irc://irc.freenode.net/openocd}
209 @chapter OpenOCD Developer Resources
212 If you are interested in improving the state of OpenOCD's debugging and
213 testing support, new contributions will be welcome. Motivated developers
214 can produce new target, flash or interface drivers, improve the
215 documentation, as well as more conventional bug fixes and enhancements.
217 The resources in this chapter are available for developers wishing to explore
218 or expand the OpenOCD source code.
220 @section OpenOCD Git Repository
222 During the 0.3.x release cycle, OpenOCD switched from Subversion to
223 a Git repository hosted at SourceForge. The repository URL is:
225 @uref{git://git.code.sf.net/p/openocd/code}
229 @uref{http://git.code.sf.net/p/openocd/code}
231 You may prefer to use a mirror and the HTTP protocol:
233 @uref{http://repo.or.cz/r/openocd.git}
235 With standard Git tools, use @command{git clone} to initialize
236 a local repository, and @command{git pull} to update it.
237 There are also gitweb pages letting you browse the repository
238 with a web browser, or download arbitrary snapshots without
239 needing a Git client:
241 @uref{http://repo.or.cz/w/openocd.git}
243 The @file{README} file contains the instructions for building the project
244 from the repository or a snapshot.
246 Developers that want to contribute patches to the OpenOCD system are
247 @b{strongly} encouraged to work against mainline.
248 Patches created against older versions may require additional
249 work from their submitter in order to be updated for newer releases.
251 @section Doxygen Developer Manual
253 During the 0.2.x release cycle, the OpenOCD project began
254 providing a Doxygen reference manual. This document contains more
255 technical information about the software internals, development
256 processes, and similar documentation:
258 @uref{http://openocd.org/doc/doxygen/html/index.html}
260 This document is a work-in-progress, but contributions would be welcome
261 to fill in the gaps. All of the source files are provided in-tree,
262 listed in the Doxyfile configuration at the top of the source tree.
264 @section Gerrit Review System
266 All changes in the OpenOCD Git repository go through the web-based Gerrit
269 @uref{http://openocd.zylin.com/}
271 After a one-time registration and repository setup, anyone can push commits
272 from their local Git repository directly into Gerrit.
273 All users and developers are encouraged to review, test, discuss and vote
274 for changes in Gerrit. The feedback provides the basis for a maintainer to
275 eventually submit the change to the main Git repository.
277 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
278 Developer Manual, contains basic information about how to connect a
279 repository to Gerrit, prepare and push patches. Patch authors are expected to
280 maintain their changes while they're in Gerrit, respond to feedback and if
281 necessary rework and push improved versions of the change.
283 @section OpenOCD Developer Mailing List
285 The OpenOCD Developer Mailing List provides the primary means of
286 communication between developers:
288 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
290 @section OpenOCD Bug Tracker
292 The OpenOCD Bug Tracker is hosted on SourceForge:
294 @uref{http://bugs.openocd.org/}
297 @node Debug Adapter Hardware
298 @chapter Debug Adapter Hardware
307 Defined: @b{dongle}: A small device that plugs into a computer and serves as
308 an adapter .... [snip]
310 In the OpenOCD case, this generally refers to @b{a small adapter} that
311 attaches to your computer via USB or the parallel port. One
312 exception is the Ultimate Solutions ZY1000, packaged as a small box you
313 attach via an ethernet cable. The ZY1000 has the advantage that it does not
314 require any drivers to be installed on the developer PC. It also has
315 a built in web interface. It supports RTCK/RCLK or adaptive clocking
316 and has a built-in relay to power cycle targets remotely.
319 @section Choosing a Dongle
321 There are several things you should keep in mind when choosing a dongle.
324 @item @b{Transport} Does it support the kind of communication that you need?
325 OpenOCD focusses mostly on JTAG. Your version may also support
326 other ways to communicate with target devices.
327 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
328 Does your dongle support it? You might need a level converter.
329 @item @b{Pinout} What pinout does your target board use?
330 Does your dongle support it? You may be able to use jumper
331 wires, or an "octopus" connector, to convert pinouts.
332 @item @b{Connection} Does your computer have the USB, parallel, or
333 Ethernet port needed?
334 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
335 RTCK support (also known as ``adaptive clocking'')?
338 @section Stand-alone JTAG Probe
340 The ZY1000 from Ultimate Solutions is technically not a dongle but a
341 stand-alone JTAG probe that, unlike most dongles, doesn't require any drivers
342 running on the developer's host computer.
343 Once installed on a network using DHCP or a static IP assignment, users can
344 access the ZY1000 probe locally or remotely from any host with access to the
345 IP address assigned to the probe.
346 The ZY1000 provides an intuitive web interface with direct access to the
348 Users may also run a GDBSERVER directly on the ZY1000 to take full advantage
349 of GCC & GDB to debug any distribution of embedded Linux or NetBSD running on
351 The ZY1000 supports RTCK & RCLK or adaptive clocking and has a built-in relay
352 to power cycle the target remotely.
354 For more information, visit:
356 @b{ZY1000} See: @url{http://www.ultsol.com/index.php/component/content/article/8/210-zylin-zy1000-main}
358 @section USB FT2232 Based
360 There are many USB JTAG dongles on the market, many of them based
361 on a chip from ``Future Technology Devices International'' (FTDI)
362 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
363 See: @url{http://www.ftdichip.com} for more information.
364 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
365 chips started to become available in JTAG adapters. Around 2012, a new
366 variant appeared - FT232H - this is a single-channel version of FT2232H.
367 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
370 The FT2232 chips are flexible enough to support some other
371 transport options, such as SWD or the SPI variants used to
372 program some chips. They have two communications channels,
373 and one can be used for a UART adapter at the same time the
374 other one is used to provide a debug adapter.
376 Also, some development boards integrate an FT2232 chip to serve as
377 a built-in low-cost debug adapter and USB-to-serial solution.
381 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
383 @* See: @url{http://www.amontec.com/jtagkey.shtml}
385 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
387 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
389 @* See: @url{http://www.signalyzer.com}
390 @item @b{Stellaris Eval Boards}
391 @* See: @url{http://www.ti.com} - The Stellaris eval boards
392 bundle FT2232-based JTAG and SWD support, which can be used to debug
393 the Stellaris chips. Using separate JTAG adapters is optional.
394 These boards can also be used in a "pass through" mode as JTAG adapters
395 to other target boards, disabling the Stellaris chip.
396 @item @b{TI/Luminary ICDI}
397 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
398 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
399 Evaluation Kits. Like the non-detachable FT2232 support on the other
400 Stellaris eval boards, they can be used to debug other target boards.
401 @item @b{olimex-jtag}
402 @* See: @url{http://www.olimex.com}
403 @item @b{Flyswatter/Flyswatter2}
404 @* See: @url{http://www.tincantools.com}
405 @item @b{turtelizer2}
407 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
408 @url{http://www.ethernut.de}
410 @* Link: @url{http://www.hitex.com/index.php?id=383}
412 @* Link @url{http://www.hitex.com/stm32-stick}
413 @item @b{axm0432_jtag}
414 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
415 to be available anymore as of April 2012.
417 @* Link @url{http://www.hitex.com/index.php?id=cortino}
418 @item @b{dlp-usb1232h}
419 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
420 @item @b{digilent-hs1}
421 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
423 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
425 @item @b{JTAG-lock-pick Tiny 2}
426 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
429 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
433 @section USB-JTAG / Altera USB-Blaster compatibles
435 These devices also show up as FTDI devices, but are not
436 protocol-compatible with the FT2232 devices. They are, however,
437 protocol-compatible among themselves. USB-JTAG devices typically consist
438 of a FT245 followed by a CPLD that understands a particular protocol,
439 or emulates this protocol using some other hardware.
441 They may appear under different USB VID/PID depending on the particular
442 product. The driver can be configured to search for any VID/PID pair
443 (see the section on driver commands).
446 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
447 @* Link: @url{http://ixo-jtag.sourceforge.net/}
448 @item @b{Altera USB-Blaster}
449 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
452 @section USB J-Link based
453 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
454 an example of a microcontroller based JTAG adapter, it uses an
455 AT91SAM764 internally.
458 @item @b{SEGGER J-Link}
459 @* Link: @url{http://www.segger.com/jlink.html}
460 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
461 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
465 @section USB RLINK based
466 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
467 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
468 SWD and not JTAG, thus not supported.
471 @item @b{Raisonance RLink}
472 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
473 @item @b{STM32 Primer}
474 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
475 @item @b{STM32 Primer2}
476 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
479 @section USB ST-LINK based
480 ST Micro has an adapter called @b{ST-LINK}.
481 They only work with ST Micro chips, notably STM32 and STM8.
485 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
486 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
488 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
489 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
492 For info the original ST-LINK enumerates using the mass storage usb class; however,
493 its implementation is completely broken. The result is this causes issues under Linux.
494 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
496 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
497 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
500 @section USB TI/Stellaris ICDI based
501 Texas Instruments has an adapter called @b{ICDI}.
502 It is not to be confused with the FTDI based adapters that were originally fitted to their
503 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
505 @section USB CMSIS-DAP based
506 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
507 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
512 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
514 @item @b{USB - Presto}
515 @* Link: @url{http://tools.asix.net/prg_presto.htm}
517 @item @b{Versaloon-Link}
518 @* Link: @url{http://www.versaloon.com}
520 @item @b{ARM-JTAG-EW}
521 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
524 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
527 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
530 @* Link: @url{http://code.google.com/p/estick-jtag/}
532 @item @b{Keil ULINK v1}
533 @* Link: @url{http://www.keil.com/ulink1/}
536 @section IBM PC Parallel Printer Port Based
538 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
539 and the Macraigor Wiggler. There are many clones and variations of
542 Note that parallel ports are becoming much less common, so if you
543 have the choice you should probably avoid these adapters in favor
548 @item @b{Wiggler} - There are many clones of this.
549 @* Link: @url{http://www.macraigor.com/wiggler.htm}
551 @item @b{DLC5} - From XILINX - There are many clones of this
552 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
553 produced, PDF schematics are easily found and it is easy to make.
555 @item @b{Amontec - JTAG Accelerator}
556 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
559 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
561 @item @b{Wiggler_ntrst_inverted}
562 @* Yet another variation - See the source code, src/jtag/parport.c
564 @item @b{old_amt_wiggler}
565 @* Unknown - probably not on the market today
568 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
571 @* Link: @url{http://www.amontec.com/chameleon.shtml}
577 @* ispDownload from Lattice Semiconductor
578 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
581 @* From ST Microsystems;
582 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
590 @* An EP93xx based Linux machine using the GPIO pins directly.
593 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
595 @item @b{bcm2835gpio}
596 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
599 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
602 @* A JTAG driver acting as a client for the JTAG VPI server interface.
603 @* Link: @url{http://github.com/fjullien/jtag_vpi}
608 @chapter About Jim-Tcl
612 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
613 This programming language provides a simple and extensible
616 All commands presented in this Guide are extensions to Jim-Tcl.
617 You can use them as simple commands, without needing to learn
618 much of anything about Tcl.
619 Alternatively, you can write Tcl programs with them.
621 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
622 There is an active and responsive community, get on the mailing list
623 if you have any questions. Jim-Tcl maintainers also lurk on the
624 OpenOCD mailing list.
627 @item @b{Jim vs. Tcl}
628 @* Jim-Tcl is a stripped down version of the well known Tcl language,
629 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
630 fewer features. Jim-Tcl is several dozens of .C files and .H files and
631 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
632 4.2 MB .zip file containing 1540 files.
634 @item @b{Missing Features}
635 @* Our practice has been: Add/clone the real Tcl feature if/when
636 needed. We welcome Jim-Tcl improvements, not bloat. Also there
637 are a large number of optional Jim-Tcl features that are not
641 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
642 command interpreter today is a mixture of (newer)
643 Jim-Tcl commands, and the (older) original command interpreter.
646 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
647 can type a Tcl for() loop, set variables, etc.
648 Some of the commands documented in this guide are implemented
649 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
651 @item @b{Historical Note}
652 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
653 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
654 as a Git submodule, which greatly simplified upgrading Jim-Tcl
655 to benefit from new features and bugfixes in Jim-Tcl.
657 @item @b{Need a crash course in Tcl?}
658 @*@xref{Tcl Crash Course}.
663 @cindex command line options
665 @cindex directory search
667 Properly installing OpenOCD sets up your operating system to grant it access
668 to the debug adapters. On Linux, this usually involves installing a file
669 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
670 that works for many common adapters is shipped with OpenOCD in the
671 @file{contrib} directory. MS-Windows needs
672 complex and confusing driver configuration for every peripheral. Such issues
673 are unique to each operating system, and are not detailed in this User's Guide.
675 Then later you will invoke the OpenOCD server, with various options to
676 tell it how each debug session should work.
677 The @option{--help} option shows:
681 --help | -h display this help
682 --version | -v display OpenOCD version
683 --file | -f use configuration file <name>
684 --search | -s dir to search for config files and scripts
685 --debug | -d set debug level to 3
686 | -d<n> set debug level to <level>
687 --log_output | -l redirect log output to file <name>
688 --command | -c run <command>
691 If you don't give any @option{-f} or @option{-c} options,
692 OpenOCD tries to read the configuration file @file{openocd.cfg}.
693 To specify one or more different
694 configuration files, use @option{-f} options. For example:
697 openocd -f config1.cfg -f config2.cfg -f config3.cfg
700 Configuration files and scripts are searched for in
702 @item the current directory,
703 @item any search dir specified on the command line using the @option{-s} option,
704 @item any search dir specified using the @command{add_script_search_dir} command,
705 @item @file{$HOME/.openocd} (not on Windows),
706 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
707 @item the site wide script library @file{$pkgdatadir/site} and
708 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
710 The first found file with a matching file name will be used.
713 Don't try to use configuration script names or paths which
714 include the "#" character. That character begins Tcl comments.
717 @section Simple setup, no customization
719 In the best case, you can use two scripts from one of the script
720 libraries, hook up your JTAG adapter, and start the server ... and
721 your JTAG setup will just work "out of the box". Always try to
722 start by reusing those scripts, but assume you'll need more
723 customization even if this works. @xref{OpenOCD Project Setup}.
725 If you find a script for your JTAG adapter, and for your board or
726 target, you may be able to hook up your JTAG adapter then start
727 the server with some variation of one of the following:
730 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
731 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
734 You might also need to configure which reset signals are present,
735 using @option{-c 'reset_config trst_and_srst'} or something similar.
736 If all goes well you'll see output something like
739 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
740 For bug reports, read
741 http://openocd.org/doc/doxygen/bugs.html
742 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
743 (mfg: 0x23b, part: 0xba00, ver: 0x3)
746 Seeing that "tap/device found" message, and no warnings, means
747 the JTAG communication is working. That's a key milestone, but
748 you'll probably need more project-specific setup.
750 @section What OpenOCD does as it starts
752 OpenOCD starts by processing the configuration commands provided
753 on the command line or, if there were no @option{-c command} or
754 @option{-f file.cfg} options given, in @file{openocd.cfg}.
755 @xref{configurationstage,,Configuration Stage}.
756 At the end of the configuration stage it verifies the JTAG scan
757 chain defined using those commands; your configuration should
758 ensure that this always succeeds.
759 Normally, OpenOCD then starts running as a server.
760 Alternatively, commands may be used to terminate the configuration
761 stage early, perform work (such as updating some flash memory),
762 and then shut down without acting as a server.
764 Once OpenOCD starts running as a server, it waits for connections from
765 clients (Telnet, GDB, RPC) and processes the commands issued through
768 If you are having problems, you can enable internal debug messages via
769 the @option{-d} option.
771 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
772 @option{-c} command line switch.
774 To enable debug output (when reporting problems or working on OpenOCD
775 itself), use the @option{-d} command line switch. This sets the
776 @option{debug_level} to "3", outputting the most information,
777 including debug messages. The default setting is "2", outputting only
778 informational messages, warnings and errors. You can also change this
779 setting from within a telnet or gdb session using @command{debug_level<n>}
780 (@pxref{debuglevel,,debug_level}).
782 You can redirect all output from the server to a file using the
783 @option{-l <logfile>} switch.
785 Note! OpenOCD will launch the GDB & telnet server even if it can not
786 establish a connection with the target. In general, it is possible for
787 the JTAG controller to be unresponsive until the target is set up
788 correctly via e.g. GDB monitor commands in a GDB init script.
790 @node OpenOCD Project Setup
791 @chapter OpenOCD Project Setup
793 To use OpenOCD with your development projects, you need to do more than
794 just connect the JTAG adapter hardware (dongle) to your development board
795 and start the OpenOCD server.
796 You also need to configure your OpenOCD server so that it knows
797 about your adapter and board, and helps your work.
798 You may also want to connect OpenOCD to GDB, possibly
799 using Eclipse or some other GUI.
801 @section Hooking up the JTAG Adapter
803 Today's most common case is a dongle with a JTAG cable on one side
804 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
805 and a USB cable on the other.
806 Instead of USB, some cables use Ethernet;
807 older ones may use a PC parallel port, or even a serial port.
810 @item @emph{Start with power to your target board turned off},
811 and nothing connected to your JTAG adapter.
812 If you're particularly paranoid, unplug power to the board.
813 It's important to have the ground signal properly set up,
814 unless you are using a JTAG adapter which provides
815 galvanic isolation between the target board and the
818 @item @emph{Be sure it's the right kind of JTAG connector.}
819 If your dongle has a 20-pin ARM connector, you need some kind
820 of adapter (or octopus, see below) to hook it up to
821 boards using 14-pin or 10-pin connectors ... or to 20-pin
822 connectors which don't use ARM's pinout.
824 In the same vein, make sure the voltage levels are compatible.
825 Not all JTAG adapters have the level shifters needed to work
826 with 1.2 Volt boards.
828 @item @emph{Be certain the cable is properly oriented} or you might
829 damage your board. In most cases there are only two possible
830 ways to connect the cable.
831 Connect the JTAG cable from your adapter to the board.
832 Be sure it's firmly connected.
834 In the best case, the connector is keyed to physically
835 prevent you from inserting it wrong.
836 This is most often done using a slot on the board's male connector
837 housing, which must match a key on the JTAG cable's female connector.
838 If there's no housing, then you must look carefully and
839 make sure pin 1 on the cable hooks up to pin 1 on the board.
840 Ribbon cables are frequently all grey except for a wire on one
841 edge, which is red. The red wire is pin 1.
843 Sometimes dongles provide cables where one end is an ``octopus'' of
844 color coded single-wire connectors, instead of a connector block.
845 These are great when converting from one JTAG pinout to another,
846 but are tedious to set up.
847 Use these with connector pinout diagrams to help you match up the
848 adapter signals to the right board pins.
850 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
851 A USB, parallel, or serial port connector will go to the host which
852 you are using to run OpenOCD.
853 For Ethernet, consult the documentation and your network administrator.
855 For USB-based JTAG adapters you have an easy sanity check at this point:
856 does the host operating system see the JTAG adapter? If you're running
857 Linux, try the @command{lsusb} command. If that host is an
858 MS-Windows host, you'll need to install a driver before OpenOCD works.
860 @item @emph{Connect the adapter's power supply, if needed.}
861 This step is primarily for non-USB adapters,
862 but sometimes USB adapters need extra power.
864 @item @emph{Power up the target board.}
865 Unless you just let the magic smoke escape,
866 you're now ready to set up the OpenOCD server
867 so you can use JTAG to work with that board.
871 Talk with the OpenOCD server using
872 telnet (@code{telnet localhost 4444} on many systems) or GDB.
873 @xref{GDB and OpenOCD}.
875 @section Project Directory
877 There are many ways you can configure OpenOCD and start it up.
879 A simple way to organize them all involves keeping a
880 single directory for your work with a given board.
881 When you start OpenOCD from that directory,
882 it searches there first for configuration files, scripts,
883 files accessed through semihosting,
884 and for code you upload to the target board.
885 It is also the natural place to write files,
886 such as log files and data you download from the board.
888 @section Configuration Basics
890 There are two basic ways of configuring OpenOCD, and
891 a variety of ways you can mix them.
892 Think of the difference as just being how you start the server:
895 @item Many @option{-f file} or @option{-c command} options on the command line
896 @item No options, but a @dfn{user config file}
897 in the current directory named @file{openocd.cfg}
900 Here is an example @file{openocd.cfg} file for a setup
901 using a Signalyzer FT2232-based JTAG adapter to talk to
902 a board with an Atmel AT91SAM7X256 microcontroller:
905 source [find interface/ftdi/signalyzer.cfg]
907 # GDB can also flash my flash!
908 gdb_memory_map enable
909 gdb_flash_program enable
911 source [find target/sam7x256.cfg]
914 Here is the command line equivalent of that configuration:
917 openocd -f interface/ftdi/signalyzer.cfg \
918 -c "gdb_memory_map enable" \
919 -c "gdb_flash_program enable" \
920 -f target/sam7x256.cfg
923 You could wrap such long command lines in shell scripts,
924 each supporting a different development task.
925 One might re-flash the board with a specific firmware version.
926 Another might set up a particular debugging or run-time environment.
929 At this writing (October 2009) the command line method has
930 problems with how it treats variables.
931 For example, after @option{-c "set VAR value"}, or doing the
932 same in a script, the variable @var{VAR} will have no value
933 that can be tested in a later script.
936 Here we will focus on the simpler solution: one user config
937 file, including basic configuration plus any TCL procedures
938 to simplify your work.
940 @section User Config Files
941 @cindex config file, user
942 @cindex user config file
943 @cindex config file, overview
945 A user configuration file ties together all the parts of a project
947 One of the following will match your situation best:
950 @item Ideally almost everything comes from configuration files
951 provided by someone else.
952 For example, OpenOCD distributes a @file{scripts} directory
953 (probably in @file{/usr/share/openocd/scripts} on Linux).
954 Board and tool vendors can provide these too, as can individual
955 user sites; the @option{-s} command line option lets you say
956 where to find these files. (@xref{Running}.)
957 The AT91SAM7X256 example above works this way.
959 Three main types of non-user configuration file each have their
960 own subdirectory in the @file{scripts} directory:
963 @item @b{interface} -- one for each different debug adapter;
964 @item @b{board} -- one for each different board
965 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
968 Best case: include just two files, and they handle everything else.
969 The first is an interface config file.
970 The second is board-specific, and it sets up the JTAG TAPs and
971 their GDB targets (by deferring to some @file{target.cfg} file),
972 declares all flash memory, and leaves you nothing to do except
976 source [find interface/olimex-jtag-tiny.cfg]
977 source [find board/csb337.cfg]
980 Boards with a single microcontroller often won't need more
981 than the target config file, as in the AT91SAM7X256 example.
982 That's because there is no external memory (flash, DDR RAM), and
983 the board differences are encapsulated by application code.
985 @item Maybe you don't know yet what your board looks like to JTAG.
986 Once you know the @file{interface.cfg} file to use, you may
987 need help from OpenOCD to discover what's on the board.
988 Once you find the JTAG TAPs, you can just search for appropriate
990 configuration files ... or write your own, from the bottom up.
991 @xref{autoprobing,,Autoprobing}.
993 @item You can often reuse some standard config files but
994 need to write a few new ones, probably a @file{board.cfg} file.
995 You will be using commands described later in this User's Guide,
996 and working with the guidelines in the next chapter.
998 For example, there may be configuration files for your JTAG adapter
999 and target chip, but you need a new board-specific config file
1000 giving access to your particular flash chips.
1001 Or you might need to write another target chip configuration file
1002 for a new chip built around the Cortex-M3 core.
1005 When you write new configuration files, please submit
1006 them for inclusion in the next OpenOCD release.
1007 For example, a @file{board/newboard.cfg} file will help the
1008 next users of that board, and a @file{target/newcpu.cfg}
1009 will help support users of any board using that chip.
1013 You may may need to write some C code.
1014 It may be as simple as supporting a new FT2232 or parport
1015 based adapter; a bit more involved, like a NAND or NOR flash
1016 controller driver; or a big piece of work like supporting
1017 a new chip architecture.
1020 Reuse the existing config files when you can.
1021 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1022 You may find a board configuration that's a good example to follow.
1024 When you write config files, separate the reusable parts
1025 (things every user of that interface, chip, or board needs)
1026 from ones specific to your environment and debugging approach.
1030 For example, a @code{gdb-attach} event handler that invokes
1031 the @command{reset init} command will interfere with debugging
1032 early boot code, which performs some of the same actions
1033 that the @code{reset-init} event handler does.
1036 Likewise, the @command{arm9 vector_catch} command (or
1037 @cindex vector_catch
1038 its siblings @command{xscale vector_catch}
1039 and @command{cortex_m vector_catch}) can be a timesaver
1040 during some debug sessions, but don't make everyone use that either.
1041 Keep those kinds of debugging aids in your user config file,
1042 along with messaging and tracing setup.
1043 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1046 You might need to override some defaults.
1047 For example, you might need to move, shrink, or back up the target's
1048 work area if your application needs much SRAM.
1051 TCP/IP port configuration is another example of something which
1052 is environment-specific, and should only appear in
1053 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1056 @section Project-Specific Utilities
1058 A few project-specific utility
1059 routines may well speed up your work.
1060 Write them, and keep them in your project's user config file.
1062 For example, if you are making a boot loader work on a
1063 board, it's nice to be able to debug the ``after it's
1064 loaded to RAM'' parts separately from the finicky early
1065 code which sets up the DDR RAM controller and clocks.
1066 A script like this one, or a more GDB-aware sibling,
1070 proc ramboot @{ @} @{
1071 # Reset, running the target's "reset-init" scripts
1072 # to initialize clocks and the DDR RAM controller.
1073 # Leave the CPU halted.
1076 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1077 load_image u-boot.bin 0x20000000
1084 Then once that code is working you will need to make it
1085 boot from NOR flash; a different utility would help.
1086 Alternatively, some developers write to flash using GDB.
1087 (You might use a similar script if you're working with a flash
1088 based microcontroller application instead of a boot loader.)
1091 proc newboot @{ @} @{
1092 # Reset, leaving the CPU halted. The "reset-init" event
1093 # proc gives faster access to the CPU and to NOR flash;
1094 # "reset halt" would be slower.
1097 # Write standard version of U-Boot into the first two
1098 # sectors of NOR flash ... the standard version should
1099 # do the same lowlevel init as "reset-init".
1100 flash protect 0 0 1 off
1101 flash erase_sector 0 0 1
1102 flash write_bank 0 u-boot.bin 0x0
1103 flash protect 0 0 1 on
1105 # Reboot from scratch using that new boot loader.
1110 You may need more complicated utility procedures when booting
1112 That often involves an extra bootloader stage,
1113 running from on-chip SRAM to perform DDR RAM setup so it can load
1114 the main bootloader code (which won't fit into that SRAM).
1116 Other helper scripts might be used to write production system images,
1117 involving considerably more than just a three stage bootloader.
1119 @section Target Software Changes
1121 Sometimes you may want to make some small changes to the software
1122 you're developing, to help make JTAG debugging work better.
1123 For example, in C or assembly language code you might
1124 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1125 handling issues like:
1129 @item @b{Watchdog Timers}...
1130 Watchog timers are typically used to automatically reset systems if
1131 some application task doesn't periodically reset the timer. (The
1132 assumption is that the system has locked up if the task can't run.)
1133 When a JTAG debugger halts the system, that task won't be able to run
1134 and reset the timer ... potentially causing resets in the middle of
1135 your debug sessions.
1137 It's rarely a good idea to disable such watchdogs, since their usage
1138 needs to be debugged just like all other parts of your firmware.
1139 That might however be your only option.
1141 Look instead for chip-specific ways to stop the watchdog from counting
1142 while the system is in a debug halt state. It may be simplest to set
1143 that non-counting mode in your debugger startup scripts. You may however
1144 need a different approach when, for example, a motor could be physically
1145 damaged by firmware remaining inactive in a debug halt state. That might
1146 involve a type of firmware mode where that "non-counting" mode is disabled
1147 at the beginning then re-enabled at the end; a watchdog reset might fire
1148 and complicate the debug session, but hardware (or people) would be
1149 protected.@footnote{Note that many systems support a "monitor mode" debug
1150 that is a somewhat cleaner way to address such issues. You can think of
1151 it as only halting part of the system, maybe just one task,
1152 instead of the whole thing.
1153 At this writing, January 2010, OpenOCD based debugging does not support
1154 monitor mode debug, only "halt mode" debug.}
1156 @item @b{ARM Semihosting}...
1157 @cindex ARM semihosting
1158 When linked with a special runtime library provided with many
1159 toolchains@footnote{See chapter 8 "Semihosting" in
1160 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1161 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1162 The CodeSourcery EABI toolchain also includes a semihosting library.},
1163 your target code can use I/O facilities on the debug host. That library
1164 provides a small set of system calls which are handled by OpenOCD.
1165 It can let the debugger provide your system console and a file system,
1166 helping with early debugging or providing a more capable environment
1167 for sometimes-complex tasks like installing system firmware onto
1170 @item @b{ARM Wait-For-Interrupt}...
1171 Many ARM chips synchronize the JTAG clock using the core clock.
1172 Low power states which stop that core clock thus prevent JTAG access.
1173 Idle loops in tasking environments often enter those low power states
1174 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1176 You may want to @emph{disable that instruction} in source code,
1177 or otherwise prevent using that state,
1178 to ensure you can get JTAG access at any time.@footnote{As a more
1179 polite alternative, some processors have special debug-oriented
1180 registers which can be used to change various features including
1181 how the low power states are clocked while debugging.
1182 The STM32 DBGMCU_CR register is an example; at the cost of extra
1183 power consumption, JTAG can be used during low power states.}
1184 For example, the OpenOCD @command{halt} command may not
1185 work for an idle processor otherwise.
1187 @item @b{Delay after reset}...
1188 Not all chips have good support for debugger access
1189 right after reset; many LPC2xxx chips have issues here.
1190 Similarly, applications that reconfigure pins used for
1191 JTAG access as they start will also block debugger access.
1193 To work with boards like this, @emph{enable a short delay loop}
1194 the first thing after reset, before "real" startup activities.
1195 For example, one second's delay is usually more than enough
1196 time for a JTAG debugger to attach, so that
1197 early code execution can be debugged
1198 or firmware can be replaced.
1200 @item @b{Debug Communications Channel (DCC)}...
1201 Some processors include mechanisms to send messages over JTAG.
1202 Many ARM cores support these, as do some cores from other vendors.
1203 (OpenOCD may be able to use this DCC internally, speeding up some
1204 operations like writing to memory.)
1206 Your application may want to deliver various debugging messages
1207 over JTAG, by @emph{linking with a small library of code}
1208 provided with OpenOCD and using the utilities there to send
1209 various kinds of message.
1210 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1214 @section Target Hardware Setup
1216 Chip vendors often provide software development boards which
1217 are highly configurable, so that they can support all options
1218 that product boards may require. @emph{Make sure that any
1219 jumpers or switches match the system configuration you are
1222 Common issues include:
1226 @item @b{JTAG setup} ...
1227 Boards may support more than one JTAG configuration.
1228 Examples include jumpers controlling pullups versus pulldowns
1229 on the nTRST and/or nSRST signals, and choice of connectors
1230 (e.g. which of two headers on the base board,
1231 or one from a daughtercard).
1232 For some Texas Instruments boards, you may need to jumper the
1233 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1235 @item @b{Boot Modes} ...
1236 Complex chips often support multiple boot modes, controlled
1237 by external jumpers. Make sure this is set up correctly.
1238 For example many i.MX boards from NXP need to be jumpered
1239 to "ATX mode" to start booting using the on-chip ROM, when
1240 using second stage bootloader code stored in a NAND flash chip.
1242 Such explicit configuration is common, and not limited to
1243 booting from NAND. You might also need to set jumpers to
1244 start booting using code loaded from an MMC/SD card; external
1245 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1246 flash; some external host; or various other sources.
1249 @item @b{Memory Addressing} ...
1250 Boards which support multiple boot modes may also have jumpers
1251 to configure memory addressing. One board, for example, jumpers
1252 external chipselect 0 (used for booting) to address either
1253 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1254 or NAND flash. When it's jumpered to address NAND flash, that
1255 board must also be told to start booting from on-chip ROM.
1257 Your @file{board.cfg} file may also need to be told this jumper
1258 configuration, so that it can know whether to declare NOR flash
1259 using @command{flash bank} or instead declare NAND flash with
1260 @command{nand device}; and likewise which probe to perform in
1261 its @code{reset-init} handler.
1263 A closely related issue is bus width. Jumpers might need to
1264 distinguish between 8 bit or 16 bit bus access for the flash
1265 used to start booting.
1267 @item @b{Peripheral Access} ...
1268 Development boards generally provide access to every peripheral
1269 on the chip, sometimes in multiple modes (such as by providing
1270 multiple audio codec chips).
1271 This interacts with software
1272 configuration of pin multiplexing, where for example a
1273 given pin may be routed either to the MMC/SD controller
1274 or the GPIO controller. It also often interacts with
1275 configuration jumpers. One jumper may be used to route
1276 signals to an MMC/SD card slot or an expansion bus (which
1277 might in turn affect booting); others might control which
1278 audio or video codecs are used.
1282 Plus you should of course have @code{reset-init} event handlers
1283 which set up the hardware to match that jumper configuration.
1284 That includes in particular any oscillator or PLL used to clock
1285 the CPU, and any memory controllers needed to access external
1286 memory and peripherals. Without such handlers, you won't be
1287 able to access those resources without working target firmware
1288 which can do that setup ... this can be awkward when you're
1289 trying to debug that target firmware. Even if there's a ROM
1290 bootloader which handles a few issues, it rarely provides full
1291 access to all board-specific capabilities.
1294 @node Config File Guidelines
1295 @chapter Config File Guidelines
1297 This chapter is aimed at any user who needs to write a config file,
1298 including developers and integrators of OpenOCD and any user who
1299 needs to get a new board working smoothly.
1300 It provides guidelines for creating those files.
1302 You should find the following directories under
1303 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1304 them as-is where you can; or as models for new files.
1306 @item @file{interface} ...
1307 These are for debug adapters. Files that specify configuration to use
1308 specific JTAG, SWD and other adapters go here.
1309 @item @file{board} ...
1310 Think Circuit Board, PWA, PCB, they go by many names. Board files
1311 contain initialization items that are specific to a board.
1313 They reuse target configuration files, since the same
1314 microprocessor chips are used on many boards,
1315 but support for external parts varies widely. For
1316 example, the SDRAM initialization sequence for the board, or the type
1317 of external flash and what address it uses. Any initialization
1318 sequence to enable that external flash or SDRAM should be found in the
1319 board file. Boards may also contain multiple targets: two CPUs; or
1321 @item @file{target} ...
1322 Think chip. The ``target'' directory represents the JTAG TAPs
1324 which OpenOCD should control, not a board. Two common types of targets
1325 are ARM chips and FPGA or CPLD chips.
1326 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1327 the target config file defines all of them.
1328 @item @emph{more} ... browse for other library files which may be useful.
1329 For example, there are various generic and CPU-specific utilities.
1332 The @file{openocd.cfg} user config
1333 file may override features in any of the above files by
1334 setting variables before sourcing the target file, or by adding
1335 commands specific to their situation.
1337 @section Interface Config Files
1339 The user config file
1340 should be able to source one of these files with a command like this:
1343 source [find interface/FOOBAR.cfg]
1346 A preconfigured interface file should exist for every debug adapter
1347 in use today with OpenOCD.
1348 That said, perhaps some of these config files
1349 have only been used by the developer who created it.
1351 A separate chapter gives information about how to set these up.
1352 @xref{Debug Adapter Configuration}.
1353 Read the OpenOCD source code (and Developer's Guide)
1354 if you have a new kind of hardware interface
1355 and need to provide a driver for it.
1357 @section Board Config Files
1358 @cindex config file, board
1359 @cindex board config file
1361 The user config file
1362 should be able to source one of these files with a command like this:
1365 source [find board/FOOBAR.cfg]
1368 The point of a board config file is to package everything
1369 about a given board that user config files need to know.
1370 In summary the board files should contain (if present)
1373 @item One or more @command{source [find target/...cfg]} statements
1374 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1375 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1376 @item Target @code{reset} handlers for SDRAM and I/O configuration
1377 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1378 @item All things that are not ``inside a chip''
1381 Generic things inside target chips belong in target config files,
1382 not board config files. So for example a @code{reset-init} event
1383 handler should know board-specific oscillator and PLL parameters,
1384 which it passes to target-specific utility code.
1386 The most complex task of a board config file is creating such a
1387 @code{reset-init} event handler.
1388 Define those handlers last, after you verify the rest of the board
1389 configuration works.
1391 @subsection Communication Between Config files
1393 In addition to target-specific utility code, another way that
1394 board and target config files communicate is by following a
1395 convention on how to use certain variables.
1397 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1398 Thus the rule we follow in OpenOCD is this: Variables that begin with
1399 a leading underscore are temporary in nature, and can be modified and
1400 used at will within a target configuration file.
1402 Complex board config files can do the things like this,
1403 for a board with three chips:
1406 # Chip #1: PXA270 for network side, big endian
1407 set CHIPNAME network
1409 source [find target/pxa270.cfg]
1410 # on return: _TARGETNAME = network.cpu
1411 # other commands can refer to the "network.cpu" target.
1412 $_TARGETNAME configure .... events for this CPU..
1414 # Chip #2: PXA270 for video side, little endian
1417 source [find target/pxa270.cfg]
1418 # on return: _TARGETNAME = video.cpu
1419 # other commands can refer to the "video.cpu" target.
1420 $_TARGETNAME configure .... events for this CPU..
1422 # Chip #3: Xilinx FPGA for glue logic
1425 source [find target/spartan3.cfg]
1428 That example is oversimplified because it doesn't show any flash memory,
1429 or the @code{reset-init} event handlers to initialize external DRAM
1430 or (assuming it needs it) load a configuration into the FPGA.
1431 Such features are usually needed for low-level work with many boards,
1432 where ``low level'' implies that the board initialization software may
1433 not be working. (That's a common reason to need JTAG tools. Another
1434 is to enable working with microcontroller-based systems, which often
1435 have no debugging support except a JTAG connector.)
1437 Target config files may also export utility functions to board and user
1438 config files. Such functions should use name prefixes, to help avoid
1441 Board files could also accept input variables from user config files.
1442 For example, there might be a @code{J4_JUMPER} setting used to identify
1443 what kind of flash memory a development board is using, or how to set
1444 up other clocks and peripherals.
1446 @subsection Variable Naming Convention
1447 @cindex variable names
1449 Most boards have only one instance of a chip.
1450 However, it should be easy to create a board with more than
1451 one such chip (as shown above).
1452 Accordingly, we encourage these conventions for naming
1453 variables associated with different @file{target.cfg} files,
1454 to promote consistency and
1455 so that board files can override target defaults.
1457 Inputs to target config files include:
1460 @item @code{CHIPNAME} ...
1461 This gives a name to the overall chip, and is used as part of
1462 tap identifier dotted names.
1463 While the default is normally provided by the chip manufacturer,
1464 board files may need to distinguish between instances of a chip.
1465 @item @code{ENDIAN} ...
1466 By default @option{little} - although chips may hard-wire @option{big}.
1467 Chips that can't change endianness don't need to use this variable.
1468 @item @code{CPUTAPID} ...
1469 When OpenOCD examines the JTAG chain, it can be told verify the
1470 chips against the JTAG IDCODE register.
1471 The target file will hold one or more defaults, but sometimes the
1472 chip in a board will use a different ID (perhaps a newer revision).
1475 Outputs from target config files include:
1478 @item @code{_TARGETNAME} ...
1479 By convention, this variable is created by the target configuration
1480 script. The board configuration file may make use of this variable to
1481 configure things like a ``reset init'' script, or other things
1482 specific to that board and that target.
1483 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1484 @code{_TARGETNAME1}, ... etc.
1487 @subsection The reset-init Event Handler
1488 @cindex event, reset-init
1489 @cindex reset-init handler
1491 Board config files run in the OpenOCD configuration stage;
1492 they can't use TAPs or targets, since they haven't been
1494 This means you can't write memory or access chip registers;
1495 you can't even verify that a flash chip is present.
1496 That's done later in event handlers, of which the target @code{reset-init}
1497 handler is one of the most important.
1499 Except on microcontrollers, the basic job of @code{reset-init} event
1500 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1501 Microcontrollers rarely use boot loaders; they run right out of their
1502 on-chip flash and SRAM memory. But they may want to use one of these
1503 handlers too, if just for developer convenience.
1506 Because this is so very board-specific, and chip-specific, no examples
1508 Instead, look at the board config files distributed with OpenOCD.
1509 If you have a boot loader, its source code will help; so will
1510 configuration files for other JTAG tools
1511 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1514 Some of this code could probably be shared between different boards.
1515 For example, setting up a DRAM controller often doesn't differ by
1516 much except the bus width (16 bits or 32?) and memory timings, so a
1517 reusable TCL procedure loaded by the @file{target.cfg} file might take
1518 those as parameters.
1519 Similarly with oscillator, PLL, and clock setup;
1520 and disabling the watchdog.
1521 Structure the code cleanly, and provide comments to help
1522 the next developer doing such work.
1523 (@emph{You might be that next person} trying to reuse init code!)
1525 The last thing normally done in a @code{reset-init} handler is probing
1526 whatever flash memory was configured. For most chips that needs to be
1527 done while the associated target is halted, either because JTAG memory
1528 access uses the CPU or to prevent conflicting CPU access.
1530 @subsection JTAG Clock Rate
1532 Before your @code{reset-init} handler has set up
1533 the PLLs and clocking, you may need to run with
1534 a low JTAG clock rate.
1535 @xref{jtagspeed,,JTAG Speed}.
1536 Then you'd increase that rate after your handler has
1537 made it possible to use the faster JTAG clock.
1538 When the initial low speed is board-specific, for example
1539 because it depends on a board-specific oscillator speed, then
1540 you should probably set it up in the board config file;
1541 if it's target-specific, it belongs in the target config file.
1543 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1544 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1545 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1546 Consult chip documentation to determine the peak JTAG clock rate,
1547 which might be less than that.
1550 On most ARMs, JTAG clock detection is coupled to the core clock, so
1551 software using a @option{wait for interrupt} operation blocks JTAG access.
1552 Adaptive clocking provides a partial workaround, but a more complete
1553 solution just avoids using that instruction with JTAG debuggers.
1556 If both the chip and the board support adaptive clocking,
1557 use the @command{jtag_rclk}
1558 command, in case your board is used with JTAG adapter which
1559 also supports it. Otherwise use @command{adapter_khz}.
1560 Set the slow rate at the beginning of the reset sequence,
1561 and the faster rate as soon as the clocks are at full speed.
1563 @anchor{theinitboardprocedure}
1564 @subsection The init_board procedure
1565 @cindex init_board procedure
1567 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1568 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1569 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1570 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1571 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1572 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1573 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1574 Additionally ``linear'' board config file will most likely fail when target config file uses
1575 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1576 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1577 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1578 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1580 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1581 the original), allowing greater code reuse.
1584 ### board_file.cfg ###
1586 # source target file that does most of the config in init_targets
1587 source [find target/target.cfg]
1589 proc enable_fast_clock @{@} @{
1590 # enables fast on-board clock source
1591 # configures the chip to use it
1594 # initialize only board specifics - reset, clock, adapter frequency
1595 proc init_board @{@} @{
1596 reset_config trst_and_srst trst_pulls_srst
1598 $_TARGETNAME configure -event reset-init @{
1606 @section Target Config Files
1607 @cindex config file, target
1608 @cindex target config file
1610 Board config files communicate with target config files using
1611 naming conventions as described above, and may source one or
1612 more target config files like this:
1615 source [find target/FOOBAR.cfg]
1618 The point of a target config file is to package everything
1619 about a given chip that board config files need to know.
1620 In summary the target files should contain
1624 @item Add TAPs to the scan chain
1625 @item Add CPU targets (includes GDB support)
1626 @item CPU/Chip/CPU-Core specific features
1630 As a rule of thumb, a target file sets up only one chip.
1631 For a microcontroller, that will often include a single TAP,
1632 which is a CPU needing a GDB target, and its on-chip flash.
1634 More complex chips may include multiple TAPs, and the target
1635 config file may need to define them all before OpenOCD
1636 can talk to the chip.
1637 For example, some phone chips have JTAG scan chains that include
1638 an ARM core for operating system use, a DSP,
1639 another ARM core embedded in an image processing engine,
1640 and other processing engines.
1642 @subsection Default Value Boiler Plate Code
1644 All target configuration files should start with code like this,
1645 letting board config files express environment-specific
1646 differences in how things should be set up.
1649 # Boards may override chip names, perhaps based on role,
1650 # but the default should match what the vendor uses
1651 if @{ [info exists CHIPNAME] @} @{
1652 set _CHIPNAME $CHIPNAME
1654 set _CHIPNAME sam7x256
1657 # ONLY use ENDIAN with targets that can change it.
1658 if @{ [info exists ENDIAN] @} @{
1664 # TAP identifiers may change as chips mature, for example with
1665 # new revision fields (the "3" here). Pick a good default; you
1666 # can pass several such identifiers to the "jtag newtap" command.
1667 if @{ [info exists CPUTAPID ] @} @{
1668 set _CPUTAPID $CPUTAPID
1670 set _CPUTAPID 0x3f0f0f0f
1673 @c but 0x3f0f0f0f is for an str73x part ...
1675 @emph{Remember:} Board config files may include multiple target
1676 config files, or the same target file multiple times
1677 (changing at least @code{CHIPNAME}).
1679 Likewise, the target configuration file should define
1680 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1681 use it later on when defining debug targets:
1684 set _TARGETNAME $_CHIPNAME.cpu
1685 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1688 @subsection Adding TAPs to the Scan Chain
1689 After the ``defaults'' are set up,
1690 add the TAPs on each chip to the JTAG scan chain.
1691 @xref{TAP Declaration}, and the naming convention
1694 In the simplest case the chip has only one TAP,
1695 probably for a CPU or FPGA.
1696 The config file for the Atmel AT91SAM7X256
1697 looks (in part) like this:
1700 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1703 A board with two such at91sam7 chips would be able
1704 to source such a config file twice, with different
1705 values for @code{CHIPNAME}, so
1706 it adds a different TAP each time.
1708 If there are nonzero @option{-expected-id} values,
1709 OpenOCD attempts to verify the actual tap id against those values.
1710 It will issue error messages if there is mismatch, which
1711 can help to pinpoint problems in OpenOCD configurations.
1714 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1715 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1716 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1717 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1718 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1721 There are more complex examples too, with chips that have
1722 multiple TAPs. Ones worth looking at include:
1725 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1726 plus a JRC to enable them
1727 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1728 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1729 is not currently used)
1732 @subsection Add CPU targets
1734 After adding a TAP for a CPU, you should set it up so that
1735 GDB and other commands can use it.
1736 @xref{CPU Configuration}.
1737 For the at91sam7 example above, the command can look like this;
1738 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1739 to little endian, and this chip doesn't support changing that.
1742 set _TARGETNAME $_CHIPNAME.cpu
1743 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1746 Work areas are small RAM areas associated with CPU targets.
1747 They are used by OpenOCD to speed up downloads,
1748 and to download small snippets of code to program flash chips.
1749 If the chip includes a form of ``on-chip-ram'' - and many do - define
1750 a work area if you can.
1751 Again using the at91sam7 as an example, this can look like:
1754 $_TARGETNAME configure -work-area-phys 0x00200000 \
1755 -work-area-size 0x4000 -work-area-backup 0
1758 @anchor{definecputargetsworkinginsmp}
1759 @subsection Define CPU targets working in SMP
1761 After setting targets, you can define a list of targets working in SMP.
1764 set _TARGETNAME_1 $_CHIPNAME.cpu1
1765 set _TARGETNAME_2 $_CHIPNAME.cpu2
1766 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1767 -coreid 0 -dbgbase $_DAP_DBG1
1768 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1769 -coreid 1 -dbgbase $_DAP_DBG2
1770 #define 2 targets working in smp.
1771 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1773 In the above example on cortex_a, 2 cpus are working in SMP.
1774 In SMP only one GDB instance is created and :
1776 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1777 @item halt command triggers the halt of all targets in the list.
1778 @item resume command triggers the write context and the restart of all targets in the list.
1779 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1780 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1781 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1784 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1785 command have been implemented.
1787 @item cortex_a smp_on : enable SMP mode, behaviour is as described above.
1788 @item cortex_a smp_off : disable SMP mode, the current target is the one
1789 displayed in the GDB session, only this target is now controlled by GDB
1790 session. This behaviour is useful during system boot up.
1791 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1798 #0 : coreid 0 is displayed to GDB ,
1799 #-> -1 : next resume triggers a real resume
1800 > cortex_a smp_gdb 1
1802 #0 :coreid 0 is displayed to GDB ,
1803 #->1 : next resume displays coreid 1 to GDB
1807 #1 :coreid 1 is displayed to GDB ,
1808 #->1 : next resume displays coreid 1 to GDB
1809 > cortex_a smp_gdb -1
1811 #1 :coreid 1 is displayed to GDB,
1812 #->-1 : next resume triggers a real resume
1816 @subsection Chip Reset Setup
1818 As a rule, you should put the @command{reset_config} command
1819 into the board file. Most things you think you know about a
1820 chip can be tweaked by the board.
1822 Some chips have specific ways the TRST and SRST signals are
1823 managed. In the unusual case that these are @emph{chip specific}
1824 and can never be changed by board wiring, they could go here.
1825 For example, some chips can't support JTAG debugging without
1828 Provide a @code{reset-assert} event handler if you can.
1829 Such a handler uses JTAG operations to reset the target,
1830 letting this target config be used in systems which don't
1831 provide the optional SRST signal, or on systems where you
1832 don't want to reset all targets at once.
1833 Such a handler might write to chip registers to force a reset,
1834 use a JRC to do that (preferable -- the target may be wedged!),
1835 or force a watchdog timer to trigger.
1836 (For Cortex-M targets, this is not necessary. The target
1837 driver knows how to use trigger an NVIC reset when SRST is
1840 Some chips need special attention during reset handling if
1841 they're going to be used with JTAG.
1842 An example might be needing to send some commands right
1843 after the target's TAP has been reset, providing a
1844 @code{reset-deassert-post} event handler that writes a chip
1845 register to report that JTAG debugging is being done.
1846 Another would be reconfiguring the watchdog so that it stops
1847 counting while the core is halted in the debugger.
1849 JTAG clocking constraints often change during reset, and in
1850 some cases target config files (rather than board config files)
1851 are the right places to handle some of those issues.
1852 For example, immediately after reset most chips run using a
1853 slower clock than they will use later.
1854 That means that after reset (and potentially, as OpenOCD
1855 first starts up) they must use a slower JTAG clock rate
1856 than they will use later.
1857 @xref{jtagspeed,,JTAG Speed}.
1859 @quotation Important
1860 When you are debugging code that runs right after chip
1861 reset, getting these issues right is critical.
1862 In particular, if you see intermittent failures when
1863 OpenOCD verifies the scan chain after reset,
1864 look at how you are setting up JTAG clocking.
1867 @anchor{theinittargetsprocedure}
1868 @subsection The init_targets procedure
1869 @cindex init_targets procedure
1871 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1872 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1873 procedure called @code{init_targets}, which will be executed when entering run stage
1874 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1875 Such procedure can be overriden by ``next level'' script (which sources the original).
1876 This concept faciliates code reuse when basic target config files provide generic configuration
1877 procedures and @code{init_targets} procedure, which can then be sourced and enchanced or changed in
1878 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1879 because sourcing them executes every initialization commands they provide.
1882 ### generic_file.cfg ###
1884 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1885 # basic initialization procedure ...
1888 proc init_targets @{@} @{
1889 # initializes generic chip with 4kB of flash and 1kB of RAM
1890 setup_my_chip MY_GENERIC_CHIP 4096 1024
1893 ### specific_file.cfg ###
1895 source [find target/generic_file.cfg]
1897 proc init_targets @{@} @{
1898 # initializes specific chip with 128kB of flash and 64kB of RAM
1899 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1903 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1904 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1906 For an example of this scheme see LPC2000 target config files.
1908 The @code{init_boards} procedure is a similar concept concerning board config files
1909 (@xref{theinitboardprocedure,,The init_board procedure}.)
1911 @anchor{theinittargeteventsprocedure}
1912 @subsection The init_target_events procedure
1913 @cindex init_target_events procedure
1915 A special procedure called @code{init_target_events} is run just after
1916 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1917 procedure}.) and before @code{init_board}
1918 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1919 to set up default target events for the targets that do not have those
1920 events already assigned.
1922 @subsection ARM Core Specific Hacks
1924 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1925 special high speed download features - enable it.
1927 If present, the MMU, the MPU and the CACHE should be disabled.
1929 Some ARM cores are equipped with trace support, which permits
1930 examination of the instruction and data bus activity. Trace
1931 activity is controlled through an ``Embedded Trace Module'' (ETM)
1932 on one of the core's scan chains. The ETM emits voluminous data
1933 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1934 If you are using an external trace port,
1935 configure it in your board config file.
1936 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1937 configure it in your target config file.
1940 etm config $_TARGETNAME 16 normal full etb
1941 etb config $_TARGETNAME $_CHIPNAME.etb
1944 @subsection Internal Flash Configuration
1946 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1948 @b{Never ever} in the ``target configuration file'' define any type of
1949 flash that is external to the chip. (For example a BOOT flash on
1950 Chip Select 0.) Such flash information goes in a board file - not
1951 the TARGET (chip) file.
1955 @item at91sam7x256 - has 256K flash YES enable it.
1956 @item str912 - has flash internal YES enable it.
1957 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1958 @item pxa270 - again - CS0 flash - it goes in the board file.
1961 @anchor{translatingconfigurationfiles}
1962 @section Translating Configuration Files
1964 If you have a configuration file for another hardware debugger
1965 or toolset (Abatron, BDI2000, BDI3000, CCS,
1966 Lauterbach, SEGGER, Macraigor, etc.), translating
1967 it into OpenOCD syntax is often quite straightforward. The most tricky
1968 part of creating a configuration script is oftentimes the reset init
1969 sequence where e.g. PLLs, DRAM and the like is set up.
1971 One trick that you can use when translating is to write small
1972 Tcl procedures to translate the syntax into OpenOCD syntax. This
1973 can avoid manual translation errors and make it easier to
1974 convert other scripts later on.
1976 Example of transforming quirky arguments to a simple search and
1980 # Lauterbach syntax(?)
1982 # Data.Set c15:0x042f %long 0x40000015
1984 # OpenOCD syntax when using procedure below.
1986 # setc15 0x01 0x00050078
1988 proc setc15 @{regs value@} @{
1991 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
1993 arm mcr 15 [expr ($regs>>12)&0x7] \
1994 [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
1995 [expr ($regs>>8)&0x7] $value
2001 @node Server Configuration
2002 @chapter Server Configuration
2003 @cindex initialization
2004 The commands here are commonly found in the openocd.cfg file and are
2005 used to specify what TCP/IP ports are used, and how GDB should be
2008 @anchor{configurationstage}
2009 @section Configuration Stage
2010 @cindex configuration stage
2011 @cindex config command
2013 When the OpenOCD server process starts up, it enters a
2014 @emph{configuration stage} which is the only time that
2015 certain commands, @emph{configuration commands}, may be issued.
2016 Normally, configuration commands are only available
2017 inside startup scripts.
2019 In this manual, the definition of a configuration command is
2020 presented as a @emph{Config Command}, not as a @emph{Command}
2021 which may be issued interactively.
2022 The runtime @command{help} command also highlights configuration
2023 commands, and those which may be issued at any time.
2025 Those configuration commands include declaration of TAPs,
2027 the interface used for JTAG communication,
2028 and other basic setup.
2029 The server must leave the configuration stage before it
2030 may access or activate TAPs.
2031 After it leaves this stage, configuration commands may no
2034 @anchor{enteringtherunstage}
2035 @section Entering the Run Stage
2037 The first thing OpenOCD does after leaving the configuration
2038 stage is to verify that it can talk to the scan chain
2039 (list of TAPs) which has been configured.
2040 It will warn if it doesn't find TAPs it expects to find,
2041 or finds TAPs that aren't supposed to be there.
2042 You should see no errors at this point.
2043 If you see errors, resolve them by correcting the
2044 commands you used to configure the server.
2045 Common errors include using an initial JTAG speed that's too
2046 fast, and not providing the right IDCODE values for the TAPs
2049 Once OpenOCD has entered the run stage, a number of commands
2051 A number of these relate to the debug targets you may have declared.
2052 For example, the @command{mww} command will not be available until
2053 a target has been successfuly instantiated.
2054 If you want to use those commands, you may need to force
2055 entry to the run stage.
2057 @deffn {Config Command} init
2058 This command terminates the configuration stage and
2059 enters the run stage. This helps when you need to have
2060 the startup scripts manage tasks such as resetting the target,
2061 programming flash, etc. To reset the CPU upon startup, add "init" and
2062 "reset" at the end of the config script or at the end of the OpenOCD
2063 command line using the @option{-c} command line switch.
2065 If this command does not appear in any startup/configuration file
2066 OpenOCD executes the command for you after processing all
2067 configuration files and/or command line options.
2069 @b{NOTE:} This command normally occurs at or near the end of your
2070 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2071 targets ready. For example: If your openocd.cfg file needs to
2072 read/write memory on your target, @command{init} must occur before
2073 the memory read/write commands. This includes @command{nand probe}.
2076 @deffn {Overridable Procedure} jtag_init
2077 This is invoked at server startup to verify that it can talk
2078 to the scan chain (list of TAPs) which has been configured.
2080 The default implementation first tries @command{jtag arp_init},
2081 which uses only a lightweight JTAG reset before examining the
2083 If that fails, it tries again, using a harder reset
2084 from the overridable procedure @command{init_reset}.
2086 Implementations must have verified the JTAG scan chain before
2088 This is done by calling @command{jtag arp_init}
2089 (or @command{jtag arp_init-reset}).
2093 @section TCP/IP Ports
2098 The OpenOCD server accepts remote commands in several syntaxes.
2099 Each syntax uses a different TCP/IP port, which you may specify
2100 only during configuration (before those ports are opened).
2102 For reasons including security, you may wish to prevent remote
2103 access using one or more of these ports.
2104 In such cases, just specify the relevant port number as "disabled".
2105 If you disable all access through TCP/IP, you will need to
2106 use the command line @option{-pipe} option.
2108 @deffn {Command} gdb_port [number]
2110 Normally gdb listens to a TCP/IP port, but GDB can also
2111 communicate via pipes(stdin/out or named pipes). The name
2112 "gdb_port" stuck because it covers probably more than 90% of
2113 the normal use cases.
2115 No arguments reports GDB port. "pipe" means listen to stdin
2116 output to stdout, an integer is base port number, "disabled"
2117 disables the gdb server.
2119 When using "pipe", also use log_output to redirect the log
2120 output to a file so as not to flood the stdin/out pipes.
2122 The -p/--pipe option is deprecated and a warning is printed
2123 as it is equivalent to passing in -c "gdb_port pipe; log_output openocd.log".
2125 Any other string is interpreted as named pipe to listen to.
2126 Output pipe is the same name as input pipe, but with 'o' appended,
2127 e.g. /var/gdb, /var/gdbo.
2129 The GDB port for the first target will be the base port, the
2130 second target will listen on gdb_port + 1, and so on.
2131 When not specified during the configuration stage,
2132 the port @var{number} defaults to 3333.
2134 Note: when using "gdb_port pipe", increasing the default remote timeout in
2135 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2136 cause initialization to fail with "Unknown remote qXfer reply: OK".
2140 @deffn {Command} tcl_port [number]
2141 Specify or query the port used for a simplified RPC
2142 connection that can be used by clients to issue TCL commands and get the
2143 output from the Tcl engine.
2144 Intended as a machine interface.
2145 When not specified during the configuration stage,
2146 the port @var{number} defaults to 6666.
2147 When specified as "disabled", this service is not activated.
2150 @deffn {Command} telnet_port [number]
2151 Specify or query the
2152 port on which to listen for incoming telnet connections.
2153 This port is intended for interaction with one human through TCL commands.
2154 When not specified during the configuration stage,
2155 the port @var{number} defaults to 4444.
2156 When specified as "disabled", this service is not activated.
2159 @anchor{gdbconfiguration}
2160 @section GDB Configuration
2162 @cindex GDB configuration
2163 You can reconfigure some GDB behaviors if needed.
2164 The ones listed here are static and global.
2165 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2166 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2168 @anchor{gdbbreakpointoverride}
2169 @deffn {Command} gdb_breakpoint_override [@option{hard}|@option{soft}|@option{disable}]
2170 Force breakpoint type for gdb @command{break} commands.
2171 This option supports GDB GUIs which don't
2172 distinguish hard versus soft breakpoints, if the default OpenOCD and
2173 GDB behaviour is not sufficient. GDB normally uses hardware
2174 breakpoints if the memory map has been set up for flash regions.
2177 @anchor{gdbflashprogram}
2178 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
2179 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2180 vFlash packet is received.
2181 The default behaviour is @option{enable}.
2184 @deffn {Config Command} gdb_memory_map (@option{enable}|@option{disable})
2185 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2186 requested. GDB will then know when to set hardware breakpoints, and program flash
2187 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2188 for flash programming to work.
2189 Default behaviour is @option{enable}.
2190 @xref{gdbflashprogram,,gdb_flash_program}.
2193 @deffn {Config Command} gdb_report_data_abort (@option{enable}|@option{disable})
2194 Specifies whether data aborts cause an error to be reported
2195 by GDB memory read packets.
2196 The default behaviour is @option{disable};
2197 use @option{enable} see these errors reported.
2200 @deffn {Config Command} gdb_target_description (@option{enable}|@option{disable})
2201 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2202 The default behaviour is @option{enable}.
2205 @deffn {Command} gdb_save_tdesc
2206 Saves the target descripton file to the local file system.
2208 The file name is @i{target_name}.xml.
2211 @anchor{eventpolling}
2212 @section Event Polling
2214 Hardware debuggers are parts of asynchronous systems,
2215 where significant events can happen at any time.
2216 The OpenOCD server needs to detect some of these events,
2217 so it can report them to through TCL command line
2220 Examples of such events include:
2223 @item One of the targets can stop running ... maybe it triggers
2224 a code breakpoint or data watchpoint, or halts itself.
2225 @item Messages may be sent over ``debug message'' channels ... many
2226 targets support such messages sent over JTAG,
2227 for receipt by the person debugging or tools.
2228 @item Loss of power ... some adapters can detect these events.
2229 @item Resets not issued through JTAG ... such reset sources
2230 can include button presses or other system hardware, sometimes
2231 including the target itself (perhaps through a watchdog).
2232 @item Debug instrumentation sometimes supports event triggering
2233 such as ``trace buffer full'' (so it can quickly be emptied)
2234 or other signals (to correlate with code behavior).
2237 None of those events are signaled through standard JTAG signals.
2238 However, most conventions for JTAG connectors include voltage
2239 level and system reset (SRST) signal detection.
2240 Some connectors also include instrumentation signals, which
2241 can imply events when those signals are inputs.
2243 In general, OpenOCD needs to periodically check for those events,
2244 either by looking at the status of signals on the JTAG connector
2245 or by sending synchronous ``tell me your status'' JTAG requests
2246 to the various active targets.
2247 There is a command to manage and monitor that polling,
2248 which is normally done in the background.
2250 @deffn Command poll [@option{on}|@option{off}]
2251 Poll the current target for its current state.
2252 (Also, @pxref{targetcurstate,,target curstate}.)
2253 If that target is in debug mode, architecture
2254 specific information about the current state is printed.
2255 An optional parameter
2256 allows background polling to be enabled and disabled.
2258 You could use this from the TCL command shell, or
2259 from GDB using @command{monitor poll} command.
2260 Leave background polling enabled while you're using GDB.
2263 background polling: on
2264 target state: halted
2265 target halted in ARM state due to debug-request, \
2266 current mode: Supervisor
2267 cpsr: 0x800000d3 pc: 0x11081bfc
2268 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2273 @node Debug Adapter Configuration
2274 @chapter Debug Adapter Configuration
2275 @cindex config file, interface
2276 @cindex interface config file
2278 Correctly installing OpenOCD includes making your operating system give
2279 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2280 are used to select which one is used, and to configure how it is used.
2283 Because OpenOCD started out with a focus purely on JTAG, you may find
2284 places where it wrongly presumes JTAG is the only transport protocol
2285 in use. Be aware that recent versions of OpenOCD are removing that
2286 limitation. JTAG remains more functional than most other transports.
2287 Other transports do not support boundary scan operations, or may be
2288 specific to a given chip vendor. Some might be usable only for
2289 programming flash memory, instead of also for debugging.
2292 Debug Adapters/Interfaces/Dongles are normally configured
2293 through commands in an interface configuration
2294 file which is sourced by your @file{openocd.cfg} file, or
2295 through a command line @option{-f interface/....cfg} option.
2298 source [find interface/olimex-jtag-tiny.cfg]
2302 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2303 A few cases are so simple that you only need to say what driver to use:
2310 Most adapters need a bit more configuration than that.
2313 @section Interface Configuration
2315 The interface command tells OpenOCD what type of debug adapter you are
2316 using. Depending on the type of adapter, you may need to use one or
2317 more additional commands to further identify or configure the adapter.
2319 @deffn {Config Command} {interface} name
2320 Use the interface driver @var{name} to connect to the
2324 @deffn Command {interface_list}
2325 List the debug adapter drivers that have been built into
2326 the running copy of OpenOCD.
2328 @deffn Command {interface transports} transport_name+
2329 Specifies the transports supported by this debug adapter.
2330 The adapter driver builds-in similar knowledge; use this only
2331 when external configuration (such as jumpering) changes what
2332 the hardware can support.
2337 @deffn Command {adapter_name}
2338 Returns the name of the debug adapter driver being used.
2341 @section Interface Drivers
2343 Each of the interface drivers listed here must be explicitly
2344 enabled when OpenOCD is configured, in order to be made
2345 available at run time.
2347 @deffn {Interface Driver} {amt_jtagaccel}
2348 Amontec Chameleon in its JTAG Accelerator configuration,
2349 connected to a PC's EPP mode parallel port.
2350 This defines some driver-specific commands:
2352 @deffn {Config Command} {parport_port} number
2353 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2354 the number of the @file{/dev/parport} device.
2357 @deffn {Config Command} rtck [@option{enable}|@option{disable}]
2358 Displays status of RTCK option.
2359 Optionally sets that option first.
2363 @deffn {Interface Driver} {arm-jtag-ew}
2364 Olimex ARM-JTAG-EW USB adapter
2365 This has one driver-specific command:
2367 @deffn Command {armjtagew_info}
2372 @deffn {Interface Driver} {at91rm9200}
2373 Supports bitbanged JTAG from the local system,
2374 presuming that system is an Atmel AT91rm9200
2375 and a specific set of GPIOs is used.
2376 @c command: at91rm9200_device NAME
2377 @c chooses among list of bit configs ... only one option
2380 @deffn {Interface Driver} {cmsis-dap}
2381 ARM CMSIS-DAP compliant based adapter.
2383 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2384 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2385 the driver will attempt to auto detect the CMSIS-DAP device.
2386 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2388 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2392 @deffn {Config Command} {cmsis_dap_serial} [serial]
2393 Specifies the @var{serial} of the CMSIS-DAP device to use.
2394 If not specified, serial numbers are not considered.
2397 @deffn {Command} {cmsis-dap info}
2398 Display various device information, like hardware version, firmware version, current bus status.
2402 @deffn {Interface Driver} {dummy}
2403 A dummy software-only driver for debugging.
2406 @deffn {Interface Driver} {ep93xx}
2407 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2410 @deffn {Interface Driver} {ftdi}
2411 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2412 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2414 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2415 bypassing intermediate libraries like libftdi or D2XX.
2417 Support for new FTDI based adapters can be added competely through
2418 configuration files, without the need to patch and rebuild OpenOCD.
2420 The driver uses a signal abstraction to enable Tcl configuration files to
2421 define outputs for one or several FTDI GPIO. These outputs can then be
2422 controlled using the @command{ftdi_set_signal} command. Special signal names
2423 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2424 will be used for their customary purpose. Inputs can be read using the
2425 @command{ftdi_get_signal} command.
2427 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2428 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2429 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2430 required by the protocol, to tell the adapter to drive the data output onto
2431 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2433 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2434 be controlled differently. In order to support tristateable signals such as
2435 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2436 signal. The following output buffer configurations are supported:
2439 @item Push-pull with one FTDI output as (non-)inverted data line
2440 @item Open drain with one FTDI output as (non-)inverted output-enable
2441 @item Tristate with one FTDI output as (non-)inverted data line and another
2442 FTDI output as (non-)inverted output-enable
2443 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2444 switching data and direction as necessary
2447 These interfaces have several commands, used to configure the driver
2448 before initializing the JTAG scan chain:
2450 @deffn {Config Command} {ftdi_vid_pid} [vid pid]+
2451 The vendor ID and product ID of the adapter. Up to eight
2452 [@var{vid}, @var{pid}] pairs may be given, e.g.
2454 ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003
2458 @deffn {Config Command} {ftdi_device_desc} description
2459 Provides the USB device description (the @emph{iProduct string})
2460 of the adapter. If not specified, the device description is ignored
2461 during device selection.
2464 @deffn {Config Command} {ftdi_serial} serial-number
2465 Specifies the @var{serial-number} of the adapter to use,
2466 in case the vendor provides unique IDs and more than one adapter
2467 is connected to the host.
2468 If not specified, serial numbers are not considered.
2469 (Note that USB serial numbers can be arbitrary Unicode strings,
2470 and are not restricted to containing only decimal digits.)
2473 @deffn {Config Command} {ftdi_location} <bus>:<port>[,<port>]...
2474 Specifies the physical USB port of the adapter to use. The path
2475 roots at @var{bus} and walks down the physical ports, with each
2476 @var{port} option specifying a deeper level in the bus topology, the last
2477 @var{port} denoting where the target adapter is actually plugged.
2478 The USB bus topology can be queried with the command @emph{lsusb -t}.
2480 This command is only available if your libusb1 is at least version 1.0.16.
2483 @deffn {Config Command} {ftdi_channel} channel
2484 Selects the channel of the FTDI device to use for MPSSE operations. Most
2485 adapters use the default, channel 0, but there are exceptions.
2488 @deffn {Config Command} {ftdi_layout_init} data direction
2489 Specifies the initial values of the FTDI GPIO data and direction registers.
2490 Each value is a 16-bit number corresponding to the concatenation of the high
2491 and low FTDI GPIO registers. The values should be selected based on the
2492 schematics of the adapter, such that all signals are set to safe levels with
2493 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2494 and initially asserted reset signals.
2497 @deffn {Config Command} {ftdi_layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2498 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2499 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2500 register bitmasks to tell the driver the connection and type of the output
2501 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2502 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2503 used with inverting data inputs and @option{-data} with non-inverting inputs.
2504 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2505 not-output-enable) input to the output buffer is connected. The options
2506 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2507 with the method @command{ftdi_get_signal}.
2509 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2510 simple open-collector transistor driver would be specified with @option{-oe}
2511 only. In that case the signal can only be set to drive low or to Hi-Z and the
2512 driver will complain if the signal is set to drive high. Which means that if
2513 it's a reset signal, @command{reset_config} must be specified as
2514 @option{srst_open_drain}, not @option{srst_push_pull}.
2516 A special case is provided when @option{-data} and @option{-oe} is set to the
2517 same bitmask. Then the FTDI pin is considered being connected straight to the
2518 target without any buffer. The FTDI pin is then switched between output and
2519 input as necessary to provide the full set of low, high and Hi-Z
2520 characteristics. In all other cases, the pins specified in a signal definition
2521 are always driven by the FTDI.
2523 If @option{-alias} or @option{-nalias} is used, the signal is created
2524 identical (or with data inverted) to an already specified signal
2528 @deffn {Command} {ftdi_set_signal} name @option{0}|@option{1}|@option{z}
2529 Set a previously defined signal to the specified level.
2531 @item @option{0}, drive low
2532 @item @option{1}, drive high
2533 @item @option{z}, set to high-impedance
2537 @deffn {Command} {ftdi_get_signal} name
2538 Get the value of a previously defined signal.
2541 @deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
2542 Configure TCK edge at which the adapter samples the value of the TDO signal
2544 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2545 peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
2546 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2547 stability at higher JTAG clocks.
2549 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2550 @item @option{falling}, sample TDO on falling edge of TCK
2554 For example adapter definitions, see the configuration files shipped in the
2555 @file{interface/ftdi} directory.
2559 @deffn {Interface Driver} {remote_bitbang}
2560 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2561 with a remote process and sends ASCII encoded bitbang requests to that process
2562 instead of directly driving JTAG.
2564 The remote_bitbang driver is useful for debugging software running on
2565 processors which are being simulated.
2567 @deffn {Config Command} {remote_bitbang_port} number
2568 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2569 sockets instead of TCP.
2572 @deffn {Config Command} {remote_bitbang_host} hostname
2573 Specifies the hostname of the remote process to connect to using TCP, or the
2574 name of the UNIX socket to use if remote_bitbang_port is 0.
2577 For example, to connect remotely via TCP to the host foobar you might have
2581 interface remote_bitbang
2582 remote_bitbang_port 3335
2583 remote_bitbang_host foobar
2586 To connect to another process running locally via UNIX sockets with socket
2590 interface remote_bitbang
2591 remote_bitbang_port 0
2592 remote_bitbang_host mysocket
2596 @deffn {Interface Driver} {usb_blaster}
2597 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2598 for FTDI chips. These interfaces have several commands, used to
2599 configure the driver before initializing the JTAG scan chain:
2601 @deffn {Config Command} {usb_blaster_device_desc} description
2602 Provides the USB device description (the @emph{iProduct string})
2603 of the FTDI FT245 device. If not
2604 specified, the FTDI default value is used. This setting is only valid
2605 if compiled with FTD2XX support.
2608 @deffn {Config Command} {usb_blaster_vid_pid} vid pid
2609 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2610 default values are used.
2611 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2612 Altera USB-Blaster (default):
2614 usb_blaster_vid_pid 0x09FB 0x6001
2616 The following VID/PID is for Kolja Waschk's USB JTAG:
2618 usb_blaster_vid_pid 0x16C0 0x06AD
2622 @deffn {Command} {usb_blaster_pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2623 Sets the state or function of the unused GPIO pins on USB-Blasters
2624 (pins 6 and 8 on the female JTAG header). These pins can be used as
2625 SRST and/or TRST provided the appropriate connections are made on the
2628 For example, to use pin 6 as SRST:
2630 usb_blaster_pin pin6 s
2631 reset_config srst_only
2635 @deffn {Command} {usb_blaster_lowlevel_driver} (@option{ftdi}|@option{ublast2})
2636 Chooses the low level access method for the adapter. If not specified,
2637 @option{ftdi} is selected unless it wasn't enabled during the
2638 configure stage. USB-Blaster II needs @option{ublast2}.
2641 @deffn {Command} {usb_blaster_firmware} @var{path}
2642 This command specifies @var{path} to access USB-Blaster II firmware
2643 image. To be used with USB-Blaster II only.
2648 @deffn {Interface Driver} {gw16012}
2649 Gateworks GW16012 JTAG programmer.
2650 This has one driver-specific command:
2652 @deffn {Config Command} {parport_port} [port_number]
2653 Display either the address of the I/O port
2654 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2655 If a parameter is provided, first switch to use that port.
2656 This is a write-once setting.
2660 @deffn {Interface Driver} {jlink}
2661 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2664 @quotation Compatibility Note
2665 SEGGER released many firmware versions for the many harware versions they
2666 produced. OpenOCD was extensively tested and intended to run on all of them,
2667 but some combinations were reported as incompatible. As a general
2668 recommendation, it is advisable to use the latest firmware version
2669 available for each hardware version. However the current V8 is a moving
2670 target, and SEGGER firmware versions released after the OpenOCD was
2671 released may not be compatible. In such cases it is recommended to
2672 revert to the last known functional version. For 0.5.0, this is from
2673 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2674 version is from "May 3 2012 18:36:22", packed with 4.46f.
2677 @deffn {Command} {jlink hwstatus}
2678 Display various hardware related information, for example target voltage and pin
2681 @deffn {Command} {jlink freemem}
2682 Display free device internal memory.
2684 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2685 Set the JTAG command version to be used. Without argument, show the actual JTAG
2688 @deffn {Command} {jlink config}
2689 Display the device configuration.
2691 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2692 Set the target power state on JTAG-pin 19. Without argument, show the target
2695 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2696 Set the MAC address of the device. Without argument, show the MAC address.
2698 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2699 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2700 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2703 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2704 Set the USB address of the device. This will also change the USB Product ID
2705 (PID) of the device. Without argument, show the USB address.
2707 @deffn {Command} {jlink config reset}
2708 Reset the current configuration.
2710 @deffn {Command} {jlink config write}
2711 Write the current configuration to the internal persistent storage.
2713 @deffn {Command} {jlink emucom write <channel> <data>}
2714 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2717 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2718 the EMUCOM channel 0x10:
2720 > jlink emucom write 0x10 aa0b23
2723 @deffn {Command} {jlink emucom read <channel> <length>}
2724 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2727 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2729 > jlink emucom read 0x0 4
2733 @deffn {Config} {jlink usb} <@option{0} to @option{3}>
2734 Set the USB address of the interface, in case more than one adapter is connected
2735 to the host. If not specified, USB addresses are not considered. Device
2736 selection via USB address is deprecated and the serial number should be used
2739 As a configuration command, it can be used only before 'init'.
2741 @deffn {Config} {jlink serial} <serial number>
2742 Set the serial number of the interface, in case more than one adapter is
2743 connected to the host. If not specified, serial numbers are not considered.
2745 As a configuration command, it can be used only before 'init'.
2749 @deffn {Interface Driver} {kitprog}
2750 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2751 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2752 families, but it is possible to use it with some other devices. If you are using
2753 this adapter with a PSoC or a PRoC, you may need to add
2754 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2755 configuration script.
2757 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2758 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2759 be used with this driver, and must either be used with the cmsis-dap driver or
2760 switched back to KitProg mode. See the Cypress KitProg User Guide for
2761 instructions on how to switch KitProg modes.
2765 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2767 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2768 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2769 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2770 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2771 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2772 SWD sequence must be sent after every target reset in order to re-establish
2773 communications with the target.
2774 @item Due in part to the limitation above, KitProg devices with firmware below
2775 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2776 communicate with PSoC 5LP devices. This is because, assuming debug is not
2777 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2778 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2779 could only be sent with an acquisition sequence.
2782 @deffn {Config Command} {kitprog_init_acquire_psoc}
2783 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2784 Please be aware that the acquisition sequence hard-resets the target.
2787 @deffn {Config Command} {kitprog_serial} serial
2788 Select a KitProg device by its @var{serial}. If left unspecified, the first
2789 device detected by OpenOCD will be used.
2792 @deffn {Command} {kitprog acquire_psoc}
2793 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2794 outside of the target-specific configuration scripts since it hard-resets the
2795 target as a side-effect.
2796 This is necessary for "reset halt" on some PSoC 4 series devices.
2799 @deffn {Command} {kitprog info}
2800 Display various adapter information, such as the hardware version, firmware
2801 version, and target voltage.
2805 @deffn {Interface Driver} {parport}
2806 Supports PC parallel port bit-banging cables:
2807 Wigglers, PLD download cable, and more.
2808 These interfaces have several commands, used to configure the driver
2809 before initializing the JTAG scan chain:
2811 @deffn {Config Command} {parport_cable} name
2812 Set the layout of the parallel port cable used to connect to the target.
2813 This is a write-once setting.
2814 Currently valid cable @var{name} values include:
2817 @item @b{altium} Altium Universal JTAG cable.
2818 @item @b{arm-jtag} Same as original wiggler except SRST and
2819 TRST connections reversed and TRST is also inverted.
2820 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2821 in configuration mode. This is only used to
2822 program the Chameleon itself, not a connected target.
2823 @item @b{dlc5} The Xilinx Parallel cable III.
2824 @item @b{flashlink} The ST Parallel cable.
2825 @item @b{lattice} Lattice ispDOWNLOAD Cable
2826 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2828 Amontec's Chameleon Programmer. The new version available from
2829 the website uses the original Wiggler layout ('@var{wiggler}')
2830 @item @b{triton} The parallel port adapter found on the
2831 ``Karo Triton 1 Development Board''.
2832 This is also the layout used by the HollyGates design
2833 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
2834 @item @b{wiggler} The original Wiggler layout, also supported by
2835 several clones, such as the Olimex ARM-JTAG
2836 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
2837 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
2841 @deffn {Config Command} {parport_port} [port_number]
2842 Display either the address of the I/O port
2843 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2844 If a parameter is provided, first switch to use that port.
2845 This is a write-once setting.
2847 When using PPDEV to access the parallel port, use the number of the parallel port:
2848 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
2849 you may encounter a problem.
2852 @deffn Command {parport_toggling_time} [nanoseconds]
2853 Displays how many nanoseconds the hardware needs to toggle TCK;
2854 the parport driver uses this value to obey the
2855 @command{adapter_khz} configuration.
2856 When the optional @var{nanoseconds} parameter is given,
2857 that setting is changed before displaying the current value.
2859 The default setting should work reasonably well on commodity PC hardware.
2860 However, you may want to calibrate for your specific hardware.
2862 To measure the toggling time with a logic analyzer or a digital storage
2863 oscilloscope, follow the procedure below:
2865 > parport_toggling_time 1000
2868 This sets the maximum JTAG clock speed of the hardware, but
2869 the actual speed probably deviates from the requested 500 kHz.
2870 Now, measure the time between the two closest spaced TCK transitions.
2871 You can use @command{runtest 1000} or something similar to generate a
2872 large set of samples.
2873 Update the setting to match your measurement:
2875 > parport_toggling_time <measured nanoseconds>
2877 Now the clock speed will be a better match for @command{adapter_khz rate}
2878 commands given in OpenOCD scripts and event handlers.
2880 You can do something similar with many digital multimeters, but note
2881 that you'll probably need to run the clock continuously for several
2882 seconds before it decides what clock rate to show. Adjust the
2883 toggling time up or down until the measured clock rate is a good
2884 match for the adapter_khz rate you specified; be conservative.
2888 @deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
2889 This will configure the parallel driver to write a known
2890 cable-specific value to the parallel interface on exiting OpenOCD.
2893 For example, the interface configuration file for a
2894 classic ``Wiggler'' cable on LPT2 might look something like this:
2899 parport_cable wiggler
2903 @deffn {Interface Driver} {presto}
2904 ASIX PRESTO USB JTAG programmer.
2905 @deffn {Config Command} {presto_serial} serial_string
2906 Configures the USB serial number of the Presto device to use.
2910 @deffn {Interface Driver} {rlink}
2911 Raisonance RLink USB adapter
2914 @deffn {Interface Driver} {usbprog}
2915 usbprog is a freely programmable USB adapter.
2918 @deffn {Interface Driver} {vsllink}
2919 vsllink is part of Versaloon which is a versatile USB programmer.
2922 This defines quite a few driver-specific commands,
2923 which are not currently documented here.
2927 @anchor{hla_interface}
2928 @deffn {Interface Driver} {hla}
2929 This is a driver that supports multiple High Level Adapters.
2930 This type of adapter does not expose some of the lower level api's
2931 that OpenOCD would normally use to access the target.
2933 Currently supported adapters include the ST STLINK and TI ICDI.
2934 STLINK firmware version >= V2.J21.S4 recommended due to issues with earlier
2935 versions of firmware where serial number is reset after first use. Suggest
2936 using ST firmware update utility to upgrade STLINK firmware even if current
2937 version reported is V2.J21.S4.
2939 @deffn {Config Command} {hla_device_desc} description
2940 Currently Not Supported.
2943 @deffn {Config Command} {hla_serial} serial
2944 Specifies the serial number of the adapter.
2947 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
2948 Specifies the adapter layout to use.
2951 @deffn {Config Command} {hla_vid_pid} [vid pid]+
2952 Pairs of vendor IDs and product IDs of the device.
2955 @deffn {Command} {hla_command} command
2956 Execute a custom adapter-specific command. The @var{command} string is
2957 passed as is to the underlying adapter layout handler.
2961 @deffn {Interface Driver} {opendous}
2962 opendous-jtag is a freely programmable USB adapter.
2965 @deffn {Interface Driver} {ulink}
2966 This is the Keil ULINK v1 JTAG debugger.
2969 @deffn {Interface Driver} {ZY1000}
2970 This is the Zylin ZY1000 JTAG debugger.
2974 This defines some driver-specific commands,
2975 which are not currently documented here.
2978 @deffn Command power [@option{on}|@option{off}]
2979 Turn power switch to target on/off.
2980 No arguments: print status.
2983 @deffn {Interface Driver} {bcm2835gpio}
2984 This SoC is present in Raspberry Pi which is a cheap single-board computer
2985 exposing some GPIOs on its expansion header.
2987 The driver accesses memory-mapped GPIO peripheral registers directly
2988 for maximum performance, but the only possible race condition is for
2989 the pins' modes/muxing (which is highly unlikely), so it should be
2990 able to coexist nicely with both sysfs bitbanging and various
2991 peripherals' kernel drivers. The driver restores the previous
2992 configuration on exit.
2994 See @file{interface/raspberrypi-native.cfg} for a sample config and
2999 @deffn {Interface Driver} {imx_gpio}
3000 i.MX SoC is present in many community boards. Wandboard is an example
3001 of the one which is most popular.
3003 This driver is mostly the same as bcm2835gpio.
3005 See @file{interface/imx-native.cfg} for a sample config and
3011 @deffn {Interface Driver} {openjtag}
3012 OpenJTAG compatible USB adapter.
3013 This defines some driver-specific commands:
3015 @deffn {Config Command} {openjtag_variant} variant
3016 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3017 Currently valid @var{variant} values include:
3020 @item @b{standard} Standard variant (default).
3021 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3022 (see @uref{http://www.cypress.com/?rID=82870}).
3026 @deffn {Config Command} {openjtag_device_desc} string
3027 The USB device description string of the adapter.
3028 This value is only used with the standard variant.
3032 @section Transport Configuration
3034 As noted earlier, depending on the version of OpenOCD you use,
3035 and the debug adapter you are using,
3036 several transports may be available to
3037 communicate with debug targets (or perhaps to program flash memory).
3038 @deffn Command {transport list}
3039 displays the names of the transports supported by this
3043 @deffn Command {transport select} @option{transport_name}
3044 Select which of the supported transports to use in this OpenOCD session.
3046 When invoked with @option{transport_name}, attempts to select the named
3047 transport. The transport must be supported by the debug adapter
3048 hardware and by the version of OpenOCD you are using (including the
3051 If no transport has been selected and no @option{transport_name} is
3052 provided, @command{transport select} auto-selects the first transport
3053 supported by the debug adapter.
3055 @command{transport select} always returns the name of the session's selected
3059 @subsection JTAG Transport
3061 JTAG is the original transport supported by OpenOCD, and most
3062 of the OpenOCD commands support it.
3063 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3064 each of which must be explicitly declared.
3065 JTAG supports both debugging and boundary scan testing.
3066 Flash programming support is built on top of debug support.
3068 JTAG transport is selected with the command @command{transport select
3069 jtag}. Unless your adapter uses @ref{hla_interface,the hla interface
3070 driver}, in which case the command is @command{transport select
3073 @subsection SWD Transport
3075 @cindex Serial Wire Debug
3076 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3077 Debug Access Point (DAP, which must be explicitly declared.
3078 (SWD uses fewer signal wires than JTAG.)
3079 SWD is debug-oriented, and does not support boundary scan testing.
3080 Flash programming support is built on top of debug support.
3081 (Some processors support both JTAG and SWD.)
3083 SWD transport is selected with the command @command{transport select
3084 swd}. Unless your adapter uses @ref{hla_interface,the hla interface
3085 driver}, in which case the command is @command{transport select
3088 @deffn Command {swd newdap} ...
3089 Declares a single DAP which uses SWD transport.
3090 Parameters are currently the same as "jtag newtap" but this is
3093 @deffn Command {swd wcr trn prescale}
3094 Updates TRN (turnaraound delay) and prescaling.fields of the
3095 Wire Control Register (WCR).
3096 No parameters: displays current settings.
3099 @subsection SPI Transport
3101 @cindex Serial Peripheral Interface
3102 The Serial Peripheral Interface (SPI) is a general purpose transport
3103 which uses four wire signaling. Some processors use it as part of a
3104 solution for flash programming.
3108 JTAG clock setup is part of system setup.
3109 It @emph{does not belong with interface setup} since any interface
3110 only knows a few of the constraints for the JTAG clock speed.
3111 Sometimes the JTAG speed is
3112 changed during the target initialization process: (1) slow at
3113 reset, (2) program the CPU clocks, (3) run fast.
3114 Both the "slow" and "fast" clock rates are functions of the
3115 oscillators used, the chip, the board design, and sometimes
3116 power management software that may be active.
3118 The speed used during reset, and the scan chain verification which
3119 follows reset, can be adjusted using a @code{reset-start}
3120 target event handler.
3121 It can then be reconfigured to a faster speed by a
3122 @code{reset-init} target event handler after it reprograms those
3123 CPU clocks, or manually (if something else, such as a boot loader,
3124 sets up those clocks).
3125 @xref{targetevents,,Target Events}.
3126 When the initial low JTAG speed is a chip characteristic, perhaps
3127 because of a required oscillator speed, provide such a handler
3128 in the target config file.
3129 When that speed is a function of a board-specific characteristic
3130 such as which speed oscillator is used, it belongs in the board
3131 config file instead.
3132 In both cases it's safest to also set the initial JTAG clock rate
3133 to that same slow speed, so that OpenOCD never starts up using a
3134 clock speed that's faster than the scan chain can support.
3138 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3141 If your system supports adaptive clocking (RTCK), configuring
3142 JTAG to use that is probably the most robust approach.
3143 However, it introduces delays to synchronize clocks; so it
3144 may not be the fastest solution.
3146 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3147 instead of @command{adapter_khz}, but only for (ARM) cores and boards
3148 which support adaptive clocking.
3150 @deffn {Command} adapter_khz max_speed_kHz
3151 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3152 JTAG interfaces usually support a limited number of
3153 speeds. The speed actually used won't be faster
3154 than the speed specified.
3156 Chip data sheets generally include a top JTAG clock rate.
3157 The actual rate is often a function of a CPU core clock,
3158 and is normally less than that peak rate.
3159 For example, most ARM cores accept at most one sixth of the CPU clock.
3161 Speed 0 (khz) selects RTCK method.
3162 @xref{faqrtck,,FAQ RTCK}.
3163 If your system uses RTCK, you won't need to change the
3164 JTAG clocking after setup.
3165 Not all interfaces, boards, or targets support ``rtck''.
3166 If the interface device can not
3167 support it, an error is returned when you try to use RTCK.
3170 @defun jtag_rclk fallback_speed_kHz
3171 @cindex adaptive clocking
3173 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3174 If that fails (maybe the interface, board, or target doesn't
3175 support it), falls back to the specified frequency.
3177 # Fall back to 3mhz if RTCK is not supported
3182 @node Reset Configuration
3183 @chapter Reset Configuration
3184 @cindex Reset Configuration
3186 Every system configuration may require a different reset
3187 configuration. This can also be quite confusing.
3188 Resets also interact with @var{reset-init} event handlers,
3189 which do things like setting up clocks and DRAM, and
3190 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3191 They can also interact with JTAG routers.
3192 Please see the various board files for examples.
3195 To maintainers and integrators:
3196 Reset configuration touches several things at once.
3197 Normally the board configuration file
3198 should define it and assume that the JTAG adapter supports
3199 everything that's wired up to the board's JTAG connector.
3201 However, the target configuration file could also make note
3202 of something the silicon vendor has done inside the chip,
3203 which will be true for most (or all) boards using that chip.
3204 And when the JTAG adapter doesn't support everything, the
3205 user configuration file will need to override parts of
3206 the reset configuration provided by other files.
3209 @section Types of Reset
3211 There are many kinds of reset possible through JTAG, but
3212 they may not all work with a given board and adapter.
3213 That's part of why reset configuration can be error prone.
3217 @emph{System Reset} ... the @emph{SRST} hardware signal
3218 resets all chips connected to the JTAG adapter, such as processors,
3219 power management chips, and I/O controllers. Normally resets triggered
3220 with this signal behave exactly like pressing a RESET button.
3222 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3223 just the TAP controllers connected to the JTAG adapter.
3224 Such resets should not be visible to the rest of the system; resetting a
3225 device's TAP controller just puts that controller into a known state.
3227 @emph{Emulation Reset} ... many devices can be reset through JTAG
3228 commands. These resets are often distinguishable from system
3229 resets, either explicitly (a "reset reason" register says so)
3230 or implicitly (not all parts of the chip get reset).
3232 @emph{Other Resets} ... system-on-chip devices often support
3233 several other types of reset.
3234 You may need to arrange that a watchdog timer stops
3235 while debugging, preventing a watchdog reset.
3236 There may be individual module resets.
3239 In the best case, OpenOCD can hold SRST, then reset
3240 the TAPs via TRST and send commands through JTAG to halt the
3241 CPU at the reset vector before the 1st instruction is executed.
3242 Then when it finally releases the SRST signal, the system is
3243 halted under debugger control before any code has executed.
3244 This is the behavior required to support the @command{reset halt}
3245 and @command{reset init} commands; after @command{reset init} a
3246 board-specific script might do things like setting up DRAM.
3247 (@xref{resetcommand,,Reset Command}.)
3249 @anchor{srstandtrstissues}
3250 @section SRST and TRST Issues
3252 Because SRST and TRST are hardware signals, they can have a
3253 variety of system-specific constraints. Some of the most
3258 @item @emph{Signal not available} ... Some boards don't wire
3259 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3260 support such signals even if they are wired up.
3261 Use the @command{reset_config} @var{signals} options to say
3262 when either of those signals is not connected.
3263 When SRST is not available, your code might not be able to rely
3264 on controllers having been fully reset during code startup.
3265 Missing TRST is not a problem, since JTAG-level resets can
3266 be triggered using with TMS signaling.
3268 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3269 adapter will connect SRST to TRST, instead of keeping them separate.
3270 Use the @command{reset_config} @var{combination} options to say
3271 when those signals aren't properly independent.
3273 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3274 delay circuit, reset supervisor, or on-chip features can extend
3275 the effect of a JTAG adapter's reset for some time after the adapter
3276 stops issuing the reset. For example, there may be chip or board
3277 requirements that all reset pulses last for at least a
3278 certain amount of time; and reset buttons commonly have
3279 hardware debouncing.
3280 Use the @command{adapter_nsrst_delay} and @command{jtag_ntrst_delay}
3281 commands to say when extra delays are needed.
3283 @item @emph{Drive type} ... Reset lines often have a pullup
3284 resistor, letting the JTAG interface treat them as open-drain
3285 signals. But that's not a requirement, so the adapter may need
3286 to use push/pull output drivers.
3287 Also, with weak pullups it may be advisable to drive
3288 signals to both levels (push/pull) to minimize rise times.
3289 Use the @command{reset_config} @var{trst_type} and
3290 @var{srst_type} parameters to say how to drive reset signals.
3292 @item @emph{Special initialization} ... Targets sometimes need
3293 special JTAG initialization sequences to handle chip-specific
3294 issues (not limited to errata).
3295 For example, certain JTAG commands might need to be issued while
3296 the system as a whole is in a reset state (SRST active)
3297 but the JTAG scan chain is usable (TRST inactive).
3298 Many systems treat combined assertion of SRST and TRST as a
3299 trigger for a harder reset than SRST alone.
3300 Such custom reset handling is discussed later in this chapter.
3303 There can also be other issues.
3304 Some devices don't fully conform to the JTAG specifications.
3305 Trivial system-specific differences are common, such as
3306 SRST and TRST using slightly different names.
3307 There are also vendors who distribute key JTAG documentation for
3308 their chips only to developers who have signed a Non-Disclosure
3311 Sometimes there are chip-specific extensions like a requirement to use
3312 the normally-optional TRST signal (precluding use of JTAG adapters which
3313 don't pass TRST through), or needing extra steps to complete a TAP reset.
3315 In short, SRST and especially TRST handling may be very finicky,
3316 needing to cope with both architecture and board specific constraints.
3318 @section Commands for Handling Resets
3320 @deffn {Command} adapter_nsrst_assert_width milliseconds
3321 Minimum amount of time (in milliseconds) OpenOCD should wait
3322 after asserting nSRST (active-low system reset) before
3323 allowing it to be deasserted.
3326 @deffn {Command} adapter_nsrst_delay milliseconds
3327 How long (in milliseconds) OpenOCD should wait after deasserting
3328 nSRST (active-low system reset) before starting new JTAG operations.
3329 When a board has a reset button connected to SRST line it will
3330 probably have hardware debouncing, implying you should use this.
3333 @deffn {Command} jtag_ntrst_assert_width milliseconds
3334 Minimum amount of time (in milliseconds) OpenOCD should wait
3335 after asserting nTRST (active-low JTAG TAP reset) before
3336 allowing it to be deasserted.
3339 @deffn {Command} jtag_ntrst_delay milliseconds
3340 How long (in milliseconds) OpenOCD should wait after deasserting
3341 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3344 @deffn {Command} reset_config mode_flag ...
3345 This command displays or modifies the reset configuration
3346 of your combination of JTAG board and target in target
3347 configuration scripts.
3349 Information earlier in this section describes the kind of problems
3350 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3351 As a rule this command belongs only in board config files,
3352 describing issues like @emph{board doesn't connect TRST};
3353 or in user config files, addressing limitations derived
3354 from a particular combination of interface and board.
3355 (An unlikely example would be using a TRST-only adapter
3356 with a board that only wires up SRST.)
3358 The @var{mode_flag} options can be specified in any order, but only one
3359 of each type -- @var{signals}, @var{combination}, @var{gates},
3360 @var{trst_type}, @var{srst_type} and @var{connect_type}
3361 -- may be specified at a time.
3362 If you don't provide a new value for a given type, its previous
3363 value (perhaps the default) is unchanged.
3364 For example, this means that you don't need to say anything at all about
3365 TRST just to declare that if the JTAG adapter should want to drive SRST,
3366 it must explicitly be driven high (@option{srst_push_pull}).
3370 @var{signals} can specify which of the reset signals are connected.
3371 For example, If the JTAG interface provides SRST, but the board doesn't
3372 connect that signal properly, then OpenOCD can't use it.
3373 Possible values are @option{none} (the default), @option{trst_only},
3374 @option{srst_only} and @option{trst_and_srst}.
3377 If your board provides SRST and/or TRST through the JTAG connector,
3378 you must declare that so those signals can be used.
3382 The @var{combination} is an optional value specifying broken reset
3383 signal implementations.
3384 The default behaviour if no option given is @option{separate},
3385 indicating everything behaves normally.
3386 @option{srst_pulls_trst} states that the
3387 test logic is reset together with the reset of the system (e.g. NXP
3388 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
3389 the system is reset together with the test logic (only hypothetical, I
3390 haven't seen hardware with such a bug, and can be worked around).
3391 @option{combined} implies both @option{srst_pulls_trst} and
3392 @option{trst_pulls_srst}.
3395 The @var{gates} tokens control flags that describe some cases where
3396 JTAG may be unvailable during reset.
3397 @option{srst_gates_jtag} (default)
3398 indicates that asserting SRST gates the
3399 JTAG clock. This means that no communication can happen on JTAG
3400 while SRST is asserted.
3401 Its converse is @option{srst_nogate}, indicating that JTAG commands
3402 can safely be issued while SRST is active.
3405 The @var{connect_type} tokens control flags that describe some cases where
3406 SRST is asserted while connecting to the target. @option{srst_nogate}
3407 is required to use this option.
3408 @option{connect_deassert_srst} (default)
3409 indicates that SRST will not be asserted while connecting to the target.
3410 Its converse is @option{connect_assert_srst}, indicating that SRST will
3411 be asserted before any target connection.
3412 Only some targets support this feature, STM32 and STR9 are examples.
3413 This feature is useful if you are unable to connect to your target due
3414 to incorrect options byte config or illegal program execution.
3417 The optional @var{trst_type} and @var{srst_type} parameters allow the
3418 driver mode of each reset line to be specified. These values only affect
3419 JTAG interfaces with support for different driver modes, like the Amontec
3420 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
3421 relevant signal (TRST or SRST) is not connected.
3425 Possible @var{trst_type} driver modes for the test reset signal (TRST)
3426 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
3427 Most boards connect this signal to a pulldown, so the JTAG TAPs
3428 never leave reset unless they are hooked up to a JTAG adapter.
3431 Possible @var{srst_type} driver modes for the system reset signal (SRST)
3432 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
3433 Most boards connect this signal to a pullup, and allow the
3434 signal to be pulled low by various events including system
3435 powerup and pressing a reset button.
3439 @section Custom Reset Handling
3442 OpenOCD has several ways to help support the various reset
3443 mechanisms provided by chip and board vendors.
3444 The commands shown in the previous section give standard parameters.
3445 There are also @emph{event handlers} associated with TAPs or Targets.
3446 Those handlers are Tcl procedures you can provide, which are invoked
3447 at particular points in the reset sequence.
3449 @emph{When SRST is not an option} you must set
3450 up a @code{reset-assert} event handler for your target.
3451 For example, some JTAG adapters don't include the SRST signal;
3452 and some boards have multiple targets, and you won't always
3453 want to reset everything at once.
3455 After configuring those mechanisms, you might still
3456 find your board doesn't start up or reset correctly.
3457 For example, maybe it needs a slightly different sequence
3458 of SRST and/or TRST manipulations, because of quirks that
3459 the @command{reset_config} mechanism doesn't address;
3460 or asserting both might trigger a stronger reset, which
3461 needs special attention.
3463 Experiment with lower level operations, such as @command{jtag_reset}
3464 and the @command{jtag arp_*} operations shown here,
3465 to find a sequence of operations that works.
3466 @xref{JTAG Commands}.
3467 When you find a working sequence, it can be used to override
3468 @command{jtag_init}, which fires during OpenOCD startup
3469 (@pxref{configurationstage,,Configuration Stage});
3470 or @command{init_reset}, which fires during reset processing.
3472 You might also want to provide some project-specific reset
3473 schemes. For example, on a multi-target board the standard
3474 @command{reset} command would reset all targets, but you
3475 may need the ability to reset only one target at time and
3476 thus want to avoid using the board-wide SRST signal.
3478 @deffn {Overridable Procedure} init_reset mode
3479 This is invoked near the beginning of the @command{reset} command,
3480 usually to provide as much of a cold (power-up) reset as practical.
3481 By default it is also invoked from @command{jtag_init} if
3482 the scan chain does not respond to pure JTAG operations.
3483 The @var{mode} parameter is the parameter given to the
3484 low level reset command (@option{halt},
3485 @option{init}, or @option{run}), @option{setup},
3486 or potentially some other value.
3488 The default implementation just invokes @command{jtag arp_init-reset}.
3489 Replacements will normally build on low level JTAG
3490 operations such as @command{jtag_reset}.
3491 Operations here must not address individual TAPs
3492 (or their associated targets)
3493 until the JTAG scan chain has first been verified to work.
3495 Implementations must have verified the JTAG scan chain before
3497 This is done by calling @command{jtag arp_init}
3498 (or @command{jtag arp_init-reset}).
3501 @deffn Command {jtag arp_init}
3502 This validates the scan chain using just the four
3503 standard JTAG signals (TMS, TCK, TDI, TDO).
3504 It starts by issuing a JTAG-only reset.
3505 Then it performs checks to verify that the scan chain configuration
3506 matches the TAPs it can observe.
3507 Those checks include checking IDCODE values for each active TAP,
3508 and verifying the length of their instruction registers using
3509 TAP @code{-ircapture} and @code{-irmask} values.
3510 If these tests all pass, TAP @code{setup} events are
3511 issued to all TAPs with handlers for that event.
3514 @deffn Command {jtag arp_init-reset}
3515 This uses TRST and SRST to try resetting
3516 everything on the JTAG scan chain
3517 (and anything else connected to SRST).
3518 It then invokes the logic of @command{jtag arp_init}.
3522 @node TAP Declaration
3523 @chapter TAP Declaration
3524 @cindex TAP declaration
3525 @cindex TAP configuration
3527 @emph{Test Access Ports} (TAPs) are the core of JTAG.
3528 TAPs serve many roles, including:
3531 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
3532 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
3533 Others do it indirectly, making a CPU do it.
3534 @item @b{Program Download} Using the same CPU support GDB uses,
3535 you can initialize a DRAM controller, download code to DRAM, and then
3536 start running that code.
3537 @item @b{Boundary Scan} Most chips support boundary scan, which
3538 helps test for board assembly problems like solder bridges
3539 and missing connections.
3542 OpenOCD must know about the active TAPs on your board(s).
3543 Setting up the TAPs is the core task of your configuration files.
3544 Once those TAPs are set up, you can pass their names to code
3545 which sets up CPUs and exports them as GDB targets,
3546 probes flash memory, performs low-level JTAG operations, and more.
3548 @section Scan Chains
3551 TAPs are part of a hardware @dfn{scan chain},
3552 which is a daisy chain of TAPs.
3553 They also need to be added to
3554 OpenOCD's software mirror of that hardware list,
3555 giving each member a name and associating other data with it.
3556 Simple scan chains, with a single TAP, are common in
3557 systems with a single microcontroller or microprocessor.
3558 More complex chips may have several TAPs internally.
3559 Very complex scan chains might have a dozen or more TAPs:
3560 several in one chip, more in the next, and connecting
3561 to other boards with their own chips and TAPs.
3563 You can display the list with the @command{scan_chain} command.
3564 (Don't confuse this with the list displayed by the @command{targets}
3565 command, presented in the next chapter.
3566 That only displays TAPs for CPUs which are configured as
3568 Here's what the scan chain might look like for a chip more than one TAP:
3571 TapName Enabled IdCode Expected IrLen IrCap IrMask
3572 -- ------------------ ------- ---------- ---------- ----- ----- ------
3573 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
3574 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
3575 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
3578 OpenOCD can detect some of that information, but not all
3579 of it. @xref{autoprobing,,Autoprobing}.
3580 Unfortunately, those TAPs can't always be autoconfigured,
3581 because not all devices provide good support for that.
3582 JTAG doesn't require supporting IDCODE instructions, and
3583 chips with JTAG routers may not link TAPs into the chain
3584 until they are told to do so.
3586 The configuration mechanism currently supported by OpenOCD
3587 requires explicit configuration of all TAP devices using
3588 @command{jtag newtap} commands, as detailed later in this chapter.
3589 A command like this would declare one tap and name it @code{chip1.cpu}:
3592 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
3595 Each target configuration file lists the TAPs provided
3597 Board configuration files combine all the targets on a board,
3599 Note that @emph{the order in which TAPs are declared is very important.}
3600 That declaration order must match the order in the JTAG scan chain,
3601 both inside a single chip and between them.
3602 @xref{faqtaporder,,FAQ TAP Order}.
3604 For example, the ST Microsystems STR912 chip has
3605 three separate TAPs@footnote{See the ST
3606 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
3607 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
3608 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
3609 To configure those taps, @file{target/str912.cfg}
3610 includes commands something like this:
3613 jtag newtap str912 flash ... params ...
3614 jtag newtap str912 cpu ... params ...
3615 jtag newtap str912 bs ... params ...
3618 Actual config files typically use a variable such as @code{$_CHIPNAME}
3619 instead of literals like @option{str912}, to support more than one chip
3620 of each type. @xref{Config File Guidelines}.
3622 @deffn Command {jtag names}
3623 Returns the names of all current TAPs in the scan chain.
3624 Use @command{jtag cget} or @command{jtag tapisenabled}
3625 to examine attributes and state of each TAP.
3627 foreach t [jtag names] @{
3628 puts [format "TAP: %s\n" $t]
3633 @deffn Command {scan_chain}
3634 Displays the TAPs in the scan chain configuration,
3636 The set of TAPs listed by this command is fixed by
3637 exiting the OpenOCD configuration stage,
3638 but systems with a JTAG router can
3639 enable or disable TAPs dynamically.
3642 @c FIXME! "jtag cget" should be able to return all TAP
3643 @c attributes, like "$target_name cget" does for targets.
3645 @c Probably want "jtag eventlist", and a "tap-reset" event
3646 @c (on entry to RESET state).
3651 When TAP objects are declared with @command{jtag newtap},
3652 a @dfn{dotted.name} is created for the TAP, combining the
3653 name of a module (usually a chip) and a label for the TAP.
3654 For example: @code{xilinx.tap}, @code{str912.flash},
3655 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
3656 Many other commands use that dotted.name to manipulate or
3657 refer to the TAP. For example, CPU configuration uses the
3658 name, as does declaration of NAND or NOR flash banks.
3660 The components of a dotted name should follow ``C'' symbol
3661 name rules: start with an alphabetic character, then numbers
3662 and underscores are OK; while others (including dots!) are not.
3664 @section TAP Declaration Commands
3666 @c shouldn't this be(come) a {Config Command}?
3667 @deffn Command {jtag newtap} chipname tapname configparams...
3668 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
3669 and configured according to the various @var{configparams}.
3671 The @var{chipname} is a symbolic name for the chip.
3672 Conventionally target config files use @code{$_CHIPNAME},
3673 defaulting to the model name given by the chip vendor but
3676 @cindex TAP naming convention
3677 The @var{tapname} reflects the role of that TAP,
3678 and should follow this convention:
3681 @item @code{bs} -- For boundary scan if this is a separate TAP;
3682 @item @code{cpu} -- The main CPU of the chip, alternatively
3683 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
3684 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
3685 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
3686 @item @code{flash} -- If the chip has a flash TAP, like the str912;
3687 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
3688 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
3689 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
3691 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
3692 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
3693 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
3694 a JTAG TAP; that TAP should be named @code{sdma}.
3697 Every TAP requires at least the following @var{configparams}:
3700 @item @code{-irlen} @var{NUMBER}
3701 @*The length in bits of the
3702 instruction register, such as 4 or 5 bits.
3705 A TAP may also provide optional @var{configparams}:
3708 @item @code{-disable} (or @code{-enable})
3709 @*Use the @code{-disable} parameter to flag a TAP which is not
3710 linked into the scan chain after a reset using either TRST
3711 or the JTAG state machine's @sc{reset} state.
3712 You may use @code{-enable} to highlight the default state
3713 (the TAP is linked in).
3714 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
3715 @item @code{-expected-id} @var{NUMBER}
3716 @*A non-zero @var{number} represents a 32-bit IDCODE
3717 which you expect to find when the scan chain is examined.
3718 These codes are not required by all JTAG devices.
3719 @emph{Repeat the option} as many times as required if more than one
3720 ID code could appear (for example, multiple versions).
3721 Specify @var{number} as zero to suppress warnings about IDCODE
3722 values that were found but not included in the list.
3724 Provide this value if at all possible, since it lets OpenOCD
3725 tell when the scan chain it sees isn't right. These values
3726 are provided in vendors' chip documentation, usually a technical
3727 reference manual. Sometimes you may need to probe the JTAG
3728 hardware to find these values.
3729 @xref{autoprobing,,Autoprobing}.
3730 @item @code{-ignore-version}
3731 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
3732 option. When vendors put out multiple versions of a chip, or use the same
3733 JTAG-level ID for several largely-compatible chips, it may be more practical
3734 to ignore the version field than to update config files to handle all of
3735 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
3736 @item @code{-ircapture} @var{NUMBER}
3737 @*The bit pattern loaded by the TAP into the JTAG shift register
3738 on entry to the @sc{ircapture} state, such as 0x01.
3739 JTAG requires the two LSBs of this value to be 01.
3740 By default, @code{-ircapture} and @code{-irmask} are set
3741 up to verify that two-bit value. You may provide
3742 additional bits if you know them, or indicate that
3743 a TAP doesn't conform to the JTAG specification.
3744 @item @code{-irmask} @var{NUMBER}
3745 @*A mask used with @code{-ircapture}
3746 to verify that instruction scans work correctly.
3747 Such scans are not used by OpenOCD except to verify that
3748 there seems to be no problems with JTAG scan chain operations.
3752 @section Other TAP commands
3754 @deffn Command {jtag cget} dotted.name @option{-event} event_name
3755 @deffnx Command {jtag configure} dotted.name @option{-event} event_name handler
3756 At this writing this TAP attribute
3757 mechanism is used only for event handling.
3758 (It is not a direct analogue of the @code{cget}/@code{configure}
3759 mechanism for debugger targets.)
3760 See the next section for information about the available events.
3762 The @code{configure} subcommand assigns an event handler,
3763 a TCL string which is evaluated when the event is triggered.
3764 The @code{cget} subcommand returns that handler.
3771 OpenOCD includes two event mechanisms.
3772 The one presented here applies to all JTAG TAPs.
3773 The other applies to debugger targets,
3774 which are associated with certain TAPs.
3776 The TAP events currently defined are:
3779 @item @b{post-reset}
3780 @* The TAP has just completed a JTAG reset.
3781 The tap may still be in the JTAG @sc{reset} state.
3782 Handlers for these events might perform initialization sequences
3783 such as issuing TCK cycles, TMS sequences to ensure
3784 exit from the ARM SWD mode, and more.
3786 Because the scan chain has not yet been verified, handlers for these events
3787 @emph{should not issue commands which scan the JTAG IR or DR registers}
3788 of any particular target.
3789 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
3791 @* The scan chain has been reset and verified.
3792 This handler may enable TAPs as needed.
3793 @item @b{tap-disable}
3794 @* The TAP needs to be disabled. This handler should
3795 implement @command{jtag tapdisable}
3796 by issuing the relevant JTAG commands.
3797 @item @b{tap-enable}
3798 @* The TAP needs to be enabled. This handler should
3799 implement @command{jtag tapenable}
3800 by issuing the relevant JTAG commands.
3803 If you need some action after each JTAG reset which isn't actually
3804 specific to any TAP (since you can't yet trust the scan chain's
3805 contents to be accurate), you might:
3808 jtag configure CHIP.jrc -event post-reset @{
3809 echo "JTAG Reset done"
3810 ... non-scan jtag operations to be done after reset
3815 @anchor{enablinganddisablingtaps}
3816 @section Enabling and Disabling TAPs
3817 @cindex JTAG Route Controller
3820 In some systems, a @dfn{JTAG Route Controller} (JRC)
3821 is used to enable and/or disable specific JTAG TAPs.
3822 Many ARM-based chips from Texas Instruments include
3823 an ``ICEPick'' module, which is a JRC.
3824 Such chips include DaVinci and OMAP3 processors.
3826 A given TAP may not be visible until the JRC has been
3827 told to link it into the scan chain; and if the JRC
3828 has been told to unlink that TAP, it will no longer
3830 Such routers address problems that JTAG ``bypass mode''
3834 @item The scan chain can only go as fast as its slowest TAP.
3835 @item Having many TAPs slows instruction scans, since all
3836 TAPs receive new instructions.
3837 @item TAPs in the scan chain must be powered up, which wastes
3838 power and prevents debugging some power management mechanisms.
3841 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
3842 as implied by the existence of JTAG routers.
3843 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
3844 does include a kind of JTAG router functionality.
3846 @c (a) currently the event handlers don't seem to be able to
3847 @c fail in a way that could lead to no-change-of-state.
3849 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
3850 shown below, and is implemented using TAP event handlers.
3851 So for example, when defining a TAP for a CPU connected to
3852 a JTAG router, your @file{target.cfg} file
3853 should define TAP event handlers using
3854 code that looks something like this:
3857 jtag configure CHIP.cpu -event tap-enable @{
3858 ... jtag operations using CHIP.jrc
3860 jtag configure CHIP.cpu -event tap-disable @{
3861 ... jtag operations using CHIP.jrc
3865 Then you might want that CPU's TAP enabled almost all the time:
3868 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
3871 Note how that particular setup event handler declaration
3872 uses quotes to evaluate @code{$CHIP} when the event is configured.
3873 Using brackets @{ @} would cause it to be evaluated later,
3874 at runtime, when it might have a different value.
3876 @deffn Command {jtag tapdisable} dotted.name
3877 If necessary, disables the tap
3878 by sending it a @option{tap-disable} event.
3879 Returns the string "1" if the tap
3880 specified by @var{dotted.name} is enabled,
3881 and "0" if it is disabled.
3884 @deffn Command {jtag tapenable} dotted.name
3885 If necessary, enables the tap
3886 by sending it a @option{tap-enable} event.
3887 Returns the string "1" if the tap
3888 specified by @var{dotted.name} is enabled,
3889 and "0" if it is disabled.
3892 @deffn Command {jtag tapisenabled} dotted.name
3893 Returns the string "1" if the tap
3894 specified by @var{dotted.name} is enabled,
3895 and "0" if it is disabled.
3898 Humans will find the @command{scan_chain} command more helpful
3899 for querying the state of the JTAG taps.
3903 @anchor{autoprobing}
3904 @section Autoprobing
3906 @cindex JTAG autoprobe
3908 TAP configuration is the first thing that needs to be done
3909 after interface and reset configuration. Sometimes it's
3910 hard finding out what TAPs exist, or how they are identified.
3911 Vendor documentation is not always easy to find and use.
3913 To help you get past such problems, OpenOCD has a limited
3914 @emph{autoprobing} ability to look at the scan chain, doing
3915 a @dfn{blind interrogation} and then reporting the TAPs it finds.
3916 To use this mechanism, start the OpenOCD server with only data
3917 that configures your JTAG interface, and arranges to come up
3918 with a slow clock (many devices don't support fast JTAG clocks
3919 right when they come out of reset).
3921 For example, your @file{openocd.cfg} file might have:
3924 source [find interface/olimex-arm-usb-tiny-h.cfg]
3925 reset_config trst_and_srst
3929 When you start the server without any TAPs configured, it will
3930 attempt to autoconfigure the TAPs. There are two parts to this:
3933 @item @emph{TAP discovery} ...
3934 After a JTAG reset (sometimes a system reset may be needed too),
3935 each TAP's data registers will hold the contents of either the
3936 IDCODE or BYPASS register.
3937 If JTAG communication is working, OpenOCD will see each TAP,
3938 and report what @option{-expected-id} to use with it.
3939 @item @emph{IR Length discovery} ...
3940 Unfortunately JTAG does not provide a reliable way to find out
3941 the value of the @option{-irlen} parameter to use with a TAP
3943 If OpenOCD can discover the length of a TAP's instruction
3944 register, it will report it.
3945 Otherwise you may need to consult vendor documentation, such
3946 as chip data sheets or BSDL files.
3949 In many cases your board will have a simple scan chain with just
3950 a single device. Here's what OpenOCD reported with one board
3951 that's a bit more complex:
3955 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
3956 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
3957 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
3958 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
3959 AUTO auto0.tap - use "... -irlen 4"
3960 AUTO auto1.tap - use "... -irlen 4"
3961 AUTO auto2.tap - use "... -irlen 6"
3962 no gdb ports allocated as no target has been specified
3965 Given that information, you should be able to either find some existing
3966 config files to use, or create your own. If you create your own, you
3967 would configure from the bottom up: first a @file{target.cfg} file
3968 with these TAPs, any targets associated with them, and any on-chip
3969 resources; then a @file{board.cfg} with off-chip resources, clocking,
3972 @node CPU Configuration
3973 @chapter CPU Configuration
3976 This chapter discusses how to set up GDB debug targets for CPUs.
3977 You can also access these targets without GDB
3978 (@pxref{Architecture and Core Commands},
3979 and @ref{targetstatehandling,,Target State handling}) and
3980 through various kinds of NAND and NOR flash commands.
3981 If you have multiple CPUs you can have multiple such targets.
3983 We'll start by looking at how to examine the targets you have,
3984 then look at how to add one more target and how to configure it.
3986 @section Target List
3987 @cindex target, current
3988 @cindex target, list
3990 All targets that have been set up are part of a list,
3991 where each member has a name.
3992 That name should normally be the same as the TAP name.
3993 You can display the list with the @command{targets}
3995 This display often has only one CPU; here's what it might
3996 look like with more than one:
3998 TargetName Type Endian TapName State
3999 -- ------------------ ---------- ------ ------------------ ------------
4000 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4001 1 MyTarget cortex_m little mychip.foo tap-disabled
4004 One member of that list is the @dfn{current target}, which
4005 is implicitly referenced by many commands.
4006 It's the one marked with a @code{*} near the target name.
4007 In particular, memory addresses often refer to the address
4008 space seen by that current target.
4009 Commands like @command{mdw} (memory display words)
4010 and @command{flash erase_address} (erase NOR flash blocks)
4011 are examples; and there are many more.
4013 Several commands let you examine the list of targets:
4015 @deffn Command {target current}
4016 Returns the name of the current target.
4019 @deffn Command {target names}
4020 Lists the names of all current targets in the list.
4022 foreach t [target names] @{
4023 puts [format "Target: %s\n" $t]
4028 @c yep, "target list" would have been better.
4029 @c plus maybe "target setdefault".
4031 @deffn Command targets [name]
4032 @emph{Note: the name of this command is plural. Other target
4033 command names are singular.}
4035 With no parameter, this command displays a table of all known
4036 targets in a user friendly form.
4038 With a parameter, this command sets the current target to
4039 the given target with the given @var{name}; this is
4040 only relevant on boards which have more than one target.
4043 @section Target CPU Types
4047 Each target has a @dfn{CPU type}, as shown in the output of
4048 the @command{targets} command. You need to specify that type
4049 when calling @command{target create}.
4050 The CPU type indicates more than just the instruction set.
4051 It also indicates how that instruction set is implemented,
4052 what kind of debug support it integrates,
4053 whether it has an MMU (and if so, what kind),
4054 what core-specific commands may be available
4055 (@pxref{Architecture and Core Commands}),
4058 It's easy to see what target types are supported,
4059 since there's a command to list them.
4061 @anchor{targettypes}
4062 @deffn Command {target types}
4063 Lists all supported target types.
4064 At this writing, the supported CPU types are:
4067 @item @code{arm11} -- this is a generation of ARMv6 cores
4068 @item @code{arm720t} -- this is an ARMv4 core with an MMU
4069 @item @code{arm7tdmi} -- this is an ARMv4 core
4070 @item @code{arm920t} -- this is an ARMv4 core with an MMU
4071 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU
4072 @item @code{arm966e} -- this is an ARMv5 core
4073 @item @code{arm9tdmi} -- this is an ARMv4 core
4074 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4075 (Support for this is preliminary and incomplete.)
4076 @item @code{cortex_a} -- this is an ARMv7 core with an MMU
4077 @item @code{cortex_m} -- this is an ARMv7 core, supporting only the
4078 compact Thumb2 instruction set.
4079 @item @code{aarch64} -- this is an ARMv8-A core with an MMU
4080 @item @code{dragonite} -- resembles arm966e
4081 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4082 (Support for this is still incomplete.)
4083 @item @code{fa526} -- resembles arm920 (w/o Thumb)
4084 @item @code{feroceon} -- resembles arm926
4085 @item @code{mips_m4k} -- a MIPS core
4086 @item @code{xscale} -- this is actually an architecture,
4087 not a CPU type. It is based on the ARMv5 architecture.
4088 @item @code{openrisc} -- this is an OpenRISC 1000 core.
4089 The current implementation supports three JTAG TAP cores:
4090 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4091 allowing access to physical memory addresses independently of CPU cores.
4093 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
4094 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4095 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4097 And two debug interfaces cores:
4099 @item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys})
4100 @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface})
4105 To avoid being confused by the variety of ARM based cores, remember
4106 this key point: @emph{ARM is a technology licencing company}.
4107 (See: @url{http://www.arm.com}.)
4108 The CPU name used by OpenOCD will reflect the CPU design that was
4109 licenced, not a vendor brand which incorporates that design.
4110 Name prefixes like arm7, arm9, arm11, and cortex
4111 reflect design generations;
4112 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4113 reflect an architecture version implemented by a CPU design.
4115 @anchor{targetconfiguration}
4116 @section Target Configuration
4118 Before creating a ``target'', you must have added its TAP to the scan chain.
4119 When you've added that TAP, you will have a @code{dotted.name}
4120 which is used to set up the CPU support.
4121 The chip-specific configuration file will normally configure its CPU(s)
4122 right after it adds all of the chip's TAPs to the scan chain.
4124 Although you can set up a target in one step, it's often clearer if you
4125 use shorter commands and do it in two steps: create it, then configure
4127 All operations on the target after it's created will use a new
4128 command, created as part of target creation.
4130 The two main things to configure after target creation are
4131 a work area, which usually has target-specific defaults even
4132 if the board setup code overrides them later;
4133 and event handlers (@pxref{targetevents,,Target Events}), which tend
4134 to be much more board-specific.
4135 The key steps you use might look something like this
4138 target create MyTarget cortex_m -chain-position mychip.cpu
4139 $MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4140 $MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4141 $MyTarget configure -event reset-init @{ myboard_reinit @}
4144 You should specify a working area if you can; typically it uses some
4146 Such a working area can speed up many things, including bulk
4147 writes to target memory;
4148 flash operations like checking to see if memory needs to be erased;
4149 GDB memory checksumming;
4153 On more complex chips, the work area can become
4154 inaccessible when application code
4155 (such as an operating system)
4156 enables or disables the MMU.
4157 For example, the particular MMU context used to acess the virtual
4158 address will probably matter ... and that context might not have
4159 easy access to other addresses needed.
4160 At this writing, OpenOCD doesn't have much MMU intelligence.
4163 It's often very useful to define a @code{reset-init} event handler.
4164 For systems that are normally used with a boot loader,
4165 common tasks include updating clocks and initializing memory
4167 That may be needed to let you write the boot loader into flash,
4168 in order to ``de-brick'' your board; or to load programs into
4169 external DDR memory without having run the boot loader.
4171 @deffn Command {target create} target_name type configparams...
4172 This command creates a GDB debug target that refers to a specific JTAG tap.
4173 It enters that target into a list, and creates a new
4174 command (@command{@var{target_name}}) which is used for various
4175 purposes including additional configuration.
4178 @item @var{target_name} ... is the name of the debug target.
4179 By convention this should be the same as the @emph{dotted.name}
4180 of the TAP associated with this target, which must be specified here
4181 using the @code{-chain-position @var{dotted.name}} configparam.
4183 This name is also used to create the target object command,
4184 referred to here as @command{$target_name},
4185 and in other places the target needs to be identified.
4186 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
4187 @item @var{configparams} ... all parameters accepted by
4188 @command{$target_name configure} are permitted.
4189 If the target is big-endian, set it here with @code{-endian big}.
4191 You @emph{must} set the @code{-chain-position @var{dotted.name}} here.
4195 @deffn Command {$target_name configure} configparams...
4196 The options accepted by this command may also be
4197 specified as parameters to @command{target create}.
4198 Their values can later be queried one at a time by
4199 using the @command{$target_name cget} command.
4201 @emph{Warning:} changing some of these after setup is dangerous.
4202 For example, moving a target from one TAP to another;
4203 and changing its endianness.
4207 @item @code{-chain-position} @var{dotted.name} -- names the TAP
4208 used to access this target.
4210 @item @code{-endian} (@option{big}|@option{little}) -- specifies
4211 whether the CPU uses big or little endian conventions
4213 @item @code{-event} @var{event_name} @var{event_body} --
4214 @xref{targetevents,,Target Events}.
4215 Note that this updates a list of named event handlers.
4216 Calling this twice with two different event names assigns
4217 two different handlers, but calling it twice with the
4218 same event name assigns only one handler.
4220 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
4221 whether the work area gets backed up; by default,
4222 @emph{it is not backed up.}
4223 When possible, use a working_area that doesn't need to be backed up,
4224 since performing a backup slows down operations.
4225 For example, the beginning of an SRAM block is likely to
4226 be used by most build systems, but the end is often unused.
4228 @item @code{-work-area-size} @var{size} -- specify work are size,
4229 in bytes. The same size applies regardless of whether its physical
4230 or virtual address is being used.
4232 @item @code{-work-area-phys} @var{address} -- set the work area
4233 base @var{address} to be used when no MMU is active.
4235 @item @code{-work-area-virt} @var{address} -- set the work area
4236 base @var{address} to be used when an MMU is active.
4237 @emph{Do not specify a value for this except on targets with an MMU.}
4238 The value should normally correspond to a static mapping for the
4239 @code{-work-area-phys} address, set up by the current operating system.
4242 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
4243 @var{rtos_type} can be one of @option{auto}, @option{eCos},
4244 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
4245 @option{embKernel}, @option{mqx}, @option{uCOS-III}
4246 @xref{gdbrtossupport,,RTOS Support}.
4248 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
4249 scan and after a reset. A manual call to arp_examine is required to
4250 access the target for debugging.
4252 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target,
4253 @var{ap_number} is the numeric index of the DAP AP the target is connected to.
4254 Use this option with systems where multiple, independent cores are connected
4255 to separate access ports of the same DAP.
4257 @item @code{-ctibase} @var{address} -- set base address of Cross-Trigger interface (CTI) connected
4258 to the target. Currently, only the @code{aarch64} target makes use of this option, where it is
4259 a mandatory configuration for the target run control.
4263 @section Other $target_name Commands
4264 @cindex object command
4266 The Tcl/Tk language has the concept of object commands,
4267 and OpenOCD adopts that same model for targets.
4269 A good Tk example is a on screen button.
4270 Once a button is created a button
4271 has a name (a path in Tk terms) and that name is useable as a first
4272 class command. For example in Tk, one can create a button and later
4273 configure it like this:
4277 button .foobar -background red -command @{ foo @}
4279 .foobar configure -foreground blue
4281 set x [.foobar cget -background]
4283 puts [format "The button is %s" $x]
4286 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
4287 button, and its object commands are invoked the same way.
4290 str912.cpu mww 0x1234 0x42
4291 omap3530.cpu mww 0x5555 123
4294 The commands supported by OpenOCD target objects are:
4296 @deffn Command {$target_name arp_examine} @option{allow-defer}
4297 @deffnx Command {$target_name arp_halt}
4298 @deffnx Command {$target_name arp_poll}
4299 @deffnx Command {$target_name arp_reset}
4300 @deffnx Command {$target_name arp_waitstate}
4301 Internal OpenOCD scripts (most notably @file{startup.tcl})
4302 use these to deal with specific reset cases.
4303 They are not otherwise documented here.
4306 @deffn Command {$target_name array2mem} arrayname width address count
4307 @deffnx Command {$target_name mem2array} arrayname width address count
4308 These provide an efficient script-oriented interface to memory.
4309 The @code{array2mem} primitive writes bytes, halfwords, or words;
4310 while @code{mem2array} reads them.
4311 In both cases, the TCL side uses an array, and
4312 the target side uses raw memory.
4314 The efficiency comes from enabling the use of
4315 bulk JTAG data transfer operations.
4316 The script orientation comes from working with data
4317 values that are packaged for use by TCL scripts;
4318 @command{mdw} type primitives only print data they retrieve,
4319 and neither store nor return those values.
4322 @item @var{arrayname} ... is the name of an array variable
4323 @item @var{width} ... is 8/16/32 - indicating the memory access size
4324 @item @var{address} ... is the target memory address
4325 @item @var{count} ... is the number of elements to process
4329 @deffn Command {$target_name cget} queryparm
4330 Each configuration parameter accepted by
4331 @command{$target_name configure}
4332 can be individually queried, to return its current value.
4333 The @var{queryparm} is a parameter name
4334 accepted by that command, such as @code{-work-area-phys}.
4335 There are a few special cases:
4338 @item @code{-event} @var{event_name} -- returns the handler for the
4339 event named @var{event_name}.
4340 This is a special case because setting a handler requires
4342 @item @code{-type} -- returns the target type.
4343 This is a special case because this is set using
4344 @command{target create} and can't be changed
4345 using @command{$target_name configure}.
4348 For example, if you wanted to summarize information about
4349 all the targets you might use something like this:
4352 foreach name [target names] @{
4353 set y [$name cget -endian]
4354 set z [$name cget -type]
4355 puts [format "Chip %d is %s, Endian: %s, type: %s" \
4361 @anchor{targetcurstate}
4362 @deffn Command {$target_name curstate}
4363 Displays the current target state:
4364 @code{debug-running},
4367 @code{running}, or @code{unknown}.
4368 (Also, @pxref{eventpolling,,Event Polling}.)
4371 @deffn Command {$target_name eventlist}
4372 Displays a table listing all event handlers
4373 currently associated with this target.
4374 @xref{targetevents,,Target Events}.
4377 @deffn Command {$target_name invoke-event} event_name
4378 Invokes the handler for the event named @var{event_name}.
4379 (This is primarily intended for use by OpenOCD framework
4380 code, for example by the reset code in @file{startup.tcl}.)
4383 @deffn Command {$target_name mdw} addr [count]
4384 @deffnx Command {$target_name mdh} addr [count]
4385 @deffnx Command {$target_name mdb} addr [count]
4386 Display contents of address @var{addr}, as
4387 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
4388 or 8-bit bytes (@command{mdb}).
4389 If @var{count} is specified, displays that many units.
4390 (If you want to manipulate the data instead of displaying it,
4391 see the @code{mem2array} primitives.)
4394 @deffn Command {$target_name mww} addr word
4395 @deffnx Command {$target_name mwh} addr halfword
4396 @deffnx Command {$target_name mwb} addr byte
4397 Writes the specified @var{word} (32 bits),
4398 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4399 at the specified address @var{addr}.
4402 @anchor{targetevents}
4403 @section Target Events
4404 @cindex target events
4406 At various times, certain things can happen, or you want them to happen.
4409 @item What should happen when GDB connects? Should your target reset?
4410 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
4411 @item Is using SRST appropriate (and possible) on your system?
4412 Or instead of that, do you need to issue JTAG commands to trigger reset?
4413 SRST usually resets everything on the scan chain, which can be inappropriate.
4414 @item During reset, do you need to write to certain memory locations
4415 to set up system clocks or
4416 to reconfigure the SDRAM?
4417 How about configuring the watchdog timer, or other peripherals,
4418 to stop running while you hold the core stopped for debugging?
4421 All of the above items can be addressed by target event handlers.
4422 These are set up by @command{$target_name configure -event} or
4423 @command{target create ... -event}.
4425 The programmer's model matches the @code{-command} option used in Tcl/Tk
4426 buttons and events. The two examples below act the same, but one creates
4427 and invokes a small procedure while the other inlines it.
4430 proc my_attach_proc @{ @} @{
4434 mychip.cpu configure -event gdb-attach my_attach_proc
4435 mychip.cpu configure -event gdb-attach @{
4437 # To make flash probe and gdb load to flash work
4438 # we need a reset init.
4443 The following target events are defined:
4446 @item @b{debug-halted}
4447 @* The target has halted for debug reasons (i.e.: breakpoint)
4448 @item @b{debug-resumed}
4449 @* The target has resumed (i.e.: gdb said run)
4450 @item @b{early-halted}
4451 @* Occurs early in the halt process
4452 @item @b{examine-start}
4453 @* Before target examine is called.
4454 @item @b{examine-end}
4455 @* After target examine is called with no errors.
4456 @item @b{gdb-attach}
4457 @* When GDB connects. This is before any communication with the target, so this
4458 can be used to set up the target so it is possible to probe flash. Probing flash
4459 is necessary during gdb connect if gdb load is to write the image to flash. Another
4460 use of the flash memory map is for GDB to automatically hardware/software breakpoints
4461 depending on whether the breakpoint is in RAM or read only memory.
4462 @item @b{gdb-detach}
4463 @* When GDB disconnects
4465 @* When the target has halted and GDB is not doing anything (see early halt)
4466 @item @b{gdb-flash-erase-start}
4467 @* Before the GDB flash process tries to erase the flash (default is
4469 @item @b{gdb-flash-erase-end}
4470 @* After the GDB flash process has finished erasing the flash
4471 @item @b{gdb-flash-write-start}
4472 @* Before GDB writes to the flash
4473 @item @b{gdb-flash-write-end}
4474 @* After GDB writes to the flash (default is @code{reset halt})
4476 @* Before the target steps, gdb is trying to start/resume the target
4478 @* The target has halted
4479 @item @b{reset-assert-pre}
4480 @* Issued as part of @command{reset} processing
4481 after @command{reset_init} was triggered
4482 but before either SRST alone is re-asserted on the scan chain,
4483 or @code{reset-assert} is triggered.
4484 @item @b{reset-assert}
4485 @* Issued as part of @command{reset} processing
4486 after @command{reset-assert-pre} was triggered.
4487 When such a handler is present, cores which support this event will use
4488 it instead of asserting SRST.
4489 This support is essential for debugging with JTAG interfaces which
4490 don't include an SRST line (JTAG doesn't require SRST), and for
4491 selective reset on scan chains that have multiple targets.
4492 @item @b{reset-assert-post}
4493 @* Issued as part of @command{reset} processing
4494 after @code{reset-assert} has been triggered.
4495 or the target asserted SRST on the entire scan chain.
4496 @item @b{reset-deassert-pre}
4497 @* Issued as part of @command{reset} processing
4498 after @code{reset-assert-post} has been triggered.
4499 @item @b{reset-deassert-post}
4500 @* Issued as part of @command{reset} processing
4501 after @code{reset-deassert-pre} has been triggered
4502 and (if the target is using it) after SRST has been
4503 released on the scan chain.
4505 @* Issued as the final step in @command{reset} processing.
4507 @item @b{reset-halt-post}
4508 @* Currently not used
4509 @item @b{reset-halt-pre}
4510 @* Currently not used
4512 @item @b{reset-init}
4513 @* Used by @b{reset init} command for board-specific initialization.
4514 This event fires after @emph{reset-deassert-post}.
4516 This is where you would configure PLLs and clocking, set up DRAM so
4517 you can download programs that don't fit in on-chip SRAM, set up pin
4518 multiplexing, and so on.
4519 (You may be able to switch to a fast JTAG clock rate here, after
4520 the target clocks are fully set up.)
4521 @item @b{reset-start}
4522 @* Issued as part of @command{reset} processing
4523 before @command{reset_init} is called.
4525 This is the most robust place to use @command{jtag_rclk}
4526 or @command{adapter_khz} to switch to a low JTAG clock rate,
4527 when reset disables PLLs needed to use a fast clock.
4529 @item @b{reset-wait-pos}
4530 @* Currently not used
4531 @item @b{reset-wait-pre}
4532 @* Currently not used
4534 @item @b{resume-start}
4535 @* Before any target is resumed
4536 @item @b{resume-end}
4537 @* After all targets have resumed
4539 @* Target has resumed
4540 @item @b{trace-config}
4541 @* After target hardware trace configuration was changed
4544 @node Flash Commands
4545 @chapter Flash Commands
4547 OpenOCD has different commands for NOR and NAND flash;
4548 the ``flash'' command works with NOR flash, while
4549 the ``nand'' command works with NAND flash.
4550 This partially reflects different hardware technologies:
4551 NOR flash usually supports direct CPU instruction and data bus access,
4552 while data from a NAND flash must be copied to memory before it can be
4553 used. (SPI flash must also be copied to memory before use.)
4554 However, the documentation also uses ``flash'' as a generic term;
4555 for example, ``Put flash configuration in board-specific files''.
4559 @item Configure via the command @command{flash bank}
4560 @* Do this in a board-specific configuration file,
4561 passing parameters as needed by the driver.
4562 @item Operate on the flash via @command{flash subcommand}
4563 @* Often commands to manipulate the flash are typed by a human, or run
4564 via a script in some automated way. Common tasks include writing a
4565 boot loader, operating system, or other data.
4567 @* Flashing via GDB requires the flash be configured via ``flash
4568 bank'', and the GDB flash features be enabled.
4569 @xref{gdbconfiguration,,GDB Configuration}.
4572 Many CPUs have the ablity to ``boot'' from the first flash bank.
4573 This means that misprogramming that bank can ``brick'' a system,
4574 so that it can't boot.
4575 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
4576 board by (re)installing working boot firmware.
4578 @anchor{norconfiguration}
4579 @section Flash Configuration Commands
4580 @cindex flash configuration
4582 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
4583 Configures a flash bank which provides persistent storage
4584 for addresses from @math{base} to @math{base + size - 1}.
4585 These banks will often be visible to GDB through the target's memory map.
4586 In some cases, configuring a flash bank will activate extra commands;
4587 see the driver-specific documentation.
4590 @item @var{name} ... may be used to reference the flash bank
4591 in other flash commands. A number is also available.
4592 @item @var{driver} ... identifies the controller driver
4593 associated with the flash bank being declared.
4594 This is usually @code{cfi} for external flash, or else
4595 the name of a microcontroller with embedded flash memory.
4596 @xref{flashdriverlist,,Flash Driver List}.
4597 @item @var{base} ... Base address of the flash chip.
4598 @item @var{size} ... Size of the chip, in bytes.
4599 For some drivers, this value is detected from the hardware.
4600 @item @var{chip_width} ... Width of the flash chip, in bytes;
4601 ignored for most microcontroller drivers.
4602 @item @var{bus_width} ... Width of the data bus used to access the
4603 chip, in bytes; ignored for most microcontroller drivers.
4604 @item @var{target} ... Names the target used to issue
4605 commands to the flash controller.
4606 @comment Actually, it's currently a controller-specific parameter...
4607 @item @var{driver_options} ... drivers may support, or require,
4608 additional parameters. See the driver-specific documentation
4609 for more information.
4612 This command is not available after OpenOCD initialization has completed.
4613 Use it in board specific configuration files, not interactively.
4617 @comment the REAL name for this command is "ocd_flash_banks"
4618 @comment less confusing would be: "flash list" (like "nand list")
4619 @deffn Command {flash banks}
4620 Prints a one-line summary of each device that was
4621 declared using @command{flash bank}, numbered from zero.
4622 Note that this is the @emph{plural} form;
4623 the @emph{singular} form is a very different command.
4626 @deffn Command {flash list}
4627 Retrieves a list of associative arrays for each device that was
4628 declared using @command{flash bank}, numbered from zero.
4629 This returned list can be manipulated easily from within scripts.
4632 @deffn Command {flash probe} num
4633 Identify the flash, or validate the parameters of the configured flash. Operation
4634 depends on the flash type.
4635 The @var{num} parameter is a value shown by @command{flash banks}.
4636 Most flash commands will implicitly @emph{autoprobe} the bank;
4637 flash drivers can distinguish between probing and autoprobing,
4638 but most don't bother.
4641 @section Erasing, Reading, Writing to Flash
4642 @cindex flash erasing
4643 @cindex flash reading
4644 @cindex flash writing
4645 @cindex flash programming
4646 @anchor{flashprogrammingcommands}
4648 One feature distinguishing NOR flash from NAND or serial flash technologies
4649 is that for read access, it acts exactly like any other addressible memory.
4650 This means you can use normal memory read commands like @command{mdw} or
4651 @command{dump_image} with it, with no special @command{flash} subcommands.
4652 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
4654 Write access works differently. Flash memory normally needs to be erased
4655 before it's written. Erasing a sector turns all of its bits to ones, and
4656 writing can turn ones into zeroes. This is why there are special commands
4657 for interactive erasing and writing, and why GDB needs to know which parts
4658 of the address space hold NOR flash memory.
4661 Most of these erase and write commands leverage the fact that NOR flash
4662 chips consume target address space. They implicitly refer to the current
4663 JTAG target, and map from an address in that target's address space
4664 back to a flash bank.
4665 @comment In May 2009, those mappings may fail if any bank associated
4666 @comment with that target doesn't succesfuly autoprobe ... bug worth fixing?
4667 A few commands use abstract addressing based on bank and sector numbers,
4668 and don't depend on searching the current target and its address space.
4669 Avoid confusing the two command models.
4672 Some flash chips implement software protection against accidental writes,
4673 since such buggy writes could in some cases ``brick'' a system.
4674 For such systems, erasing and writing may require sector protection to be
4676 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
4677 and AT91SAM7 on-chip flash.
4678 @xref{flashprotect,,flash protect}.
4680 @deffn Command {flash erase_sector} num first last
4681 Erase sectors in bank @var{num}, starting at sector @var{first}
4682 up to and including @var{last}.
4683 Sector numbering starts at 0.
4684 Providing a @var{last} sector of @option{last}
4685 specifies "to the end of the flash bank".
4686 The @var{num} parameter is a value shown by @command{flash banks}.
4689 @deffn Command {flash erase_address} [@option{pad}] [@option{unlock}] address length
4690 Erase sectors starting at @var{address} for @var{length} bytes.
4691 Unless @option{pad} is specified, @math{address} must begin a
4692 flash sector, and @math{address + length - 1} must end a sector.
4693 Specifying @option{pad} erases extra data at the beginning and/or
4694 end of the specified region, as needed to erase only full sectors.
4695 The flash bank to use is inferred from the @var{address}, and
4696 the specified length must stay within that bank.
4697 As a special case, when @var{length} is zero and @var{address} is
4698 the start of the bank, the whole flash is erased.
4699 If @option{unlock} is specified, then the flash is unprotected
4700 before erase starts.
4703 @deffn Command {flash fillw} address word length
4704 @deffnx Command {flash fillh} address halfword length
4705 @deffnx Command {flash fillb} address byte length
4706 Fills flash memory with the specified @var{word} (32 bits),
4707 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
4708 starting at @var{address} and continuing
4709 for @var{length} units (word/halfword/byte).
4710 No erasure is done before writing; when needed, that must be done
4711 before issuing this command.
4712 Writes are done in blocks of up to 1024 bytes, and each write is
4713 verified by reading back the data and comparing it to what was written.
4714 The flash bank to use is inferred from the @var{address} of
4715 each block, and the specified length must stay within that bank.
4717 @comment no current checks for errors if fill blocks touch multiple banks!
4719 @deffn Command {flash write_bank} num filename [offset]
4720 Write the binary @file{filename} to flash bank @var{num},
4721 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
4722 is omitted, start at the beginning of the flash bank.
4723 The @var{num} parameter is a value shown by @command{flash banks}.
4726 @deffn Command {flash read_bank} num filename [offset [length]]
4727 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
4728 and write the contents to the binary @file{filename}. If @var{offset} is
4729 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
4730 read the remaining bytes from the flash bank.
4731 The @var{num} parameter is a value shown by @command{flash banks}.
4734 @deffn Command {flash verify_bank} num filename [offset]
4735 Compare the contents of the binary file @var{filename} with the contents of the
4736 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
4737 start at the beginning of the flash bank. Fail if the contents do not match.
4738 The @var{num} parameter is a value shown by @command{flash banks}.
4741 @deffn Command {flash write_image} [erase] [unlock] filename [offset] [type]
4742 Write the image @file{filename} to the current target's flash bank(s).
4743 Only loadable sections from the image are written.
4744 A relocation @var{offset} may be specified, in which case it is added
4745 to the base address for each section in the image.
4746 The file [@var{type}] can be specified
4747 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
4748 @option{elf} (ELF file), @option{s19} (Motorola s19).
4749 @option{mem}, or @option{builder}.
4750 The relevant flash sectors will be erased prior to programming
4751 if the @option{erase} parameter is given. If @option{unlock} is
4752 provided, then the flash banks are unlocked before erase and
4753 program. The flash bank to use is inferred from the address of
4757 Be careful using the @option{erase} flag when the flash is holding
4758 data you want to preserve.
4759 Portions of the flash outside those described in the image's
4760 sections might be erased with no notice.
4763 When a section of the image being written does not fill out all the
4764 sectors it uses, the unwritten parts of those sectors are necessarily
4765 also erased, because sectors can't be partially erased.
4767 Data stored in sector "holes" between image sections are also affected.
4768 For example, "@command{flash write_image erase ...}" of an image with
4769 one byte at the beginning of a flash bank and one byte at the end
4770 erases the entire bank -- not just the two sectors being written.
4772 Also, when flash protection is important, you must re-apply it after
4773 it has been removed by the @option{unlock} flag.
4778 @section Other Flash commands
4779 @cindex flash protection
4781 @deffn Command {flash erase_check} num
4782 Check erase state of sectors in flash bank @var{num},
4783 and display that status.
4784 The @var{num} parameter is a value shown by @command{flash banks}.
4787 @deffn Command {flash info} num [sectors]
4788 Print info about flash bank @var{num}, a list of protection blocks
4789 and their status. Use @option{sectors} to show a list of sectors instead.
4791 The @var{num} parameter is a value shown by @command{flash banks}.
4792 This command will first query the hardware, it does not print cached
4793 and possibly stale information.
4796 @anchor{flashprotect}
4797 @deffn Command {flash protect} num first last (@option{on}|@option{off})
4798 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
4799 in flash bank @var{num}, starting at protection block @var{first}
4800 and continuing up to and including @var{last}.
4801 Providing a @var{last} block of @option{last}
4802 specifies "to the end of the flash bank".
4803 The @var{num} parameter is a value shown by @command{flash banks}.
4804 The protection block is usually identical to a flash sector.
4805 Some devices may utilize a protection block distinct from flash sector.
4806 See @command{flash info} for a list of protection blocks.
4809 @deffn Command {flash padded_value} num value
4810 Sets the default value used for padding any image sections, This should
4811 normally match the flash bank erased value. If not specified by this
4812 comamnd or the flash driver then it defaults to 0xff.
4816 @deffn Command {program} filename [verify] [reset] [exit] [offset]
4817 This is a helper script that simplifies using OpenOCD as a standalone
4818 programmer. The only required parameter is @option{filename}, the others are optional.
4819 @xref{Flash Programming}.
4822 @anchor{flashdriverlist}
4823 @section Flash Driver List
4824 As noted above, the @command{flash bank} command requires a driver name,
4825 and allows driver-specific options and behaviors.
4826 Some drivers also activate driver-specific commands.
4828 @deffn {Flash Driver} virtual
4829 This is a special driver that maps a previously defined bank to another
4830 address. All bank settings will be copied from the master physical bank.
4832 The @var{virtual} driver defines one mandatory parameters,
4835 @item @var{master_bank} The bank that this virtual address refers to.
4838 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
4839 the flash bank defined at address 0x1fc00000. Any cmds executed on
4840 the virtual banks are actually performed on the physical banks.
4842 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
4843 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
4844 $_TARGETNAME $_FLASHNAME
4845 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
4846 $_TARGETNAME $_FLASHNAME
4850 @subsection External Flash
4852 @deffn {Flash Driver} cfi
4853 @cindex Common Flash Interface
4855 The ``Common Flash Interface'' (CFI) is the main standard for
4856 external NOR flash chips, each of which connects to a
4857 specific external chip select on the CPU.
4858 Frequently the first such chip is used to boot the system.
4859 Your board's @code{reset-init} handler might need to
4860 configure additional chip selects using other commands (like: @command{mww} to
4861 configure a bus and its timings), or
4862 perhaps configure a GPIO pin that controls the ``write protect'' pin
4864 The CFI driver can use a target-specific working area to significantly
4867 The CFI driver can accept the following optional parameters, in any order:
4870 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
4871 like AM29LV010 and similar types.
4872 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
4873 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
4874 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
4875 swapped when writing data values (ie. not CFI commands).
4878 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
4879 wide on a sixteen bit bus:
4882 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
4883 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
4886 To configure one bank of 32 MBytes
4887 built from two sixteen bit (two byte) wide parts wired in parallel
4888 to create a thirty-two bit (four byte) bus with doubled throughput:
4891 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
4894 @c "cfi part_id" disabled
4897 @deffn {Flash Driver} jtagspi
4898 @cindex Generic JTAG2SPI driver
4902 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
4903 SPI flash connected to them. To access this flash from the host, the device
4904 is first programmed with a special proxy bitstream that
4905 exposes the SPI flash on the device's JTAG interface. The flash can then be
4906 accessed through JTAG.
4908 Since signaling between JTAG and SPI is compatible, all that is required for
4909 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
4910 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
4911 a bitstream for several Xilinx FPGAs can be found in
4912 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
4913 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
4915 This flash bank driver requires a target on a JTAG tap and will access that
4916 tap directly. Since no support from the target is needed, the target can be a
4917 "testee" dummy. Since the target does not expose the flash memory
4918 mapping, target commands that would otherwise be expected to access the flash
4919 will not work. These include all @command{*_image} and
4920 @command{$target_name m*} commands as well as @command{program}. Equivalent
4921 functionality is available through the @command{flash write_bank},
4922 @command{flash read_bank}, and @command{flash verify_bank} commands.
4925 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
4926 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
4927 @var{USER1} instruction.
4928 @item @var{dr_length} ... is the length of the DR register. This will be 1 for
4929 @file{xilinx_bscan_spi.py} bitstreams and most other cases.
4933 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
4934 set _XILINX_USER1 0x02
4936 flash bank $_FLASHNAME spi 0x0 0 0 0 \
4937 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
4941 @deffn {Flash Driver} lpcspifi
4942 @cindex NXP SPI Flash Interface
4945 NXP's LPC43xx and LPC18xx families include a proprietary SPI
4946 Flash Interface (SPIFI) peripheral that can drive and provide
4947 memory mapped access to external SPI flash devices.
4949 The lpcspifi driver initializes this interface and provides
4950 program and erase functionality for these serial flash devices.
4951 Use of this driver @b{requires} a working area of at least 1kB
4952 to be configured on the target device; more than this will
4953 significantly reduce flash programming times.
4955 The setup command only requires the @var{base} parameter. All
4956 other parameters are ignored, and the flash size and layout
4957 are configured by the driver.
4960 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
4965 @deffn {Flash Driver} stmsmi
4966 @cindex STMicroelectronics Serial Memory Interface
4969 Some devices form STMicroelectronics (e.g. STR75x MCU family,
4970 SPEAr MPU family) include a proprietary
4971 ``Serial Memory Interface'' (SMI) controller able to drive external
4973 Depending on specific device and board configuration, up to 4 external
4974 flash devices can be connected.
4976 SMI makes the flash content directly accessible in the CPU address
4977 space; each external device is mapped in a memory bank.
4978 CPU can directly read data, execute code and boot from SMI banks.
4979 Normal OpenOCD commands like @command{mdw} can be used to display
4982 The setup command only requires the @var{base} parameter in order
4983 to identify the memory bank.
4984 All other parameters are ignored. Additional information, like
4985 flash size, are detected automatically.
4988 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
4993 @deffn {Flash Driver} mrvlqspi
4994 This driver supports QSPI flash controller of Marvell's Wireless
4995 Microcontroller platform.
4997 The flash size is autodetected based on the table of known JEDEC IDs
4998 hardcoded in the OpenOCD sources.
5001 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
5006 @deffn {Flash Driver} ath79
5007 @cindex Atheros ath79 SPI driver
5009 Members of ATH79 SoC family from Atheros include a SPI interface with 3
5011 On reset a SPI flash connected to the first chip select (CS0) is made
5012 directly read-accessible in the CPU address space (up to 16MBytes)
5013 and is usually used to store the bootloader and operating system.
5014 Normal OpenOCD commands like @command{mdw} can be used to display
5015 the flash content while it is in memory-mapped mode (only the first
5016 4MBytes are accessible without additional configuration on reset).
5018 The setup command only requires the @var{base} parameter in order
5019 to identify the memory bank. The actual value for the base address
5020 is not otherwise used by the driver. However the mapping is passed
5021 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
5022 address should be the actual memory mapped base address. For unmapped
5023 chipselects (CS1 and CS2) care should be taken to use a base address
5024 that does not overlap with real memory regions.
5025 Additional information, like flash size, are detected automatically.
5026 An optional additional parameter sets the chipselect for the bank,
5027 with the default CS0.
5028 CS1 and CS2 require additional GPIO setup before they can be used
5029 since the alternate function must be enabled on the GPIO pin
5030 CS1/CS2 is routed to on the given SoC.
5033 flash bank $_FLASHNAME ath79 0 0 0 0 $_TARGETNAME
5035 # When using multiple chipselects the base should be different for each,
5036 # otherwise the write_image command is not able to distinguish the
5038 flash bank flash0 ath79 0x00000000 0 0 0 $_TARGETNAME cs0
5039 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
5040 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
5045 @subsection Internal Flash (Microcontrollers)
5047 @deffn {Flash Driver} aduc702x
5048 The ADUC702x analog microcontrollers from Analog Devices
5049 include internal flash and use ARM7TDMI cores.
5050 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
5051 The setup command only requires the @var{target} argument
5052 since all devices in this family have the same memory layout.
5055 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
5059 @deffn {Flash Driver} ambiqmicro
5062 All members of the Apollo microcontroller family from
5063 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
5064 The host connects over USB to an FTDI interface that communicates
5065 with the target using SWD.
5067 The @var{ambiqmicro} driver reads the Chip Information Register detect
5068 the device class of the MCU.
5069 The Flash and Sram sizes directly follow device class, and are used
5070 to set up the flash banks.
5071 If this fails, the driver will use default values set to the minimum
5072 sizes of an Apollo chip.
5074 All Apollo chips have two flash banks of the same size.
5075 In all cases the first flash bank starts at location 0,
5076 and the second bank starts after the first.
5080 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
5081 # Flash bank 1 - same size as bank0, starts after bank 0.
5082 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
5086 Flash is programmed using custom entry points into the bootloader.
5087 This is the only way to program the flash as no flash control registers
5088 are available to the user.
5090 The @var{ambiqmicro} driver adds some additional commands:
5092 @deffn Command {ambiqmicro mass_erase} <bank>
5095 @deffn Command {ambiqmicro page_erase} <bank> <first> <last>
5098 @deffn Command {ambiqmicro program_otp} <bank> <offset> <count>
5099 Program OTP is a one time operation to create write protected flash.
5100 The user writes sectors to sram starting at 0x10000010.
5101 Program OTP will write these sectors from sram to flash, and write protect
5107 @deffn {Flash Driver} at91samd
5109 All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller
5110 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
5111 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5113 @deffn Command {at91samd chip-erase}
5114 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
5115 used to erase a chip back to its factory state and does not require the
5116 processor to be halted.
5119 @deffn Command {at91samd set-security}
5120 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
5121 to the Flash and can only be undone by using the chip-erase command which
5122 erases the Flash contents and turns off the security bit. Warning: at this
5123 time, openocd will not be able to communicate with a secured chip and it is
5124 therefore not possible to chip-erase it without using another tool.
5127 at91samd set-security enable
5131 @deffn Command {at91samd eeprom}
5132 Shows or sets the EEPROM emulation size configuration, stored in the User Row
5133 of the Flash. When setting, the EEPROM size must be specified in bytes and it
5134 must be one of the permitted sizes according to the datasheet. Settings are
5135 written immediately but only take effect on MCU reset. EEPROM emulation
5136 requires additional firmware support and the minumum EEPROM size may not be
5137 the same as the minimum that the hardware supports. Set the EEPROM size to 0
5138 in order to disable this feature.
5142 at91samd eeprom 1024
5146 @deffn Command {at91samd bootloader}
5147 Shows or sets the bootloader size configuration, stored in the User Row of the
5148 Flash. This is called the BOOTPROT region. When setting, the bootloader size
5149 must be specified in bytes and it must be one of the permitted sizes according
5150 to the datasheet. Settings are written immediately but only take effect on
5151 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
5155 at91samd bootloader 16384
5159 @deffn Command {at91samd dsu_reset_deassert}
5160 This command releases internal reset held by DSU
5161 and prepares reset vector catch in case of reset halt.
5162 Command is used internally in event event reset-deassert-post.
5168 @deffn {Flash Driver} at91sam3
5170 All members of the AT91SAM3 microcontroller family from
5171 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
5172 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
5173 that the driver was orginaly developed and tested using the
5174 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
5175 the family was cribbed from the data sheet. @emph{Note to future
5176 readers/updaters: Please remove this worrysome comment after other
5177 chips are confirmed.}
5179 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
5180 have one flash bank. In all cases the flash banks are at
5181 the following fixed locations:
5184 # Flash bank 0 - all chips
5185 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
5186 # Flash bank 1 - only 256K chips
5187 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
5190 Internally, the AT91SAM3 flash memory is organized as follows.
5191 Unlike the AT91SAM7 chips, these are not used as parameters
5192 to the @command{flash bank} command:
5195 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
5196 @item @emph{Bank Size:} 128K/64K Per flash bank
5197 @item @emph{Sectors:} 16 or 8 per bank
5198 @item @emph{SectorSize:} 8K Per Sector
5199 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
5202 The AT91SAM3 driver adds some additional commands:
5204 @deffn Command {at91sam3 gpnvm}
5205 @deffnx Command {at91sam3 gpnvm clear} number
5206 @deffnx Command {at91sam3 gpnvm set} number
5207 @deffnx Command {at91sam3 gpnvm show} [@option{all}|number]
5208 With no parameters, @command{show} or @command{show all},
5209 shows the status of all GPNVM bits.
5210 With @command{show} @var{number}, displays that bit.
5212 With @command{set} @var{number} or @command{clear} @var{number},
5213 modifies that GPNVM bit.
5216 @deffn Command {at91sam3 info}
5217 This command attempts to display information about the AT91SAM3
5218 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
5219 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
5220 document id: doc6430A] and decodes the values. @emph{Second} it reads the
5221 various clock configuration registers and attempts to display how it
5222 believes the chip is configured. By default, the SLOWCLK is assumed to
5223 be 32768 Hz, see the command @command{at91sam3 slowclk}.
5226 @deffn Command {at91sam3 slowclk} [value]
5227 This command shows/sets the slow clock frequency used in the
5228 @command{at91sam3 info} command calculations above.
5232 @deffn {Flash Driver} at91sam4
5234 All members of the AT91SAM4 microcontroller family from
5235 Atmel include internal flash and use ARM's Cortex-M4 core.
5236 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5239 @deffn {Flash Driver} at91sam4l
5241 All members of the AT91SAM4L microcontroller family from
5242 Atmel include internal flash and use ARM's Cortex-M4 core.
5243 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5245 The AT91SAM4L driver adds some additional commands:
5246 @deffn Command {at91sam4l smap_reset_deassert}
5247 This command releases internal reset held by SMAP
5248 and prepares reset vector catch in case of reset halt.
5249 Command is used internally in event event reset-deassert-post.
5253 @deffn {Flash Driver} atsamv
5255 All members of the ATSAMV, ATSAMS, and ATSAME families from
5256 Atmel include internal flash and use ARM's Cortex-M7 core.
5257 This driver uses the same cmd names/syntax as @xref{at91sam3}.
5260 @deffn {Flash Driver} at91sam7
5261 All members of the AT91SAM7 microcontroller family from Atmel include
5262 internal flash and use ARM7TDMI cores. The driver automatically
5263 recognizes a number of these chips using the chip identification
5264 register, and autoconfigures itself.
5267 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
5270 For chips which are not recognized by the controller driver, you must
5271 provide additional parameters in the following order:
5274 @item @var{chip_model} ... label used with @command{flash info}
5276 @item @var{sectors_per_bank}
5277 @item @var{pages_per_sector}
5278 @item @var{pages_size}
5279 @item @var{num_nvm_bits}
5280 @item @var{freq_khz} ... required if an external clock is provided,
5281 optional (but recommended) when the oscillator frequency is known
5284 It is recommended that you provide zeroes for all of those values
5285 except the clock frequency, so that everything except that frequency
5286 will be autoconfigured.
5287 Knowing the frequency helps ensure correct timings for flash access.
5289 The flash controller handles erases automatically on a page (128/256 byte)
5290 basis, so explicit erase commands are not necessary for flash programming.
5291 However, there is an ``EraseAll`` command that can erase an entire flash
5292 plane (of up to 256KB), and it will be used automatically when you issue
5293 @command{flash erase_sector} or @command{flash erase_address} commands.
5295 @deffn Command {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
5296 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
5297 bit for the processor. Each processor has a number of such bits,
5298 used for controlling features such as brownout detection (so they
5299 are not truly general purpose).
5301 This assumes that the first flash bank (number 0) is associated with
5302 the appropriate at91sam7 target.
5307 @deffn {Flash Driver} avr
5308 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
5309 @emph{The current implementation is incomplete.}
5310 @comment - defines mass_erase ... pointless given flash_erase_address
5313 @deffn {Flash Driver} efm32
5314 All members of the EFM32 microcontroller family from Energy Micro include
5315 internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
5316 a number of these chips using the chip identification register, and
5317 autoconfigures itself.
5319 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
5321 A special feature of efm32 controllers is that it is possible to completely disable the
5322 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
5323 this via the following command:
5327 The @var{num} parameter is a value shown by @command{flash banks}.
5328 Note that in order for this command to take effect, the target needs to be reset.
5329 @emph{The current implementation is incomplete. Unprotecting flash pages is not
5333 @deffn {Flash Driver} fm3
5334 All members of the FM3 microcontroller family from Fujitsu
5335 include internal flash and use ARM Cortex-M3 cores.
5336 The @var{fm3} driver uses the @var{target} parameter to select the
5337 correct bank config, it can currently be one of the following:
5338 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
5339 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
5342 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
5346 @deffn {Flash Driver} fm4
5347 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
5348 include internal flash and use ARM Cortex-M4 cores.
5349 The @var{fm4} driver uses a @var{family} parameter to select the
5350 correct bank config, it can currently be one of the following:
5351 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
5352 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
5353 with @code{x} treated as wildcard and otherwise case (and any trailing
5354 characters) ignored.
5357 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
5358 $_TARGETNAME S6E2CCAJ0A
5359 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
5360 $_TARGETNAME S6E2CCAJ0A
5362 @emph{The current implementation is incomplete. Protection is not supported,
5363 nor is Chip Erase (only Sector Erase is implemented).}
5366 @deffn {Flash Driver} kinetis
5368 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
5369 from NXP (former Freescale) include
5370 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
5371 recognizes flash size and a number of flash banks (1-4) using the chip
5372 identification register, and autoconfigures itself.
5373 Use kinetis_ke driver for KE0x devices.
5375 The @var{kinetis} driver defines option:
5377 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
5381 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
5384 @deffn Command {kinetis create_banks}
5385 Configuration command enables automatic creation of additional flash banks
5386 based on real flash layout of device. Banks are created during device probe.
5387 Use 'flash probe 0' to force probe.
5390 @deffn Command {kinetis fcf_source} [protection|write]
5391 Select what source is used when writing to a Flash Configuration Field.
5392 @option{protection} mode builds FCF content from protection bits previously
5393 set by 'flash protect' command.
5394 This mode is default. MCU is protected from unwanted locking by immediate
5395 writing FCF after erase of relevant sector.
5396 @option{write} mode enables direct write to FCF.
5397 Protection cannot be set by 'flash protect' command. FCF is written along
5398 with the rest of a flash image.
5399 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
5402 @deffn Command {kinetis fopt} [num]
5403 Set value to write to FOPT byte of Flash Configuration Field.
5404 Used in kinetis 'fcf_source protection' mode only.
5407 @deffn Command {kinetis mdm check_security}
5408 Checks status of device security lock. Used internally in examine-end event.
5411 @deffn Command {kinetis mdm halt}
5412 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
5413 loop when connecting to an unsecured target.
5416 @deffn Command {kinetis mdm mass_erase}
5417 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
5418 back to its factory state, removing security. It does not require the processor
5419 to be halted, however the target will remain in a halted state after this
5423 @deffn Command {kinetis nvm_partition}
5424 For FlexNVM devices only (KxxDX and KxxFX).
5425 Command shows or sets data flash or EEPROM backup size in kilobytes,
5426 sets two EEPROM blocks sizes in bytes and enables/disables loading
5427 of EEPROM contents to FlexRAM during reset.
5429 For details see device reference manual, Flash Memory Module,
5430 Program Partition command.
5432 Setting is possible only once after mass_erase.
5433 Reset the device after partition setting.
5435 Show partition size:
5437 kinetis nvm_partition info
5440 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
5441 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
5443 kinetis nvm_partition dataflash 32 512 1536 on
5446 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
5447 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
5449 kinetis nvm_partition eebkp 16 1024 1024 off
5453 @deffn Command {kinetis mdm reset}
5454 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
5455 RESET pin, which can be used to reset other hardware on board.
5458 @deffn Command {kinetis disable_wdog}
5459 For Kx devices only (KLx has different COP watchdog, it is not supported).
5460 Command disables watchdog timer.
5464 @deffn {Flash Driver} kinetis_ke
5466 KE0x members of the Kinetis microcontroller family from Freescale include
5467 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
5468 the KE0x sub-family using the chip identification register, and
5469 autoconfigures itself.
5470 Use kinetis (not kinetis_ke) driver for KE1x devices.
5473 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
5476 @deffn Command {kinetis_ke mdm check_security}
5477 Checks status of device security lock. Used internally in examine-end event.
5480 @deffn Command {kinetis_ke mdm mass_erase}
5481 Issues a complete Flash erase via the MDM-AP.
5482 This can be used to erase a chip back to its factory state.
5483 Command removes security lock from a device (use of SRST highly recommended).
5484 It does not require the processor to be halted.
5487 @deffn Command {kinetis_ke disable_wdog}
5488 Command disables watchdog timer.
5492 @deffn {Flash Driver} lpc2000
5493 This is the driver to support internal flash of all members of the
5494 LPC11(x)00 and LPC1300 microcontroller families and most members of
5495 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
5496 microcontroller families from NXP.
5499 There are LPC2000 devices which are not supported by the @var{lpc2000}
5501 The LPC2888 is supported by the @var{lpc288x} driver.
5502 The LPC29xx family is supported by the @var{lpc2900} driver.
5505 The @var{lpc2000} driver defines two mandatory and one optional parameters,
5506 which must appear in the following order:
5509 @item @var{variant} ... required, may be
5510 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
5511 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
5512 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
5513 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
5515 @option{lpc800} (LPC8xx)
5516 @option{lpc1100} (LPC11(x)xx and LPC13xx)
5517 @option{lpc1500} (LPC15xx)
5518 @option{lpc54100} (LPC541xx)
5519 @option{lpc4000} (LPC40xx)
5520 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
5521 LPC8xx, LPC13xx, LPC17xx and LPC40xx
5522 @item @var{clock_kHz} ... the frequency, in kiloHertz,
5523 at which the core is running
5524 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
5525 telling the driver to calculate a valid checksum for the exception vector table.
5527 If you don't provide @option{calc_checksum} when you're writing the vector
5528 table, the boot ROM will almost certainly ignore your flash image.
5529 However, if you do provide it,
5530 with most tool chains @command{verify_image} will fail.
5534 LPC flashes don't require the chip and bus width to be specified.
5537 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
5538 lpc2000_v2 14765 calc_checksum
5541 @deffn {Command} {lpc2000 part_id} bank
5542 Displays the four byte part identifier associated with
5543 the specified flash @var{bank}.
5547 @deffn {Flash Driver} lpc288x
5548 The LPC2888 microcontroller from NXP needs slightly different flash
5549 support from its lpc2000 siblings.
5550 The @var{lpc288x} driver defines one mandatory parameter,
5551 the programming clock rate in Hz.
5552 LPC flashes don't require the chip and bus width to be specified.
5555 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
5559 @deffn {Flash Driver} lpc2900
5560 This driver supports the LPC29xx ARM968E based microcontroller family
5563 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
5564 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
5565 sector layout are auto-configured by the driver.
5566 The driver has one additional mandatory parameter: The CPU clock rate
5567 (in kHz) at the time the flash operations will take place. Most of the time this
5568 will not be the crystal frequency, but a higher PLL frequency. The
5569 @code{reset-init} event handler in the board script is usually the place where
5572 The driver rejects flashless devices (currently the LPC2930).
5574 The EEPROM in LPC2900 devices is not mapped directly into the address space.
5575 It must be handled much more like NAND flash memory, and will therefore be
5576 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
5578 Sector protection in terms of the LPC2900 is handled transparently. Every time a
5579 sector needs to be erased or programmed, it is automatically unprotected.
5580 What is shown as protection status in the @code{flash info} command, is
5581 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
5582 sector from ever being erased or programmed again. As this is an irreversible
5583 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
5584 and not by the standard @code{flash protect} command.
5586 Example for a 125 MHz clock frequency:
5588 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
5591 Some @code{lpc2900}-specific commands are defined. In the following command list,
5592 the @var{bank} parameter is the bank number as obtained by the
5593 @code{flash banks} command.
5595 @deffn Command {lpc2900 signature} bank
5596 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
5597 content. This is a hardware feature of the flash block, hence the calculation is
5598 very fast. You may use this to verify the content of a programmed device against
5603 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
5607 @deffn Command {lpc2900 read_custom} bank filename
5608 Reads the 912 bytes of customer information from the flash index sector, and
5609 saves it to a file in binary format.
5612 lpc2900 read_custom 0 /path_to/customer_info.bin
5616 The index sector of the flash is a @emph{write-only} sector. It cannot be
5617 erased! In order to guard against unintentional write access, all following
5618 commands need to be preceeded by a successful call to the @code{password}
5621 @deffn Command {lpc2900 password} bank password
5622 You need to use this command right before each of the following commands:
5623 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
5624 @code{lpc2900 secure_jtag}.
5626 The password string is fixed to "I_know_what_I_am_doing".
5629 lpc2900 password 0 I_know_what_I_am_doing
5630 Potentially dangerous operation allowed in next command!
5634 @deffn Command {lpc2900 write_custom} bank filename type
5635 Writes the content of the file into the customer info space of the flash index
5636 sector. The filetype can be specified with the @var{type} field. Possible values
5637 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
5638 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
5639 contain a single section, and the contained data length must be exactly
5641 @quotation Attention
5642 This cannot be reverted! Be careful!
5646 lpc2900 write_custom 0 /path_to/customer_info.bin bin
5650 @deffn Command {lpc2900 secure_sector} bank first last
5651 Secures the sector range from @var{first} to @var{last} (including) against
5652 further program and erase operations. The sector security will be effective
5653 after the next power cycle.
5654 @quotation Attention
5655 This cannot be reverted! Be careful!
5657 Secured sectors appear as @emph{protected} in the @code{flash info} command.
5660 lpc2900 secure_sector 0 1 1
5662 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
5663 # 0: 0x00000000 (0x2000 8kB) not protected
5664 # 1: 0x00002000 (0x2000 8kB) protected
5665 # 2: 0x00004000 (0x2000 8kB) not protected
5669 @deffn Command {lpc2900 secure_jtag} bank
5670 Irreversibly disable the JTAG port. The new JTAG security setting will be
5671 effective after the next power cycle.
5672 @quotation Attention
5673 This cannot be reverted! Be careful!
5677 lpc2900 secure_jtag 0
5682 @deffn {Flash Driver} mdr
5683 This drivers handles the integrated NOR flash on Milandr Cortex-M
5684 based controllers. A known limitation is that the Info memory can't be
5685 read or verified as it's not memory mapped.
5688 flash bank <name> mdr <base> <size> \
5689 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
5693 @item @var{type} - 0 for main memory, 1 for info memory
5694 @item @var{page_count} - total number of pages
5695 @item @var{sec_count} - number of sector per page count
5700 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
5701 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
5702 0 0 $_TARGETNAME 1 1 4
5704 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
5705 0 0 $_TARGETNAME 0 32 4
5710 @deffn {Flash Driver} niietcm4
5711 This drivers handles the integrated NOR flash on NIIET Cortex-M4
5712 based controllers. Flash size and sector layout are auto-configured by the driver.
5713 Main flash memory is called "Bootflash" and has main region and info region.
5714 Info region is NOT memory mapped by default,
5715 but it can replace first part of main region if needed.
5716 Full erase, single and block writes are supported for both main and info regions.
5717 There is additional not memory mapped flash called "Userflash", which
5718 also have division into regions: main and info.
5719 Purpose of userflash - to store system and user settings.
5720 Driver has special commands to perform operations with this memmory.
5723 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
5726 Some niietcm4-specific commands are defined:
5728 @deffn Command {niietcm4 uflash_read_byte} bank ('main'|'info') address
5729 Read byte from main or info userflash region.
5732 @deffn Command {niietcm4 uflash_write_byte} bank ('main'|'info') address value
5733 Write byte to main or info userflash region.
5736 @deffn Command {niietcm4 uflash_full_erase} bank
5737 Erase all userflash including info region.
5740 @deffn Command {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
5741 Erase sectors of main or info userflash region, starting at sector first up to and including last.
5744 @deffn Command {niietcm4 uflash_protect_check} bank ('main'|'info')
5745 Check sectors protect.
5748 @deffn Command {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
5749 Protect sectors of main or info userflash region, starting at sector first up to and including last.
5752 @deffn Command {niietcm4 bflash_info_remap} bank ('on'|'off')
5753 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
5756 @deffn Command {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
5757 Configure external memory interface for boot.
5760 @deffn Command {niietcm4 service_mode_erase} bank
5761 Perform emergency erase of all flash (bootflash and userflash).
5764 @deffn Command {niietcm4 driver_info} bank
5765 Show information about flash driver.
5770 @deffn {Flash Driver} nrf5
5771 All members of the nRF51 microcontroller families from Nordic Semiconductor
5772 include internal flash and use ARM Cortex-M0 core.
5773 Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
5774 internal flash and use an ARM Cortex-M4F core.
5777 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
5780 Some nrf5-specific commands are defined:
5782 @deffn Command {nrf5 mass_erase}
5783 Erases the contents of the code memory and user information
5784 configuration registers as well. It must be noted that this command
5785 works only for chips that do not have factory pre-programmed region 0
5791 @deffn {Flash Driver} ocl
5792 This driver is an implementation of the ``on chip flash loader''
5793 protocol proposed by Pavel Chromy.
5795 It is a minimalistic command-response protocol intended to be used
5796 over a DCC when communicating with an internal or external flash
5797 loader running from RAM. An example implementation for AT91SAM7x is
5798 available in @file{contrib/loaders/flash/at91sam7x/}.
5801 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
5805 @deffn {Flash Driver} pic32mx
5806 The PIC32MX microcontrollers are based on the MIPS 4K cores,
5807 and integrate flash memory.
5810 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
5811 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
5814 @comment numerous *disabled* commands are defined:
5815 @comment - chip_erase ... pointless given flash_erase_address
5816 @comment - lock, unlock ... pointless given protect on/off (yes?)
5817 @comment - pgm_word ... shouldn't bank be deduced from address??
5818 Some pic32mx-specific commands are defined:
5819 @deffn Command {pic32mx pgm_word} address value bank
5820 Programs the specified 32-bit @var{value} at the given @var{address}
5821 in the specified chip @var{bank}.
5823 @deffn Command {pic32mx unlock} bank
5824 Unlock and erase specified chip @var{bank}.
5825 This will remove any Code Protection.
5829 @deffn {Flash Driver} psoc4
5830 All members of the PSoC 41xx/42xx microcontroller family from Cypress
5831 include internal flash and use ARM Cortex-M0 cores.
5832 The driver automatically recognizes a number of these chips using
5833 the chip identification register, and autoconfigures itself.
5835 Note: Erased internal flash reads as 00.
5836 System ROM of PSoC 4 does not implement erase of a flash sector.
5839 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
5842 psoc4-specific commands
5843 @deffn Command {psoc4 flash_autoerase} num (on|off)
5844 Enables or disables autoerase mode for a flash bank.
5846 If flash_autoerase is off, use mass_erase before flash programming.
5847 Flash erase command fails if region to erase is not whole flash memory.
5849 If flash_autoerase is on, a sector is both erased and programmed in one
5850 system ROM call. Flash erase command is ignored.
5851 This mode is suitable for gdb load.
5853 The @var{num} parameter is a value shown by @command{flash banks}.
5856 @deffn Command {psoc4 mass_erase} num
5857 Erases the contents of the flash memory, protection and security lock.
5859 The @var{num} parameter is a value shown by @command{flash banks}.
5863 @deffn {Flash Driver} sim3x
5864 All members of the SiM3 microcontroller family from Silicon Laboratories
5865 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
5867 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
5868 If this failes, it will use the @var{size} parameter as the size of flash bank.
5871 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
5874 There are 2 commands defined in the @var{sim3x} driver:
5876 @deffn Command {sim3x mass_erase}
5877 Erases the complete flash. This is used to unlock the flash.
5878 And this command is only possible when using the SWD interface.
5881 @deffn Command {sim3x lock}
5882 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
5886 @deffn {Flash Driver} stellaris
5887 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
5888 families from Texas Instruments include internal flash. The driver
5889 automatically recognizes a number of these chips using the chip
5890 identification register, and autoconfigures itself.
5893 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
5896 @deffn Command {stellaris recover}
5897 Performs the @emph{Recovering a "Locked" Device} procedure to restore
5898 the flash and its associated nonvolatile registers to their factory
5899 default values (erased). This is the only way to remove flash
5900 protection or re-enable debugging if that capability has been
5903 Note that the final "power cycle the chip" step in this procedure
5904 must be performed by hand, since OpenOCD can't do it.
5906 if more than one Stellaris chip is connected, the procedure is
5907 applied to all of them.
5912 @deffn {Flash Driver} stm32f1x
5913 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
5914 from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores.
5915 The driver automatically recognizes a number of these chips using
5916 the chip identification register, and autoconfigures itself.
5919 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
5922 Note that some devices have been found that have a flash size register that contains
5923 an invalid value, to workaround this issue you can override the probed value used by
5927 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
5930 If you have a target with dual flash banks then define the second bank
5931 as per the following example.
5933 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
5936 Some stm32f1x-specific commands are defined:
5938 @deffn Command {stm32f1x lock} num
5939 Locks the entire stm32 device.
5940 The @var{num} parameter is a value shown by @command{flash banks}.
5943 @deffn Command {stm32f1x unlock} num
5944 Unlocks the entire stm32 device.
5945 The @var{num} parameter is a value shown by @command{flash banks}.
5948 @deffn Command {stm32f1x mass_erase} num
5949 Mass erases the entire stm32f1x device.
5950 The @var{num} parameter is a value shown by @command{flash banks}.
5953 @deffn Command {stm32f1x options_read} num
5954 Read and display the stm32 option bytes written by
5955 the @command{stm32f1x options_write} command.
5956 The @var{num} parameter is a value shown by @command{flash banks}.
5959 @deffn Command {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP})
5960 Writes the stm32 option byte with the specified values.
5961 The @var{num} parameter is a value shown by @command{flash banks}.
5965 @deffn {Flash Driver} stm32f2x
5966 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from ST Microelectronics
5967 include internal flash and use ARM Cortex-M3/M4/M7 cores.
5968 The driver automatically recognizes a number of these chips using
5969 the chip identification register, and autoconfigures itself.
5972 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
5975 Note that some devices have been found that have a flash size register that contains
5976 an invalid value, to workaround this issue you can override the probed value used by
5980 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
5983 Some stm32f2x-specific commands are defined:
5985 @deffn Command {stm32f2x lock} num
5986 Locks the entire stm32 device.
5987 The @var{num} parameter is a value shown by @command{flash banks}.
5990 @deffn Command {stm32f2x unlock} num
5991 Unlocks the entire stm32 device.
5992 The @var{num} parameter is a value shown by @command{flash banks}.
5995 @deffn Command {stm32f2x mass_erase} num
5996 Mass erases the entire stm32f2x device.
5997 The @var{num} parameter is a value shown by @command{flash banks}.
6000 @deffn Command {stm32f2x options_read} num
6001 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
6002 The @var{num} parameter is a value shown by @command{flash banks}.
6005 @deffn Command {stm32f2x options_write} num user_options boot_addr0 boot_addr1
6006 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
6007 Warning: The meaning of the various bits depends on the device, always check datasheet!
6008 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
6009 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
6010 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
6013 @deffn Command {stm32f2x optcr2_write} num optcr2
6014 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
6015 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
6019 @deffn {Flash Driver} stm32h7x
6020 All members of the STM32H7 microcontroller families from ST Microelectronics
6021 include internal flash and use ARM Cortex-M7 core.
6022 The driver automatically recognizes a number of these chips using
6023 the chip identification register, and autoconfigures itself.
6026 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
6029 Note that some devices have been found that have a flash size register that contains
6030 an invalid value, to workaround this issue you can override the probed value used by
6034 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
6037 Some stm32h7x-specific commands are defined:
6039 @deffn Command {stm32h7x lock} num
6040 Locks the entire stm32 device.
6041 The @var{num} parameter is a value shown by @command{flash banks}.
6044 @deffn Command {stm32h7x unlock} num
6045 Unlocks the entire stm32 device.
6046 The @var{num} parameter is a value shown by @command{flash banks}.
6049 @deffn Command {stm32h7x mass_erase} num
6050 Mass erases the entire stm32h7x device.
6051 The @var{num} parameter is a value shown by @command{flash banks}.
6055 @deffn {Flash Driver} stm32lx
6056 All members of the STM32L microcontroller families from ST Microelectronics
6057 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
6058 The driver automatically recognizes a number of these chips using
6059 the chip identification register, and autoconfigures itself.
6062 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
6065 Note that some devices have been found that have a flash size register that contains
6066 an invalid value, to workaround this issue you can override the probed value used by
6067 the flash driver. If you use 0 as the bank base address, it tells the
6068 driver to autodetect the bank location assuming you're configuring the
6072 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
6075 Some stm32lx-specific commands are defined:
6077 @deffn Command {stm32lx lock} num
6078 Locks the entire stm32 device.
6079 The @var{num} parameter is a value shown by @command{flash banks}.
6082 @deffn Command {stm32lx unlock} num
6083 Unlocks the entire stm32 device.
6084 The @var{num} parameter is a value shown by @command{flash banks}.
6087 @deffn Command {stm32lx mass_erase} num
6088 Mass erases the entire stm32lx device (all flash banks and EEPROM
6089 data). This is the only way to unlock a protected flash (unless RDP
6090 Level is 2 which can't be unlocked at all).
6091 The @var{num} parameter is a value shown by @command{flash banks}.
6095 @deffn {Flash Driver} stm32l4x
6096 All members of the STM32L4 microcontroller families from ST Microelectronics
6097 include internal flash and use ARM Cortex-M4 cores.
6098 The driver automatically recognizes a number of these chips using
6099 the chip identification register, and autoconfigures itself.
6102 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
6105 Note that some devices have been found that have a flash size register that contains
6106 an invalid value, to workaround this issue you can override the probed value used by
6110 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
6113 Some stm32l4x-specific commands are defined:
6115 @deffn Command {stm32l4x lock} num
6116 Locks the entire stm32 device.
6117 The @var{num} parameter is a value shown by @command{flash banks}.
6120 @deffn Command {stm32l4x unlock} num
6121 Unlocks the entire stm32 device.
6122 The @var{num} parameter is a value shown by @command{flash banks}.
6125 @deffn Command {stm32l4x mass_erase} num
6126 Mass erases the entire stm32l4x device.
6127 The @var{num} parameter is a value shown by @command{flash banks}.
6131 @deffn {Flash Driver} str7x
6132 All members of the STR7 microcontroller family from ST Microelectronics
6133 include internal flash and use ARM7TDMI cores.
6134 The @var{str7x} driver defines one mandatory parameter, @var{variant},
6135 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
6138 flash bank $_FLASHNAME str7x \
6139 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
6142 @deffn Command {str7x disable_jtag} bank
6143 Activate the Debug/Readout protection mechanism
6144 for the specified flash bank.
6148 @deffn {Flash Driver} str9x
6149 Most members of the STR9 microcontroller family from ST Microelectronics
6150 include internal flash and use ARM966E cores.
6151 The str9 needs the flash controller to be configured using
6152 the @command{str9x flash_config} command prior to Flash programming.
6155 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
6156 str9x flash_config 0 4 2 0 0x80000
6159 @deffn Command {str9x flash_config} num bbsr nbbsr bbadr nbbadr
6160 Configures the str9 flash controller.
6161 The @var{num} parameter is a value shown by @command{flash banks}.
6164 @item @var{bbsr} - Boot Bank Size register
6165 @item @var{nbbsr} - Non Boot Bank Size register
6166 @item @var{bbadr} - Boot Bank Start Address register
6167 @item @var{nbbadr} - Boot Bank Start Address register
6173 @deffn {Flash Driver} str9xpec
6176 Only use this driver for locking/unlocking the device or configuring the option bytes.
6177 Use the standard str9 driver for programming.
6178 Before using the flash commands the turbo mode must be enabled using the
6179 @command{str9xpec enable_turbo} command.
6181 Here is some background info to help
6182 you better understand how this driver works. OpenOCD has two flash drivers for
6186 Standard driver @option{str9x} programmed via the str9 core. Normally used for
6187 flash programming as it is faster than the @option{str9xpec} driver.
6189 Direct programming @option{str9xpec} using the flash controller. This is an
6190 ISC compilant (IEEE 1532) tap connected in series with the str9 core. The str9
6191 core does not need to be running to program using this flash driver. Typical use
6192 for this driver is locking/unlocking the target and programming the option bytes.
6195 Before we run any commands using the @option{str9xpec} driver we must first disable
6196 the str9 core. This example assumes the @option{str9xpec} driver has been
6197 configured for flash bank 0.
6199 # assert srst, we do not want core running
6200 # while accessing str9xpec flash driver
6202 # turn off target polling
6205 str9xpec enable_turbo 0
6207 str9xpec options_read 0
6208 # re-enable str9 core
6209 str9xpec disable_turbo 0
6213 The above example will read the str9 option bytes.
6214 When performing a unlock remember that you will not be able to halt the str9 - it
6215 has been locked. Halting the core is not required for the @option{str9xpec} driver
6216 as mentioned above, just issue the commands above manually or from a telnet prompt.
6218 Several str9xpec-specific commands are defined:
6220 @deffn Command {str9xpec disable_turbo} num
6221 Restore the str9 into JTAG chain.
6224 @deffn Command {str9xpec enable_turbo} num
6225 Enable turbo mode, will simply remove the str9 from the chain and talk
6226 directly to the embedded flash controller.
6229 @deffn Command {str9xpec lock} num
6230 Lock str9 device. The str9 will only respond to an unlock command that will
6234 @deffn Command {str9xpec part_id} num
6235 Prints the part identifier for bank @var{num}.
6238 @deffn Command {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
6239 Configure str9 boot bank.
6242 @deffn Command {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
6243 Configure str9 lvd source.
6246 @deffn Command {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
6247 Configure str9 lvd threshold.
6250 @deffn Command {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
6251 Configure str9 lvd reset warning source.
6254 @deffn Command {str9xpec options_read} num
6255 Read str9 option bytes.
6258 @deffn Command {str9xpec options_write} num
6259 Write str9 option bytes.
6262 @deffn Command {str9xpec unlock} num
6268 @deffn {Flash Driver} tms470
6269 Most members of the TMS470 microcontroller family from Texas Instruments
6270 include internal flash and use ARM7TDMI cores.
6271 This driver doesn't require the chip and bus width to be specified.
6273 Some tms470-specific commands are defined:
6275 @deffn Command {tms470 flash_keyset} key0 key1 key2 key3
6276 Saves programming keys in a register, to enable flash erase and write commands.
6279 @deffn Command {tms470 osc_mhz} clock_mhz
6280 Reports the clock speed, which is used to calculate timings.
6283 @deffn Command {tms470 plldis} (0|1)
6284 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
6289 @deffn {Flash Driver} xmc1xxx
6290 All members of the XMC1xxx microcontroller family from Infineon.
6291 This driver does not require the chip and bus width to be specified.
6294 @deffn {Flash Driver} xmc4xxx
6295 All members of the XMC4xxx microcontroller family from Infineon.
6296 This driver does not require the chip and bus width to be specified.
6298 Some xmc4xxx-specific commands are defined:
6300 @deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2
6301 Saves flash protection passwords which are used to lock the user flash
6304 @deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1]
6305 Removes Flash write protection from the selected user bank
6310 @section NAND Flash Commands
6313 Compared to NOR or SPI flash, NAND devices are inexpensive
6314 and high density. Today's NAND chips, and multi-chip modules,
6315 commonly hold multiple GigaBytes of data.
6317 NAND chips consist of a number of ``erase blocks'' of a given
6318 size (such as 128 KBytes), each of which is divided into a
6319 number of pages (of perhaps 512 or 2048 bytes each). Each
6320 page of a NAND flash has an ``out of band'' (OOB) area to hold
6321 Error Correcting Code (ECC) and other metadata, usually 16 bytes
6322 of OOB for every 512 bytes of page data.
6324 One key characteristic of NAND flash is that its error rate
6325 is higher than that of NOR flash. In normal operation, that
6326 ECC is used to correct and detect errors. However, NAND
6327 blocks can also wear out and become unusable; those blocks
6328 are then marked "bad". NAND chips are even shipped from the
6329 manufacturer with a few bad blocks. The highest density chips
6330 use a technology (MLC) that wears out more quickly, so ECC
6331 support is increasingly important as a way to detect blocks
6332 that have begun to fail, and help to preserve data integrity
6333 with techniques such as wear leveling.
6335 Software is used to manage the ECC. Some controllers don't
6336 support ECC directly; in those cases, software ECC is used.
6337 Other controllers speed up the ECC calculations with hardware.
6338 Single-bit error correction hardware is routine. Controllers
6339 geared for newer MLC chips may correct 4 or more errors for
6340 every 512 bytes of data.
6342 You will need to make sure that any data you write using
6343 OpenOCD includes the apppropriate kind of ECC. For example,
6344 that may mean passing the @code{oob_softecc} flag when
6345 writing NAND data, or ensuring that the correct hardware
6348 The basic steps for using NAND devices include:
6350 @item Declare via the command @command{nand device}
6351 @* Do this in a board-specific configuration file,
6352 passing parameters as needed by the controller.
6353 @item Configure each device using @command{nand probe}.
6354 @* Do this only after the associated target is set up,
6355 such as in its reset-init script or in procures defined
6356 to access that device.
6357 @item Operate on the flash via @command{nand subcommand}
6358 @* Often commands to manipulate the flash are typed by a human, or run
6359 via a script in some automated way. Common task include writing a
6360 boot loader, operating system, or other data needed to initialize or
6364 @b{NOTE:} At the time this text was written, the largest NAND
6365 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
6366 This is because the variables used to hold offsets and lengths
6367 are only 32 bits wide.
6368 (Larger chips may work in some cases, unless an offset or length
6369 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
6370 Some larger devices will work, since they are actually multi-chip
6371 modules with two smaller chips and individual chipselect lines.
6373 @anchor{nandconfiguration}
6374 @subsection NAND Configuration Commands
6375 @cindex NAND configuration
6377 NAND chips must be declared in configuration scripts,
6378 plus some additional configuration that's done after
6379 OpenOCD has initialized.
6381 @deffn {Config Command} {nand device} name driver target [configparams...]
6382 Declares a NAND device, which can be read and written to
6383 after it has been configured through @command{nand probe}.
6384 In OpenOCD, devices are single chips; this is unlike some
6385 operating systems, which may manage multiple chips as if
6386 they were a single (larger) device.
6387 In some cases, configuring a device will activate extra
6388 commands; see the controller-specific documentation.
6390 @b{NOTE:} This command is not available after OpenOCD
6391 initialization has completed. Use it in board specific
6392 configuration files, not interactively.
6395 @item @var{name} ... may be used to reference the NAND bank
6396 in most other NAND commands. A number is also available.
6397 @item @var{driver} ... identifies the NAND controller driver
6398 associated with the NAND device being declared.
6399 @xref{nanddriverlist,,NAND Driver List}.
6400 @item @var{target} ... names the target used when issuing
6401 commands to the NAND controller.
6402 @comment Actually, it's currently a controller-specific parameter...
6403 @item @var{configparams} ... controllers may support, or require,
6404 additional parameters. See the controller-specific documentation
6405 for more information.
6409 @deffn Command {nand list}
6410 Prints a summary of each device declared
6411 using @command{nand device}, numbered from zero.
6412 Note that un-probed devices show no details.
6415 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6416 blocksize: 131072, blocks: 8192
6417 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
6418 blocksize: 131072, blocks: 8192
6423 @deffn Command {nand probe} num
6424 Probes the specified device to determine key characteristics
6425 like its page and block sizes, and how many blocks it has.
6426 The @var{num} parameter is the value shown by @command{nand list}.
6427 You must (successfully) probe a device before you can use
6428 it with most other NAND commands.
6431 @subsection Erasing, Reading, Writing to NAND Flash
6433 @deffn Command {nand dump} num filename offset length [oob_option]
6434 @cindex NAND reading
6435 Reads binary data from the NAND device and writes it to the file,
6436 starting at the specified offset.
6437 The @var{num} parameter is the value shown by @command{nand list}.
6439 Use a complete path name for @var{filename}, so you don't depend
6440 on the directory used to start the OpenOCD server.
6442 The @var{offset} and @var{length} must be exact multiples of the
6443 device's page size. They describe a data region; the OOB data
6444 associated with each such page may also be accessed.
6446 @b{NOTE:} At the time this text was written, no error correction
6447 was done on the data that's read, unless raw access was disabled
6448 and the underlying NAND controller driver had a @code{read_page}
6449 method which handled that error correction.
6451 By default, only page data is saved to the specified file.
6452 Use an @var{oob_option} parameter to save OOB data:
6454 @item no oob_* parameter
6455 @*Output file holds only page data; OOB is discarded.
6456 @item @code{oob_raw}
6457 @*Output file interleaves page data and OOB data;
6458 the file will be longer than "length" by the size of the
6459 spare areas associated with each data page.
6460 Note that this kind of "raw" access is different from
6461 what's implied by @command{nand raw_access}, which just
6462 controls whether a hardware-aware access method is used.
6463 @item @code{oob_only}
6464 @*Output file has only raw OOB data, and will
6465 be smaller than "length" since it will contain only the
6466 spare areas associated with each data page.
6470 @deffn Command {nand erase} num [offset length]
6471 @cindex NAND erasing
6472 @cindex NAND programming
6473 Erases blocks on the specified NAND device, starting at the
6474 specified @var{offset} and continuing for @var{length} bytes.
6475 Both of those values must be exact multiples of the device's
6476 block size, and the region they specify must fit entirely in the chip.
6477 If those parameters are not specified,
6478 the whole NAND chip will be erased.
6479 The @var{num} parameter is the value shown by @command{nand list}.
6481 @b{NOTE:} This command will try to erase bad blocks, when told
6482 to do so, which will probably invalidate the manufacturer's bad
6484 For the remainder of the current server session, @command{nand info}
6485 will still report that the block ``is'' bad.
6488 @deffn Command {nand write} num filename offset [option...]
6489 @cindex NAND writing
6490 @cindex NAND programming
6491 Writes binary data from the file into the specified NAND device,
6492 starting at the specified offset. Those pages should already
6493 have been erased; you can't change zero bits to one bits.
6494 The @var{num} parameter is the value shown by @command{nand list}.
6496 Use a complete path name for @var{filename}, so you don't depend
6497 on the directory used to start the OpenOCD server.
6499 The @var{offset} must be an exact multiple of the device's page size.
6500 All data in the file will be written, assuming it doesn't run
6501 past the end of the device.
6502 Only full pages are written, and any extra space in the last
6503 page will be filled with 0xff bytes. (That includes OOB data,
6504 if that's being written.)
6506 @b{NOTE:} At the time this text was written, bad blocks are
6507 ignored. That is, this routine will not skip bad blocks,
6508 but will instead try to write them. This can cause problems.
6510 Provide at most one @var{option} parameter. With some
6511 NAND drivers, the meanings of these parameters may change
6512 if @command{nand raw_access} was used to disable hardware ECC.
6514 @item no oob_* parameter
6515 @*File has only page data, which is written.
6516 If raw acccess is in use, the OOB area will not be written.
6517 Otherwise, if the underlying NAND controller driver has
6518 a @code{write_page} routine, that routine may write the OOB
6519 with hardware-computed ECC data.
6520 @item @code{oob_only}
6521 @*File has only raw OOB data, which is written to the OOB area.
6522 Each page's data area stays untouched. @i{This can be a dangerous
6523 option}, since it can invalidate the ECC data.
6524 You may need to force raw access to use this mode.
6525 @item @code{oob_raw}
6526 @*File interleaves data and OOB data, both of which are written
6527 If raw access is enabled, the data is written first, then the
6529 Otherwise, if the underlying NAND controller driver has
6530 a @code{write_page} routine, that routine may modify the OOB
6531 before it's written, to include hardware-computed ECC data.
6532 @item @code{oob_softecc}
6533 @*File has only page data, which is written.
6534 The OOB area is filled with 0xff, except for a standard 1-bit
6535 software ECC code stored in conventional locations.
6536 You might need to force raw access to use this mode, to prevent
6537 the underlying driver from applying hardware ECC.
6538 @item @code{oob_softecc_kw}
6539 @*File has only page data, which is written.
6540 The OOB area is filled with 0xff, except for a 4-bit software ECC
6541 specific to the boot ROM in Marvell Kirkwood SoCs.
6542 You might need to force raw access to use this mode, to prevent
6543 the underlying driver from applying hardware ECC.
6547 @deffn Command {nand verify} num filename offset [option...]
6548 @cindex NAND verification
6549 @cindex NAND programming
6550 Verify the binary data in the file has been programmed to the
6551 specified NAND device, starting at the specified offset.
6552 The @var{num} parameter is the value shown by @command{nand list}.
6554 Use a complete path name for @var{filename}, so you don't depend
6555 on the directory used to start the OpenOCD server.
6557 The @var{offset} must be an exact multiple of the device's page size.
6558 All data in the file will be read and compared to the contents of the
6559 flash, assuming it doesn't run past the end of the device.
6560 As with @command{nand write}, only full pages are verified, so any extra
6561 space in the last page will be filled with 0xff bytes.
6563 The same @var{options} accepted by @command{nand write},
6564 and the file will be processed similarly to produce the buffers that
6565 can be compared against the contents produced from @command{nand dump}.
6567 @b{NOTE:} This will not work when the underlying NAND controller
6568 driver's @code{write_page} routine must update the OOB with a
6569 hardward-computed ECC before the data is written. This limitation may
6570 be removed in a future release.
6573 @subsection Other NAND commands
6574 @cindex NAND other commands
6576 @deffn Command {nand check_bad_blocks} num [offset length]
6577 Checks for manufacturer bad block markers on the specified NAND
6578 device. If no parameters are provided, checks the whole
6579 device; otherwise, starts at the specified @var{offset} and
6580 continues for @var{length} bytes.
6581 Both of those values must be exact multiples of the device's
6582 block size, and the region they specify must fit entirely in the chip.
6583 The @var{num} parameter is the value shown by @command{nand list}.
6585 @b{NOTE:} Before using this command you should force raw access
6586 with @command{nand raw_access enable} to ensure that the underlying
6587 driver will not try to apply hardware ECC.
6590 @deffn Command {nand info} num
6591 The @var{num} parameter is the value shown by @command{nand list}.
6592 This prints the one-line summary from "nand list", plus for
6593 devices which have been probed this also prints any known
6594 status for each block.
6597 @deffn Command {nand raw_access} num (@option{enable}|@option{disable})
6598 Sets or clears an flag affecting how page I/O is done.
6599 The @var{num} parameter is the value shown by @command{nand list}.
6601 This flag is cleared (disabled) by default, but changing that
6602 value won't affect all NAND devices. The key factor is whether
6603 the underlying driver provides @code{read_page} or @code{write_page}
6604 methods. If it doesn't provide those methods, the setting of
6605 this flag is irrelevant; all access is effectively ``raw''.
6607 When those methods exist, they are normally used when reading
6608 data (@command{nand dump} or reading bad block markers) or
6609 writing it (@command{nand write}). However, enabling
6610 raw access (setting the flag) prevents use of those methods,
6611 bypassing hardware ECC logic.
6612 @i{This can be a dangerous option}, since writing blocks
6613 with the wrong ECC data can cause them to be marked as bad.
6616 @anchor{nanddriverlist}
6617 @subsection NAND Driver List
6618 As noted above, the @command{nand device} command allows
6619 driver-specific options and behaviors.
6620 Some controllers also activate controller-specific commands.
6622 @deffn {NAND Driver} at91sam9
6623 This driver handles the NAND controllers found on AT91SAM9 family chips from
6624 Atmel. It takes two extra parameters: address of the NAND chip;
6625 address of the ECC controller.
6627 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
6629 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
6630 @code{read_page} methods are used to utilize the ECC hardware unless they are
6631 disabled by using the @command{nand raw_access} command. There are four
6632 additional commands that are needed to fully configure the AT91SAM9 NAND
6633 controller. Two are optional; most boards use the same wiring for ALE/CLE:
6634 @deffn Command {at91sam9 cle} num addr_line
6635 Configure the address line used for latching commands. The @var{num}
6636 parameter is the value shown by @command{nand list}.
6638 @deffn Command {at91sam9 ale} num addr_line
6639 Configure the address line used for latching addresses. The @var{num}
6640 parameter is the value shown by @command{nand list}.
6643 For the next two commands, it is assumed that the pins have already been
6644 properly configured for input or output.
6645 @deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
6646 Configure the RDY/nBUSY input from the NAND device. The @var{num}
6647 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6648 is the base address of the PIO controller and @var{pin} is the pin number.
6650 @deffn Command {at91sam9 ce} num pio_base_addr pin
6651 Configure the chip enable input to the NAND device. The @var{num}
6652 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
6653 is the base address of the PIO controller and @var{pin} is the pin number.
6657 @deffn {NAND Driver} davinci
6658 This driver handles the NAND controllers found on DaVinci family
6659 chips from Texas Instruments.
6660 It takes three extra parameters:
6661 address of the NAND chip;
6662 hardware ECC mode to use (@option{hwecc1},
6663 @option{hwecc4}, @option{hwecc4_infix});
6664 address of the AEMIF controller on this processor.
6666 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
6668 All DaVinci processors support the single-bit ECC hardware,
6669 and newer ones also support the four-bit ECC hardware.
6670 The @code{write_page} and @code{read_page} methods are used
6671 to implement those ECC modes, unless they are disabled using
6672 the @command{nand raw_access} command.
6675 @deffn {NAND Driver} lpc3180
6676 These controllers require an extra @command{nand device}
6677 parameter: the clock rate used by the controller.
6678 @deffn Command {lpc3180 select} num [mlc|slc]
6679 Configures use of the MLC or SLC controller mode.
6680 MLC implies use of hardware ECC.
6681 The @var{num} parameter is the value shown by @command{nand list}.
6684 At this writing, this driver includes @code{write_page}
6685 and @code{read_page} methods. Using @command{nand raw_access}
6686 to disable those methods will prevent use of hardware ECC
6687 in the MLC controller mode, but won't change SLC behavior.
6689 @comment current lpc3180 code won't issue 5-byte address cycles
6691 @deffn {NAND Driver} mx3
6692 This driver handles the NAND controller in i.MX31. The mxc driver
6693 should work for this chip aswell.
6696 @deffn {NAND Driver} mxc
6697 This driver handles the NAND controller found in Freescale i.MX
6698 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
6699 The driver takes 3 extra arguments, chip (@option{mx27},
6700 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
6701 and optionally if bad block information should be swapped between
6702 main area and spare area (@option{biswap}), defaults to off.
6704 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
6706 @deffn Command {mxc biswap} bank_num [enable|disable]
6707 Turns on/off bad block information swaping from main area,
6708 without parameter query status.
6712 @deffn {NAND Driver} orion
6713 These controllers require an extra @command{nand device}
6714 parameter: the address of the controller.
6716 nand device orion 0xd8000000
6718 These controllers don't define any specialized commands.
6719 At this writing, their drivers don't include @code{write_page}
6720 or @code{read_page} methods, so @command{nand raw_access} won't
6721 change any behavior.
6724 @deffn {NAND Driver} s3c2410
6725 @deffnx {NAND Driver} s3c2412
6726 @deffnx {NAND Driver} s3c2440
6727 @deffnx {NAND Driver} s3c2443
6728 @deffnx {NAND Driver} s3c6400
6729 These S3C family controllers don't have any special
6730 @command{nand device} options, and don't define any
6731 specialized commands.
6732 At this writing, their drivers don't include @code{write_page}
6733 or @code{read_page} methods, so @command{nand raw_access} won't
6734 change any behavior.
6739 @subsection mFlash Configuration
6740 @cindex mFlash Configuration
6742 @deffn {Config Command} {mflash bank} soc base RST_pin target
6743 Configures a mflash for @var{soc} host bank at
6745 The pin number format depends on the host GPIO naming convention.
6746 Currently, the mflash driver supports s3c2440 and pxa270.
6748 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
6751 mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
6754 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
6757 mflash bank $_FLASHNAME pxa270 0x08000000 43 0
6761 @subsection mFlash commands
6762 @cindex mFlash commands
6764 @deffn Command {mflash config pll} frequency
6765 Configure mflash PLL.
6766 The @var{frequency} is the mflash input frequency, in Hz.
6767 Issuing this command will erase mflash's whole internal nand and write new pll.
6768 After this command, mflash needs power-on-reset for normal operation.
6769 If pll was newly configured, storage and boot(optional) info also need to be update.
6772 @deffn Command {mflash config boot}
6773 Configure bootable option.
6774 If bootable option is set, mflash offer the first 8 sectors
6778 @deffn Command {mflash config storage}
6779 Configure storage information.
6780 For the normal storage operation, this information must be
6784 @deffn Command {mflash dump} num filename offset size
6785 Dump @var{size} bytes, starting at @var{offset} bytes from the
6786 beginning of the bank @var{num}, to the file named @var{filename}.
6789 @deffn Command {mflash probe}
6793 @deffn Command {mflash write} num filename offset
6794 Write the binary file @var{filename} to mflash bank @var{num}, starting at
6795 @var{offset} bytes from the beginning of the bank.
6798 @node Flash Programming
6799 @chapter Flash Programming
6801 OpenOCD implements numerous ways to program the target flash, whether internal or external.
6802 Programming can be acheived by either using GDB @ref{programmingusinggdb,,Programming using GDB},
6803 or using the cmds given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
6805 @*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage.
6806 OpenOCD will program/verify/reset the target and optionally shutdown.
6808 The script is executed as follows and by default the following actions will be peformed.
6810 @item 'init' is executed.
6811 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
6812 @item @code{flash write_image} is called to erase and write any flash using the filename given.
6813 @item @code{verify_image} is called if @option{verify} parameter is given.
6814 @item @code{reset run} is called if @option{reset} parameter is given.
6815 @item OpenOCD is shutdown if @option{exit} parameter is given.
6818 An example of usage is given below. @xref{program}.
6821 # program and verify using elf/hex/s19. verify and reset
6822 # are optional parameters
6823 openocd -f board/stm32f3discovery.cfg \
6824 -c "program filename.elf verify reset exit"
6826 # binary files need the flash address passing
6827 openocd -f board/stm32f3discovery.cfg \
6828 -c "program filename.bin exit 0x08000000"
6831 @node PLD/FPGA Commands
6832 @chapter PLD/FPGA Commands
6836 Programmable Logic Devices (PLDs) and the more flexible
6837 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
6838 OpenOCD can support programming them.
6839 Although PLDs are generally restrictive (cells are less functional, and
6840 there are no special purpose cells for memory or computational tasks),
6841 they share the same OpenOCD infrastructure.
6842 Accordingly, both are called PLDs here.
6844 @section PLD/FPGA Configuration and Commands
6846 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
6847 OpenOCD maintains a list of PLDs available for use in various commands.
6848 Also, each such PLD requires a driver.
6850 They are referenced by the number shown by the @command{pld devices} command,
6851 and new PLDs are defined by @command{pld device driver_name}.
6853 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
6854 Defines a new PLD device, supported by driver @var{driver_name},
6855 using the TAP named @var{tap_name}.
6856 The driver may make use of any @var{driver_options} to configure its
6860 @deffn {Command} {pld devices}
6861 Lists the PLDs and their numbers.
6864 @deffn {Command} {pld load} num filename
6865 Loads the file @file{filename} into the PLD identified by @var{num}.
6866 The file format must be inferred by the driver.
6869 @section PLD/FPGA Drivers, Options, and Commands
6871 Drivers may support PLD-specific options to the @command{pld device}
6872 definition command, and may also define commands usable only with
6873 that particular type of PLD.
6875 @deffn {FPGA Driver} virtex2 [no_jstart]
6876 Virtex-II is a family of FPGAs sold by Xilinx.
6877 It supports the IEEE 1532 standard for In-System Configuration (ISC).
6879 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
6880 loading the bitstream. While required for Series2, Series3, and Series6, it
6881 breaks bitstream loading on Series7.
6883 @deffn {Command} {virtex2 read_stat} num
6884 Reads and displays the Virtex-II status register (STAT)
6889 @node General Commands
6890 @chapter General Commands
6893 The commands documented in this chapter here are common commands that
6894 you, as a human, may want to type and see the output of. Configuration type
6895 commands are documented elsewhere.
6899 @item @b{Source Of Commands}
6900 @* OpenOCD commands can occur in a configuration script (discussed
6901 elsewhere) or typed manually by a human or supplied programatically,
6902 or via one of several TCP/IP Ports.
6904 @item @b{From the human}
6905 @* A human should interact with the telnet interface (default port: 4444)
6906 or via GDB (default port 3333).
6908 To issue commands from within a GDB session, use the @option{monitor}
6909 command, e.g. use @option{monitor poll} to issue the @option{poll}
6910 command. All output is relayed through the GDB session.
6912 @item @b{Machine Interface}
6913 The Tcl interface's intent is to be a machine interface. The default Tcl
6918 @section Server Commands
6920 @deffn {Command} exit
6921 Exits the current telnet session.
6924 @deffn {Command} help [string]
6925 With no parameters, prints help text for all commands.
6926 Otherwise, prints each helptext containing @var{string}.
6927 Not every command provides helptext.
6929 Configuration commands, and commands valid at any time, are
6930 explicitly noted in parenthesis.
6931 In most cases, no such restriction is listed; this indicates commands
6932 which are only available after the configuration stage has completed.
6935 @deffn Command sleep msec [@option{busy}]
6936 Wait for at least @var{msec} milliseconds before resuming.
6937 If @option{busy} is passed, busy-wait instead of sleeping.
6938 (This option is strongly discouraged.)
6939 Useful in connection with script files
6940 (@command{script} command and @command{target_name} configuration).
6943 @deffn Command shutdown [@option{error}]
6944 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
6945 other). If option @option{error} is used, OpenOCD will return a
6946 non-zero exit code to the parent process.
6950 @deffn Command debug_level [n]
6951 @cindex message level
6952 Display debug level.
6953 If @var{n} (from 0..4) is provided, then set it to that level.
6954 This affects the kind of messages sent to the server log.
6955 Level 0 is error messages only;
6956 level 1 adds warnings;
6957 level 2 adds informational messages;
6958 level 3 adds debugging messages;
6959 and level 4 adds verbose low-level debug messages.
6960 The default is level 2, but that can be overridden on
6961 the command line along with the location of that log
6962 file (which is normally the server's standard output).
6966 @deffn Command echo [-n] message
6967 Logs a message at "user" priority.
6968 Output @var{message} to stdout.
6969 Option "-n" suppresses trailing newline.
6971 echo "Downloading kernel -- please wait"
6975 @deffn Command log_output [filename]
6976 Redirect logging to @var{filename};
6977 the initial log output channel is stderr.
6980 @deffn Command add_script_search_dir [directory]
6981 Add @var{directory} to the file/script search path.
6984 @deffn Command bindto [name]
6985 Specify address by name on which to listen for incoming TCP/IP connections.
6986 By default, OpenOCD will listen on all available interfaces.
6989 @anchor{targetstatehandling}
6990 @section Target State handling
6993 @cindex target initialization
6995 In this section ``target'' refers to a CPU configured as
6996 shown earlier (@pxref{CPU Configuration}).
6997 These commands, like many, implicitly refer to
6998 a current target which is used to perform the
6999 various operations. The current target may be changed
7000 by using @command{targets} command with the name of the
7001 target which should become current.
7003 @deffn Command reg [(number|name) [(value|'force')]]
7004 Access a single register by @var{number} or by its @var{name}.
7005 The target must generally be halted before access to CPU core
7006 registers is allowed. Depending on the hardware, some other
7007 registers may be accessible while the target is running.
7009 @emph{With no arguments}:
7010 list all available registers for the current target,
7011 showing number, name, size, value, and cache status.
7012 For valid entries, a value is shown; valid entries
7013 which are also dirty (and will be written back later)
7014 are flagged as such.
7016 @emph{With number/name}: display that register's value.
7017 Use @var{force} argument to read directly from the target,
7018 bypassing any internal cache.
7020 @emph{With both number/name and value}: set register's value.
7021 Writes may be held in a writeback cache internal to OpenOCD,
7022 so that setting the value marks the register as dirty instead
7023 of immediately flushing that value. Resuming CPU execution
7024 (including by single stepping) or otherwise activating the
7025 relevant module will flush such values.
7027 Cores may have surprisingly many registers in their
7028 Debug and trace infrastructure:
7033 (0) r0 (/32): 0x0000D3C2 (dirty)
7034 (1) r1 (/32): 0xFD61F31C
7037 (164) ETM_contextid_comparator_mask (/32)
7042 @deffn Command halt [ms]
7043 @deffnx Command wait_halt [ms]
7044 The @command{halt} command first sends a halt request to the target,
7045 which @command{wait_halt} doesn't.
7046 Otherwise these behave the same: wait up to @var{ms} milliseconds,
7047 or 5 seconds if there is no parameter, for the target to halt
7048 (and enter debug mode).
7049 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
7052 On ARM cores, software using the @emph{wait for interrupt} operation
7053 often blocks the JTAG access needed by a @command{halt} command.
7054 This is because that operation also puts the core into a low
7055 power mode by gating the core clock;
7056 but the core clock is needed to detect JTAG clock transitions.
7058 One partial workaround uses adaptive clocking: when the core is
7059 interrupted the operation completes, then JTAG clocks are accepted
7060 at least until the interrupt handler completes.
7061 However, this workaround is often unusable since the processor, board,
7062 and JTAG adapter must all support adaptive JTAG clocking.
7063 Also, it can't work until an interrupt is issued.
7065 A more complete workaround is to not use that operation while you
7066 work with a JTAG debugger.
7067 Tasking environments generaly have idle loops where the body is the
7068 @emph{wait for interrupt} operation.
7069 (On older cores, it is a coprocessor action;
7070 newer cores have a @option{wfi} instruction.)
7071 Such loops can just remove that operation, at the cost of higher
7072 power consumption (because the CPU is needlessly clocked).
7077 @deffn Command resume [address]
7078 Resume the target at its current code position,
7079 or the optional @var{address} if it is provided.
7080 OpenOCD will wait 5 seconds for the target to resume.
7083 @deffn Command step [address]
7084 Single-step the target at its current code position,
7085 or the optional @var{address} if it is provided.
7088 @anchor{resetcommand}
7089 @deffn Command reset
7090 @deffnx Command {reset run}
7091 @deffnx Command {reset halt}
7092 @deffnx Command {reset init}
7093 Perform as hard a reset as possible, using SRST if possible.
7094 @emph{All defined targets will be reset, and target
7095 events will fire during the reset sequence.}
7097 The optional parameter specifies what should
7098 happen after the reset.
7099 If there is no parameter, a @command{reset run} is executed.
7100 The other options will not work on all systems.
7101 @xref{Reset Configuration}.
7104 @item @b{run} Let the target run
7105 @item @b{halt} Immediately halt the target
7106 @item @b{init} Immediately halt the target, and execute the reset-init script
7110 @deffn Command soft_reset_halt
7111 Requesting target halt and executing a soft reset. This is often used
7112 when a target cannot be reset and halted. The target, after reset is
7113 released begins to execute code. OpenOCD attempts to stop the CPU and
7114 then sets the program counter back to the reset vector. Unfortunately
7115 the code that was executed may have left the hardware in an unknown
7119 @section I/O Utilities
7121 These commands are available when
7122 OpenOCD is built with @option{--enable-ioutil}.
7123 They are mainly useful on embedded targets,
7125 Hosts with operating systems have complementary tools.
7127 @emph{Note:} there are several more such commands.
7129 @deffn Command append_file filename [string]*
7130 Appends the @var{string} parameters to
7131 the text file @file{filename}.
7132 Each string except the last one is followed by one space.
7133 The last string is followed by a newline.
7136 @deffn Command cat filename
7137 Reads and displays the text file @file{filename}.
7140 @deffn Command cp src_filename dest_filename
7141 Copies contents from the file @file{src_filename}
7142 into @file{dest_filename}.
7146 @emph{No description provided.}
7150 @emph{No description provided.}
7154 @emph{No description provided.}
7157 @deffn Command meminfo
7158 Display available RAM memory on OpenOCD host.
7159 Used in OpenOCD regression testing scripts.
7163 @emph{No description provided.}
7167 @emph{No description provided.}
7170 @deffn Command rm filename
7171 @c "rm" has both normal and Jim-level versions??
7172 Unlinks the file @file{filename}.
7175 @deffn Command trunc filename
7176 Removes all data in the file @file{filename}.
7179 @anchor{memoryaccess}
7180 @section Memory access commands
7181 @cindex memory access
7183 These commands allow accesses of a specific size to the memory
7184 system. Often these are used to configure the current target in some
7185 special way. For example - one may need to write certain values to the
7186 SDRAM controller to enable SDRAM.
7189 @item Use the @command{targets} (plural) command
7190 to change the current target.
7191 @item In system level scripts these commands are deprecated.
7192 Please use their TARGET object siblings to avoid making assumptions
7193 about what TAP is the current target, or about MMU configuration.
7196 @deffn Command mdw [phys] addr [count]
7197 @deffnx Command mdh [phys] addr [count]
7198 @deffnx Command mdb [phys] addr [count]
7199 Display contents of address @var{addr}, as
7200 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
7201 or 8-bit bytes (@command{mdb}).
7202 When the current target has an MMU which is present and active,
7203 @var{addr} is interpreted as a virtual address.
7204 Otherwise, or if the optional @var{phys} flag is specified,
7205 @var{addr} is interpreted as a physical address.
7206 If @var{count} is specified, displays that many units.
7207 (If you want to manipulate the data instead of displaying it,
7208 see the @code{mem2array} primitives.)
7211 @deffn Command mww [phys] addr word
7212 @deffnx Command mwh [phys] addr halfword
7213 @deffnx Command mwb [phys] addr byte
7214 Writes the specified @var{word} (32 bits),
7215 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
7216 at the specified address @var{addr}.
7217 When the current target has an MMU which is present and active,
7218 @var{addr} is interpreted as a virtual address.
7219 Otherwise, or if the optional @var{phys} flag is specified,
7220 @var{addr} is interpreted as a physical address.
7223 @anchor{imageaccess}
7224 @section Image loading commands
7225 @cindex image loading
7226 @cindex image dumping
7228 @deffn Command {dump_image} filename address size
7229 Dump @var{size} bytes of target memory starting at @var{address} to the
7230 binary file named @var{filename}.
7233 @deffn Command {fast_load}
7234 Loads an image stored in memory by @command{fast_load_image} to the
7235 current target. Must be preceeded by fast_load_image.
7238 @deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
7239 Normally you should be using @command{load_image} or GDB load. However, for
7240 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
7241 host), storing the image in memory and uploading the image to the target
7242 can be a way to upload e.g. multiple debug sessions when the binary does not change.
7243 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
7244 memory, i.e. does not affect target. This approach is also useful when profiling
7245 target programming performance as I/O and target programming can easily be profiled
7249 @deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
7250 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
7251 The file format may optionally be specified
7252 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
7253 In addition the following arguments may be specifed:
7254 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
7255 @var{max_length} - maximum number of bytes to load.
7257 proc load_image_bin @{fname foffset address length @} @{
7258 # Load data from fname filename at foffset offset to
7259 # target at address. Load at most length bytes.
7260 load_image $fname [expr $address - $foffset] bin \
7266 @deffn Command {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
7267 Displays image section sizes and addresses
7268 as if @var{filename} were loaded into target memory
7269 starting at @var{address} (defaults to zero).
7270 The file format may optionally be specified
7271 (@option{bin}, @option{ihex}, or @option{elf})
7274 @deffn Command {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
7275 Verify @var{filename} against target memory starting at @var{address}.
7276 The file format may optionally be specified
7277 (@option{bin}, @option{ihex}, or @option{elf})
7278 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
7281 @deffn Command {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
7282 Verify @var{filename} against target memory starting at @var{address}.
7283 The file format may optionally be specified
7284 (@option{bin}, @option{ihex}, or @option{elf})
7285 This perform a comparison using a CRC checksum only
7289 @section Breakpoint and Watchpoint commands
7293 CPUs often make debug modules accessible through JTAG, with
7294 hardware support for a handful of code breakpoints and data
7296 In addition, CPUs almost always support software breakpoints.
7298 @deffn Command {bp} [address len [@option{hw}]]
7299 With no parameters, lists all active breakpoints.
7300 Else sets a breakpoint on code execution starting
7301 at @var{address} for @var{length} bytes.
7302 This is a software breakpoint, unless @option{hw} is specified
7303 in which case it will be a hardware breakpoint.
7305 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
7306 for similar mechanisms that do not consume hardware breakpoints.)
7309 @deffn Command {rbp} address
7310 Remove the breakpoint at @var{address}.
7313 @deffn Command {rwp} address
7314 Remove data watchpoint on @var{address}
7317 @deffn Command {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
7318 With no parameters, lists all active watchpoints.
7319 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
7320 The watch point is an "access" watchpoint unless
7321 the @option{r} or @option{w} parameter is provided,
7322 defining it as respectively a read or write watchpoint.
7323 If a @var{value} is provided, that value is used when determining if
7324 the watchpoint should trigger. The value may be first be masked
7325 using @var{mask} to mark ``don't care'' fields.
7328 @section Misc Commands
7331 @deffn Command {profile} seconds filename [start end]
7332 Profiling samples the CPU's program counter as quickly as possible,
7333 which is useful for non-intrusive stochastic profiling.
7334 Saves up to 10000 samples in @file{filename} using ``gmon.out''
7335 format. Optional @option{start} and @option{end} parameters allow to
7336 limit the address range.
7339 @deffn Command {version}
7340 Displays a string identifying the version of this OpenOCD server.
7343 @deffn Command {virt2phys} virtual_address
7344 Requests the current target to map the specified @var{virtual_address}
7345 to its corresponding physical address, and displays the result.
7348 @node Architecture and Core Commands
7349 @chapter Architecture and Core Commands
7350 @cindex Architecture Specific Commands
7351 @cindex Core Specific Commands
7353 Most CPUs have specialized JTAG operations to support debugging.
7354 OpenOCD packages most such operations in its standard command framework.
7355 Some of those operations don't fit well in that framework, so they are
7356 exposed here as architecture or implementation (core) specific commands.
7358 @anchor{armhardwaretracing}
7359 @section ARM Hardware Tracing
7364 CPUs based on ARM cores may include standard tracing interfaces,
7365 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
7366 address and data bus trace records to a ``Trace Port''.
7370 Development-oriented boards will sometimes provide a high speed
7371 trace connector for collecting that data, when the particular CPU
7372 supports such an interface.
7373 (The standard connector is a 38-pin Mictor, with both JTAG
7374 and trace port support.)
7375 Those trace connectors are supported by higher end JTAG adapters
7376 and some logic analyzer modules; frequently those modules can
7377 buffer several megabytes of trace data.
7378 Configuring an ETM coupled to such an external trace port belongs
7379 in the board-specific configuration file.
7381 If the CPU doesn't provide an external interface, it probably
7382 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
7383 dedicated SRAM. 4KBytes is one common ETB size.
7384 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
7385 (target) configuration file, since it works the same on all boards.
7388 ETM support in OpenOCD doesn't seem to be widely used yet.
7391 ETM support may be buggy, and at least some @command{etm config}
7392 parameters should be detected by asking the ETM for them.
7394 ETM trigger events could also implement a kind of complex
7395 hardware breakpoint, much more powerful than the simple
7396 watchpoint hardware exported by EmbeddedICE modules.
7397 @emph{Such breakpoints can be triggered even when using the
7398 dummy trace port driver}.
7400 It seems like a GDB hookup should be possible,
7401 as well as tracing only during specific states
7402 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
7404 There should be GUI tools to manipulate saved trace data and help
7405 analyse it in conjunction with the source code.
7406 It's unclear how much of a common interface is shared
7407 with the current XScale trace support, or should be
7408 shared with eventual Nexus-style trace module support.
7410 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
7411 for ETM modules is available. The code should be able to
7412 work with some newer cores; but not all of them support
7413 this original style of JTAG access.
7416 @subsection ETM Configuration
7417 ETM setup is coupled with the trace port driver configuration.
7419 @deffn {Config Command} {etm config} target width mode clocking driver
7420 Declares the ETM associated with @var{target}, and associates it
7421 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
7423 Several of the parameters must reflect the trace port capabilities,
7424 which are a function of silicon capabilties (exposed later
7425 using @command{etm info}) and of what hardware is connected to
7426 that port (such as an external pod, or ETB).
7427 The @var{width} must be either 4, 8, or 16,
7428 except with ETMv3.0 and newer modules which may also
7429 support 1, 2, 24, 32, 48, and 64 bit widths.
7430 (With those versions, @command{etm info} also shows whether
7431 the selected port width and mode are supported.)
7433 The @var{mode} must be @option{normal}, @option{multiplexed},
7434 or @option{demultiplexed}.
7435 The @var{clocking} must be @option{half} or @option{full}.
7438 With ETMv3.0 and newer, the bits set with the @var{mode} and
7439 @var{clocking} parameters both control the mode.
7440 This modified mode does not map to the values supported by
7441 previous ETM modules, so this syntax is subject to change.
7445 You can see the ETM registers using the @command{reg} command.
7446 Not all possible registers are present in every ETM.
7447 Most of the registers are write-only, and are used to configure
7448 what CPU activities are traced.
7452 @deffn Command {etm info}
7453 Displays information about the current target's ETM.
7454 This includes resource counts from the @code{ETM_CONFIG} register,
7455 as well as silicon capabilities (except on rather old modules).
7456 from the @code{ETM_SYS_CONFIG} register.
7459 @deffn Command {etm status}
7460 Displays status of the current target's ETM and trace port driver:
7461 is the ETM idle, or is it collecting data?
7462 Did trace data overflow?
7466 @deffn Command {etm tracemode} [type context_id_bits cycle_accurate branch_output]
7467 Displays what data that ETM will collect.
7468 If arguments are provided, first configures that data.
7469 When the configuration changes, tracing is stopped
7470 and any buffered trace data is invalidated.
7473 @item @var{type} ... describing how data accesses are traced,
7474 when they pass any ViewData filtering that that was set up.
7476 @option{none} (save nothing),
7477 @option{data} (save data),
7478 @option{address} (save addresses),
7479 @option{all} (save data and addresses)
7480 @item @var{context_id_bits} ... 0, 8, 16, or 32
7481 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
7482 cycle-accurate instruction tracing.
7483 Before ETMv3, enabling this causes much extra data to be recorded.
7484 @item @var{branch_output} ... @option{enable} or @option{disable}.
7485 Disable this unless you need to try reconstructing the instruction
7486 trace stream without an image of the code.
7490 @deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
7491 Displays whether ETM triggering debug entry (like a breakpoint) is
7492 enabled or disabled, after optionally modifying that configuration.
7493 The default behaviour is @option{disable}.
7494 Any change takes effect after the next @command{etm start}.
7496 By using script commands to configure ETM registers, you can make the
7497 processor enter debug state automatically when certain conditions,
7498 more complex than supported by the breakpoint hardware, happen.
7501 @subsection ETM Trace Operation
7503 After setting up the ETM, you can use it to collect data.
7504 That data can be exported to files for later analysis.
7505 It can also be parsed with OpenOCD, for basic sanity checking.
7507 To configure what is being traced, you will need to write
7508 various trace registers using @command{reg ETM_*} commands.
7509 For the definitions of these registers, read ARM publication
7510 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
7511 Be aware that most of the relevant registers are write-only,
7512 and that ETM resources are limited. There are only a handful
7513 of address comparators, data comparators, counters, and so on.
7515 Examples of scenarios you might arrange to trace include:
7518 @item Code flow within a function, @emph{excluding} subroutines
7519 it calls. Use address range comparators to enable tracing
7520 for instruction access within that function's body.
7521 @item Code flow within a function, @emph{including} subroutines
7522 it calls. Use the sequencer and address comparators to activate
7523 tracing on an ``entered function'' state, then deactivate it by
7524 exiting that state when the function's exit code is invoked.
7525 @item Code flow starting at the fifth invocation of a function,
7526 combining one of the above models with a counter.
7527 @item CPU data accesses to the registers for a particular device,
7528 using address range comparators and the ViewData logic.
7529 @item Such data accesses only during IRQ handling, combining the above
7530 model with sequencer triggers which on entry and exit to the IRQ handler.
7531 @item @emph{... more}
7534 At this writing, September 2009, there are no Tcl utility
7535 procedures to help set up any common tracing scenarios.
7537 @deffn Command {etm analyze}
7538 Reads trace data into memory, if it wasn't already present.
7539 Decodes and prints the data that was collected.
7542 @deffn Command {etm dump} filename
7543 Stores the captured trace data in @file{filename}.
7546 @deffn Command {etm image} filename [base_address] [type]
7547 Opens an image file.
7550 @deffn Command {etm load} filename
7551 Loads captured trace data from @file{filename}.
7554 @deffn Command {etm start}
7555 Starts trace data collection.
7558 @deffn Command {etm stop}
7559 Stops trace data collection.
7562 @anchor{traceportdrivers}
7563 @subsection Trace Port Drivers
7565 To use an ETM trace port it must be associated with a driver.
7567 @deffn {Trace Port Driver} dummy
7568 Use the @option{dummy} driver if you are configuring an ETM that's
7569 not connected to anything (on-chip ETB or off-chip trace connector).
7570 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
7571 any trace data collection.}
7572 @deffn {Config Command} {etm_dummy config} target
7573 Associates the ETM for @var{target} with a dummy driver.
7577 @deffn {Trace Port Driver} etb
7578 Use the @option{etb} driver if you are configuring an ETM
7579 to use on-chip ETB memory.
7580 @deffn {Config Command} {etb config} target etb_tap
7581 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
7582 You can see the ETB registers using the @command{reg} command.
7584 @deffn Command {etb trigger_percent} [percent]
7585 This displays, or optionally changes, ETB behavior after the
7586 ETM's configured @emph{trigger} event fires.
7587 It controls how much more trace data is saved after the (single)
7588 trace trigger becomes active.
7591 @item The default corresponds to @emph{trace around} usage,
7592 recording 50 percent data before the event and the rest
7594 @item The minimum value of @var{percent} is 2 percent,
7595 recording almost exclusively data before the trigger.
7596 Such extreme @emph{trace before} usage can help figure out
7597 what caused that event to happen.
7598 @item The maximum value of @var{percent} is 100 percent,
7599 recording data almost exclusively after the event.
7600 This extreme @emph{trace after} usage might help sort out
7601 how the event caused trouble.
7603 @c REVISIT allow "break" too -- enter debug mode.
7608 @deffn {Trace Port Driver} oocd_trace
7609 This driver isn't available unless OpenOCD was explicitly configured
7610 with the @option{--enable-oocd_trace} option. You probably don't want
7611 to configure it unless you've built the appropriate prototype hardware;
7612 it's @emph{proof-of-concept} software.
7614 Use the @option{oocd_trace} driver if you are configuring an ETM that's
7615 connected to an off-chip trace connector.
7617 @deffn {Config Command} {oocd_trace config} target tty
7618 Associates the ETM for @var{target} with a trace driver which
7619 collects data through the serial port @var{tty}.
7622 @deffn Command {oocd_trace resync}
7623 Re-synchronizes with the capture clock.
7626 @deffn Command {oocd_trace status}
7627 Reports whether the capture clock is locked or not.
7632 @section Generic ARM
7635 These commands should be available on all ARM processors.
7636 They are available in addition to other core-specific
7637 commands that may be available.
7639 @deffn Command {arm core_state} [@option{arm}|@option{thumb}]
7640 Displays the core_state, optionally changing it to process
7641 either @option{arm} or @option{thumb} instructions.
7642 The target may later be resumed in the currently set core_state.
7643 (Processors may also support the Jazelle state, but
7644 that is not currently supported in OpenOCD.)
7647 @deffn Command {arm disassemble} address [count [@option{thumb}]]
7649 Disassembles @var{count} instructions starting at @var{address}.
7650 If @var{count} is not specified, a single instruction is disassembled.
7651 If @option{thumb} is specified, or the low bit of the address is set,
7652 Thumb2 (mixed 16/32-bit) instructions are used;
7653 else ARM (32-bit) instructions are used.
7654 (Processors may also support the Jazelle state, but
7655 those instructions are not currently understood by OpenOCD.)
7657 Note that all Thumb instructions are Thumb2 instructions,
7658 so older processors (without Thumb2 support) will still
7659 see correct disassembly of Thumb code.
7660 Also, ThumbEE opcodes are the same as Thumb2,
7661 with a handful of exceptions.
7662 ThumbEE disassembly currently has no explicit support.
7665 @deffn Command {arm mcr} pX op1 CRn CRm op2 value
7666 Write @var{value} to a coprocessor @var{pX} register
7667 passing parameters @var{CRn},
7668 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7669 and using the MCR instruction.
7670 (Parameter sequence matches the ARM instruction, but omits
7674 @deffn Command {arm mrc} pX coproc op1 CRn CRm op2
7675 Read a coprocessor @var{pX} register passing parameters @var{CRn},
7676 @var{CRm}, opcodes @var{opc1} and @var{opc2},
7677 and the MRC instruction.
7678 Returns the result so it can be manipulated by Jim scripts.
7679 (Parameter sequence matches the ARM instruction, but omits
7683 @deffn Command {arm reg}
7684 Display a table of all banked core registers, fetching the current value from every
7685 core mode if necessary.
7688 @deffn Command {arm semihosting} [@option{enable}|@option{disable}]
7689 @cindex ARM semihosting
7690 Display status of semihosting, after optionally changing that status.
7692 Semihosting allows for code executing on an ARM target to use the
7693 I/O facilities on the host computer i.e. the system where OpenOCD
7694 is running. The target application must be linked against a library
7695 implementing the ARM semihosting convention that forwards operation
7696 requests by using a special SVC instruction that is trapped at the
7697 Supervisor Call vector by OpenOCD.
7700 @deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
7701 @cindex ARM semihosting
7702 Set the command line to be passed to the debuggee.
7705 arm semihosting_cmdline argv0 argv1 argv2 ...
7708 This option lets one set the command line arguments to be passed to
7709 the program. The first argument (argv0) is the program name in a
7710 standard C environment (argv[0]). Depending on the program (not much
7711 programs look at argv[0]), argv0 is ignored and can be any string.
7714 @deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
7715 @cindex ARM semihosting
7716 Display status of semihosting fileio, after optionally changing that
7719 Enabling this option forwards semihosting I/O to GDB process using the
7720 File-I/O remote protocol extension. This is especially useful for
7721 interacting with remote files or displaying console messages in the
7725 @section ARMv4 and ARMv5 Architecture
7729 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
7730 and introduced core parts of the instruction set in use today.
7731 That includes the Thumb instruction set, introduced in the ARMv4T
7734 @subsection ARM7 and ARM9 specific commands
7738 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
7739 ARM9TDMI, ARM920T or ARM926EJ-S.
7740 They are available in addition to the ARM commands,
7741 and any other core-specific commands that may be available.
7743 @deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
7744 Displays the value of the flag controlling use of the
7745 the EmbeddedIce DBGRQ signal to force entry into debug mode,
7746 instead of breakpoints.
7747 If a boolean parameter is provided, first assigns that flag.
7750 safe for all but ARM7TDMI-S cores (like NXP LPC).
7751 This feature is enabled by default on most ARM9 cores,
7752 including ARM9TDMI, ARM920T, and ARM926EJ-S.
7755 @deffn Command {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
7757 Displays the value of the flag controlling use of the debug communications
7758 channel (DCC) to write larger (>128 byte) amounts of memory.
7759 If a boolean parameter is provided, first assigns that flag.
7761 DCC downloads offer a huge speed increase, but might be
7762 unsafe, especially with targets running at very low speeds. This command was introduced
7763 with OpenOCD rev. 60, and requires a few bytes of working area.
7766 @deffn Command {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
7767 Displays the value of the flag controlling use of memory writes and reads
7768 that don't check completion of the operation.
7769 If a boolean parameter is provided, first assigns that flag.
7771 This provides a huge speed increase, especially with USB JTAG
7772 cables (FT2232), but might be unsafe if used with targets running at very low
7773 speeds, like the 32kHz startup clock of an AT91RM9200.
7776 @subsection ARM720T specific commands
7779 These commands are available to ARM720T based CPUs,
7780 which are implementations of the ARMv4T architecture
7781 based on the ARM7TDMI-S integer core.
7782 They are available in addition to the ARM and ARM7/ARM9 commands.
7784 @deffn Command {arm720t cp15} opcode [value]
7785 @emph{DEPRECATED -- avoid using this.
7786 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7788 Display cp15 register returned by the ARM instruction @var{opcode};
7789 else if a @var{value} is provided, that value is written to that register.
7790 The @var{opcode} should be the value of either an MRC or MCR instruction.
7793 @subsection ARM9 specific commands
7796 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
7798 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
7800 @c 9-june-2009: tried this on arm920t, it didn't work.
7801 @c no-params always lists nothing caught, and that's how it acts.
7802 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
7803 @c versions have different rules about when they commit writes.
7805 @anchor{arm9vectorcatch}
7806 @deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
7807 @cindex vector_catch
7808 Vector Catch hardware provides a sort of dedicated breakpoint
7809 for hardware events such as reset, interrupt, and abort.
7810 You can use this to conserve normal breakpoint resources,
7811 so long as you're not concerned with code that branches directly
7812 to those hardware vectors.
7814 This always finishes by listing the current configuration.
7815 If parameters are provided, it first reconfigures the
7816 vector catch hardware to intercept
7817 @option{all} of the hardware vectors,
7818 @option{none} of them,
7819 or a list with one or more of the following:
7820 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
7821 @option{irq} @option{fiq}.
7824 @subsection ARM920T specific commands
7827 These commands are available to ARM920T based CPUs,
7828 which are implementations of the ARMv4T architecture
7829 built using the ARM9TDMI integer core.
7830 They are available in addition to the ARM, ARM7/ARM9,
7833 @deffn Command {arm920t cache_info}
7834 Print information about the caches found. This allows to see whether your target
7835 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
7838 @deffn Command {arm920t cp15} regnum [value]
7839 Display cp15 register @var{regnum};
7840 else if a @var{value} is provided, that value is written to that register.
7841 This uses "physical access" and the register number is as
7842 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
7843 (Not all registers can be written.)
7846 @deffn Command {arm920t cp15i} opcode [value [address]]
7847 @emph{DEPRECATED -- avoid using this.
7848 Use the @command{arm mrc} or @command{arm mcr} commands instead.}
7850 Interpreted access using ARM instruction @var{opcode}, which should
7851 be the value of either an MRC or MCR instruction
7852 (as shown tables 9-11, 9-12, and 9-13 in the ARM920T TRM).
7853 If no @var{value} is provided, the result is displayed.
7854 Else if that value is written using the specified @var{address},
7855 or using zero if no other address is provided.
7858 @deffn Command {arm920t read_cache} filename
7859 Dump the content of ICache and DCache to a file named @file{filename}.
7862 @deffn Command {arm920t read_mmu} filename
7863 Dump the content of the ITLB and DTLB to a file named @file{filename}.
7866 @subsection ARM926ej-s specific commands
7869 These commands are available to ARM926ej-s based CPUs,
7870 which are implementations of the ARMv5TEJ architecture
7871 based on the ARM9EJ-S integer core.
7872 They are available in addition to the ARM, ARM7/ARM9,
7875 The Feroceon cores also support these commands, although
7876 they are not built from ARM926ej-s designs.
7878 @deffn Command {arm926ejs cache_info}
7879 Print information about the caches found.
7882 @subsection ARM966E specific commands
7885 These commands are available to ARM966 based CPUs,
7886 which are implementations of the ARMv5TE architecture.
7887 They are available in addition to the ARM, ARM7/ARM9,
7890 @deffn Command {arm966e cp15} regnum [value]
7891 Display cp15 register @var{regnum};
7892 else if a @var{value} is provided, that value is written to that register.
7893 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
7895 There is no current control over bits 31..30 from that table,
7896 as required for BIST support.
7899 @subsection XScale specific commands
7902 Some notes about the debug implementation on the XScale CPUs:
7904 The XScale CPU provides a special debug-only mini-instruction cache
7905 (mini-IC) in which exception vectors and target-resident debug handler
7906 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
7907 must point vector 0 (the reset vector) to the entry of the debug
7908 handler. However, this means that the complete first cacheline in the
7909 mini-IC is marked valid, which makes the CPU fetch all exception
7910 handlers from the mini-IC, ignoring the code in RAM.
7912 To address this situation, OpenOCD provides the @code{xscale
7913 vector_table} command, which allows the user to explicity write
7914 individual entries to either the high or low vector table stored in
7917 It is recommended to place a pc-relative indirect branch in the vector
7918 table, and put the branch destination somewhere in memory. Doing so
7919 makes sure the code in the vector table stays constant regardless of
7920 code layout in memory:
7923 ldr pc,[pc,#0x100-8]
7924 ldr pc,[pc,#0x100-8]
7925 ldr pc,[pc,#0x100-8]
7926 ldr pc,[pc,#0x100-8]
7927 ldr pc,[pc,#0x100-8]
7928 ldr pc,[pc,#0x100-8]
7929 ldr pc,[pc,#0x100-8]
7930 ldr pc,[pc,#0x100-8]
7932 .long real_reset_vector
7933 .long real_ui_handler
7934 .long real_swi_handler
7936 .long real_data_abort
7937 .long 0 /* unused */
7938 .long real_irq_handler
7939 .long real_fiq_handler
7942 Alternatively, you may choose to keep some or all of the mini-IC
7943 vector table entries synced with those written to memory by your
7944 system software. The mini-IC can not be modified while the processor
7945 is executing, but for each vector table entry not previously defined
7946 using the @code{xscale vector_table} command, OpenOCD will copy the
7947 value from memory to the mini-IC every time execution resumes from a
7948 halt. This is done for both high and low vector tables (although the
7949 table not in use may not be mapped to valid memory, and in this case
7950 that copy operation will silently fail). This means that you will
7951 need to briefly halt execution at some strategic point during system
7952 start-up; e.g., after the software has initialized the vector table,
7953 but before exceptions are enabled. A breakpoint can be used to
7954 accomplish this once the appropriate location in the start-up code has
7955 been identified. A watchpoint over the vector table region is helpful
7956 in finding the location if you're not sure. Note that the same
7957 situation exists any time the vector table is modified by the system
7960 The debug handler must be placed somewhere in the address space using
7961 the @code{xscale debug_handler} command. The allowed locations for the
7962 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
7963 0xfffff800). The default value is 0xfe000800.
7965 XScale has resources to support two hardware breakpoints and two
7966 watchpoints. However, the following restrictions on watchpoint
7967 functionality apply: (1) the value and mask arguments to the @code{wp}
7968 command are not supported, (2) the watchpoint length must be a
7969 power of two and not less than four, and can not be greater than the
7970 watchpoint address, and (3) a watchpoint with a length greater than
7971 four consumes all the watchpoint hardware resources. This means that
7972 at any one time, you can have enabled either two watchpoints with a
7973 length of four, or one watchpoint with a length greater than four.
7975 These commands are available to XScale based CPUs,
7976 which are implementations of the ARMv5TE architecture.
7978 @deffn Command {xscale analyze_trace}
7979 Displays the contents of the trace buffer.
7982 @deffn Command {xscale cache_clean_address} address
7983 Changes the address used when cleaning the data cache.
7986 @deffn Command {xscale cache_info}
7987 Displays information about the CPU caches.
7990 @deffn Command {xscale cp15} regnum [value]
7991 Display cp15 register @var{regnum};
7992 else if a @var{value} is provided, that value is written to that register.
7995 @deffn Command {xscale debug_handler} target address
7996 Changes the address used for the specified target's debug handler.
7999 @deffn Command {xscale dcache} [@option{enable}|@option{disable}]
8000 Enables or disable the CPU's data cache.
8003 @deffn Command {xscale dump_trace} filename
8004 Dumps the raw contents of the trace buffer to @file{filename}.
8007 @deffn Command {xscale icache} [@option{enable}|@option{disable}]
8008 Enables or disable the CPU's instruction cache.
8011 @deffn Command {xscale mmu} [@option{enable}|@option{disable}]
8012 Enables or disable the CPU's memory management unit.
8015 @deffn Command {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
8016 Displays the trace buffer status, after optionally
8017 enabling or disabling the trace buffer
8018 and modifying how it is emptied.
8021 @deffn Command {xscale trace_image} filename [offset [type]]
8022 Opens a trace image from @file{filename}, optionally rebasing
8023 its segment addresses by @var{offset}.
8024 The image @var{type} may be one of
8025 @option{bin} (binary), @option{ihex} (Intel hex),
8026 @option{elf} (ELF file), @option{s19} (Motorola s19),
8027 @option{mem}, or @option{builder}.
8030 @anchor{xscalevectorcatch}
8031 @deffn Command {xscale vector_catch} [mask]
8032 @cindex vector_catch
8033 Display a bitmask showing the hardware vectors to catch.
8034 If the optional parameter is provided, first set the bitmask to that value.
8036 The mask bits correspond with bit 16..23 in the DCSR:
8039 0x02 Trap Undefined Instructions
8040 0x04 Trap Software Interrupt
8041 0x08 Trap Prefetch Abort
8042 0x10 Trap Data Abort
8049 @deffn Command {xscale vector_table} [(@option{low}|@option{high}) index value]
8050 @cindex vector_table
8052 Set an entry in the mini-IC vector table. There are two tables: one for
8053 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
8054 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
8055 points to the debug handler entry and can not be overwritten.
8056 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
8058 Without arguments, the current settings are displayed.
8062 @section ARMv6 Architecture
8065 @subsection ARM11 specific commands
8068 @deffn Command {arm11 memwrite burst} [@option{enable}|@option{disable}]
8069 Displays the value of the memwrite burst-enable flag,
8070 which is enabled by default.
8071 If a boolean parameter is provided, first assigns that flag.
8072 Burst writes are only used for memory writes larger than 1 word.
8073 They improve performance by assuming that the CPU has read each data
8074 word over JTAG and completed its write before the next word arrives,
8075 instead of polling for a status flag to verify that completion.
8076 This is usually safe, because JTAG runs much slower than the CPU.
8079 @deffn Command {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
8080 Displays the value of the memwrite error_fatal flag,
8081 which is enabled by default.
8082 If a boolean parameter is provided, first assigns that flag.
8083 When set, certain memory write errors cause earlier transfer termination.
8086 @deffn Command {arm11 step_irq_enable} [@option{enable}|@option{disable}]
8087 Displays the value of the flag controlling whether
8088 IRQs are enabled during single stepping;
8089 they are disabled by default.
8090 If a boolean parameter is provided, first assigns that.
8093 @deffn Command {arm11 vcr} [value]
8094 @cindex vector_catch
8095 Displays the value of the @emph{Vector Catch Register (VCR)},
8096 coprocessor 14 register 7.
8097 If @var{value} is defined, first assigns that.
8099 Vector Catch hardware provides dedicated breakpoints
8100 for certain hardware events.
8101 The specific bit values are core-specific (as in fact is using
8102 coprocessor 14 register 7 itself) but all current ARM11
8103 cores @emph{except the ARM1176} use the same six bits.
8106 @section ARMv7 and ARMv8 Architecture
8110 @subsection ARMv7 and ARMv8 Debug Access Port (DAP) specific commands
8111 @cindex Debug Access Port
8113 These commands are specific to ARM architecture v7 and v8 Debug Access Port (DAP),
8114 included on Cortex-M and Cortex-A systems.
8115 They are available in addition to other core-specific commands that may be available.
8117 @deffn Command {dap apid} [num]
8118 Displays ID register from AP @var{num},
8119 defaulting to the currently selected AP.
8122 @deffn Command {dap apreg} ap_num reg [value]
8123 Displays content of a register @var{reg} from AP @var{ap_num}
8124 or set a new value @var{value}.
8125 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
8128 @deffn Command {dap apsel} [num]
8129 Select AP @var{num}, defaulting to 0.
8132 @deffn Command {dap baseaddr} [num]
8133 Displays debug base address from MEM-AP @var{num},
8134 defaulting to the currently selected AP.
8137 @deffn Command {dap info} [num]
8138 Displays the ROM table for MEM-AP @var{num},
8139 defaulting to the currently selected AP.
8142 @deffn Command {dap memaccess} [value]
8143 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
8144 memory bus access [0-255], giving additional time to respond to reads.
8145 If @var{value} is defined, first assigns that.
8148 @deffn Command {dap apcsw} [0 / 1]
8149 fix CSW_SPROT from register AP_REG_CSW on selected dap.
8153 @deffn Command {dap ti_be_32_quirks} [@option{enable}]
8154 Set/get quirks mode for TI TMS450/TMS570 processors
8159 @subsection ARMv7-A specific commands
8162 @deffn Command {cortex_a cache_info}
8163 display information about target caches
8166 @deffn Command {cortex_a dacrfixup [@option{on}|@option{off}]}
8167 Work around issues with software breakpoints when the program text is
8168 mapped read-only by the operating system. This option sets the CP15 DACR
8169 to "all-manager" to bypass MMU permission checks on memory access.
8173 @deffn Command {cortex_a dbginit}
8174 Initialize core debug
8175 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8178 @deffn Command {cortex_a smp_off}
8182 @deffn Command {cortex_a smp_on}
8186 @deffn Command {cortex_a smp_gdb} [core_id]
8187 Display/set the current core displayed in GDB
8190 @deffn Command {cortex_a maskisr} [@option{on}|@option{off}]
8191 Selects whether interrupts will be processed when single stepping
8194 @deffn Command {cache_config l2x} [base way]
8199 @subsection ARMv7-R specific commands
8202 @deffn Command {cortex_r dbginit}
8203 Initialize core debug
8204 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
8207 @deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
8208 Selects whether interrupts will be processed when single stepping
8212 @subsection ARMv7-M specific commands
8220 @deffn Command {tpiu config} (@option{disable} | ((@option{external} | @option{internal (@var{filename} | -)}) @
8221 (@option{sync @var{port_width}} | ((@option{manchester} | @option{uart}) @var{formatter_enable})) @
8222 @var{TRACECLKIN_freq} [@var{trace_freq}]))
8224 ARMv7-M architecture provides several modules to generate debugging
8225 information internally (ITM, DWT and ETM). Their output is directed
8226 through TPIU to be captured externally either on an SWO pin (this
8227 configuration is called SWV) or on a synchronous parallel trace port.
8229 This command configures the TPIU module of the target and, if internal
8230 capture mode is selected, starts to capture trace output by using the
8231 debugger adapter features.
8233 Some targets require additional actions to be performed in the
8234 @b{trace-config} handler for trace port to be activated.
8238 @item @option{disable} disable TPIU handling;
8239 @item @option{external} configure TPIU to let user capture trace
8240 output externally (with an additional UART or logic analyzer hardware);
8241 @item @option{internal @var{filename}} configure TPIU and debug adapter to
8242 gather trace data and append it to @var{filename} (which can be
8243 either a regular file or a named pipe);
8244 @item @option{internal -} configure TPIU and debug adapter to
8245 gather trace data, but not write to any file. Useful in conjunction with the @command{tcl_trace} command;
8246 @item @option{sync @var{port_width}} use synchronous parallel trace output
8247 mode, and set port width to @var{port_width};
8248 @item @option{manchester} use asynchronous SWO mode with Manchester
8250 @item @option{uart} use asynchronous SWO mode with NRZ (same as
8251 regular UART 8N1) coding;
8252 @item @var{formatter_enable} is @option{on} or @option{off} to enable
8253 or disable TPIU formatter which needs to be used when both ITM and ETM
8254 data is to be output via SWO;
8255 @item @var{TRACECLKIN_freq} this should be specified to match target's
8256 current TRACECLKIN frequency (usually the same as HCLK);
8257 @item @var{trace_freq} trace port frequency. Can be omitted in
8258 internal mode to let the adapter driver select the maximum supported
8264 @item STM32L152 board is programmed with an application that configures
8265 PLL to provide core clock with 24MHz frequency; to use ITM output it's
8268 #include <libopencm3/cm3/itm.h>
8273 (the most obvious way is to use the first stimulus port for printf,
8274 for that this ITM_STIM8 assignment can be used inside _write(); to make it
8275 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
8276 ITM_STIM_FIFOREADY));});
8277 @item An FT2232H UART is connected to the SWO pin of the board;
8278 @item Commands to configure UART for 12MHz baud rate:
8280 $ setserial /dev/ttyUSB1 spd_cust divisor 5
8281 $ stty -F /dev/ttyUSB1 38400
8283 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
8284 baud with our custom divisor to get 12MHz)
8285 @item @code{itmdump -f /dev/ttyUSB1 -d1}
8286 @item OpenOCD invocation line:
8288 openocd -f interface/stlink-v2-1.cfg \
8289 -c "transport select hla_swd" \
8290 -f target/stm32l1.cfg \
8291 -c "tpiu config external uart off 24000000 12000000"
8296 @deffn Command {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
8297 Enable or disable trace output for ITM stimulus @var{port} (counting
8298 from 0). Port 0 is enabled on target creation automatically.
8301 @deffn Command {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
8302 Enable or disable trace output for all ITM stimulus ports.
8305 @subsection Cortex-M specific commands
8308 @deffn Command {cortex_m maskisr} (@option{auto}|@option{on}|@option{off})
8309 Control masking (disabling) interrupts during target step/resume.
8311 The @option{auto} option handles interrupts during stepping a way they get
8312 served but don't disturb the program flow. The step command first allows
8313 pending interrupt handlers to execute, then disables interrupts and steps over
8314 the next instruction where the core was halted. After the step interrupts
8315 are enabled again. If the interrupt handlers don't complete within 500ms,
8316 the step command leaves with the core running.
8318 Note that a free breakpoint is required for the @option{auto} option. If no
8319 breakpoint is available at the time of the step, then the step is taken
8320 with interrupts enabled, i.e. the same way the @option{off} option does.
8322 Default is @option{auto}.
8325 @deffn Command {cortex_m vector_catch} [@option{all}|@option{none}|list]
8326 @cindex vector_catch
8327 Vector Catch hardware provides dedicated breakpoints
8328 for certain hardware events.
8330 Parameters request interception of
8331 @option{all} of these hardware event vectors,
8332 @option{none} of them,
8333 or one or more of the following:
8334 @option{hard_err} for a HardFault exception;
8335 @option{mm_err} for a MemManage exception;
8336 @option{bus_err} for a BusFault exception;
8339 @option{chk_err}, or
8340 @option{nocp_err} for various UsageFault exceptions; or
8342 If NVIC setup code does not enable them,
8343 MemManage, BusFault, and UsageFault exceptions
8344 are mapped to HardFault.
8345 UsageFault checks for
8346 divide-by-zero and unaligned access
8347 must also be explicitly enabled.
8349 This finishes by listing the current vector catch configuration.
8352 @deffn Command {cortex_m reset_config} (@option{srst}|@option{sysresetreq}|@option{vectreset})
8353 Control reset handling. The default @option{srst} is to use srst if fitted,
8354 otherwise fallback to @option{vectreset}.
8356 @item @option{srst} use hardware srst if fitted otherwise fallback to @option{vectreset}.
8357 @item @option{sysresetreq} use NVIC SYSRESETREQ to reset system.
8358 @item @option{vectreset} use NVIC VECTRESET to reset system.
8360 Using @option{vectreset} is a safe option for all current Cortex-M cores.
8361 This however has the disadvantage of only resetting the core, all peripherals
8362 are uneffected. A solution would be to use a @code{reset-init} event handler to manually reset
8364 @xref{targetevents,,Target Events}.
8367 @subsection ARMv8-A specific commands
8371 @deffn Command {aarch64 cache_info}
8372 Display information about target caches
8375 @deffn Command {aarch64 dbginit}
8376 This command enables debugging by clearing the OS Lock and sticky power-down and reset
8377 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
8378 target code relies on. In a configuration file, the command would typically be called from a
8379 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
8380 However, normally it is not necessary to use the command at all.
8383 @deffn Command {aarch64 smp_on|smp_off}
8384 Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group
8385 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
8386 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
8387 group. With SMP handling disabled, all targets need to be treated individually.
8390 @section Intel Architecture
8392 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
8393 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
8394 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
8395 software debug and the CLTAP is used for SoC level operations.
8396 Useful docs are here: https://communities.intel.com/community/makers/documentation
8398 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
8399 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
8400 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
8403 @subsection x86 32-bit specific commands
8404 The three main address spaces for x86 are memory, I/O and configuration space.
8405 These commands allow a user to read and write to the 64Kbyte I/O address space.
8407 @deffn Command {x86_32 idw} address
8408 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
8411 @deffn Command {x86_32 idh} address
8412 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
8415 @deffn Command {x86_32 idb} address
8416 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
8419 @deffn Command {x86_32 iww} address
8420 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
8423 @deffn Command {x86_32 iwh} address
8424 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
8427 @deffn Command {x86_32 iwb} address
8428 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
8431 @section OpenRISC Architecture
8433 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
8434 configured with any of the TAP / Debug Unit available.
8436 @subsection TAP and Debug Unit selection commands
8437 @deffn Command {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
8438 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
8440 @deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
8441 Select between the Advanced Debug Interface and the classic one.
8443 An option can be passed as a second argument to the debug unit.
8445 When using the Advanced Debug Interface, option = 1 means the RTL core is
8446 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
8447 between bytes while doing read or write bursts.
8450 @subsection Registers commands
8451 @deffn Command {addreg} [name] [address] [feature] [reg_group]
8452 Add a new register in the cpu register list. This register will be
8453 included in the generated target descriptor file.
8455 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
8457 @strong{[reg_group]} can be anything. The default register list defines "system",
8458 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
8463 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
8468 @deffn Command {readgroup} (@option{group})
8469 Display all registers in @emph{group}.
8471 @emph{group} can be "system",
8472 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
8473 "timer" or any new group created with addreg command.
8476 @anchor{softwaredebugmessagesandtracing}
8477 @section Software Debug Messages and Tracing
8478 @cindex Linux-ARM DCC support
8482 OpenOCD can process certain requests from target software, when
8483 the target uses appropriate libraries.
8484 The most powerful mechanism is semihosting, but there is also
8485 a lighter weight mechanism using only the DCC channel.
8487 Currently @command{target_request debugmsgs}
8488 is supported only for @option{arm7_9} and @option{cortex_m} cores.
8489 These messages are received as part of target polling, so
8490 you need to have @command{poll on} active to receive them.
8491 They are intrusive in that they will affect program execution
8492 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
8494 See @file{libdcc} in the contrib dir for more details.
8495 In addition to sending strings, characters, and
8496 arrays of various size integers from the target,
8497 @file{libdcc} also exports a software trace point mechanism.
8498 The target being debugged may
8499 issue trace messages which include a 24-bit @dfn{trace point} number.
8500 Trace point support includes two distinct mechanisms,
8501 each supported by a command:
8504 @item @emph{History} ... A circular buffer of trace points
8505 can be set up, and then displayed at any time.
8506 This tracks where code has been, which can be invaluable in
8507 finding out how some fault was triggered.
8509 The buffer may overflow, since it collects records continuously.
8510 It may be useful to use some of the 24 bits to represent a
8511 particular event, and other bits to hold data.
8513 @item @emph{Counting} ... An array of counters can be set up,
8514 and then displayed at any time.
8515 This can help establish code coverage and identify hot spots.
8517 The array of counters is directly indexed by the trace point
8518 number, so trace points with higher numbers are not counted.
8521 Linux-ARM kernels have a ``Kernel low-level debugging
8522 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
8523 depends on CONFIG_DEBUG_LL) which uses this mechanism to
8524 deliver messages before a serial console can be activated.
8525 This is not the same format used by @file{libdcc}.
8526 Other software, such as the U-Boot boot loader, sometimes
8527 does the same thing.
8529 @deffn Command {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
8530 Displays current handling of target DCC message requests.
8531 These messages may be sent to the debugger while the target is running.
8532 The optional @option{enable} and @option{charmsg} parameters
8533 both enable the messages, while @option{disable} disables them.
8535 With @option{charmsg} the DCC words each contain one character,
8536 as used by Linux with CONFIG_DEBUG_ICEDCC;
8537 otherwise the libdcc format is used.
8540 @deffn Command {trace history} [@option{clear}|count]
8541 With no parameter, displays all the trace points that have triggered
8542 in the order they triggered.
8543 With the parameter @option{clear}, erases all current trace history records.
8544 With a @var{count} parameter, allocates space for that many
8548 @deffn Command {trace point} [@option{clear}|identifier]
8549 With no parameter, displays all trace point identifiers and how many times
8550 they have been triggered.
8551 With the parameter @option{clear}, erases all current trace point counters.
8552 With a numeric @var{identifier} parameter, creates a new a trace point counter
8553 and associates it with that identifier.
8555 @emph{Important:} The identifier and the trace point number
8556 are not related except by this command.
8557 These trace point numbers always start at zero (from server startup,
8558 or after @command{trace point clear}) and count up from there.
8563 @chapter JTAG Commands
8564 @cindex JTAG Commands
8565 Most general purpose JTAG commands have been presented earlier.
8566 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
8567 Lower level JTAG commands, as presented here,
8568 may be needed to work with targets which require special
8569 attention during operations such as reset or initialization.
8571 To use these commands you will need to understand some
8572 of the basics of JTAG, including:
8575 @item A JTAG scan chain consists of a sequence of individual TAP
8576 devices such as a CPUs.
8577 @item Control operations involve moving each TAP through the same
8578 standard state machine (in parallel)
8579 using their shared TMS and clock signals.
8580 @item Data transfer involves shifting data through the chain of
8581 instruction or data registers of each TAP, writing new register values
8582 while the reading previous ones.
8583 @item Data register sizes are a function of the instruction active in
8584 a given TAP, while instruction register sizes are fixed for each TAP.
8585 All TAPs support a BYPASS instruction with a single bit data register.
8586 @item The way OpenOCD differentiates between TAP devices is by
8587 shifting different instructions into (and out of) their instruction
8591 @section Low Level JTAG Commands
8593 These commands are used by developers who need to access
8594 JTAG instruction or data registers, possibly controlling
8595 the order of TAP state transitions.
8596 If you're not debugging OpenOCD internals, or bringing up a
8597 new JTAG adapter or a new type of TAP device (like a CPU or
8598 JTAG router), you probably won't need to use these commands.
8599 In a debug session that doesn't use JTAG for its transport protocol,
8600 these commands are not available.
8602 @deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
8603 Loads the data register of @var{tap} with a series of bit fields
8604 that specify the entire register.
8605 Each field is @var{numbits} bits long with
8606 a numeric @var{value} (hexadecimal encouraged).
8607 The return value holds the original value of each
8610 For example, a 38 bit number might be specified as one
8611 field of 32 bits then one of 6 bits.
8612 @emph{For portability, never pass fields which are more
8613 than 32 bits long. Many OpenOCD implementations do not
8614 support 64-bit (or larger) integer values.}
8616 All TAPs other than @var{tap} must be in BYPASS mode.
8617 The single bit in their data registers does not matter.
8619 When @var{tap_state} is specified, the JTAG state machine is left
8621 For example @sc{drpause} might be specified, so that more
8622 instructions can be issued before re-entering the @sc{run/idle} state.
8623 If the end state is not specified, the @sc{run/idle} state is entered.
8626 OpenOCD does not record information about data register lengths,
8627 so @emph{it is important that you get the bit field lengths right}.
8628 Remember that different JTAG instructions refer to different
8629 data registers, which may have different lengths.
8630 Moreover, those lengths may not be fixed;
8631 the SCAN_N instruction can change the length of
8632 the register accessed by the INTEST instruction
8633 (by connecting a different scan chain).
8637 @deffn Command {flush_count}
8638 Returns the number of times the JTAG queue has been flushed.
8639 This may be used for performance tuning.
8641 For example, flushing a queue over USB involves a
8642 minimum latency, often several milliseconds, which does
8643 not change with the amount of data which is written.
8644 You may be able to identify performance problems by finding
8645 tasks which waste bandwidth by flushing small transfers too often,
8646 instead of batching them into larger operations.
8649 @deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
8650 For each @var{tap} listed, loads the instruction register
8651 with its associated numeric @var{instruction}.
8652 (The number of bits in that instruction may be displayed
8653 using the @command{scan_chain} command.)
8654 For other TAPs, a BYPASS instruction is loaded.
8656 When @var{tap_state} is specified, the JTAG state machine is left
8658 For example @sc{irpause} might be specified, so the data register
8659 can be loaded before re-entering the @sc{run/idle} state.
8660 If the end state is not specified, the @sc{run/idle} state is entered.
8663 OpenOCD currently supports only a single field for instruction
8664 register values, unlike data register values.
8665 For TAPs where the instruction register length is more than 32 bits,
8666 portable scripts currently must issue only BYPASS instructions.
8670 @deffn Command {jtag_reset} trst srst
8671 Set values of reset signals.
8672 The @var{trst} and @var{srst} parameter values may be
8673 @option{0}, indicating that reset is inactive (pulled or driven high),
8674 or @option{1}, indicating it is active (pulled or driven low).
8675 The @command{reset_config} command should already have been used
8676 to configure how the board and JTAG adapter treat these two
8677 signals, and to say if either signal is even present.
8678 @xref{Reset Configuration}.
8680 Note that TRST is specially handled.
8681 It actually signifies JTAG's @sc{reset} state.
8682 So if the board doesn't support the optional TRST signal,
8683 or it doesn't support it along with the specified SRST value,
8684 JTAG reset is triggered with TMS and TCK signals
8685 instead of the TRST signal.
8686 And no matter how that JTAG reset is triggered, once
8687 the scan chain enters @sc{reset} with TRST inactive,
8688 TAP @code{post-reset} events are delivered to all TAPs
8689 with handlers for that event.
8692 @deffn Command {pathmove} start_state [next_state ...]
8693 Start by moving to @var{start_state}, which
8694 must be one of the @emph{stable} states.
8695 Unless it is the only state given, this will often be the
8696 current state, so that no TCK transitions are needed.
8697 Then, in a series of single state transitions
8698 (conforming to the JTAG state machine) shift to
8699 each @var{next_state} in sequence, one per TCK cycle.
8700 The final state must also be stable.
8703 @deffn Command {runtest} @var{num_cycles}
8704 Move to the @sc{run/idle} state, and execute at least
8705 @var{num_cycles} of the JTAG clock (TCK).
8706 Instructions often need some time
8707 to execute before they take effect.
8710 @c tms_sequence (short|long)
8711 @c ... temporary, debug-only, other than USBprog bug workaround...
8713 @deffn Command {verify_ircapture} (@option{enable}|@option{disable})
8714 Verify values captured during @sc{ircapture} and returned
8715 during IR scans. Default is enabled, but this can be
8716 overridden by @command{verify_jtag}.
8717 This flag is ignored when validating JTAG chain configuration.
8720 @deffn Command {verify_jtag} (@option{enable}|@option{disable})
8721 Enables verification of DR and IR scans, to help detect
8722 programming errors. For IR scans, @command{verify_ircapture}
8723 must also be enabled.
8727 @section TAP state names
8728 @cindex TAP state names
8730 The @var{tap_state} names used by OpenOCD in the @command{drscan},
8731 @command{irscan}, and @command{pathmove} commands are the same
8732 as those used in SVF boundary scan documents, except that
8733 SVF uses @sc{idle} instead of @sc{run/idle}.
8736 @item @b{RESET} ... @emph{stable} (with TMS high);
8737 acts as if TRST were pulsed
8738 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
8741 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
8742 through the data register
8744 @item @b{DRPAUSE} ... @emph{stable}; data register ready
8745 for update or more shifting
8750 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
8751 through the instruction register
8753 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
8754 for update or more shifting
8759 Note that only six of those states are fully ``stable'' in the
8760 face of TMS fixed (low except for @sc{reset})
8761 and a free-running JTAG clock. For all the
8762 others, the next TCK transition changes to a new state.
8765 @item From @sc{drshift} and @sc{irshift}, clock transitions will
8766 produce side effects by changing register contents. The values
8767 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
8768 may not be as expected.
8769 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
8770 choices after @command{drscan} or @command{irscan} commands,
8771 since they are free of JTAG side effects.
8772 @item @sc{run/idle} may have side effects that appear at non-JTAG
8773 levels, such as advancing the ARM9E-S instruction pipeline.
8774 Consult the documentation for the TAP(s) you are working with.
8777 @node Boundary Scan Commands
8778 @chapter Boundary Scan Commands
8780 One of the original purposes of JTAG was to support
8781 boundary scan based hardware testing.
8782 Although its primary focus is to support On-Chip Debugging,
8783 OpenOCD also includes some boundary scan commands.
8785 @section SVF: Serial Vector Format
8786 @cindex Serial Vector Format
8789 The Serial Vector Format, better known as @dfn{SVF}, is a
8790 way to represent JTAG test patterns in text files.
8791 In a debug session using JTAG for its transport protocol,
8792 OpenOCD supports running such test files.
8794 @deffn Command {svf} filename [@option{quiet}]
8795 This issues a JTAG reset (Test-Logic-Reset) and then
8796 runs the SVF script from @file{filename}.
8797 Unless the @option{quiet} option is specified,
8798 each command is logged before it is executed.
8801 @section XSVF: Xilinx Serial Vector Format
8802 @cindex Xilinx Serial Vector Format
8805 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
8806 binary representation of SVF which is optimized for use with
8808 In a debug session using JTAG for its transport protocol,
8809 OpenOCD supports running such test files.
8811 @quotation Important
8812 Not all XSVF commands are supported.
8815 @deffn Command {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
8816 This issues a JTAG reset (Test-Logic-Reset) and then
8817 runs the XSVF script from @file{filename}.
8818 When a @var{tapname} is specified, the commands are directed at
8820 When @option{virt2} is specified, the @sc{xruntest} command counts
8821 are interpreted as TCK cycles instead of microseconds.
8822 Unless the @option{quiet} option is specified,
8823 messages are logged for comments and some retries.
8826 The OpenOCD sources also include two utility scripts
8827 for working with XSVF; they are not currently installed
8828 after building the software.
8829 You may find them useful:
8832 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
8833 syntax understood by the @command{xsvf} command; see notes below.
8834 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
8835 understands the OpenOCD extensions.
8838 The input format accepts a handful of non-standard extensions.
8839 These include three opcodes corresponding to SVF extensions
8840 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
8841 two opcodes supporting a more accurate translation of SVF
8842 (XTRST, XWAITSTATE).
8843 If @emph{xsvfdump} shows a file is using those opcodes, it
8844 probably will not be usable with other XSVF tools.
8847 @node Utility Commands
8848 @chapter Utility Commands
8849 @cindex Utility Commands
8851 @section RAM testing
8854 There is often a need to stress-test random access memory (RAM) for
8855 errors. OpenOCD comes with a Tcl implementation of well-known memory
8856 testing procedures allowing the detection of all sorts of issues with
8857 electrical wiring, defective chips, PCB layout and other common
8860 To use them, you usually need to initialise your RAM controller first;
8861 consult your SoC's documentation to get the recommended list of
8862 register operations and translate them to the corresponding
8863 @command{mww}/@command{mwb} commands.
8865 Load the memory testing functions with
8868 source [find tools/memtest.tcl]
8871 to get access to the following facilities:
8873 @deffn Command {memTestDataBus} address
8874 Test the data bus wiring in a memory region by performing a walking
8875 1's test at a fixed address within that region.
8878 @deffn Command {memTestAddressBus} baseaddress size
8879 Perform a walking 1's test on the relevant bits of the address and
8880 check for aliasing. This test will find single-bit address failures
8881 such as stuck-high, stuck-low, and shorted pins.
8884 @deffn Command {memTestDevice} baseaddress size
8885 Test the integrity of a physical memory device by performing an
8886 increment/decrement test over the entire region. In the process every
8887 storage bit in the device is tested as zero and as one.
8890 @deffn Command {runAllMemTests} baseaddress size
8891 Run all of the above tests over a specified memory region.
8894 @section Firmware recovery helpers
8895 @cindex Firmware recovery
8897 OpenOCD includes an easy-to-use script to facilitate mass-market
8898 devices recovery with JTAG.
8900 For quickstart instructions run:
8902 openocd -f tools/firmware-recovery.tcl -c firmware_help
8908 If OpenOCD runs on an embedded host (as ZY1000 does), then TFTP can
8909 be used to access files on PCs (either the developer's PC or some other PC).
8911 The way this works on the ZY1000 is to prefix a filename by
8912 "/tftp/ip/" and append the TFTP path on the TFTP
8913 server (tftpd). For example,
8916 load_image /tftp/10.0.0.96/c:\temp\abc.elf
8919 will load c:\temp\abc.elf from the developer pc (10.0.0.96) into memory as
8920 if the file was hosted on the embedded host.
8922 In order to achieve decent performance, you must choose a TFTP server
8923 that supports a packet size bigger than the default packet size (512 bytes). There
8924 are numerous TFTP servers out there (free and commercial) and you will have to do
8925 a bit of googling to find something that fits your requirements.
8927 @node GDB and OpenOCD
8928 @chapter GDB and OpenOCD
8930 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
8931 to debug remote targets.
8932 Setting up GDB to work with OpenOCD can involve several components:
8935 @item The OpenOCD server support for GDB may need to be configured.
8936 @xref{gdbconfiguration,,GDB Configuration}.
8937 @item GDB's support for OpenOCD may need configuration,
8938 as shown in this chapter.
8939 @item If you have a GUI environment like Eclipse,
8940 that also will probably need to be configured.
8943 Of course, the version of GDB you use will need to be one which has
8944 been built to know about the target CPU you're using. It's probably
8945 part of the tool chain you're using. For example, if you are doing
8946 cross-development for ARM on an x86 PC, instead of using the native
8947 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
8948 if that's the tool chain used to compile your code.
8950 @section Connecting to GDB
8951 @cindex Connecting to GDB
8952 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
8953 instance GDB 6.3 has a known bug that produces bogus memory access
8954 errors, which has since been fixed; see
8955 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
8957 OpenOCD can communicate with GDB in two ways:
8961 A socket (TCP/IP) connection is typically started as follows:
8963 target remote localhost:3333
8965 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
8967 It is also possible to use the GDB extended remote protocol as follows:
8969 target extended-remote localhost:3333
8972 A pipe connection is typically started as follows:
8974 target remote | openocd -c "gdb_port pipe; log_output openocd.log"
8976 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
8977 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
8978 session. log_output sends the log output to a file to ensure that the pipe is
8979 not saturated when using higher debug level outputs.
8982 To list the available OpenOCD commands type @command{monitor help} on the
8985 @section Sample GDB session startup
8987 With the remote protocol, GDB sessions start a little differently
8988 than they do when you're debugging locally.
8989 Here's an example showing how to start a debug session with a
8991 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
8992 Most programs would be written into flash (address 0) and run from there.
8995 $ arm-none-eabi-gdb example.elf
8996 (gdb) target remote localhost:3333
8997 Remote debugging using localhost:3333
8999 (gdb) monitor reset halt
9002 Loading section .vectors, size 0x100 lma 0x20000000
9003 Loading section .text, size 0x5a0 lma 0x20000100
9004 Loading section .data, size 0x18 lma 0x200006a0
9005 Start address 0x2000061c, load size 1720
9006 Transfer rate: 22 KB/sec, 573 bytes/write.
9012 You could then interrupt the GDB session to make the program break,
9013 type @command{where} to show the stack, @command{list} to show the
9014 code around the program counter, @command{step} through code,
9015 set breakpoints or watchpoints, and so on.
9017 @section Configuring GDB for OpenOCD
9019 OpenOCD supports the gdb @option{qSupported} packet, this enables information
9020 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
9021 packet size and the device's memory map.
9022 You do not need to configure the packet size by hand,
9023 and the relevant parts of the memory map should be automatically
9024 set up when you declare (NOR) flash banks.
9026 However, there are other things which GDB can't currently query.
9027 You may need to set those up by hand.
9028 As OpenOCD starts up, you will often see a line reporting
9032 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
9035 You can pass that information to GDB with these commands:
9038 set remote hardware-breakpoint-limit 6
9039 set remote hardware-watchpoint-limit 4
9042 With that particular hardware (Cortex-M3) the hardware breakpoints
9043 only work for code running from flash memory. Most other ARM systems
9044 do not have such restrictions.
9046 Another example of useful GDB configuration came from a user who
9047 found that single stepping his Cortex-M3 didn't work well with IRQs
9048 and an RTOS until he told GDB to disable the IRQs while stepping:
9052 mon cortex_m maskisr on
9054 define hookpost-step
9055 mon cortex_m maskisr off
9059 Rather than typing such commands interactively, you may prefer to
9060 save them in a file and have GDB execute them as it starts, perhaps
9061 using a @file{.gdbinit} in your project directory or starting GDB
9062 using @command{gdb -x filename}.
9064 @section Programming using GDB
9065 @cindex Programming using GDB
9066 @anchor{programmingusinggdb}
9068 By default the target memory map is sent to GDB. This can be disabled by
9069 the following OpenOCD configuration option:
9071 gdb_memory_map disable
9073 For this to function correctly a valid flash configuration must also be set
9074 in OpenOCD. For faster performance you should also configure a valid
9077 Informing GDB of the memory map of the target will enable GDB to protect any
9078 flash areas of the target and use hardware breakpoints by default. This means
9079 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
9080 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
9082 To view the configured memory map in GDB, use the GDB command @option{info mem}.
9083 All other unassigned addresses within GDB are treated as RAM.
9085 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
9086 This can be changed to the old behaviour by using the following GDB command
9088 set mem inaccessible-by-default off
9091 If @command{gdb_flash_program enable} is also used, GDB will be able to
9092 program any flash memory using the vFlash interface.
9094 GDB will look at the target memory map when a load command is given, if any
9095 areas to be programmed lie within the target flash area the vFlash packets
9098 If the target needs configuring before GDB programming, an event
9099 script can be executed:
9101 $_TARGETNAME configure -event EVENTNAME BODY
9104 To verify any flash programming the GDB command @option{compare-sections}
9106 @anchor{usingopenocdsmpwithgdb}
9107 @section Using OpenOCD SMP with GDB
9109 For SMP support following GDB serial protocol packet have been defined :
9111 @item j - smp status request
9112 @item J - smp set request
9115 OpenOCD implements :
9117 @item @option{jc} packet for reading core id displayed by
9118 GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or
9119 @option{E01} for target not smp.
9120 @item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue
9121 (core id -1 is reserved for returning to normal resume mode). Reply @option{E01}
9122 for target not smp or @option{OK} on success.
9125 Handling of this packet within GDB can be done :
9127 @item by the creation of an internal variable (i.e @option{_core}) by mean
9128 of function allocate_computed_value allowing following GDB command.
9131 #Jc01 packet is sent
9133 #jc packet is sent and result is affected in $
9136 @item by the usage of GDB maintenance command as described in following example (2 cpus in SMP with
9137 core id 0 and 1 @pxref{definecputargetsworkinginsmp,,Define CPU targets working in SMP}).
9140 # toggle0 : force display of coreid 0
9146 # toggle1 : force display of coreid 1
9155 @section RTOS Support
9156 @cindex RTOS Support
9157 @anchor{gdbrtossupport}
9159 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
9160 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
9162 @xref{Threads, Debugging Programs with Multiple Threads,
9163 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
9166 @* An example setup is below:
9169 $_TARGETNAME configure -rtos auto
9172 This will attempt to auto detect the RTOS within your application.
9174 Currently supported rtos's include:
9177 @item @option{ThreadX}
9178 @item @option{FreeRTOS}
9179 @item @option{linux}
9180 @item @option{ChibiOS}
9181 @item @option{embKernel}
9183 @item @option{uCOS-III}
9187 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
9188 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
9193 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
9194 @item ThreadX symbols
9195 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
9196 @item FreeRTOS symbols
9197 @c The following is taken from recent texinfo to provide compatibility
9198 @c with ancient versions that do not support @raggedright
9201 \rightskip0pt plus2em \spaceskip.3333em \xspaceskip.5em\relax
9202 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
9203 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
9204 uxCurrentNumberOfTasks, uxTopUsedPriority.
9210 @item ChibiOS symbols
9211 rlist, ch_debug, chSysInit.
9212 @item embKernel symbols
9213 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
9214 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
9216 _mqx_kernel_data, MQX_init_struct.
9217 @item uC/OS-III symbols
9218 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
9221 For most RTOS supported the above symbols will be exported by default. However for
9222 some, eg. FreeRTOS and uC/OS-III, extra steps must be taken.
9224 These RTOSes may require additional OpenOCD-specific file to be linked
9225 along with the project:
9229 contrib/rtos-helpers/FreeRTOS-openocd.c
9231 contrib/rtos-helpers/uCOS-III-openocd.c
9234 @node Tcl Scripting API
9235 @chapter Tcl Scripting API
9236 @cindex Tcl Scripting API
9240 Tcl commands are stateless; e.g. the @command{telnet} command has
9241 a concept of currently active target, the Tcl API proc's take this sort
9242 of state information as an argument to each proc.
9244 There are three main types of return values: single value, name value
9245 pair list and lists.
9247 Name value pair. The proc 'foo' below returns a name/value pair
9252 > set foo(you) Oyvind
9253 > set foo(mouse) Micky
9254 > set foo(duck) Donald
9266 me Duane you Oyvind mouse Micky duck Donald
9269 Thus, to get the names of the associative array is easy:
9272 foreach { name value } [set foo] {
9273 puts "Name: $name, Value: $value"
9277 Lists returned should be relatively small. Otherwise, a range
9278 should be passed in to the proc in question.
9280 @section Internal low-level Commands
9282 By "low-level," we mean commands that a human would typically not
9285 Some low-level commands need to be prefixed with "ocd_"; e.g.
9286 @command{ocd_flash_banks}
9287 is the low-level API upon which @command{flash banks} is implemented.
9290 @item @b{mem2array} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9292 Read memory and return as a Tcl array for script processing
9293 @item @b{array2mem} <@var{varname}> <@var{width}> <@var{addr}> <@var{nelems}>
9295 Convert a Tcl array to memory locations and write the values
9296 @item @b{ocd_flash_banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
9298 Return information about the flash banks
9300 @item @b{capture} <@var{command}>
9302 Run <@var{command}> and return full log output that was produced during
9303 its execution. Example:
9306 > capture "reset init"
9311 OpenOCD commands can consist of two words, e.g. "flash banks". The
9312 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
9313 called "flash_banks".
9315 @section OpenOCD specific Global Variables
9317 Real Tcl has ::tcl_platform(), and platform::identify, and many other
9318 variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
9319 holds one of the following values:
9322 @item @b{cygwin} Running under Cygwin
9323 @item @b{darwin} Darwin (Mac-OS) is the underlying operating sytem.
9324 @item @b{freebsd} Running under FreeBSD
9325 @item @b{openbsd} Running under OpenBSD
9326 @item @b{netbsd} Running under NetBSD
9327 @item @b{linux} Linux is the underlying operating sytem
9328 @item @b{mingw32} Running under MingW32
9329 @item @b{winxx} Built using Microsoft Visual Studio
9330 @item @b{ecos} Running under eCos
9331 @item @b{other} Unknown, none of the above.
9334 Note: 'winxx' was choosen because today (March-2009) no distinction is made between Win32 and Win64.
9337 We should add support for a variable like Tcl variable
9338 @code{tcl_platform(platform)}, it should be called
9339 @code{jim_platform} (because it
9340 is jim, not real tcl).
9343 @section Tcl RPC server
9346 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
9347 commands and receive the results.
9349 To access it, your application needs to connect to a configured TCP port
9350 (see @command{tcl_port}). Then it can pass any string to the
9351 interpreter terminating it with @code{0x1a} and wait for the return
9352 value (it will be terminated with @code{0x1a} as well). This can be
9353 repeated as many times as desired without reopening the connection.
9355 Remember that most of the OpenOCD commands need to be prefixed with
9356 @code{ocd_} to get the results back. Sometimes you might also need the
9357 @command{capture} command.
9359 See @file{contrib/rpc_examples/} for specific client implementations.
9361 @section Tcl RPC server notifications
9362 @cindex RPC Notifications
9364 Notifications are sent asynchronously to other commands being executed over
9365 the RPC server, so the port must be polled continuously.
9367 Target event, state and reset notifications are emitted as Tcl associative arrays
9368 in the following format.
9371 type target_event event [event-name]
9372 type target_state state [state-name]
9373 type target_reset mode [reset-mode]
9376 @deffn {Command} tcl_notifications [on/off]
9377 Toggle output of target notifications to the current Tcl RPC server.
9378 Only available from the Tcl RPC server.
9383 @section Tcl RPC server trace output
9384 @cindex RPC trace output
9386 Trace data is sent asynchronously to other commands being executed over
9387 the RPC server, so the port must be polled continuously.
9389 Target trace data is emitted as a Tcl associative array in the following format.
9392 type target_trace data [trace-data-hex-encoded]
9395 @deffn {Command} tcl_trace [on/off]
9396 Toggle output of target trace data to the current Tcl RPC server.
9397 Only available from the Tcl RPC server.
9400 See an example application here:
9401 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
9410 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
9412 @cindex adaptive clocking
9415 In digital circuit design it is often refered to as ``clock
9416 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
9417 operating at some speed, your CPU target is operating at another.
9418 The two clocks are not synchronised, they are ``asynchronous''
9420 In order for the two to work together they must be synchronised
9421 well enough to work; JTAG can't go ten times faster than the CPU,
9422 for example. There are 2 basic options:
9425 Use a special "adaptive clocking" circuit to change the JTAG
9426 clock rate to match what the CPU currently supports.
9428 The JTAG clock must be fixed at some speed that's enough slower than
9429 the CPU clock that all TMS and TDI transitions can be detected.
9432 @b{Does this really matter?} For some chips and some situations, this
9433 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
9434 the CPU has no difficulty keeping up with JTAG.
9435 Startup sequences are often problematic though, as are other
9436 situations where the CPU clock rate changes (perhaps to save
9439 For example, Atmel AT91SAM chips start operation from reset with
9440 a 32kHz system clock. Boot firmware may activate the main oscillator
9441 and PLL before switching to a faster clock (perhaps that 500 MHz
9443 If you're using JTAG to debug that startup sequence, you must slow
9444 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
9445 JTAG can use a faster clock.
9447 Consider also debugging a 500MHz ARM926 hand held battery powered
9448 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
9449 clock, between keystrokes unless it has work to do. When would
9450 that 5 MHz JTAG clock be usable?
9452 @b{Solution #1 - A special circuit}
9454 In order to make use of this,
9455 your CPU, board, and JTAG adapter must all support the RTCK
9456 feature. Not all of them support this; keep reading!
9458 The RTCK ("Return TCK") signal in some ARM chips is used to help with
9459 this problem. ARM has a good description of the problem described at
9460 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
9461 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
9462 work? / how does adaptive clocking work?''.
9464 The nice thing about adaptive clocking is that ``battery powered hand
9465 held device example'' - the adaptiveness works perfectly all the
9466 time. One can set a break point or halt the system in the deep power
9467 down code, slow step out until the system speeds up.
9469 Note that adaptive clocking may also need to work at the board level,
9470 when a board-level scan chain has multiple chips.
9471 Parallel clock voting schemes are good way to implement this,
9472 both within and between chips, and can easily be implemented
9474 It's not difficult to have logic fan a module's input TCK signal out
9475 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
9476 back with the right polarity before changing the output RTCK signal.
9477 Texas Instruments makes some clock voting logic available
9478 for free (with no support) in VHDL form; see
9479 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
9481 @b{Solution #2 - Always works - but may be slower}
9483 Often this is a perfectly acceptable solution.
9485 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
9486 the target clock speed. But what that ``magic division'' is varies
9487 depending on the chips on your board.
9488 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
9489 ARM11 cores use an 8:1 division.
9490 @b{Xilinx rule of thumb} is 1/12 the clock speed.
9492 Note: most full speed FT2232 based JTAG adapters are limited to a
9493 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
9494 often support faster clock rates (and adaptive clocking).
9496 You can still debug the 'low power' situations - you just need to
9497 either use a fixed and very slow JTAG clock rate ... or else
9498 manually adjust the clock speed at every step. (Adjusting is painful
9499 and tedious, and is not always practical.)
9501 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
9502 have a special debug mode in your application that does a ``high power
9503 sleep''. If you are careful - 98% of your problems can be debugged
9506 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
9507 operation in your idle loops even if you don't otherwise change the CPU
9509 That operation gates the CPU clock, and thus the JTAG clock; which
9510 prevents JTAG access. One consequence is not being able to @command{halt}
9511 cores which are executing that @emph{wait for interrupt} operation.
9513 To set the JTAG frequency use the command:
9521 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
9523 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
9524 around Windows filenames.
9537 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
9539 Make sure you have Cygwin installed, or at least a version of OpenOCD that
9540 claims to come with all the necessary DLLs. When using Cygwin, try launching
9541 OpenOCD from the Cygwin shell.
9543 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a frontend like Insight or
9544 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
9545 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
9547 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
9548 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
9549 software breakpoints consume one of the two available hardware breakpoints.
9551 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
9553 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
9554 clock at the time you're programming the flash. If you've specified the crystal's
9555 frequency, make sure the PLL is disabled. If you've specified the full core speed
9556 (e.g. 60MHz), make sure the PLL is enabled.
9558 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
9559 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
9560 out while waiting for end of scan, rtck was disabled".
9562 Make sure your PC's parallel port operates in EPP mode. You might have to try several
9563 settings in your PC BIOS (ECP, EPP, and different versions of those).
9565 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
9566 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
9567 memory read caused data abort".
9569 The errors are non-fatal, and are the result of GDB trying to trace stack frames
9570 beyond the last valid frame. It might be possible to prevent this by setting up
9571 a proper "initial" stack frame, if you happen to know what exactly has to
9572 be done, feel free to add this here.
9574 @b{Simple:} In your startup code - push 8 registers of zeros onto the
9575 stack before calling main(). What GDB is doing is ``climbing'' the run
9576 time stack by reading various values on the stack using the standard
9577 call frame for the target. GDB keeps going - until one of 2 things
9578 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
9579 stackframes have been processed. By pushing zeros on the stack, GDB
9582 @b{Debugging Interrupt Service Routines} - In your ISR before you call
9583 your C code, do the same - artifically push some zeros onto the stack,
9584 remember to pop them off when the ISR is done.
9586 @b{Also note:} If you have a multi-threaded operating system, they
9587 often do not @b{in the intrest of saving memory} waste these few
9591 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
9592 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
9594 This warning doesn't indicate any serious problem, as long as you don't want to
9595 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
9596 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
9597 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
9598 independently. With this setup, it's not possible to halt the core right out of
9599 reset, everything else should work fine.
9601 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
9602 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
9603 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
9604 quit with an error message. Is there a stability issue with OpenOCD?
9606 No, this is not a stability issue concerning OpenOCD. Most users have solved
9607 this issue by simply using a self-powered USB hub, which they connect their
9608 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
9609 supply stable enough for the Amontec JTAGkey to be operated.
9611 @b{Laptops running on battery have this problem too...}
9613 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
9614 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
9615 What does that mean and what might be the reason for this?
9617 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
9618 has closed the connection to OpenOCD. This might be a GDB issue.
9620 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
9621 are described, there is a parameter for specifying the clock frequency
9622 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
9623 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
9624 specified in kilohertz. However, I do have a quartz crystal of a
9625 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
9626 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
9629 No. The clock frequency specified here must be given as an integral number.
9630 However, this clock frequency is used by the In-Application-Programming (IAP)
9631 routines of the LPC2000 family only, which seems to be very tolerant concerning
9632 the given clock frequency, so a slight difference between the specified clock
9633 frequency and the actual clock frequency will not cause any trouble.
9635 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
9637 Well, yes and no. Commands can be given in arbitrary order, yet the
9638 devices listed for the JTAG scan chain must be given in the right
9639 order (jtag newdevice), with the device closest to the TDO-Pin being
9640 listed first. In general, whenever objects of the same type exist
9641 which require an index number, then these objects must be given in the
9642 right order (jtag newtap, targets and flash banks - a target
9643 references a jtag newtap and a flash bank references a target).
9645 You can use the ``scan_chain'' command to verify and display the tap order.
9647 Also, some commands can't execute until after @command{init} has been
9648 processed. Such commands include @command{nand probe} and everything
9649 else that needs to write to controller registers, perhaps for setting
9650 up DRAM and loading it with code.
9652 @anchor{faqtaporder}
9653 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
9656 Yes; whenever you have more than one, you must declare them in
9657 the same order used by the hardware.
9659 Many newer devices have multiple JTAG TAPs. For example: ST
9660 Microsystems STM32 chips have two TAPs, a ``boundary scan TAP'' and
9661 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
9662 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
9663 connected to the boundary scan TAP, which then connects to the
9664 Cortex-M3 TAP, which then connects to the TDO pin.
9666 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
9667 (2) The boundary scan TAP. If your board includes an additional JTAG
9668 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
9669 place it before or after the STM32 chip in the chain. For example:
9672 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
9673 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
9674 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
9675 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
9676 @item Xilinx TDO Pin -> OpenOCD TDO (input)
9679 The ``jtag device'' commands would thus be in the order shown below. Note:
9682 @item jtag newtap Xilinx tap -irlen ...
9683 @item jtag newtap stm32 cpu -irlen ...
9684 @item jtag newtap stm32 bs -irlen ...
9685 @item # Create the debug target and say where it is
9686 @item target create stm32.cpu -chain-position stm32.cpu ...
9690 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
9691 log file, I can see these error messages: Error: arm7_9_common.c:561
9692 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
9698 @node Tcl Crash Course
9699 @chapter Tcl Crash Course
9702 Not everyone knows Tcl - this is not intended to be a replacement for
9703 learning Tcl, the intent of this chapter is to give you some idea of
9704 how the Tcl scripts work.
9706 This chapter is written with two audiences in mind. (1) OpenOCD users
9707 who need to understand a bit more of how Jim-Tcl works so they can do
9708 something useful, and (2) those that want to add a new command to
9711 @section Tcl Rule #1
9712 There is a famous joke, it goes like this:
9714 @item Rule #1: The wife is always correct
9715 @item Rule #2: If you think otherwise, See Rule #1
9718 The Tcl equal is this:
9721 @item Rule #1: Everything is a string
9722 @item Rule #2: If you think otherwise, See Rule #1
9725 As in the famous joke, the consequences of Rule #1 are profound. Once
9726 you understand Rule #1, you will understand Tcl.
9728 @section Tcl Rule #1b
9729 There is a second pair of rules.
9731 @item Rule #1: Control flow does not exist. Only commands
9732 @* For example: the classic FOR loop or IF statement is not a control
9733 flow item, they are commands, there is no such thing as control flow
9735 @item Rule #2: If you think otherwise, See Rule #1
9736 @* Actually what happens is this: There are commands that by
9737 convention, act like control flow key words in other languages. One of
9738 those commands is the word ``for'', another command is ``if''.
9741 @section Per Rule #1 - All Results are strings
9742 Every Tcl command results in a string. The word ``result'' is used
9743 deliberatly. No result is just an empty string. Remember: @i{Rule #1 -
9744 Everything is a string}
9746 @section Tcl Quoting Operators
9747 In life of a Tcl script, there are two important periods of time, the
9748 difference is subtle.
9751 @item Evaluation Time
9754 The two key items here are how ``quoted things'' work in Tcl. Tcl has
9755 three primary quoting constructs, the [square-brackets] the
9756 @{curly-braces@} and ``double-quotes''
9758 By now you should know $VARIABLES always start with a $DOLLAR
9759 sign. BTW: To set a variable, you actually use the command ``set'', as
9760 in ``set VARNAME VALUE'' much like the ancient BASIC langauge ``let x
9761 = 1'' statement, but without the equal sign.
9764 @item @b{[square-brackets]}
9765 @* @b{[square-brackets]} are command substitutions. It operates much
9766 like Unix Shell `back-ticks`. The result of a [square-bracket]
9767 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
9768 string}. These two statements are roughly identical:
9772 echo "The Date is: $X"
9775 puts "The Date is: $X"
9777 @item @b{``double-quoted-things''}
9778 @* @b{``double-quoted-things''} are just simply quoted
9779 text. $VARIABLES and [square-brackets] are expanded in place - the
9780 result however is exactly 1 string. @i{Remember Rule #1 - Everything
9784 puts "It is now \"[date]\", $x is in 1 hour"
9786 @item @b{@{Curly-Braces@}}
9787 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
9788 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
9789 'single-quote' operators in BASH shell scripts, with the added
9790 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
9791 nested 3 times@}@}@} NOTE: [date] is a bad example;
9792 at this writing, Jim/OpenOCD does not have a date command.
9795 @section Consequences of Rule 1/2/3/4
9797 The consequences of Rule 1 are profound.
9799 @subsection Tokenisation & Execution.
9801 Of course, whitespace, blank lines and #comment lines are handled in
9804 As a script is parsed, each (multi) line in the script file is
9805 tokenised and according to the quoting rules. After tokenisation, that
9806 line is immedatly executed.
9808 Multi line statements end with one or more ``still-open''
9809 @{curly-braces@} which - eventually - closes a few lines later.
9811 @subsection Command Execution
9813 Remember earlier: There are no ``control flow''
9814 statements in Tcl. Instead there are COMMANDS that simply act like
9815 control flow operators.
9817 Commands are executed like this:
9820 @item Parse the next line into (argc) and (argv[]).
9821 @item Look up (argv[0]) in a table and call its function.
9822 @item Repeat until End Of File.
9825 It sort of works like this:
9828 ReadAndParse( &argc, &argv );
9830 cmdPtr = LookupCommand( argv[0] );
9832 (*cmdPtr->Execute)( argc, argv );
9836 When the command ``proc'' is parsed (which creates a procedure
9837 function) it gets 3 parameters on the command line. @b{1} the name of
9838 the proc (function), @b{2} the list of parameters, and @b{3} the body
9839 of the function. Not the choice of words: LIST and BODY. The PROC
9840 command stores these items in a table somewhere so it can be found by
9843 @subsection The FOR command
9845 The most interesting command to look at is the FOR command. In Tcl,
9846 the FOR command is normally implemented in C. Remember, FOR is a
9847 command just like any other command.
9849 When the ascii text containing the FOR command is parsed, the parser
9850 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
9854 @item The ascii text 'for'
9855 @item The start text
9856 @item The test expression
9861 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
9862 Remember @i{Rule #1 - Everything is a string.} The key point is this:
9863 Often many of those parameters are in @{curly-braces@} - thus the
9864 variables inside are not expanded or replaced until later.
9866 Remember that every Tcl command looks like the classic ``main( argc,
9867 argv )'' function in C. In JimTCL - they actually look like this:
9871 MyCommand( Jim_Interp *interp,
9873 Jim_Obj * const *argvs );
9876 Real Tcl is nearly identical. Although the newer versions have
9877 introduced a byte-code parser and intepreter, but at the core, it
9878 still operates in the same basic way.
9880 @subsection FOR command implementation
9882 To understand Tcl it is perhaps most helpful to see the FOR
9883 command. Remember, it is a COMMAND not a control flow structure.
9885 In Tcl there are two underlying C helper functions.
9887 Remember Rule #1 - You are a string.
9889 The @b{first} helper parses and executes commands found in an ascii
9890 string. Commands can be seperated by semicolons, or newlines. While
9891 parsing, variables are expanded via the quoting rules.
9893 The @b{second} helper evaluates an ascii string as a numerical
9894 expression and returns a value.
9896 Here is an example of how the @b{FOR} command could be
9897 implemented. The pseudo code below does not show error handling.
9899 void Execute_AsciiString( void *interp, const char *string );
9901 int Evaluate_AsciiExpression( void *interp, const char *string );
9904 MyForCommand( void *interp,
9909 SetResult( interp, "WRONG number of parameters");
9913 // argv[0] = the ascii string just like C
9915 // Execute the start statement.
9916 Execute_AsciiString( interp, argv[1] );
9920 i = Evaluate_AsciiExpression(interp, argv[2]);
9925 Execute_AsciiString( interp, argv[3] );
9927 // Execute the LOOP part
9928 Execute_AsciiString( interp, argv[4] );
9932 SetResult( interp, "" );
9937 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
9938 in the same basic way.
9940 @section OpenOCD Tcl Usage
9942 @subsection source and find commands
9943 @b{Where:} In many configuration files
9944 @* Example: @b{ source [find FILENAME] }
9945 @*Remember the parsing rules
9947 @item The @command{find} command is in square brackets,
9948 and is executed with the parameter FILENAME. It should find and return
9949 the full path to a file with that name; it uses an internal search path.
9950 The RESULT is a string, which is substituted into the command line in
9951 place of the bracketed @command{find} command.
9952 (Don't try to use a FILENAME which includes the "#" character.
9953 That character begins Tcl comments.)
9954 @item The @command{source} command is executed with the resulting filename;
9955 it reads a file and executes as a script.
9957 @subsection format command
9958 @b{Where:} Generally occurs in numerous places.
9959 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
9965 puts [format "The answer: %d" [expr $x * $y]]
9968 @item The SET command creates 2 variables, X and Y.
9969 @item The double [nested] EXPR command performs math
9970 @* The EXPR command produces numerical result as a string.
9972 @item The format command is executed, producing a single string
9973 @* Refer to Rule #1.
9974 @item The PUTS command outputs the text.
9976 @subsection Body or Inlined Text
9977 @b{Where:} Various TARGET scripts.
9980 proc someproc @{@} @{
9981 ... multiple lines of stuff ...
9983 $_TARGETNAME configure -event FOO someproc
9984 #2 Good - no variables
9985 $_TARGETNAME confgure -event foo "this ; that;"
9986 #3 Good Curly Braces
9987 $_TARGETNAME configure -event FOO @{
9990 #4 DANGER DANGER DANGER
9991 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
9994 @item The $_TARGETNAME is an OpenOCD variable convention.
9995 @*@b{$_TARGETNAME} represents the last target created, the value changes
9996 each time a new target is created. Remember the parsing rules. When
9997 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
9998 the name of the target which happens to be a TARGET (object)
10000 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
10001 @*There are 4 examples:
10003 @item The TCLBODY is a simple string that happens to be a proc name
10004 @item The TCLBODY is several simple commands seperated by semicolons
10005 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
10006 @item The TCLBODY is a string with variables that get expanded.
10009 In the end, when the target event FOO occurs the TCLBODY is
10010 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
10011 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
10013 Remember the parsing rules. In case #3, @{curly-braces@} mean the
10014 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
10015 and the text is evaluated. In case #4, they are replaced before the
10016 ``Target Object Command'' is executed. This occurs at the same time
10017 $_TARGETNAME is replaced. In case #4 the date will never
10018 change. @{BTW: [date] is a bad example; at this writing,
10019 Jim/OpenOCD does not have a date command@}
10021 @subsection Global Variables
10022 @b{Where:} You might discover this when writing your own procs @* In
10023 simple terms: Inside a PROC, if you need to access a global variable
10024 you must say so. See also ``upvar''. Example:
10026 proc myproc @{ @} @{
10027 set y 0 #Local variable Y
10028 global x #Global variable X
10029 puts [format "X=%d, Y=%d" $x $y]
10032 @section Other Tcl Hacks
10033 @b{Dynamic variable creation}
10035 # Dynamically create a bunch of variables.
10036 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr $x + 1]@} @{
10038 set vn [format "BIT%d" $x]
10042 set $vn [expr (1 << $x)]
10045 @b{Dynamic proc/command creation}
10047 # One "X" function - 5 uart functions.
10048 foreach who @{A B C D E@}
10049 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
10055 @node OpenOCD Concept Index
10056 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
10057 @comment case issue with ``Index.html'' and ``index.html''
10058 @comment Occurs when creating ``--html --no-split'' output
10059 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
10060 @unnumbered OpenOCD Concept Index
10064 @node Command and Driver Index
10065 @unnumbered Command and Driver Index