1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle OpenOCD User's Guide
5 @dircategory Development
7 * OpenOCD: (openocd). OpenOCD User's Guide
16 This User's Guide documents
17 release @value{VERSION},
18 dated @value{UPDATED},
19 of the Open On-Chip Debugger (OpenOCD).
22 @item Copyright @copyright{} 2008 The OpenOCD Project
23 @item Copyright @copyright{} 2007-2008 Spencer Oliver @email{spen@@spen-soft.co.uk}
24 @item Copyright @copyright{} 2008-2010 Oyvind Harboe @email{oyvind.harboe@@zylin.com}
25 @item Copyright @copyright{} 2008 Duane Ellis @email{openocd@@duaneellis.com}
26 @item Copyright @copyright{} 2009-2010 David Brownell
30 Permission is granted to copy, distribute and/or modify this document
31 under the terms of the GNU Free Documentation License, Version 1.2 or
32 any later version published by the Free Software Foundation; with no
33 Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A
34 copy of the license is included in the section entitled ``GNU Free
35 Documentation License''.
40 @titlefont{@emph{Open On-Chip Debugger:}}
42 @title OpenOCD User's Guide
43 @subtitle for release @value{VERSION}
44 @subtitle @value{UPDATED}
47 @vskip 0pt plus 1filll
56 @top OpenOCD User's Guide
62 * About:: About OpenOCD
63 * Developers:: OpenOCD Developer Resources
64 * Debug Adapter Hardware:: Debug Adapter Hardware
65 * About Jim-Tcl:: About Jim-Tcl
66 * Running:: Running OpenOCD
67 * OpenOCD Project Setup:: OpenOCD Project Setup
68 * Config File Guidelines:: Config File Guidelines
69 * Server Configuration:: Server Configuration
70 * Debug Adapter Configuration:: Debug Adapter Configuration
71 * Reset Configuration:: Reset Configuration
72 * TAP Declaration:: TAP Declaration
73 * CPU Configuration:: CPU Configuration
74 * Flash Commands:: Flash Commands
75 * Flash Programming:: Flash Programming
76 * PLD/FPGA Commands:: PLD/FPGA Commands
77 * General Commands:: General Commands
78 * Architecture and Core Commands:: Architecture and Core Commands
79 * JTAG Commands:: JTAG Commands
80 * Boundary Scan Commands:: Boundary Scan Commands
81 * Utility Commands:: Utility Commands
82 * GDB and OpenOCD:: Using GDB and OpenOCD
83 * Tcl Scripting API:: Tcl Scripting API
84 * FAQ:: Frequently Asked Questions
85 * Tcl Crash Course:: Tcl Crash Course
86 * License:: GNU Free Documentation License
88 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
89 @comment case issue with ``Index.html'' and ``index.html''
90 @comment Occurs when creating ``--html --no-split'' output
91 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
92 * OpenOCD Concept Index:: Concept Index
93 * Command and Driver Index:: Command and Driver Index
100 OpenOCD was created by Dominic Rath as part of a 2005 diploma thesis written
101 at the University of Applied Sciences Augsburg (@uref{http://www.hs-augsburg.de}).
102 Since that time, the project has grown into an active open-source project,
103 supported by a diverse community of software and hardware developers from
106 @section What is OpenOCD?
110 The Open On-Chip Debugger (OpenOCD) aims to provide debugging,
111 in-system programming and boundary-scan testing for embedded target
114 It does so with the assistance of a @dfn{debug adapter}, which is
115 a small hardware module which helps provide the right kind of
116 electrical signaling to the target being debugged. These are
117 required since the debug host (on which OpenOCD runs) won't
118 usually have native support for such signaling, or the connector
119 needed to hook up to the target.
121 Such debug adapters support one or more @dfn{transport} protocols,
122 each of which involves different electrical signaling (and uses
123 different messaging protocols on top of that signaling). There
124 are many types of debug adapter, and little uniformity in what
125 they are called. (There are also product naming differences.)
127 These adapters are sometimes packaged as discrete dongles, which
128 may generically be called @dfn{hardware interface dongles}.
129 Some development boards also integrate them directly, which may
130 let the development board connect directly to the debug
131 host over USB (and sometimes also to power it over USB).
133 For example, a @dfn{JTAG Adapter} supports JTAG
134 signaling, and is used to communicate
135 with JTAG (IEEE 1149.1) compliant TAPs on your target board.
136 A @dfn{TAP} is a ``Test Access Port'', a module which processes
137 special instructions and data. TAPs are daisy-chained within and
138 between chips and boards. JTAG supports debugging and boundary
141 There are also @dfn{SWD Adapters} that support Serial Wire Debug (SWD)
142 signaling to communicate with some newer ARM cores, as well as debug
143 adapters which support both JTAG and SWD transports. SWD supports only
144 debugging, whereas JTAG also supports boundary scan operations.
146 For some chips, there are also @dfn{Programming Adapters} supporting
147 special transports used only to write code to flash memory, without
148 support for on-chip debugging or boundary scan.
149 (At this writing, OpenOCD does not support such non-debug adapters.)
152 @b{Dongles:} OpenOCD currently supports many types of hardware dongles:
153 USB-based, parallel port-based, and other standalone boxes that run
154 OpenOCD internally. @xref{Debug Adapter Hardware}.
156 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
157 ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
158 (Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
159 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
161 @b{Flash Programming:} Flash writing is supported for external
162 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
163 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
164 STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
165 controllers (LPC3180, Orion, S3C24xx, more) is included.
167 @section OpenOCD Web Site
169 The OpenOCD web site provides the latest public news from the community:
171 @uref{http://openocd.org/}
173 @section Latest User's Guide:
175 The user's guide you are now reading may not be the latest one
176 available. A version for more recent code may be available.
177 Its HTML form is published regularly at:
179 @uref{http://openocd.org/doc/html/index.html}
181 PDF form is likewise published at:
183 @uref{http://openocd.org/doc/pdf/openocd.pdf}
185 @section OpenOCD User's Forum
187 There is an OpenOCD forum (phpBB) hosted by SparkFun,
188 which might be helpful to you. Note that if you want
189 anything to come to the attention of developers, you
190 should post it to the OpenOCD Developer Mailing List
191 instead of this forum.
193 @uref{http://forum.sparkfun.com/viewforum.php?f=18}
195 @section OpenOCD User's Mailing List
197 The OpenOCD User Mailing List provides the primary means of
198 communication between users:
200 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-user}
204 Support can also be found on irc:
205 @uref{irc://irc.libera.chat/openocd}
208 @chapter OpenOCD Developer Resources
211 If you are interested in improving the state of OpenOCD's debugging and
212 testing support, new contributions will be welcome. Motivated developers
213 can produce new target, flash or interface drivers, improve the
214 documentation, as well as more conventional bug fixes and enhancements.
216 The resources in this chapter are available for developers wishing to explore
217 or expand the OpenOCD source code.
219 @section OpenOCD Git Repository
221 During the 0.3.x release cycle, OpenOCD switched from Subversion to
222 a Git repository hosted at SourceForge. The repository URL is:
224 @uref{git://git.code.sf.net/p/openocd/code}
228 @uref{http://git.code.sf.net/p/openocd/code}
230 You may prefer to use a mirror and the HTTP protocol:
232 @uref{http://repo.or.cz/r/openocd.git}
234 With standard Git tools, use @command{git clone} to initialize
235 a local repository, and @command{git pull} to update it.
236 There are also gitweb pages letting you browse the repository
237 with a web browser, or download arbitrary snapshots without
238 needing a Git client:
240 @uref{http://repo.or.cz/w/openocd.git}
242 The @file{README} file contains the instructions for building the project
243 from the repository or a snapshot.
245 Developers that want to contribute patches to the OpenOCD system are
246 @b{strongly} encouraged to work against mainline.
247 Patches created against older versions may require additional
248 work from their submitter in order to be updated for newer releases.
250 @section Doxygen Developer Manual
252 During the 0.2.x release cycle, the OpenOCD project began
253 providing a Doxygen reference manual. This document contains more
254 technical information about the software internals, development
255 processes, and similar documentation:
257 @uref{http://openocd.org/doc/doxygen/html/index.html}
259 This document is a work-in-progress, but contributions would be welcome
260 to fill in the gaps. All of the source files are provided in-tree,
261 listed in the Doxyfile configuration at the top of the source tree.
263 @section Gerrit Review System
265 All changes in the OpenOCD Git repository go through the web-based Gerrit
268 @uref{https://review.openocd.org/}
270 After a one-time registration and repository setup, anyone can push commits
271 from their local Git repository directly into Gerrit.
272 All users and developers are encouraged to review, test, discuss and vote
273 for changes in Gerrit. The feedback provides the basis for a maintainer to
274 eventually submit the change to the main Git repository.
276 The @file{HACKING} file, also available as the Patch Guide in the Doxygen
277 Developer Manual, contains basic information about how to connect a
278 repository to Gerrit, prepare and push patches. Patch authors are expected to
279 maintain their changes while they're in Gerrit, respond to feedback and if
280 necessary rework and push improved versions of the change.
282 @section OpenOCD Developer Mailing List
284 The OpenOCD Developer Mailing List provides the primary means of
285 communication between developers:
287 @uref{https://lists.sourceforge.net/mailman/listinfo/openocd-devel}
289 @section OpenOCD Bug Tracker
291 The OpenOCD Bug Tracker is hosted on SourceForge:
293 @uref{http://bugs.openocd.org/}
296 @node Debug Adapter Hardware
297 @chapter Debug Adapter Hardware
305 Defined: @b{dongle}: A small device that plugs into a computer and serves as
306 an adapter .... [snip]
308 In the OpenOCD case, this generally refers to @b{a small adapter} that
309 attaches to your computer via USB or the parallel port.
312 @section Choosing a Dongle
314 There are several things you should keep in mind when choosing a dongle.
317 @item @b{Transport} Does it support the kind of communication that you need?
318 OpenOCD focuses mostly on JTAG. Your version may also support
319 other ways to communicate with target devices.
320 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
321 Does your dongle support it? You might need a level converter.
322 @item @b{Pinout} What pinout does your target board use?
323 Does your dongle support it? You may be able to use jumper
324 wires, or an "octopus" connector, to convert pinouts.
325 @item @b{Connection} Does your computer have the USB, parallel, or
326 Ethernet port needed?
327 @item @b{RTCK} Do you expect to use it with ARM chips and boards with
328 RTCK support (also known as ``adaptive clocking'')?
331 @section USB FT2232 Based
333 There are many USB JTAG dongles on the market, many of them based
334 on a chip from ``Future Technology Devices International'' (FTDI)
335 known as the FTDI FT2232; this is a USB full speed (12 Mbps) chip.
336 See: @url{http://www.ftdichip.com} for more information.
337 In summer 2009, USB high speed (480 Mbps) versions of these FTDI
338 chips started to become available in JTAG adapters. Around 2012, a new
339 variant appeared - FT232H - this is a single-channel version of FT2232H.
340 (Adapters using those high speed FT2232H or FT232H chips may support adaptive
343 The FT2232 chips are flexible enough to support some other
344 transport options, such as SWD or the SPI variants used to
345 program some chips. They have two communications channels,
346 and one can be used for a UART adapter at the same time the
347 other one is used to provide a debug adapter.
349 Also, some development boards integrate an FT2232 chip to serve as
350 a built-in low-cost debug adapter and USB-to-serial solution.
354 @* Link @url{http://elk.informatik.fh-augsburg.de/hhweb/doc/openocd/usbjtag/usbjtag.html}
356 @* See: @url{http://www.amontec.com/jtagkey.shtml}
358 @* See: @url{http://www.amontec.com/jtagkey2.shtml}
360 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
362 @* See: @url{http://www.signalyzer.com}
363 @item @b{Stellaris Eval Boards}
364 @* See: @url{http://www.ti.com} - The Stellaris eval boards
365 bundle FT2232-based JTAG and SWD support, which can be used to debug
366 the Stellaris chips. Using separate JTAG adapters is optional.
367 These boards can also be used in a "pass through" mode as JTAG adapters
368 to other target boards, disabling the Stellaris chip.
369 @item @b{TI/Luminary ICDI}
370 @* See: @url{http://www.ti.com} - TI/Luminary In-Circuit Debug
371 Interface (ICDI) Boards are included in Stellaris LM3S9B9x
372 Evaluation Kits. Like the non-detachable FT2232 support on the other
373 Stellaris eval boards, they can be used to debug other target boards.
374 @item @b{olimex-jtag}
375 @* See: @url{http://www.olimex.com}
376 @item @b{Flyswatter/Flyswatter2}
377 @* See: @url{http://www.tincantools.com}
378 @item @b{turtelizer2}
380 @uref{http://www.ethernut.de/en/hardware/turtelizer/index.html, Turtelizer 2}, or
381 @url{http://www.ethernut.de}
383 @* Link: @url{http://www.hitex.com/index.php?id=383}
385 @* Link @url{http://www.hitex.com/stm32-stick}
386 @item @b{axm0432_jtag}
387 @* Axiom AXM-0432 Link @url{http://www.axman.com} - NOTE: This JTAG does not appear
388 to be available anymore as of April 2012.
390 @* Link @url{http://www.hitex.com/index.php?id=cortino}
391 @item @b{dlp-usb1232h}
392 @* Link @url{http://www.dlpdesign.com/usb/usb1232h.shtml}
393 @item @b{digilent-hs1}
394 @* Link @url{http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-HS1}
396 @* Link @url{http://code.google.com/p/opendous/wiki/JTAG} FT2232H-based
398 @item @b{JTAG-lock-pick Tiny 2}
399 @* Link @url{http://www.distortec.com/jtag-lock-pick-tiny-2} FT232H-based
402 @* Link: @url{http://shop.gateworks.com/index.php?route=product/product&path=70_80&product_id=64}
406 @section USB-JTAG / Altera USB-Blaster compatibles
408 These devices also show up as FTDI devices, but are not
409 protocol-compatible with the FT2232 devices. They are, however,
410 protocol-compatible among themselves. USB-JTAG devices typically consist
411 of a FT245 followed by a CPLD that understands a particular protocol,
412 or emulates this protocol using some other hardware.
414 They may appear under different USB VID/PID depending on the particular
415 product. The driver can be configured to search for any VID/PID pair
416 (see the section on driver commands).
419 @item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
420 @* Link: @url{http://ixo-jtag.sourceforge.net/}
421 @item @b{Altera USB-Blaster}
422 @* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
425 @section USB J-Link based
426 There are several OEM versions of the SEGGER @b{J-Link} adapter. It is
427 an example of a microcontroller based JTAG adapter, it uses an
428 AT91SAM764 internally.
431 @item @b{SEGGER J-Link}
432 @* Link: @url{http://www.segger.com/jlink.html}
433 @item @b{Atmel SAM-ICE} (Only works with Atmel chips!)
434 @* Link: @url{http://www.atmel.com/tools/atmelsam-ice.aspx}
438 @section USB RLINK based
439 Raisonance has an adapter called @b{RLink}. It exists in a stripped-down form on the STM32 Primer,
440 permanently attached to the JTAG lines. It also exists on the STM32 Primer2, but that is wired for
441 SWD and not JTAG, thus not supported.
444 @item @b{Raisonance RLink}
445 @* Link: @url{http://www.mcu-raisonance.com/~rlink-debugger-programmer__@/microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html}
446 @item @b{STM32 Primer}
447 @* Link: @url{http://www.stm32circle.com/resources/stm32primer.php}
448 @item @b{STM32 Primer2}
449 @* Link: @url{http://www.stm32circle.com/resources/stm32primer2.php}
452 @section USB ST-LINK based
453 STMicroelectronics has an adapter called @b{ST-LINK}.
454 They only work with STMicroelectronics chips, notably STM32 and STM8.
458 @* This is available standalone and as part of some kits, eg. STM32VLDISCOVERY.
459 @* Link: @url{http://www.st.com/internet/evalboard/product/219866.jsp}
461 @* This is available standalone and as part of some kits, eg. STM32F4DISCOVERY.
462 @* Link: @url{http://www.st.com/internet/evalboard/product/251168.jsp}
464 @* This is available standalone and as part of some kits.
465 @* Link: @url{http://www.st.com/stlink-v3}
468 For info the original ST-LINK enumerates using the mass storage usb class; however,
469 its implementation is completely broken. The result is this causes issues under Linux.
470 The simplest solution is to get Linux to ignore the ST-LINK using one of the following methods:
472 @item modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i
473 @item add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf
476 @section USB TI/Stellaris ICDI based
477 Texas Instruments has an adapter called @b{ICDI}.
478 It is not to be confused with the FTDI based adapters that were originally fitted to their
479 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
481 @section USB Nuvoton Nu-Link
482 Nuvoton has an adapter called @b{Nu-Link}.
483 It is available either as stand-alone dongle and embedded on development boards.
484 It supports SWD, serial port bridge and mass storage for firmware update.
485 Both Nu-Link v1 and v2 are supported.
487 @section USB CMSIS-DAP based
488 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
489 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
494 @* Link: @url{http://shop.embedded-projects.net/} - which uses an Atmel MEGA32 and a UBN9604
496 @item @b{USB - Presto}
497 @* Link: @url{http://tools.asix.net/prg_presto.htm}
499 @item @b{Versaloon-Link}
500 @* Link: @url{http://www.versaloon.com}
502 @item @b{ARM-JTAG-EW}
503 @* Link: @url{http://www.olimex.com/dev/arm-jtag-ew.html}
506 @* Link: @url{http://dangerousprototypes.com/bus-pirate-manual/}
509 @* Link: @url{http://code.google.com/p/opendous-jtag/} - which uses an AT90USB162
512 @* Link: @url{http://code.google.com/p/estick-jtag/}
514 @item @b{Keil ULINK v1}
515 @* Link: @url{http://www.keil.com/ulink1/}
517 @item @b{TI XDS110 Debug Probe}
518 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
519 @* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
522 @section IBM PC Parallel Printer Port Based
524 The two well-known ``JTAG Parallel Ports'' cables are the Xilinx DLC5
525 and the Macraigor Wiggler. There are many clones and variations of
528 Note that parallel ports are becoming much less common, so if you
529 have the choice you should probably avoid these adapters in favor
534 @item @b{Wiggler} - There are many clones of this.
535 @* Link: @url{http://www.macraigor.com/wiggler.htm}
537 @item @b{DLC5} - From XILINX - There are many clones of this
538 @* Link: Search the web for: ``XILINX DLC5'' - it is no longer
539 produced, PDF schematics are easily found and it is easy to make.
541 @item @b{Amontec - JTAG Accelerator}
542 @* Link: @url{http://www.amontec.com/jtag_accelerator.shtml}
545 @* Link: @url{http://www.ccac.rwth-aachen.de/~michaels/index.php/hardware/armjtag}
547 @item @b{Wiggler_ntrst_inverted}
548 @* Yet another variation - See the source code, src/jtag/parport.c
550 @item @b{old_amt_wiggler}
551 @* Unknown - probably not on the market today
554 @* Link: Most likely @url{http://www.olimex.com/dev/arm-jtag.html} [another wiggler clone]
557 @* Link: @url{http://www.amontec.com/chameleon.shtml}
563 @* ispDownload from Lattice Semiconductor
564 @url{http://www.latticesemi.com/lit/docs/@/devtools/dlcable.pdf}
567 @* From STMicroelectronics;
568 @* Link: @url{http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/DM00039500.pdf}
576 @* An EP93xx based Linux machine using the GPIO pins directly.
579 @* Like the EP93xx - but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip.
581 @item @b{bcm2835gpio}
582 @* A BCM2835-based board (e.g. Raspberry Pi) using the GPIO pins of the expansion header.
585 @* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on any i.MX processor).
588 @* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the GPIO pins of the expansion headers.
591 @* A JTAG driver acting as a client for the JTAG VPI server interface.
592 @* Link: @url{http://github.com/fjullien/jtag_vpi}
595 @* A driver for Cadence virtual Debug Interface to emulated or simulated targets.
596 It implements a client connecting to the vdebug server, which in turn communicates
597 with the emulated or simulated RTL model through a transactor. The current version
598 supports only JTAG as a transport, but other virtual transports, like DAP are planned.
601 @* A JTAG driver acting as a client for the SystemVerilog Direct Programming
602 Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
603 interface of a hardware model written in SystemVerilog, for example, on an
604 emulation model of target hardware.
606 @item @b{xlnx_pcie_xvc}
607 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
610 @* A bitbang JTAG driver using Linux GPIO through library libgpiod.
613 @* A bitbang JTAG driver using Linux legacy sysfs GPIO.
614 This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
619 @chapter About Jim-Tcl
623 OpenOCD uses a small ``Tcl Interpreter'' known as Jim-Tcl.
624 This programming language provides a simple and extensible
627 All commands presented in this Guide are extensions to Jim-Tcl.
628 You can use them as simple commands, without needing to learn
629 much of anything about Tcl.
630 Alternatively, you can write Tcl programs with them.
632 You can learn more about Jim at its website, @url{http://jim.tcl.tk}.
633 There is an active and responsive community, get on the mailing list
634 if you have any questions. Jim-Tcl maintainers also lurk on the
635 OpenOCD mailing list.
638 @item @b{Jim vs. Tcl}
639 @* Jim-Tcl is a stripped down version of the well known Tcl language,
640 which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far
641 fewer features. Jim-Tcl is several dozens of .C files and .H files and
642 implements the basic Tcl command set. In contrast: Tcl 8.6 is a
643 4.2 MB .zip file containing 1540 files.
645 @item @b{Missing Features}
646 @* Our practice has been: Add/clone the real Tcl feature if/when
647 needed. We welcome Jim-Tcl improvements, not bloat. Also there
648 are a large number of optional Jim-Tcl features that are not
652 @* OpenOCD configuration scripts are Jim-Tcl Scripts. OpenOCD's
653 command interpreter today is a mixture of (newer)
654 Jim-Tcl commands, and the (older) original command interpreter.
657 @* At the OpenOCD telnet command line (or via the GDB monitor command) one
658 can type a Tcl for() loop, set variables, etc.
659 Some of the commands documented in this guide are implemented
660 as Tcl scripts, from a @file{startup.tcl} file internal to the server.
662 @item @b{Historical Note}
663 @* Jim-Tcl was introduced to OpenOCD in spring 2008. Fall 2010,
664 before OpenOCD 0.5 release, OpenOCD switched to using Jim-Tcl
665 as a Git submodule, which greatly simplified upgrading Jim-Tcl
666 to benefit from new features and bugfixes in Jim-Tcl.
668 @item @b{Need a crash course in Tcl?}
669 @*@xref{Tcl Crash Course}.
674 @cindex command line options
676 @cindex directory search
678 Properly installing OpenOCD sets up your operating system to grant it access
679 to the debug adapters. On Linux, this usually involves installing a file
680 in @file{/etc/udev/rules.d,} so OpenOCD has permissions. An example rules file
681 that works for many common adapters is shipped with OpenOCD in the
682 @file{contrib} directory. MS-Windows needs
683 complex and confusing driver configuration for every peripheral. Such issues
684 are unique to each operating system, and are not detailed in this User's Guide.
686 Then later you will invoke the OpenOCD server, with various options to
687 tell it how each debug session should work.
688 The @option{--help} option shows:
692 --help | -h display this help
693 --version | -v display OpenOCD version
694 --file | -f use configuration file <name>
695 --search | -s dir to search for config files and scripts
696 --debug | -d set debug level to 3
697 | -d<n> set debug level to <level>
698 --log_output | -l redirect log output to file <name>
699 --command | -c run <command>
702 If you don't give any @option{-f} or @option{-c} options,
703 OpenOCD tries to read the configuration file @file{openocd.cfg}.
704 To specify one or more different
705 configuration files, use @option{-f} options. For example:
708 openocd -f config1.cfg -f config2.cfg -f config3.cfg
711 Configuration files and scripts are searched for in
713 @item the current directory,
714 @item any search dir specified on the command line using the @option{-s} option,
715 @item any search dir specified using the @command{add_script_search_dir} command,
716 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
717 @item @file{%APPDATA%/OpenOCD} (only on Windows),
718 @item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
719 @item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
720 @item @file{$HOME/.openocd},
721 @item the site wide script library @file{$pkgdatadir/site} and
722 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
724 The first found file with a matching file name will be used.
727 Don't try to use configuration script names or paths which
728 include the "#" character. That character begins Tcl comments.
731 @section Simple setup, no customization
733 In the best case, you can use two scripts from one of the script
734 libraries, hook up your JTAG adapter, and start the server ... and
735 your JTAG setup will just work "out of the box". Always try to
736 start by reusing those scripts, but assume you'll need more
737 customization even if this works. @xref{OpenOCD Project Setup}.
739 If you find a script for your JTAG adapter, and for your board or
740 target, you may be able to hook up your JTAG adapter then start
741 the server with some variation of one of the following:
744 openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
745 openocd -f interface/ftdi/ADAPTER.cfg -f board/MYBOARD.cfg
748 You might also need to configure which reset signals are present,
749 using @option{-c 'reset_config trst_and_srst'} or something similar.
750 If all goes well you'll see output something like
753 Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
754 For bug reports, read
755 http://openocd.org/doc/doxygen/bugs.html
756 Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
757 (mfg: 0x23b, part: 0xba00, ver: 0x3)
760 Seeing that "tap/device found" message, and no warnings, means
761 the JTAG communication is working. That's a key milestone, but
762 you'll probably need more project-specific setup.
764 @section What OpenOCD does as it starts
766 OpenOCD starts by processing the configuration commands provided
767 on the command line or, if there were no @option{-c command} or
768 @option{-f file.cfg} options given, in @file{openocd.cfg}.
769 @xref{configurationstage,,Configuration Stage}.
770 At the end of the configuration stage it verifies the JTAG scan
771 chain defined using those commands; your configuration should
772 ensure that this always succeeds.
773 Normally, OpenOCD then starts running as a server.
774 Alternatively, commands may be used to terminate the configuration
775 stage early, perform work (such as updating some flash memory),
776 and then shut down without acting as a server.
778 Once OpenOCD starts running as a server, it waits for connections from
779 clients (Telnet, GDB, RPC) and processes the commands issued through
782 If you are having problems, you can enable internal debug messages via
783 the @option{-d} option.
785 Also it is possible to interleave Jim-Tcl commands w/config scripts using the
786 @option{-c} command line switch.
788 To enable debug output (when reporting problems or working on OpenOCD
789 itself), use the @option{-d} command line switch. This sets the
790 @option{debug_level} to "3", outputting the most information,
791 including debug messages. The default setting is "2", outputting only
792 informational messages, warnings and errors. You can also change this
793 setting from within a telnet or gdb session using @command{debug_level<n>}
794 (@pxref{debuglevel,,debug_level}).
796 You can redirect all output from the server to a file using the
797 @option{-l <logfile>} switch.
799 Note! OpenOCD will launch the GDB & telnet server even if it can not
800 establish a connection with the target. In general, it is possible for
801 the JTAG controller to be unresponsive until the target is set up
802 correctly via e.g. GDB monitor commands in a GDB init script.
804 @node OpenOCD Project Setup
805 @chapter OpenOCD Project Setup
807 To use OpenOCD with your development projects, you need to do more than
808 just connect the JTAG adapter hardware (dongle) to your development board
809 and start the OpenOCD server.
810 You also need to configure your OpenOCD server so that it knows
811 about your adapter and board, and helps your work.
812 You may also want to connect OpenOCD to GDB, possibly
813 using Eclipse or some other GUI.
815 @section Hooking up the JTAG Adapter
817 Today's most common case is a dongle with a JTAG cable on one side
818 (such as a ribbon cable with a 10-pin or 20-pin IDC connector)
819 and a USB cable on the other.
820 Instead of USB, some dongles use Ethernet;
821 older ones may use a PC parallel port, or even a serial port.
824 @item @emph{Start with power to your target board turned off},
825 and nothing connected to your JTAG adapter.
826 If you're particularly paranoid, unplug power to the board.
827 It's important to have the ground signal properly set up,
828 unless you are using a JTAG adapter which provides
829 galvanic isolation between the target board and the
832 @item @emph{Be sure it's the right kind of JTAG connector.}
833 If your dongle has a 20-pin ARM connector, you need some kind
834 of adapter (or octopus, see below) to hook it up to
835 boards using 14-pin or 10-pin connectors ... or to 20-pin
836 connectors which don't use ARM's pinout.
838 In the same vein, make sure the voltage levels are compatible.
839 Not all JTAG adapters have the level shifters needed to work
840 with 1.2 Volt boards.
842 @item @emph{Be certain the cable is properly oriented} or you might
843 damage your board. In most cases there are only two possible
844 ways to connect the cable.
845 Connect the JTAG cable from your adapter to the board.
846 Be sure it's firmly connected.
848 In the best case, the connector is keyed to physically
849 prevent you from inserting it wrong.
850 This is most often done using a slot on the board's male connector
851 housing, which must match a key on the JTAG cable's female connector.
852 If there's no housing, then you must look carefully and
853 make sure pin 1 on the cable hooks up to pin 1 on the board.
854 Ribbon cables are frequently all grey except for a wire on one
855 edge, which is red. The red wire is pin 1.
857 Sometimes dongles provide cables where one end is an ``octopus'' of
858 color coded single-wire connectors, instead of a connector block.
859 These are great when converting from one JTAG pinout to another,
860 but are tedious to set up.
861 Use these with connector pinout diagrams to help you match up the
862 adapter signals to the right board pins.
864 @item @emph{Connect the adapter's other end} once the JTAG cable is connected.
865 A USB, parallel, or serial port connector will go to the host which
866 you are using to run OpenOCD.
867 For Ethernet, consult the documentation and your network administrator.
869 For USB-based JTAG adapters you have an easy sanity check at this point:
870 does the host operating system see the JTAG adapter? If you're running
871 Linux, try the @command{lsusb} command. If that host is an
872 MS-Windows host, you'll need to install a driver before OpenOCD works.
874 @item @emph{Connect the adapter's power supply, if needed.}
875 This step is primarily for non-USB adapters,
876 but sometimes USB adapters need extra power.
878 @item @emph{Power up the target board.}
879 Unless you just let the magic smoke escape,
880 you're now ready to set up the OpenOCD server
881 so you can use JTAG to work with that board.
885 Talk with the OpenOCD server using
886 telnet (@code{telnet localhost 4444} on many systems) or GDB.
887 @xref{GDB and OpenOCD}.
889 @section Project Directory
891 There are many ways you can configure OpenOCD and start it up.
893 A simple way to organize them all involves keeping a
894 single directory for your work with a given board.
895 When you start OpenOCD from that directory,
896 it searches there first for configuration files, scripts,
897 files accessed through semihosting,
898 and for code you upload to the target board.
899 It is also the natural place to write files,
900 such as log files and data you download from the board.
902 @section Configuration Basics
904 There are two basic ways of configuring OpenOCD, and
905 a variety of ways you can mix them.
906 Think of the difference as just being how you start the server:
909 @item Many @option{-f file} or @option{-c command} options on the command line
910 @item No options, but a @dfn{user config file}
911 in the current directory named @file{openocd.cfg}
914 Here is an example @file{openocd.cfg} file for a setup
915 using a Signalyzer FT2232-based JTAG adapter to talk to
916 a board with an Atmel AT91SAM7X256 microcontroller:
919 source [find interface/ftdi/signalyzer.cfg]
921 # GDB can also flash my flash!
922 gdb_memory_map enable
923 gdb_flash_program enable
925 source [find target/sam7x256.cfg]
928 Here is the command line equivalent of that configuration:
931 openocd -f interface/ftdi/signalyzer.cfg \
932 -c "gdb_memory_map enable" \
933 -c "gdb_flash_program enable" \
934 -f target/sam7x256.cfg
937 You could wrap such long command lines in shell scripts,
938 each supporting a different development task.
939 One might re-flash the board with a specific firmware version.
940 Another might set up a particular debugging or run-time environment.
943 At this writing (October 2009) the command line method has
944 problems with how it treats variables.
945 For example, after @option{-c "set VAR value"}, or doing the
946 same in a script, the variable @var{VAR} will have no value
947 that can be tested in a later script.
950 Here we will focus on the simpler solution: one user config
951 file, including basic configuration plus any TCL procedures
952 to simplify your work.
954 @section User Config Files
955 @cindex config file, user
956 @cindex user config file
957 @cindex config file, overview
959 A user configuration file ties together all the parts of a project
961 One of the following will match your situation best:
964 @item Ideally almost everything comes from configuration files
965 provided by someone else.
966 For example, OpenOCD distributes a @file{scripts} directory
967 (probably in @file{/usr/share/openocd/scripts} on Linux).
968 Board and tool vendors can provide these too, as can individual
969 user sites; the @option{-s} command line option lets you say
970 where to find these files. (@xref{Running}.)
971 The AT91SAM7X256 example above works this way.
973 Three main types of non-user configuration file each have their
974 own subdirectory in the @file{scripts} directory:
977 @item @b{interface} -- one for each different debug adapter;
978 @item @b{board} -- one for each different board
979 @item @b{target} -- the chips which integrate CPUs and other JTAG TAPs
982 Best case: include just two files, and they handle everything else.
983 The first is an interface config file.
984 The second is board-specific, and it sets up the JTAG TAPs and
985 their GDB targets (by deferring to some @file{target.cfg} file),
986 declares all flash memory, and leaves you nothing to do except
990 source [find interface/olimex-jtag-tiny.cfg]
991 source [find board/csb337.cfg]
994 Boards with a single microcontroller often won't need more
995 than the target config file, as in the AT91SAM7X256 example.
996 That's because there is no external memory (flash, DDR RAM), and
997 the board differences are encapsulated by application code.
999 @item Maybe you don't know yet what your board looks like to JTAG.
1000 Once you know the @file{interface.cfg} file to use, you may
1001 need help from OpenOCD to discover what's on the board.
1002 Once you find the JTAG TAPs, you can just search for appropriate
1004 configuration files ... or write your own, from the bottom up.
1005 @xref{autoprobing,,Autoprobing}.
1007 @item You can often reuse some standard config files but
1008 need to write a few new ones, probably a @file{board.cfg} file.
1009 You will be using commands described later in this User's Guide,
1010 and working with the guidelines in the next chapter.
1012 For example, there may be configuration files for your JTAG adapter
1013 and target chip, but you need a new board-specific config file
1014 giving access to your particular flash chips.
1015 Or you might need to write another target chip configuration file
1016 for a new chip built around the Cortex-M3 core.
1019 When you write new configuration files, please submit
1020 them for inclusion in the next OpenOCD release.
1021 For example, a @file{board/newboard.cfg} file will help the
1022 next users of that board, and a @file{target/newcpu.cfg}
1023 will help support users of any board using that chip.
1027 You may need to write some C code.
1028 It may be as simple as supporting a new FT2232 or parport
1029 based adapter; a bit more involved, like a NAND or NOR flash
1030 controller driver; or a big piece of work like supporting
1031 a new chip architecture.
1034 Reuse the existing config files when you can.
1035 Look first in the @file{scripts/boards} area, then @file{scripts/targets}.
1036 You may find a board configuration that's a good example to follow.
1038 When you write config files, separate the reusable parts
1039 (things every user of that interface, chip, or board needs)
1040 from ones specific to your environment and debugging approach.
1044 For example, a @code{gdb-attach} event handler that invokes
1045 the @command{reset init} command will interfere with debugging
1046 early boot code, which performs some of the same actions
1047 that the @code{reset-init} event handler does.
1050 Likewise, the @command{arm9 vector_catch} command (or
1051 @cindex vector_catch
1052 its siblings @command{xscale vector_catch}
1053 and @command{cortex_m vector_catch}) can be a time-saver
1054 during some debug sessions, but don't make everyone use that either.
1055 Keep those kinds of debugging aids in your user config file,
1056 along with messaging and tracing setup.
1057 (@xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.)
1060 You might need to override some defaults.
1061 For example, you might need to move, shrink, or back up the target's
1062 work area if your application needs much SRAM.
1065 TCP/IP port configuration is another example of something which
1066 is environment-specific, and should only appear in
1067 a user config file. @xref{tcpipports,,TCP/IP Ports}.
1070 @section Project-Specific Utilities
1072 A few project-specific utility
1073 routines may well speed up your work.
1074 Write them, and keep them in your project's user config file.
1076 For example, if you are making a boot loader work on a
1077 board, it's nice to be able to debug the ``after it's
1078 loaded to RAM'' parts separately from the finicky early
1079 code which sets up the DDR RAM controller and clocks.
1080 A script like this one, or a more GDB-aware sibling,
1084 proc ramboot @{ @} @{
1085 # Reset, running the target's "reset-init" scripts
1086 # to initialize clocks and the DDR RAM controller.
1087 # Leave the CPU halted.
1090 # Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM.
1091 load_image u-boot.bin 0x20000000
1098 Then once that code is working you will need to make it
1099 boot from NOR flash; a different utility would help.
1100 Alternatively, some developers write to flash using GDB.
1101 (You might use a similar script if you're working with a flash
1102 based microcontroller application instead of a boot loader.)
1105 proc newboot @{ @} @{
1106 # Reset, leaving the CPU halted. The "reset-init" event
1107 # proc gives faster access to the CPU and to NOR flash;
1108 # "reset halt" would be slower.
1111 # Write standard version of U-Boot into the first two
1112 # sectors of NOR flash ... the standard version should
1113 # do the same lowlevel init as "reset-init".
1114 flash protect 0 0 1 off
1115 flash erase_sector 0 0 1
1116 flash write_bank 0 u-boot.bin 0x0
1117 flash protect 0 0 1 on
1119 # Reboot from scratch using that new boot loader.
1124 You may need more complicated utility procedures when booting
1126 That often involves an extra bootloader stage,
1127 running from on-chip SRAM to perform DDR RAM setup so it can load
1128 the main bootloader code (which won't fit into that SRAM).
1130 Other helper scripts might be used to write production system images,
1131 involving considerably more than just a three stage bootloader.
1133 @section Target Software Changes
1135 Sometimes you may want to make some small changes to the software
1136 you're developing, to help make JTAG debugging work better.
1137 For example, in C or assembly language code you might
1138 use @code{#ifdef JTAG_DEBUG} (or its converse) around code
1139 handling issues like:
1143 @item @b{Watchdog Timers}...
1144 Watchdog timers are typically used to automatically reset systems if
1145 some application task doesn't periodically reset the timer. (The
1146 assumption is that the system has locked up if the task can't run.)
1147 When a JTAG debugger halts the system, that task won't be able to run
1148 and reset the timer ... potentially causing resets in the middle of
1149 your debug sessions.
1151 It's rarely a good idea to disable such watchdogs, since their usage
1152 needs to be debugged just like all other parts of your firmware.
1153 That might however be your only option.
1155 Look instead for chip-specific ways to stop the watchdog from counting
1156 while the system is in a debug halt state. It may be simplest to set
1157 that non-counting mode in your debugger startup scripts. You may however
1158 need a different approach when, for example, a motor could be physically
1159 damaged by firmware remaining inactive in a debug halt state. That might
1160 involve a type of firmware mode where that "non-counting" mode is disabled
1161 at the beginning then re-enabled at the end; a watchdog reset might fire
1162 and complicate the debug session, but hardware (or people) would be
1163 protected.@footnote{Note that many systems support a "monitor mode" debug
1164 that is a somewhat cleaner way to address such issues. You can think of
1165 it as only halting part of the system, maybe just one task,
1166 instead of the whole thing.
1167 At this writing, January 2010, OpenOCD based debugging does not support
1168 monitor mode debug, only "halt mode" debug.}
1170 @item @b{ARM Semihosting}...
1171 @cindex ARM semihosting
1172 When linked with a special runtime library provided with many
1173 toolchains@footnote{See chapter 8 "Semihosting" in
1174 @uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
1175 ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
1176 The CodeSourcery EABI toolchain also includes a semihosting library.},
1177 your target code can use I/O facilities on the debug host. That library
1178 provides a small set of system calls which are handled by OpenOCD.
1179 It can let the debugger provide your system console and a file system,
1180 helping with early debugging or providing a more capable environment
1181 for sometimes-complex tasks like installing system firmware onto
1184 @item @b{ARM Wait-For-Interrupt}...
1185 Many ARM chips synchronize the JTAG clock using the core clock.
1186 Low power states which stop that core clock thus prevent JTAG access.
1187 Idle loops in tasking environments often enter those low power states
1188 via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
1190 You may want to @emph{disable that instruction} in source code,
1191 or otherwise prevent using that state,
1192 to ensure you can get JTAG access at any time.@footnote{As a more
1193 polite alternative, some processors have special debug-oriented
1194 registers which can be used to change various features including
1195 how the low power states are clocked while debugging.
1196 The STM32 DBGMCU_CR register is an example; at the cost of extra
1197 power consumption, JTAG can be used during low power states.}
1198 For example, the OpenOCD @command{halt} command may not
1199 work for an idle processor otherwise.
1201 @item @b{Delay after reset}...
1202 Not all chips have good support for debugger access
1203 right after reset; many LPC2xxx chips have issues here.
1204 Similarly, applications that reconfigure pins used for
1205 JTAG access as they start will also block debugger access.
1207 To work with boards like this, @emph{enable a short delay loop}
1208 the first thing after reset, before "real" startup activities.
1209 For example, one second's delay is usually more than enough
1210 time for a JTAG debugger to attach, so that
1211 early code execution can be debugged
1212 or firmware can be replaced.
1214 @item @b{Debug Communications Channel (DCC)}...
1215 Some processors include mechanisms to send messages over JTAG.
1216 Many ARM cores support these, as do some cores from other vendors.
1217 (OpenOCD may be able to use this DCC internally, speeding up some
1218 operations like writing to memory.)
1220 Your application may want to deliver various debugging messages
1221 over JTAG, by @emph{linking with a small library of code}
1222 provided with OpenOCD and using the utilities there to send
1223 various kinds of message.
1224 @xref{softwaredebugmessagesandtracing,,Software Debug Messages and Tracing}.
1228 @section Target Hardware Setup
1230 Chip vendors often provide software development boards which
1231 are highly configurable, so that they can support all options
1232 that product boards may require. @emph{Make sure that any
1233 jumpers or switches match the system configuration you are
1236 Common issues include:
1240 @item @b{JTAG setup} ...
1241 Boards may support more than one JTAG configuration.
1242 Examples include jumpers controlling pullups versus pulldowns
1243 on the nTRST and/or nSRST signals, and choice of connectors
1244 (e.g. which of two headers on the base board,
1245 or one from a daughtercard).
1246 For some Texas Instruments boards, you may need to jumper the
1247 EMU0 and EMU1 signals (which OpenOCD won't currently control).
1249 @item @b{Boot Modes} ...
1250 Complex chips often support multiple boot modes, controlled
1251 by external jumpers. Make sure this is set up correctly.
1252 For example many i.MX boards from NXP need to be jumpered
1253 to "ATX mode" to start booting using the on-chip ROM, when
1254 using second stage bootloader code stored in a NAND flash chip.
1256 Such explicit configuration is common, and not limited to
1257 booting from NAND. You might also need to set jumpers to
1258 start booting using code loaded from an MMC/SD card; external
1259 SPI flash; Ethernet, UART, or USB links; NOR flash; OneNAND
1260 flash; some external host; or various other sources.
1263 @item @b{Memory Addressing} ...
1264 Boards which support multiple boot modes may also have jumpers
1265 to configure memory addressing. One board, for example, jumpers
1266 external chipselect 0 (used for booting) to address either
1267 a large SRAM (which must be pre-loaded via JTAG), NOR flash,
1268 or NAND flash. When it's jumpered to address NAND flash, that
1269 board must also be told to start booting from on-chip ROM.
1271 Your @file{board.cfg} file may also need to be told this jumper
1272 configuration, so that it can know whether to declare NOR flash
1273 using @command{flash bank} or instead declare NAND flash with
1274 @command{nand device}; and likewise which probe to perform in
1275 its @code{reset-init} handler.
1277 A closely related issue is bus width. Jumpers might need to
1278 distinguish between 8 bit or 16 bit bus access for the flash
1279 used to start booting.
1281 @item @b{Peripheral Access} ...
1282 Development boards generally provide access to every peripheral
1283 on the chip, sometimes in multiple modes (such as by providing
1284 multiple audio codec chips).
1285 This interacts with software
1286 configuration of pin multiplexing, where for example a
1287 given pin may be routed either to the MMC/SD controller
1288 or the GPIO controller. It also often interacts with
1289 configuration jumpers. One jumper may be used to route
1290 signals to an MMC/SD card slot or an expansion bus (which
1291 might in turn affect booting); others might control which
1292 audio or video codecs are used.
1296 Plus you should of course have @code{reset-init} event handlers
1297 which set up the hardware to match that jumper configuration.
1298 That includes in particular any oscillator or PLL used to clock
1299 the CPU, and any memory controllers needed to access external
1300 memory and peripherals. Without such handlers, you won't be
1301 able to access those resources without working target firmware
1302 which can do that setup ... this can be awkward when you're
1303 trying to debug that target firmware. Even if there's a ROM
1304 bootloader which handles a few issues, it rarely provides full
1305 access to all board-specific capabilities.
1308 @node Config File Guidelines
1309 @chapter Config File Guidelines
1311 This chapter is aimed at any user who needs to write a config file,
1312 including developers and integrators of OpenOCD and any user who
1313 needs to get a new board working smoothly.
1314 It provides guidelines for creating those files.
1316 You should find the following directories under
1317 @t{$(INSTALLDIR)/scripts}, with config files maintained upstream. Use
1318 them as-is where you can; or as models for new files.
1320 @item @file{interface} ...
1321 These are for debug adapters. Files that specify configuration to use
1322 specific JTAG, SWD and other adapters go here.
1323 @item @file{board} ...
1324 Think Circuit Board, PWA, PCB, they go by many names. Board files
1325 contain initialization items that are specific to a board.
1327 They reuse target configuration files, since the same
1328 microprocessor chips are used on many boards,
1329 but support for external parts varies widely. For
1330 example, the SDRAM initialization sequence for the board, or the type
1331 of external flash and what address it uses. Any initialization
1332 sequence to enable that external flash or SDRAM should be found in the
1333 board file. Boards may also contain multiple targets: two CPUs; or
1335 @item @file{target} ...
1336 Think chip. The ``target'' directory represents the JTAG TAPs
1338 which OpenOCD should control, not a board. Two common types of targets
1339 are ARM chips and FPGA or CPLD chips.
1340 When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
1341 the target config file defines all of them.
1342 @item @emph{more} ... browse for other library files which may be useful.
1343 For example, there are various generic and CPU-specific utilities.
1346 The @file{openocd.cfg} user config
1347 file may override features in any of the above files by
1348 setting variables before sourcing the target file, or by adding
1349 commands specific to their situation.
1351 @section Interface Config Files
1353 The user config file
1354 should be able to source one of these files with a command like this:
1357 source [find interface/FOOBAR.cfg]
1360 A preconfigured interface file should exist for every debug adapter
1361 in use today with OpenOCD.
1362 That said, perhaps some of these config files
1363 have only been used by the developer who created it.
1365 A separate chapter gives information about how to set these up.
1366 @xref{Debug Adapter Configuration}.
1367 Read the OpenOCD source code (and Developer's Guide)
1368 if you have a new kind of hardware interface
1369 and need to provide a driver for it.
1371 @deffn {Command} {find} 'filename'
1372 Prints full path to @var{filename} according to OpenOCD search rules.
1375 @deffn {Command} {ocd_find} 'filename'
1376 Prints full path to @var{filename} according to OpenOCD search rules. This
1377 is a low level function used by the @command{find}. Usually you want
1378 to use @command{find}, instead.
1381 @section Board Config Files
1382 @cindex config file, board
1383 @cindex board config file
1385 The user config file
1386 should be able to source one of these files with a command like this:
1389 source [find board/FOOBAR.cfg]
1392 The point of a board config file is to package everything
1393 about a given board that user config files need to know.
1394 In summary the board files should contain (if present)
1397 @item One or more @command{source [find target/...cfg]} statements
1398 @item NOR flash configuration (@pxref{norconfiguration,,NOR Configuration})
1399 @item NAND flash configuration (@pxref{nandconfiguration,,NAND Configuration})
1400 @item Target @code{reset} handlers for SDRAM and I/O configuration
1401 @item JTAG adapter reset configuration (@pxref{Reset Configuration})
1402 @item All things that are not ``inside a chip''
1405 Generic things inside target chips belong in target config files,
1406 not board config files. So for example a @code{reset-init} event
1407 handler should know board-specific oscillator and PLL parameters,
1408 which it passes to target-specific utility code.
1410 The most complex task of a board config file is creating such a
1411 @code{reset-init} event handler.
1412 Define those handlers last, after you verify the rest of the board
1413 configuration works.
1415 @subsection Communication Between Config files
1417 In addition to target-specific utility code, another way that
1418 board and target config files communicate is by following a
1419 convention on how to use certain variables.
1421 The full Tcl/Tk language supports ``namespaces'', but Jim-Tcl does not.
1422 Thus the rule we follow in OpenOCD is this: Variables that begin with
1423 a leading underscore are temporary in nature, and can be modified and
1424 used at will within a target configuration file.
1426 Complex board config files can do the things like this,
1427 for a board with three chips:
1430 # Chip #1: PXA270 for network side, big endian
1431 set CHIPNAME network
1433 source [find target/pxa270.cfg]
1434 # on return: _TARGETNAME = network.cpu
1435 # other commands can refer to the "network.cpu" target.
1436 $_TARGETNAME configure .... events for this CPU..
1438 # Chip #2: PXA270 for video side, little endian
1441 source [find target/pxa270.cfg]
1442 # on return: _TARGETNAME = video.cpu
1443 # other commands can refer to the "video.cpu" target.
1444 $_TARGETNAME configure .... events for this CPU..
1446 # Chip #3: Xilinx FPGA for glue logic
1449 source [find target/spartan3.cfg]
1452 That example is oversimplified because it doesn't show any flash memory,
1453 or the @code{reset-init} event handlers to initialize external DRAM
1454 or (assuming it needs it) load a configuration into the FPGA.
1455 Such features are usually needed for low-level work with many boards,
1456 where ``low level'' implies that the board initialization software may
1457 not be working. (That's a common reason to need JTAG tools. Another
1458 is to enable working with microcontroller-based systems, which often
1459 have no debugging support except a JTAG connector.)
1461 Target config files may also export utility functions to board and user
1462 config files. Such functions should use name prefixes, to help avoid
1465 Board files could also accept input variables from user config files.
1466 For example, there might be a @code{J4_JUMPER} setting used to identify
1467 what kind of flash memory a development board is using, or how to set
1468 up other clocks and peripherals.
1470 @subsection Variable Naming Convention
1471 @cindex variable names
1473 Most boards have only one instance of a chip.
1474 However, it should be easy to create a board with more than
1475 one such chip (as shown above).
1476 Accordingly, we encourage these conventions for naming
1477 variables associated with different @file{target.cfg} files,
1478 to promote consistency and
1479 so that board files can override target defaults.
1481 Inputs to target config files include:
1484 @item @code{CHIPNAME} ...
1485 This gives a name to the overall chip, and is used as part of
1486 tap identifier dotted names.
1487 While the default is normally provided by the chip manufacturer,
1488 board files may need to distinguish between instances of a chip.
1489 @item @code{ENDIAN} ...
1490 By default @option{little} - although chips may hard-wire @option{big}.
1491 Chips that can't change endianness don't need to use this variable.
1492 @item @code{CPUTAPID} ...
1493 When OpenOCD examines the JTAG chain, it can be told verify the
1494 chips against the JTAG IDCODE register.
1495 The target file will hold one or more defaults, but sometimes the
1496 chip in a board will use a different ID (perhaps a newer revision).
1499 Outputs from target config files include:
1502 @item @code{_TARGETNAME} ...
1503 By convention, this variable is created by the target configuration
1504 script. The board configuration file may make use of this variable to
1505 configure things like a ``reset init'' script, or other things
1506 specific to that board and that target.
1507 If the chip has 2 targets, the names are @code{_TARGETNAME0},
1508 @code{_TARGETNAME1}, ... etc.
1511 @subsection The reset-init Event Handler
1512 @cindex event, reset-init
1513 @cindex reset-init handler
1515 Board config files run in the OpenOCD configuration stage;
1516 they can't use TAPs or targets, since they haven't been
1518 This means you can't write memory or access chip registers;
1519 you can't even verify that a flash chip is present.
1520 That's done later in event handlers, of which the target @code{reset-init}
1521 handler is one of the most important.
1523 Except on microcontrollers, the basic job of @code{reset-init} event
1524 handlers is setting up flash and DRAM, as normally handled by boot loaders.
1525 Microcontrollers rarely use boot loaders; they run right out of their
1526 on-chip flash and SRAM memory. But they may want to use one of these
1527 handlers too, if just for developer convenience.
1530 Because this is so very board-specific, and chip-specific, no examples
1532 Instead, look at the board config files distributed with OpenOCD.
1533 If you have a boot loader, its source code will help; so will
1534 configuration files for other JTAG tools
1535 (@pxref{translatingconfigurationfiles,,Translating Configuration Files}).
1538 Some of this code could probably be shared between different boards.
1539 For example, setting up a DRAM controller often doesn't differ by
1540 much except the bus width (16 bits or 32?) and memory timings, so a
1541 reusable TCL procedure loaded by the @file{target.cfg} file might take
1542 those as parameters.
1543 Similarly with oscillator, PLL, and clock setup;
1544 and disabling the watchdog.
1545 Structure the code cleanly, and provide comments to help
1546 the next developer doing such work.
1547 (@emph{You might be that next person} trying to reuse init code!)
1549 The last thing normally done in a @code{reset-init} handler is probing
1550 whatever flash memory was configured. For most chips that needs to be
1551 done while the associated target is halted, either because JTAG memory
1552 access uses the CPU or to prevent conflicting CPU access.
1554 @subsection JTAG Clock Rate
1556 Before your @code{reset-init} handler has set up
1557 the PLLs and clocking, you may need to run with
1558 a low JTAG clock rate.
1559 @xref{jtagspeed,,JTAG Speed}.
1560 Then you'd increase that rate after your handler has
1561 made it possible to use the faster JTAG clock.
1562 When the initial low speed is board-specific, for example
1563 because it depends on a board-specific oscillator speed, then
1564 you should probably set it up in the board config file;
1565 if it's target-specific, it belongs in the target config file.
1567 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
1568 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
1569 is one sixth of the CPU clock; or one eighth for ARM11 cores.
1570 Consult chip documentation to determine the peak JTAG clock rate,
1571 which might be less than that.
1574 On most ARMs, JTAG clock detection is coupled to the core clock, so
1575 software using a @option{wait for interrupt} operation blocks JTAG access.
1576 Adaptive clocking provides a partial workaround, but a more complete
1577 solution just avoids using that instruction with JTAG debuggers.
1580 If both the chip and the board support adaptive clocking,
1581 use the @command{jtag_rclk}
1582 command, in case your board is used with JTAG adapter which
1583 also supports it. Otherwise use @command{adapter speed}.
1584 Set the slow rate at the beginning of the reset sequence,
1585 and the faster rate as soon as the clocks are at full speed.
1587 @anchor{theinitboardprocedure}
1588 @subsection The init_board procedure
1589 @cindex init_board procedure
1591 The concept of @code{init_board} procedure is very similar to @code{init_targets}
1592 (@xref{theinittargetsprocedure,,The init_targets procedure}.) - it's a replacement of ``linear''
1593 configuration scripts. This procedure is meant to be executed when OpenOCD enters run stage
1594 (@xref{enteringtherunstage,,Entering the Run Stage},) after @code{init_targets}. The idea to have
1595 separate @code{init_targets} and @code{init_board} procedures is to allow the first one to configure
1596 everything target specific (internal flash, internal RAM, etc.) and the second one to configure
1597 everything board specific (reset signals, chip frequency, reset-init event handler, external memory, etc.).
1598 Additionally ``linear'' board config file will most likely fail when target config file uses
1599 @code{init_targets} scheme (``linear'' script is executed before @code{init} and @code{init_targets} - after),
1600 so separating these two configuration stages is very convenient, as the easiest way to overcome this
1601 problem is to convert board config file to use @code{init_board} procedure. Board config scripts don't
1602 need to override @code{init_targets} defined in target config files when they only need to add some specifics.
1604 Just as @code{init_targets}, the @code{init_board} procedure can be overridden by ``next level'' script (which sources
1605 the original), allowing greater code reuse.
1608 ### board_file.cfg ###
1610 # source target file that does most of the config in init_targets
1611 source [find target/target.cfg]
1613 proc enable_fast_clock @{@} @{
1614 # enables fast on-board clock source
1615 # configures the chip to use it
1618 # initialize only board specifics - reset, clock, adapter frequency
1619 proc init_board @{@} @{
1620 reset_config trst_and_srst trst_pulls_srst
1622 $_TARGETNAME configure -event reset-start @{
1626 $_TARGETNAME configure -event reset-init @{
1633 @section Target Config Files
1634 @cindex config file, target
1635 @cindex target config file
1637 Board config files communicate with target config files using
1638 naming conventions as described above, and may source one or
1639 more target config files like this:
1642 source [find target/FOOBAR.cfg]
1645 The point of a target config file is to package everything
1646 about a given chip that board config files need to know.
1647 In summary the target files should contain
1651 @item Add TAPs to the scan chain
1652 @item Add CPU targets (includes GDB support)
1653 @item CPU/Chip/CPU-Core specific features
1657 As a rule of thumb, a target file sets up only one chip.
1658 For a microcontroller, that will often include a single TAP,
1659 which is a CPU needing a GDB target, and its on-chip flash.
1661 More complex chips may include multiple TAPs, and the target
1662 config file may need to define them all before OpenOCD
1663 can talk to the chip.
1664 For example, some phone chips have JTAG scan chains that include
1665 an ARM core for operating system use, a DSP,
1666 another ARM core embedded in an image processing engine,
1667 and other processing engines.
1669 @subsection Default Value Boiler Plate Code
1671 All target configuration files should start with code like this,
1672 letting board config files express environment-specific
1673 differences in how things should be set up.
1676 # Boards may override chip names, perhaps based on role,
1677 # but the default should match what the vendor uses
1678 if @{ [info exists CHIPNAME] @} @{
1679 set _CHIPNAME $CHIPNAME
1681 set _CHIPNAME sam7x256
1684 # ONLY use ENDIAN with targets that can change it.
1685 if @{ [info exists ENDIAN] @} @{
1691 # TAP identifiers may change as chips mature, for example with
1692 # new revision fields (the "3" here). Pick a good default; you
1693 # can pass several such identifiers to the "jtag newtap" command.
1694 if @{ [info exists CPUTAPID ] @} @{
1695 set _CPUTAPID $CPUTAPID
1697 set _CPUTAPID 0x3f0f0f0f
1700 @c but 0x3f0f0f0f is for an str73x part ...
1702 @emph{Remember:} Board config files may include multiple target
1703 config files, or the same target file multiple times
1704 (changing at least @code{CHIPNAME}).
1706 Likewise, the target configuration file should define
1707 @code{_TARGETNAME} (or @code{_TARGETNAME0} etc) and
1708 use it later on when defining debug targets:
1711 set _TARGETNAME $_CHIPNAME.cpu
1712 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1715 @subsection Adding TAPs to the Scan Chain
1716 After the ``defaults'' are set up,
1717 add the TAPs on each chip to the JTAG scan chain.
1718 @xref{TAP Declaration}, and the naming convention
1721 In the simplest case the chip has only one TAP,
1722 probably for a CPU or FPGA.
1723 The config file for the Atmel AT91SAM7X256
1724 looks (in part) like this:
1727 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
1730 A board with two such at91sam7 chips would be able
1731 to source such a config file twice, with different
1732 values for @code{CHIPNAME}, so
1733 it adds a different TAP each time.
1735 If there are nonzero @option{-expected-id} values,
1736 OpenOCD attempts to verify the actual tap id against those values.
1737 It will issue error messages if there is mismatch, which
1738 can help to pinpoint problems in OpenOCD configurations.
1741 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f
1742 (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
1743 ERROR: Tap: sam7x256.cpu - Expected id: 0x12345678, Got: 0x3f0f0f0f
1744 ERROR: expected: mfg: 0x33c, part: 0x2345, ver: 0x1
1745 ERROR: got: mfg: 0x787, part: 0xf0f0, ver: 0x3
1748 There are more complex examples too, with chips that have
1749 multiple TAPs. Ones worth looking at include:
1752 @item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
1753 plus a JRC to enable them
1754 @item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
1755 @item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
1756 is not currently used)
1759 @subsection Add CPU targets
1761 After adding a TAP for a CPU, you should set it up so that
1762 GDB and other commands can use it.
1763 @xref{CPU Configuration}.
1764 For the at91sam7 example above, the command can look like this;
1765 note that @code{$_ENDIAN} is not needed, since OpenOCD defaults
1766 to little endian, and this chip doesn't support changing that.
1769 set _TARGETNAME $_CHIPNAME.cpu
1770 target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
1773 Work areas are small RAM areas associated with CPU targets.
1774 They are used by OpenOCD to speed up downloads,
1775 and to download small snippets of code to program flash chips.
1776 If the chip includes a form of ``on-chip-ram'' - and many do - define
1777 a work area if you can.
1778 Again using the at91sam7 as an example, this can look like:
1781 $_TARGETNAME configure -work-area-phys 0x00200000 \
1782 -work-area-size 0x4000 -work-area-backup 0
1785 @anchor{definecputargetsworkinginsmp}
1786 @subsection Define CPU targets working in SMP
1788 After setting targets, you can define a list of targets working in SMP.
1791 set _TARGETNAME_1 $_CHIPNAME.cpu1
1792 set _TARGETNAME_2 $_CHIPNAME.cpu2
1793 target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
1794 -coreid 0 -dbgbase $_DAP_DBG1
1795 target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
1796 -coreid 1 -dbgbase $_DAP_DBG2
1797 #define 2 targets working in smp.
1798 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
1800 In the above example on cortex_a, 2 cpus are working in SMP.
1801 In SMP only one GDB instance is created and :
1803 @item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
1804 @item halt command triggers the halt of all targets in the list.
1805 @item resume command triggers the write context and the restart of all targets in the list.
1806 @item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
1807 @item dedicated GDB serial protocol packets are implemented for switching/retrieving the target
1808 displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
1811 The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
1812 command have been implemented.
1814 @item cortex_a smp on : enable SMP mode, behaviour is as described above.
1815 @item cortex_a smp off : disable SMP mode, the current target is the one
1816 displayed in the GDB session, only this target is now controlled by GDB
1817 session. This behaviour is useful during system boot up.
1818 @item cortex_a smp : display current SMP mode.
1819 @item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
1826 #0 : coreid 0 is displayed to GDB ,
1827 #-> -1 : next resume triggers a real resume
1828 > cortex_a smp_gdb 1
1830 #0 :coreid 0 is displayed to GDB ,
1831 #->1 : next resume displays coreid 1 to GDB
1835 #1 :coreid 1 is displayed to GDB ,
1836 #->1 : next resume displays coreid 1 to GDB
1837 > cortex_a smp_gdb -1
1839 #1 :coreid 1 is displayed to GDB,
1840 #->-1 : next resume triggers a real resume
1844 @subsection Chip Reset Setup
1846 As a rule, you should put the @command{reset_config} command
1847 into the board file. Most things you think you know about a
1848 chip can be tweaked by the board.
1850 Some chips have specific ways the TRST and SRST signals are
1851 managed. In the unusual case that these are @emph{chip specific}
1852 and can never be changed by board wiring, they could go here.
1853 For example, some chips can't support JTAG debugging without
1856 Provide a @code{reset-assert} event handler if you can.
1857 Such a handler uses JTAG operations to reset the target,
1858 letting this target config be used in systems which don't
1859 provide the optional SRST signal, or on systems where you
1860 don't want to reset all targets at once.
1861 Such a handler might write to chip registers to force a reset,
1862 use a JRC to do that (preferable -- the target may be wedged!),
1863 or force a watchdog timer to trigger.
1864 (For Cortex-M targets, this is not necessary. The target
1865 driver knows how to use trigger an NVIC reset when SRST is
1868 Some chips need special attention during reset handling if
1869 they're going to be used with JTAG.
1870 An example might be needing to send some commands right
1871 after the target's TAP has been reset, providing a
1872 @code{reset-deassert-post} event handler that writes a chip
1873 register to report that JTAG debugging is being done.
1874 Another would be reconfiguring the watchdog so that it stops
1875 counting while the core is halted in the debugger.
1877 JTAG clocking constraints often change during reset, and in
1878 some cases target config files (rather than board config files)
1879 are the right places to handle some of those issues.
1880 For example, immediately after reset most chips run using a
1881 slower clock than they will use later.
1882 That means that after reset (and potentially, as OpenOCD
1883 first starts up) they must use a slower JTAG clock rate
1884 than they will use later.
1885 @xref{jtagspeed,,JTAG Speed}.
1887 @quotation Important
1888 When you are debugging code that runs right after chip
1889 reset, getting these issues right is critical.
1890 In particular, if you see intermittent failures when
1891 OpenOCD verifies the scan chain after reset,
1892 look at how you are setting up JTAG clocking.
1895 @anchor{theinittargetsprocedure}
1896 @subsection The init_targets procedure
1897 @cindex init_targets procedure
1899 Target config files can either be ``linear'' (script executed line-by-line when parsed in
1900 configuration stage, @xref{configurationstage,,Configuration Stage},) or they can contain a special
1901 procedure called @code{init_targets}, which will be executed when entering run stage
1902 (after parsing all config files or after @code{init} command, @xref{enteringtherunstage,,Entering the Run Stage}.)
1903 Such procedure can be overridden by ``next level'' script (which sources the original).
1904 This concept facilitates code reuse when basic target config files provide generic configuration
1905 procedures and @code{init_targets} procedure, which can then be sourced and enhanced or changed in
1906 a ``more specific'' target config file. This is not possible with ``linear'' config scripts,
1907 because sourcing them executes every initialization commands they provide.
1910 ### generic_file.cfg ###
1912 proc setup_my_chip @{chip_name flash_size ram_size@} @{
1913 # basic initialization procedure ...
1916 proc init_targets @{@} @{
1917 # initializes generic chip with 4kB of flash and 1kB of RAM
1918 setup_my_chip MY_GENERIC_CHIP 4096 1024
1921 ### specific_file.cfg ###
1923 source [find target/generic_file.cfg]
1925 proc init_targets @{@} @{
1926 # initializes specific chip with 128kB of flash and 64kB of RAM
1927 setup_my_chip MY_CHIP_WITH_128K_FLASH_64KB_RAM 131072 65536
1931 The easiest way to convert ``linear'' config files to @code{init_targets} version is to
1932 enclose every line of ``code'' (i.e. not @code{source} commands, procedures, etc.) in this procedure.
1934 For an example of this scheme see LPC2000 target config files.
1936 The @code{init_boards} procedure is a similar concept concerning board config files
1937 (@xref{theinitboardprocedure,,The init_board procedure}.)
1939 @anchor{theinittargeteventsprocedure}
1940 @subsection The init_target_events procedure
1941 @cindex init_target_events procedure
1943 A special procedure called @code{init_target_events} is run just after
1944 @code{init_targets} (@xref{theinittargetsprocedure,,The init_targets
1945 procedure}.) and before @code{init_board}
1946 (@xref{theinitboardprocedure,,The init_board procedure}.) It is used
1947 to set up default target events for the targets that do not have those
1948 events already assigned.
1950 @subsection ARM Core Specific Hacks
1952 If the chip has a DCC, enable it. If the chip is an ARM9 with some
1953 special high speed download features - enable it.
1955 If present, the MMU, the MPU and the CACHE should be disabled.
1957 Some ARM cores are equipped with trace support, which permits
1958 examination of the instruction and data bus activity. Trace
1959 activity is controlled through an ``Embedded Trace Module'' (ETM)
1960 on one of the core's scan chains. The ETM emits voluminous data
1961 through a ``trace port''. (@xref{armhardwaretracing,,ARM Hardware Tracing}.)
1962 If you are using an external trace port,
1963 configure it in your board config file.
1964 If you are using an on-chip ``Embedded Trace Buffer'' (ETB),
1965 configure it in your target config file.
1968 etm config $_TARGETNAME 16 normal full etb
1969 etb config $_TARGETNAME $_CHIPNAME.etb
1972 @subsection Internal Flash Configuration
1974 This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
1976 @b{Never ever} in the ``target configuration file'' define any type of
1977 flash that is external to the chip. (For example a BOOT flash on
1978 Chip Select 0.) Such flash information goes in a board file - not
1979 the TARGET (chip) file.
1983 @item at91sam7x256 - has 256K flash YES enable it.
1984 @item str912 - has flash internal YES enable it.
1985 @item imx27 - uses boot flash on CS0 - it goes in the board file.
1986 @item pxa270 - again - CS0 flash - it goes in the board file.
1989 @anchor{translatingconfigurationfiles}
1990 @section Translating Configuration Files
1992 If you have a configuration file for another hardware debugger
1993 or toolset (Abatron, BDI2000, BDI3000, CCS,
1994 Lauterbach, SEGGER, Macraigor, etc.), translating
1995 it into OpenOCD syntax is often quite straightforward. The most tricky
1996 part of creating a configuration script is oftentimes the reset init
1997 sequence where e.g. PLLs, DRAM and the like is set up.
1999 One trick that you can use when translating is to write small
2000 Tcl procedures to translate the syntax into OpenOCD syntax. This
2001 can avoid manual translation errors and make it easier to
2002 convert other scripts later on.
2004 Example of transforming quirky arguments to a simple search and
2008 # Lauterbach syntax(?)
2010 # Data.Set c15:0x042f %long 0x40000015
2012 # OpenOCD syntax when using procedure below.
2014 # setc15 0x01 0x00050078
2016 proc setc15 @{regs value@} @{
2019 echo [format "set p15 0x%04x, 0x%08x" $regs $value]
2021 arm mcr 15 [expr @{($regs >> 12) & 0x7@}] \
2022 [expr @{($regs >> 0) & 0xf@}] [expr @{($regs >> 4) & 0xf@}] \
2023 [expr @{($regs >> 8) & 0x7@}] $value
2029 @node Server Configuration
2030 @chapter Server Configuration
2031 @cindex initialization
2032 The commands here are commonly found in the openocd.cfg file and are
2033 used to specify what TCP/IP ports are used, and how GDB should be
2036 @anchor{configurationstage}
2037 @section Configuration Stage
2038 @cindex configuration stage
2039 @cindex config command
2041 When the OpenOCD server process starts up, it enters a
2042 @emph{configuration stage} which is the only time that
2043 certain commands, @emph{configuration commands}, may be issued.
2044 Normally, configuration commands are only available
2045 inside startup scripts.
2047 In this manual, the definition of a configuration command is
2048 presented as a @emph{Config Command}, not as a @emph{Command}
2049 which may be issued interactively.
2050 The runtime @command{help} command also highlights configuration
2051 commands, and those which may be issued at any time.
2053 Those configuration commands include declaration of TAPs,
2055 the interface used for JTAG communication,
2056 and other basic setup.
2057 The server must leave the configuration stage before it
2058 may access or activate TAPs.
2059 After it leaves this stage, configuration commands may no
2062 @deffn {Command} {command mode} [command_name]
2063 Returns the command modes allowed by a command: 'any', 'config', or
2064 'exec'. If no command is specified, returns the current command
2065 mode. Returns 'unknown' if an unknown command is given. Command can be
2066 multiple tokens. (command valid any time)
2068 In this document, the modes are described as stages, 'config' and
2069 'exec' mode correspond configuration stage and run stage. 'any' means
2070 the command can be executed in either
2071 stages. @xref{configurationstage,,Configuration Stage}, and
2072 @xref{enteringtherunstage,,Entering the Run Stage}.
2075 @anchor{enteringtherunstage}
2076 @section Entering the Run Stage
2078 The first thing OpenOCD does after leaving the configuration
2079 stage is to verify that it can talk to the scan chain
2080 (list of TAPs) which has been configured.
2081 It will warn if it doesn't find TAPs it expects to find,
2082 or finds TAPs that aren't supposed to be there.
2083 You should see no errors at this point.
2084 If you see errors, resolve them by correcting the
2085 commands you used to configure the server.
2086 Common errors include using an initial JTAG speed that's too
2087 fast, and not providing the right IDCODE values for the TAPs
2090 Once OpenOCD has entered the run stage, a number of commands
2092 A number of these relate to the debug targets you may have declared.
2093 For example, the @command{mww} command will not be available until
2094 a target has been successfully instantiated.
2095 If you want to use those commands, you may need to force
2096 entry to the run stage.
2098 @deffn {Config Command} {init}
2099 This command terminates the configuration stage and
2100 enters the run stage. This helps when you need to have
2101 the startup scripts manage tasks such as resetting the target,
2102 programming flash, etc. To reset the CPU upon startup, add "init" and
2103 "reset" at the end of the config script or at the end of the OpenOCD
2104 command line using the @option{-c} command line switch.
2106 If this command does not appear in any startup/configuration file
2107 OpenOCD executes the command for you after processing all
2108 configuration files and/or command line options.
2110 @b{NOTE:} This command normally occurs near the end of your
2111 openocd.cfg file to force OpenOCD to ``initialize'' and make the
2112 targets ready. For example: If your openocd.cfg file needs to
2113 read/write memory on your target, @command{init} must occur before
2114 the memory read/write commands. This includes @command{nand probe}.
2116 @command{init} calls the following internal OpenOCD commands to initialize
2117 corresponding subsystems:
2118 @deffn {Config Command} {target init}
2119 @deffnx {Command} {transport init}
2120 @deffnx {Command} {dap init}
2121 @deffnx {Config Command} {flash init}
2122 @deffnx {Config Command} {nand init}
2123 @deffnx {Config Command} {pld init}
2124 @deffnx {Command} {tpiu init}
2127 At last, @command{init} executes all the commands that are specified in
2128 the TCL list @var{post_init_commands}. The commands are executed in the
2129 same order they occupy in the list. If one of the commands fails, then
2130 the error is propagated and OpenOCD fails too.
2132 lappend post_init_commands @{echo "OpenOCD successfully initialized."@}
2133 lappend post_init_commands @{echo "Have fun with OpenOCD !"@}
2137 @deffn {Config Command} {noinit}
2138 Prevent OpenOCD from implicit @command{init} call at the end of startup.
2139 Allows issuing configuration commands over telnet or Tcl connection.
2140 When you are done with configuration use @command{init} to enter
2144 @deffn {Overridable Procedure} {jtag_init}
2145 This is invoked at server startup to verify that it can talk
2146 to the scan chain (list of TAPs) which has been configured.
2148 The default implementation first tries @command{jtag arp_init},
2149 which uses only a lightweight JTAG reset before examining the
2151 If that fails, it tries again, using a harder reset
2152 from the overridable procedure @command{init_reset}.
2154 Implementations must have verified the JTAG scan chain before
2156 This is done by calling @command{jtag arp_init}
2157 (or @command{jtag arp_init-reset}).
2161 @section TCP/IP Ports
2166 The OpenOCD server accepts remote commands in several syntaxes.
2167 Each syntax uses a different TCP/IP port, which you may specify
2168 only during configuration (before those ports are opened).
2170 For reasons including security, you may wish to prevent remote
2171 access using one or more of these ports.
2172 In such cases, just specify the relevant port number as "disabled".
2173 If you disable all access through TCP/IP, you will need to
2174 use the command line @option{-pipe} option.
2177 @deffn {Config Command} {gdb_port} [number]
2179 Normally gdb listens to a TCP/IP port, but GDB can also
2180 communicate via pipes(stdin/out or named pipes). The name
2181 "gdb_port" stuck because it covers probably more than 90% of
2182 the normal use cases.
2184 No arguments reports GDB port. "pipe" means listen to stdin
2185 output to stdout, an integer is base port number, "disabled"
2186 disables the gdb server.
2188 When using "pipe", also use log_output to redirect the log
2189 output to a file so as not to flood the stdin/out pipes.
2191 Any other string is interpreted as named pipe to listen to.
2192 Output pipe is the same name as input pipe, but with 'o' appended,
2193 e.g. /var/gdb, /var/gdbo.
2195 The GDB port for the first target will be the base port, the
2196 second target will listen on gdb_port + 1, and so on.
2197 When not specified during the configuration stage,
2198 the port @var{number} defaults to 3333.
2199 When @var{number} is not a numeric value, incrementing it to compute
2200 the next port number does not work. In this case, specify the proper
2201 @var{number} for each target by using the option @code{-gdb-port} of the
2202 commands @command{target create} or @command{$target_name configure}.
2203 @xref{gdbportoverride,,option -gdb-port}.
2205 Note: when using "gdb_port pipe", increasing the default remote timeout in
2206 gdb (with 'set remotetimeout') is recommended. An insufficient timeout may
2207 cause initialization to fail with "Unknown remote qXfer reply: OK".
2210 @deffn {Config Command} {tcl_port} [number]
2211 Specify or query the port used for a simplified RPC
2212 connection that can be used by clients to issue TCL commands and get the
2213 output from the Tcl engine.
2214 Intended as a machine interface.
2215 When not specified during the configuration stage,
2216 the port @var{number} defaults to 6666.
2217 When specified as "disabled", this service is not activated.
2220 @deffn {Config Command} {telnet_port} [number]
2221 Specify or query the
2222 port on which to listen for incoming telnet connections.
2223 This port is intended for interaction with one human through TCL commands.
2224 When not specified during the configuration stage,
2225 the port @var{number} defaults to 4444.
2226 When specified as "disabled", this service is not activated.
2229 @anchor{gdbconfiguration}
2230 @section GDB Configuration
2232 @cindex GDB configuration
2233 You can reconfigure some GDB behaviors if needed.
2234 The ones listed here are static and global.
2235 @xref{targetconfiguration,,Target Configuration}, about configuring individual targets.
2236 @xref{targetevents,,Target Events}, about configuring target-specific event handling.
2238 @anchor{gdbbreakpointoverride}
2239 @deffn {Command} {gdb_breakpoint_override} [@option{hard}|@option{soft}|@option{disable}]
2240 Force breakpoint type for gdb @command{break} commands.
2241 This option supports GDB GUIs which don't
2242 distinguish hard versus soft breakpoints, if the default OpenOCD and
2243 GDB behaviour is not sufficient. GDB normally uses hardware
2244 breakpoints if the memory map has been set up for flash regions.
2247 @anchor{gdbflashprogram}
2248 @deffn {Config Command} {gdb_flash_program} (@option{enable}|@option{disable})
2249 Set to @option{enable} to cause OpenOCD to program the flash memory when a
2250 vFlash packet is received.
2251 The default behaviour is @option{enable}.
2254 @deffn {Config Command} {gdb_memory_map} (@option{enable}|@option{disable})
2255 Set to @option{enable} to cause OpenOCD to send the memory configuration to GDB when
2256 requested. GDB will then know when to set hardware breakpoints, and program flash
2257 using the GDB load command. @command{gdb_flash_program enable} must also be enabled
2258 for flash programming to work.
2259 Default behaviour is @option{enable}.
2260 @xref{gdbflashprogram,,gdb_flash_program}.
2263 @deffn {Config Command} {gdb_report_data_abort} (@option{enable}|@option{disable})
2264 Specifies whether data aborts cause an error to be reported
2265 by GDB memory read packets.
2266 The default behaviour is @option{disable};
2267 use @option{enable} see these errors reported.
2270 @deffn {Config Command} {gdb_report_register_access_error} (@option{enable}|@option{disable})
2271 Specifies whether register accesses requested by GDB register read/write
2272 packets report errors or not.
2273 The default behaviour is @option{disable};
2274 use @option{enable} see these errors reported.
2277 @deffn {Config Command} {gdb_target_description} (@option{enable}|@option{disable})
2278 Set to @option{enable} to cause OpenOCD to send the target descriptions to gdb via qXfer:features:read packet.
2279 The default behaviour is @option{enable}.
2282 @deffn {Command} {gdb_save_tdesc}
2283 Saves the target description file to the local file system.
2285 The file name is @i{target_name}.xml.
2288 @anchor{eventpolling}
2289 @section Event Polling
2291 Hardware debuggers are parts of asynchronous systems,
2292 where significant events can happen at any time.
2293 The OpenOCD server needs to detect some of these events,
2294 so it can report them to through TCL command line
2297 Examples of such events include:
2300 @item One of the targets can stop running ... maybe it triggers
2301 a code breakpoint or data watchpoint, or halts itself.
2302 @item Messages may be sent over ``debug message'' channels ... many
2303 targets support such messages sent over JTAG,
2304 for receipt by the person debugging or tools.
2305 @item Loss of power ... some adapters can detect these events.
2306 @item Resets not issued through JTAG ... such reset sources
2307 can include button presses or other system hardware, sometimes
2308 including the target itself (perhaps through a watchdog).
2309 @item Debug instrumentation sometimes supports event triggering
2310 such as ``trace buffer full'' (so it can quickly be emptied)
2311 or other signals (to correlate with code behavior).
2314 None of those events are signaled through standard JTAG signals.
2315 However, most conventions for JTAG connectors include voltage
2316 level and system reset (SRST) signal detection.
2317 Some connectors also include instrumentation signals, which
2318 can imply events when those signals are inputs.
2320 In general, OpenOCD needs to periodically check for those events,
2321 either by looking at the status of signals on the JTAG connector
2322 or by sending synchronous ``tell me your status'' JTAG requests
2323 to the various active targets.
2324 There is a command to manage and monitor that polling,
2325 which is normally done in the background.
2327 @deffn {Command} {poll} [@option{on}|@option{off}]
2328 Poll the current target for its current state.
2329 (Also, @pxref{targetcurstate,,target curstate}.)
2330 If that target is in debug mode, architecture
2331 specific information about the current state is printed.
2332 An optional parameter
2333 allows background polling to be enabled and disabled.
2335 You could use this from the TCL command shell, or
2336 from GDB using @command{monitor poll} command.
2337 Leave background polling enabled while you're using GDB.
2340 background polling: on
2341 target state: halted
2342 target halted in ARM state due to debug-request, \
2343 current mode: Supervisor
2344 cpsr: 0x800000d3 pc: 0x11081bfc
2345 MMU: disabled, D-Cache: disabled, I-Cache: enabled
2350 @node Debug Adapter Configuration
2351 @chapter Debug Adapter Configuration
2352 @cindex config file, interface
2353 @cindex interface config file
2355 Correctly installing OpenOCD includes making your operating system give
2356 OpenOCD access to debug adapters. Once that has been done, Tcl commands
2357 are used to select which one is used, and to configure how it is used.
2360 Because OpenOCD started out with a focus purely on JTAG, you may find
2361 places where it wrongly presumes JTAG is the only transport protocol
2362 in use. Be aware that recent versions of OpenOCD are removing that
2363 limitation. JTAG remains more functional than most other transports.
2364 Other transports do not support boundary scan operations, or may be
2365 specific to a given chip vendor. Some might be usable only for
2366 programming flash memory, instead of also for debugging.
2369 Debug Adapters/Interfaces/Dongles are normally configured
2370 through commands in an interface configuration
2371 file which is sourced by your @file{openocd.cfg} file, or
2372 through a command line @option{-f interface/....cfg} option.
2375 source [find interface/olimex-jtag-tiny.cfg]
2379 OpenOCD what type of JTAG adapter you have, and how to talk to it.
2380 A few cases are so simple that you only need to say what driver to use:
2384 adapter driver jlink
2387 Most adapters need a bit more configuration than that.
2390 @section Adapter Configuration
2392 The @command{adapter driver} command tells OpenOCD what type of debug adapter you are
2393 using. Depending on the type of adapter, you may need to use one or
2394 more additional commands to further identify or configure the adapter.
2396 @deffn {Config Command} {adapter driver} name
2397 Use the adapter driver @var{name} to connect to the
2401 @deffn {Command} {adapter list}
2402 List the debug adapter drivers that have been built into
2403 the running copy of OpenOCD.
2405 @deffn {Config Command} {adapter transports} transport_name+
2406 Specifies the transports supported by this debug adapter.
2407 The adapter driver builds-in similar knowledge; use this only
2408 when external configuration (such as jumpering) changes what
2409 the hardware can support.
2414 @deffn {Command} {adapter name}
2415 Returns the name of the debug adapter driver being used.
2418 @anchor{adapter_usb_location}
2419 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
2420 Displays or specifies the physical USB port of the adapter to use. The path
2421 roots at @var{bus} and walks down the physical ports, with each
2422 @var{port} option specifying a deeper level in the bus topology, the last
2423 @var{port} denoting where the target adapter is actually plugged.
2424 The USB bus topology can be queried with the command @emph{lsusb -t} or @emph{dmesg}.
2426 This command is only available if your libusb1 is at least version 1.0.16.
2429 @deffn {Config Command} {adapter serial} serial_string
2430 Specifies the @var{serial_string} of the adapter to use.
2431 If this command is not specified, serial strings are not checked.
2432 Only the following adapter drivers use the serial string from this command:
2433 aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
2434 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
2437 @section Interface Drivers
2439 Each of the interface drivers listed here must be explicitly
2440 enabled when OpenOCD is configured, in order to be made
2441 available at run time.
2443 @deffn {Interface Driver} {amt_jtagaccel}
2444 Amontec Chameleon in its JTAG Accelerator configuration,
2445 connected to a PC's EPP mode parallel port.
2446 This defines some driver-specific commands:
2448 @deffn {Config Command} {parport port} number
2449 Specifies either the address of the I/O port (default: 0x378 for LPT1) or
2450 the number of the @file{/dev/parport} device.
2453 @deffn {Config Command} {rtck} [@option{enable}|@option{disable}]
2454 Displays status of RTCK option.
2455 Optionally sets that option first.
2459 @deffn {Interface Driver} {arm-jtag-ew}
2460 Olimex ARM-JTAG-EW USB adapter
2461 This has one driver-specific command:
2463 @deffn {Command} {armjtagew_info}
2468 @deffn {Interface Driver} {at91rm9200}
2469 Supports bitbanged JTAG from the local system,
2470 presuming that system is an Atmel AT91rm9200
2471 and a specific set of GPIOs is used.
2472 @c command: at91rm9200_device NAME
2473 @c chooses among list of bit configs ... only one option
2476 @deffn {Interface Driver} {cmsis-dap}
2477 ARM CMSIS-DAP compliant based adapter v1 (USB HID based)
2480 @deffn {Config Command} {cmsis_dap_vid_pid} [vid pid]+
2481 The vendor ID and product ID of the CMSIS-DAP device. If not specified
2482 the driver will attempt to auto detect the CMSIS-DAP device.
2483 Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g.
2485 cmsis_dap_vid_pid 0xc251 0xf001 0x0d28 0x0204
2489 @deffn {Config Command} {cmsis_dap_backend} [@option{auto}|@option{usb_bulk}|@option{hid}]
2490 Specifies how to communicate with the adapter:
2493 @item @option{hid} Use HID generic reports - CMSIS-DAP v1
2494 @item @option{usb_bulk} Use USB bulk - CMSIS-DAP v2
2495 @item @option{auto} First try USB bulk CMSIS-DAP v2, if not found try HID CMSIS-DAP v1.
2496 This is the default if @command{cmsis_dap_backend} is not specified.
2500 @deffn {Config Command} {cmsis_dap_usb interface} [number]
2501 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
2502 In most cases need not to be specified and interfaces are searched by
2503 interface string or for user class interface.
2506 @deffn {Command} {cmsis-dap info}
2507 Display various device information, like hardware version, firmware version, current bus status.
2510 @deffn {Command} {cmsis-dap cmd} number number ...
2511 Execute an arbitrary CMSIS-DAP command. Use for adapter testing or for handling
2512 of an adapter vendor specific command from a Tcl script.
2514 Take given numbers as bytes, assemble a CMSIS-DAP protocol command packet
2515 from them and send it to the adapter. The first 4 bytes of the adapter response
2517 See @url{https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__Commands__gr.html}
2521 @deffn {Interface Driver} {dummy}
2522 A dummy software-only driver for debugging.
2525 @deffn {Interface Driver} {ep93xx}
2526 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
2529 @deffn {Interface Driver} {ftdi}
2530 This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial
2531 Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H.
2533 The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device,
2534 bypassing intermediate libraries like libftdi.
2536 Support for new FTDI based adapters can be added completely through
2537 configuration files, without the need to patch and rebuild OpenOCD.
2539 The driver uses a signal abstraction to enable Tcl configuration files to
2540 define outputs for one or several FTDI GPIO. These outputs can then be
2541 controlled using the @command{ftdi set_signal} command. Special signal names
2542 are reserved for nTRST, nSRST and LED (for blink) so that they, if defined,
2543 will be used for their customary purpose. Inputs can be read using the
2544 @command{ftdi get_signal} command.
2546 To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the
2547 SWD protocol is selected. When set, the adapter should route the SWDIO pin to
2548 the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as
2549 required by the protocol, to tell the adapter to drive the data output onto
2550 the SWDIO pin or keep the SWDIO pin Hi-Z, respectively.
2552 Depending on the type of buffer attached to the FTDI GPIO, the outputs have to
2553 be controlled differently. In order to support tristateable signals such as
2554 nSRST, both a data GPIO and an output-enable GPIO can be specified for each
2555 signal. The following output buffer configurations are supported:
2558 @item Push-pull with one FTDI output as (non-)inverted data line
2559 @item Open drain with one FTDI output as (non-)inverted output-enable
2560 @item Tristate with one FTDI output as (non-)inverted data line and another
2561 FTDI output as (non-)inverted output-enable
2562 @item Unbuffered, using the FTDI GPIO as a tristate output directly by
2563 switching data and direction as necessary
2566 These interfaces have several commands, used to configure the driver
2567 before initializing the JTAG scan chain:
2569 @deffn {Config Command} {ftdi vid_pid} [vid pid]+
2570 The vendor ID and product ID of the adapter. Up to eight
2571 [@var{vid}, @var{pid}] pairs may be given, e.g.
2573 ftdi vid_pid 0x0403 0xcff8 0x15ba 0x0003
2577 @deffn {Config Command} {ftdi device_desc} description
2578 Provides the USB device description (the @emph{iProduct string})
2579 of the adapter. If not specified, the device description is ignored
2580 during device selection.
2583 @deffn {Config Command} {ftdi channel} channel
2584 Selects the channel of the FTDI device to use for MPSSE operations. Most
2585 adapters use the default, channel 0, but there are exceptions.
2588 @deffn {Config Command} {ftdi layout_init} data direction
2589 Specifies the initial values of the FTDI GPIO data and direction registers.
2590 Each value is a 16-bit number corresponding to the concatenation of the high
2591 and low FTDI GPIO registers. The values should be selected based on the
2592 schematics of the adapter, such that all signals are set to safe levels with
2593 minimal impact on the target system. Avoid floating inputs, conflicting outputs
2594 and initially asserted reset signals.
2597 @deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
2598 Creates a signal with the specified @var{name}, controlled by one or more FTDI
2599 GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
2600 register bitmasks to tell the driver the connection and type of the output
2601 buffer driving the respective signal. @var{data_mask} is the bitmask for the
2602 pin(s) connected to the data input of the output buffer. @option{-ndata} is
2603 used with inverting data inputs and @option{-data} with non-inverting inputs.
2604 The @option{-oe} (or @option{-noe}) option tells where the output-enable (or
2605 not-output-enable) input to the output buffer is connected. The options
2606 @option{-input} and @option{-ninput} specify the bitmask for pins to be read
2607 with the method @command{ftdi get_signal}.
2609 Both @var{data_mask} and @var{oe_mask} need not be specified. For example, a
2610 simple open-collector transistor driver would be specified with @option{-oe}
2611 only. In that case the signal can only be set to drive low or to Hi-Z and the
2612 driver will complain if the signal is set to drive high. Which means that if
2613 it's a reset signal, @command{reset_config} must be specified as
2614 @option{srst_open_drain}, not @option{srst_push_pull}.
2616 A special case is provided when @option{-data} and @option{-oe} is set to the
2617 same bitmask. Then the FTDI pin is considered being connected straight to the
2618 target without any buffer. The FTDI pin is then switched between output and
2619 input as necessary to provide the full set of low, high and Hi-Z
2620 characteristics. In all other cases, the pins specified in a signal definition
2621 are always driven by the FTDI.
2623 If @option{-alias} or @option{-nalias} is used, the signal is created
2624 identical (or with data inverted) to an already specified signal
2628 @deffn {Command} {ftdi set_signal} name @option{0}|@option{1}|@option{z}
2629 Set a previously defined signal to the specified level.
2631 @item @option{0}, drive low
2632 @item @option{1}, drive high
2633 @item @option{z}, set to high-impedance
2637 @deffn {Command} {ftdi get_signal} name
2638 Get the value of a previously defined signal.
2641 @deffn {Command} {ftdi tdo_sample_edge} @option{rising}|@option{falling}
2642 Configure TCK edge at which the adapter samples the value of the TDO signal
2644 Due to signal propagation delays, sampling TDO on rising TCK can become quite
2645 peculiar at high JTAG clock speeds. However, FTDI chips offer a possibility to sample
2646 TDO on falling edge of TCK. With some board/adapter configurations, this may increase
2647 stability at higher JTAG clocks.
2649 @item @option{rising}, sample TDO on rising edge of TCK - this is the default
2650 @item @option{falling}, sample TDO on falling edge of TCK
2654 For example adapter definitions, see the configuration files shipped in the
2655 @file{interface/ftdi} directory.
2659 @deffn {Interface Driver} {ft232r}
2660 This driver is implementing synchronous bitbang mode of an FTDI FT232R,
2661 FT230X, FT231X and similar USB UART bridge ICs by reusing RS232 signals as GPIO.
2662 It currently doesn't support using CBUS pins as GPIO.
2664 List of connections (default physical pin numbers for FT232R in 28-pin SSOP package):
2671 @item DCD(10) - SRST
2674 User can change default pinout by supplying configuration
2675 commands with GPIO numbers or RS232 signal names.
2676 GPIO numbers correspond to bit numbers in FTDI GPIO register.
2677 They differ from physical pin numbers.
2678 For details see actual FTDI chip datasheets.
2679 Every JTAG line must be configured to unique GPIO number
2680 different than any other JTAG line, even those lines
2681 that are sometimes not used like TRST or SRST.
2695 These interfaces have several commands, used to configure the driver
2696 before initializing the JTAG scan chain:
2698 @deffn {Config Command} {ft232r vid_pid} @var{vid} @var{pid}
2699 The vendor ID and product ID of the adapter. If not specified, default
2700 0x0403:0x6001 is used.
2703 @deffn {Config Command} {ft232r jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
2704 Set four JTAG GPIO numbers at once.
2705 If not specified, default 0 3 1 2 or TXD CTS RXD RTS is used.
2708 @deffn {Config Command} {ft232r tck_num} @var{tck}
2709 Set TCK GPIO number. If not specified, default 0 or TXD is used.
2712 @deffn {Config Command} {ft232r tms_num} @var{tms}
2713 Set TMS GPIO number. If not specified, default 3 or CTS is used.
2716 @deffn {Config Command} {ft232r tdi_num} @var{tdi}
2717 Set TDI GPIO number. If not specified, default 1 or RXD is used.
2720 @deffn {Config Command} {ft232r tdo_num} @var{tdo}
2721 Set TDO GPIO number. If not specified, default 2 or RTS is used.
2724 @deffn {Config Command} {ft232r trst_num} @var{trst}
2725 Set TRST GPIO number. If not specified, default 4 or DTR is used.
2728 @deffn {Config Command} {ft232r srst_num} @var{srst}
2729 Set SRST GPIO number. If not specified, default 6 or DCD is used.
2732 @deffn {Config Command} {ft232r restore_serial} @var{word}
2733 Restore serial port after JTAG. This USB bitmode control word
2734 (16-bit) will be sent before quit. Lower byte should
2735 set GPIO direction register to a "sane" state:
2736 0x15 for TXD RTS DTR as outputs (1), others as inputs (0). Higher
2737 byte is usually 0 to disable bitbang mode.
2738 When kernel driver reattaches, serial port should continue to work.
2739 Value 0xFFFF disables sending control word and serial port,
2740 then kernel driver will not reattach.
2741 If not specified, default 0xFFFF is used.
2746 @deffn {Interface Driver} {remote_bitbang}
2747 Drive JTAG from a remote process. This sets up a UNIX or TCP socket connection
2748 with a remote process and sends ASCII encoded bitbang requests to that process
2749 instead of directly driving JTAG.
2751 The remote_bitbang driver is useful for debugging software running on
2752 processors which are being simulated.
2754 @deffn {Config Command} {remote_bitbang port} number
2755 Specifies the TCP port of the remote process to connect to or 0 to use UNIX
2756 sockets instead of TCP.
2759 @deffn {Config Command} {remote_bitbang host} hostname
2760 Specifies the hostname of the remote process to connect to using TCP, or the
2761 name of the UNIX socket to use if remote_bitbang port is 0.
2764 For example, to connect remotely via TCP to the host foobar you might have
2768 adapter driver remote_bitbang
2769 remote_bitbang port 3335
2770 remote_bitbang host foobar
2773 To connect to another process running locally via UNIX sockets with socket
2777 adapter driver remote_bitbang
2778 remote_bitbang port 0
2779 remote_bitbang host mysocket
2783 @deffn {Interface Driver} {usb_blaster}
2784 USB JTAG/USB-Blaster compatibles over one of the userspace libraries
2785 for FTDI chips. These interfaces have several commands, used to
2786 configure the driver before initializing the JTAG scan chain:
2788 @deffn {Config Command} {usb_blaster vid_pid} vid pid
2789 The vendor ID and product ID of the FTDI FT245 device. If not specified,
2790 default values are used.
2791 Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
2792 Altera USB-Blaster (default):
2794 usb_blaster vid_pid 0x09FB 0x6001
2796 The following VID/PID is for Kolja Waschk's USB JTAG:
2798 usb_blaster vid_pid 0x16C0 0x06AD
2802 @deffn {Command} {usb_blaster pin} (@option{pin6}|@option{pin8}) (@option{0}|@option{1}|@option{s}|@option{t})
2803 Sets the state or function of the unused GPIO pins on USB-Blasters
2804 (pins 6 and 8 on the female JTAG header). These pins can be used as
2805 SRST and/or TRST provided the appropriate connections are made on the
2808 For example, to use pin 6 as SRST:
2810 usb_blaster pin pin6 s
2811 reset_config srst_only
2815 @deffn {Config Command} {usb_blaster lowlevel_driver} (@option{ftdi}|@option{ublast2})
2816 Chooses the low level access method for the adapter. If not specified,
2817 @option{ftdi} is selected unless it wasn't enabled during the
2818 configure stage. USB-Blaster II needs @option{ublast2}.
2821 @deffn {Config Command} {usb_blaster firmware} @var{path}
2822 This command specifies @var{path} to access USB-Blaster II firmware
2823 image. To be used with USB-Blaster II only.
2828 @deffn {Interface Driver} {gw16012}
2829 Gateworks GW16012 JTAG programmer.
2830 This has one driver-specific command:
2832 @deffn {Config Command} {parport port} [port_number]
2833 Display either the address of the I/O port
2834 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
2835 If a parameter is provided, first switch to use that port.
2836 This is a write-once setting.
2840 @deffn {Interface Driver} {jlink}
2841 SEGGER J-Link family of USB adapters. It currently supports JTAG and SWD
2844 @quotation Compatibility Note
2845 SEGGER released many firmware versions for the many hardware versions they
2846 produced. OpenOCD was extensively tested and intended to run on all of them,
2847 but some combinations were reported as incompatible. As a general
2848 recommendation, it is advisable to use the latest firmware version
2849 available for each hardware version. However the current V8 is a moving
2850 target, and SEGGER firmware versions released after the OpenOCD was
2851 released may not be compatible. In such cases it is recommended to
2852 revert to the last known functional version. For 0.5.0, this is from
2853 "Feb 8 2012 14:30:39", packed with 4.42c. For 0.6.0, the last known
2854 version is from "May 3 2012 18:36:22", packed with 4.46f.
2857 @deffn {Command} {jlink hwstatus}
2858 Display various hardware related information, for example target voltage and pin
2861 @deffn {Command} {jlink freemem}
2862 Display free device internal memory.
2864 @deffn {Command} {jlink jtag} [@option{2}|@option{3}]
2865 Set the JTAG command version to be used. Without argument, show the actual JTAG
2868 @deffn {Command} {jlink config}
2869 Display the device configuration.
2871 @deffn {Command} {jlink config targetpower} [@option{on}|@option{off}]
2872 Set the target power state on JTAG-pin 19. Without argument, show the target
2875 @deffn {Command} {jlink config mac} [@option{ff:ff:ff:ff:ff:ff}]
2876 Set the MAC address of the device. Without argument, show the MAC address.
2878 @deffn {Command} {jlink config ip} [@option{A.B.C.D}(@option{/E}|@option{F.G.H.I})]
2879 Set the IP configuration of the device, where A.B.C.D is the IP address, E the
2880 bit of the subnet mask and F.G.H.I the subnet mask. Without arguments, show the
2883 @deffn {Command} {jlink config usb} [@option{0} to @option{3}]
2884 Set the USB address of the device. This will also change the USB Product ID
2885 (PID) of the device. Without argument, show the USB address.
2887 @deffn {Command} {jlink config reset}
2888 Reset the current configuration.
2890 @deffn {Command} {jlink config write}
2891 Write the current configuration to the internal persistent storage.
2893 @deffn {Command} {jlink emucom write} <channel> <data>
2894 Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal
2897 The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to
2898 the EMUCOM channel 0x10:
2900 > jlink emucom write 0x10 aa0b23
2903 @deffn {Command} {jlink emucom read} <channel> <length>
2904 Read data from an EMUCOM channel. The read data is encoded as hexadecimal
2907 The following example shows how to read 4 bytes from the EMUCOM channel 0x0:
2909 > jlink emucom read 0x0 4
2913 @deffn {Config Command} {jlink usb} <@option{0} to @option{3}>
2914 Set the USB address of the interface, in case more than one adapter is connected
2915 to the host. If not specified, USB addresses are not considered. Device
2916 selection via USB address is not always unambiguous. It is recommended to use
2917 the serial number instead, if possible.
2919 As a configuration command, it can be used only before 'init'.
2923 @deffn {Interface Driver} {kitprog}
2924 This driver is for Cypress Semiconductor's KitProg adapters. The KitProg is an
2925 SWD-only adapter that is designed to be used with Cypress's PSoC and PRoC device
2926 families, but it is possible to use it with some other devices. If you are using
2927 this adapter with a PSoC or a PRoC, you may need to add
2928 @command{kitprog_init_acquire_psoc} or @command{kitprog acquire_psoc} to your
2929 configuration script.
2931 Note that this driver is for the proprietary KitProg protocol, not the CMSIS-DAP
2932 mode introduced in firmware 2.14. If the KitProg is in CMSIS-DAP mode, it cannot
2933 be used with this driver, and must either be used with the cmsis-dap driver or
2934 switched back to KitProg mode. See the Cypress KitProg User Guide for
2935 instructions on how to switch KitProg modes.
2939 @item The frequency of SWCLK cannot be configured, and varies between 1.6 MHz
2941 @item For firmware versions below 2.14, "JTAG to SWD" sequences are replaced by
2942 "SWD line reset" in the driver. This is for two reasons. First, the KitProg does
2943 not support sending arbitrary SWD sequences, and only firmware 2.14 and later
2944 implement both "JTAG to SWD" and "SWD line reset" in firmware. Earlier firmware
2945 versions only implement "SWD line reset". Second, due to a firmware quirk, an
2946 SWD sequence must be sent after every target reset in order to re-establish
2947 communications with the target.
2948 @item Due in part to the limitation above, KitProg devices with firmware below
2949 version 2.14 will need to use @command{kitprog_init_acquire_psoc} in order to
2950 communicate with PSoC 5LP devices. This is because, assuming debug is not
2951 disabled on the PSoC, the PSoC 5LP needs its JTAG interface switched to SWD
2952 mode before communication can begin, but prior to firmware 2.14, "JTAG to SWD"
2953 could only be sent with an acquisition sequence.
2956 @deffn {Config Command} {kitprog_init_acquire_psoc}
2957 Indicate that a PSoC acquisition sequence needs to be run during adapter init.
2958 Please be aware that the acquisition sequence hard-resets the target.
2961 @deffn {Command} {kitprog acquire_psoc}
2962 Run a PSoC acquisition sequence immediately. Typically, this should not be used
2963 outside of the target-specific configuration scripts since it hard-resets the
2964 target as a side-effect.
2965 This is necessary for "reset halt" on some PSoC 4 series devices.
2968 @deffn {Command} {kitprog info}
2969 Display various adapter information, such as the hardware version, firmware
2970 version, and target voltage.
2974 @deffn {Interface Driver} {parport}
2975 Supports PC parallel port bit-banging cables:
2976 Wigglers, PLD download cable, and more.
2977 These interfaces have several commands, used to configure the driver
2978 before initializing the JTAG scan chain:
2980 @deffn {Config Command} {parport cable} name
2981 Set the layout of the parallel port cable used to connect to the target.
2982 This is a write-once setting.
2983 Currently valid cable @var{name} values include:
2986 @item @b{altium} Altium Universal JTAG cable.
2987 @item @b{arm-jtag} Same as original wiggler except SRST and
2988 TRST connections reversed and TRST is also inverted.
2989 @item @b{chameleon} The Amontec Chameleon's CPLD when operated
2990 in configuration mode. This is only used to
2991 program the Chameleon itself, not a connected target.
2992 @item @b{dlc5} The Xilinx Parallel cable III.
2993 @item @b{flashlink} The ST Parallel cable.
2994 @item @b{lattice} Lattice ispDOWNLOAD Cable
2995 @item @b{old_amt_wiggler} The Wiggler configuration that comes with
2997 Amontec's Chameleon Programmer. The new version available from
2998 the website uses the original Wiggler layout ('@var{wiggler}')
2999 @item @b{triton} The parallel port adapter found on the
3000 ``Karo Triton 1 Development Board''.
3001 This is also the layout used by the HollyGates design
3002 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
3003 @item @b{wiggler} The original Wiggler layout, also supported by
3004 several clones, such as the Olimex ARM-JTAG
3005 @item @b{wiggler2} Same as original wiggler except an led is fitted on D5.
3006 @item @b{wiggler_ntrst_inverted} Same as original wiggler except TRST is inverted.
3010 @deffn {Config Command} {parport port} [port_number]
3011 Display either the address of the I/O port
3012 (default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
3013 If a parameter is provided, first switch to use that port.
3014 This is a write-once setting.
3016 When using PPDEV to access the parallel port, use the number of the parallel port:
3017 @option{parport port 0} (the default). If @option{parport port 0x378} is specified
3018 you may encounter a problem.
3021 @deffn {Config Command} {parport toggling_time} [nanoseconds]
3022 Displays how many nanoseconds the hardware needs to toggle TCK;
3023 the parport driver uses this value to obey the
3024 @command{adapter speed} configuration.
3025 When the optional @var{nanoseconds} parameter is given,
3026 that setting is changed before displaying the current value.
3028 The default setting should work reasonably well on commodity PC hardware.
3029 However, you may want to calibrate for your specific hardware.
3031 To measure the toggling time with a logic analyzer or a digital storage
3032 oscilloscope, follow the procedure below:
3034 > parport toggling_time 1000
3037 This sets the maximum JTAG clock speed of the hardware, but
3038 the actual speed probably deviates from the requested 500 kHz.
3039 Now, measure the time between the two closest spaced TCK transitions.
3040 You can use @command{runtest 1000} or something similar to generate a
3041 large set of samples.
3042 Update the setting to match your measurement:
3044 > parport toggling_time <measured nanoseconds>
3046 Now the clock speed will be a better match for @command{adapter speed}
3047 command given in OpenOCD scripts and event handlers.
3049 You can do something similar with many digital multimeters, but note
3050 that you'll probably need to run the clock continuously for several
3051 seconds before it decides what clock rate to show. Adjust the
3052 toggling time up or down until the measured clock rate is a good
3053 match with the rate you specified in the @command{adapter speed} command;
3058 @deffn {Config Command} {parport write_on_exit} (@option{on}|@option{off})
3059 This will configure the parallel driver to write a known
3060 cable-specific value to the parallel interface on exiting OpenOCD.
3063 For example, the interface configuration file for a
3064 classic ``Wiggler'' cable on LPT2 might look something like this:
3067 adapter driver parport
3069 parport cable wiggler
3073 @deffn {Interface Driver} {presto}
3074 ASIX PRESTO USB JTAG programmer.
3077 @deffn {Interface Driver} {rlink}
3078 Raisonance RLink USB adapter
3081 @deffn {Interface Driver} {usbprog}
3082 usbprog is a freely programmable USB adapter.
3085 @deffn {Interface Driver} {vsllink}
3086 vsllink is part of Versaloon which is a versatile USB programmer.
3089 This defines quite a few driver-specific commands,
3090 which are not currently documented here.
3094 @anchor{hla_interface}
3095 @deffn {Interface Driver} {hla}
3096 This is a driver that supports multiple High Level Adapters.
3097 This type of adapter does not expose some of the lower level api's
3098 that OpenOCD would normally use to access the target.
3100 Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
3101 and Nuvoton Nu-Link.
3102 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
3103 versions of firmware where serial number is reset after first use. Suggest
3104 using ST firmware update utility to upgrade ST-LINK firmware even if current
3105 version reported is V2.J21.S4.
3107 @deffn {Config Command} {hla_device_desc} description
3108 Currently Not Supported.
3111 @deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
3112 Specifies the adapter layout to use.
3115 @deffn {Config Command} {hla_vid_pid} [vid pid]+
3116 Pairs of vendor IDs and product IDs of the device.
3119 @deffn {Config Command} {hla_stlink_backend} (usb | tcp [port])
3120 @emph{ST-Link only:} Choose between 'exclusive' USB communication (the default backend) or
3121 'shared' mode using ST-Link TCP server (the default port is 7184).
3123 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3124 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3125 ST-LINK server software module}.
3128 @deffn {Command} {hla_command} command
3129 Execute a custom adapter-specific command. The @var{command} string is
3130 passed as is to the underlying adapter layout handler.
3134 @anchor{st_link_dap_interface}
3135 @deffn {Interface Driver} {st-link}
3136 This is a driver that supports STMicroelectronics adapters ST-LINK/V2
3137 (from firmware V2J24) and STLINK-V3, thanks to a new API that provides
3138 directly access the arm ADIv5 DAP.
3140 The new API provide access to multiple AP on the same DAP, but the
3141 maximum number of the AP port is limited by the specific firmware version
3142 (e.g. firmware V2J29 has 3 as maximum AP number, while V2J32 has 8).
3143 An error is returned for any AP number above the maximum allowed value.
3145 @emph{Note:} Either these same adapters and their older versions are
3146 also supported by @ref{hla_interface, the hla interface driver}.
3148 @deffn {Config Command} {st-link backend} (usb | tcp [port])
3149 Choose between 'exclusive' USB communication (the default backend) or
3150 'shared' mode using ST-Link TCP server (the default port is 7184).
3152 @emph{Note:} ST-Link TCP server is a binary application provided by ST
3153 available from @url{https://www.st.com/en/development-tools/st-link-server.html,
3154 ST-LINK server software module}.
3156 @emph{Note:} ST-Link TCP server does not support the SWIM transport.
3159 @deffn {Config Command} {st-link vid_pid} [vid pid]+
3160 Pairs of vendor IDs and product IDs of the device.
3163 @deffn {Command} {st-link cmd} rx_n (tx_byte)+
3164 Sends an arbitrary command composed by the sequence of bytes @var{tx_byte}
3165 and receives @var{rx_n} bytes.
3167 For example, the command to read the target's supply voltage is one byte 0xf7 followed
3168 by 15 bytes zero. It returns 8 bytes, where the first 4 bytes represent the ADC sampling
3169 of the reference voltage 1.2V and the last 4 bytes represent the ADC sampling of half
3170 the target's supply voltage.
3172 > st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3173 0xf1 0x05 0x00 0x00 0x0b 0x08 0x00 0x00
3175 The result can be converted to Volts (ignoring the most significant bytes, always zero)
3177 > set a [st-link cmd 8 0xf7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
3178 > set n [expr @{[lindex $a 4] + 256 * [lindex $a 5]@}]
3179 > set d [expr @{[lindex $a 0] + 256 * [lindex $a 1]@}]
3180 > echo [expr @{2 * 1.2 * $n / $d@}]
3186 @deffn {Interface Driver} {opendous}
3187 opendous-jtag is a freely programmable USB adapter.
3190 @deffn {Interface Driver} {ulink}
3191 This is the Keil ULINK v1 JTAG debugger.
3194 @deffn {Interface Driver} {xds110}
3195 The XDS110 is included as the embedded debug probe on many Texas Instruments
3196 LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
3197 debug probe with the added capability to supply power to the target board. The
3198 following commands are supported by the XDS110 driver:
3200 @deffn {Config Command} {xds110 supply} voltage_in_millivolts
3201 Available only on the XDS110 stand-alone probe. Sets the voltage level of the
3202 XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
3203 can be set to any value in the range 1800 to 3600 millivolts.
3206 @deffn {Command} {xds110 info}
3207 Displays information about the connected XDS110 debug probe (e.g. firmware
3212 @deffn {Interface Driver} {xlnx_pcie_xvc}
3213 This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
3214 It is commonly found in Xilinx based PCI Express designs. It allows debugging
3215 fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
3216 exposed via extended capability registers in the PCI Express configuration space.
3218 For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
3220 @deffn {Config Command} {xlnx_pcie_xvc config} device
3221 Specifies the PCI Express device via parameter @var{device} to use.
3223 The correct value for @var{device} can be obtained by looking at the output
3224 of lscpi -D (first column) for the corresponding device.
3226 The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
3231 @deffn {Interface Driver} {bcm2835gpio}
3232 This SoC is present in Raspberry Pi which is a cheap single-board computer
3233 exposing some GPIOs on its expansion header.
3235 The driver accesses memory-mapped GPIO peripheral registers directly
3236 for maximum performance, but the only possible race condition is for
3237 the pins' modes/muxing (which is highly unlikely), so it should be
3238 able to coexist nicely with both sysfs bitbanging and various
3239 peripherals' kernel drivers. The driver restores the previous
3240 configuration on exit.
3242 GPIO numbers >= 32 can't be used for performance reasons.
3244 See @file{interface/raspberrypi-native.cfg} for a sample config and
3247 @deffn {Config Command} {bcm2835gpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3248 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3249 Must be specified to enable JTAG transport. These pins can also be specified
3253 @deffn {Config Command} {bcm2835gpio tck_num} @var{tck}
3254 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3255 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3258 @deffn {Config Command} {bcm2835gpio tms_num} @var{tms}
3259 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3260 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3263 @deffn {Config Command} {bcm2835gpio tdo_num} @var{tdo}
3264 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3265 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3268 @deffn {Config Command} {bcm2835gpio tdi_num} @var{tdi}
3269 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3270 specified using the configuration command @command{bcm2835gpio jtag_nums}.
3273 @deffn {Config Command} {bcm2835gpio swd_nums} @var{swclk} @var{swdio}
3274 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3275 specified to enable SWD transport. These pins can also be specified individually.
3278 @deffn {Config Command} {bcm2835gpio swclk_num} @var{swclk}
3279 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3280 specified using the configuration command @command{bcm2835gpio swd_nums}.
3283 @deffn {Config Command} {bcm2835gpio swdio_num} @var{swdio}
3284 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3285 specified using the configuration command @command{bcm2835gpio swd_nums}.
3288 @deffn {Config Command} {bcm2835gpio swdio_dir_num} @var{swdio} @var{dir}
3289 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3290 to control the direction of an external buffer on the SWDIO pin (set=output
3291 mode, clear=input mode). If not specified, this feature is disabled.
3294 @deffn {Config Command} {bcm2835gpio srst_num} @var{srst}
3295 Set SRST GPIO number. Must be specified to enable SRST.
3298 @deffn {Config Command} {bcm2835gpio trst_num} @var{trst}
3299 Set TRST GPIO number. Must be specified to enable TRST.
3302 @deffn {Config Command} {bcm2835gpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3303 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified,
3304 speed_coeff defaults to 113714, and speed_offset defaults to 28.
3307 @deffn {Config Command} {bcm2835gpio peripheral_base} @var{base}
3308 Set the peripheral base register address to access GPIOs. For the RPi1, use
3309 0x20000000. For RPi2 and RPi3, use 0x3F000000. For RPi4, use 0xFE000000. A full
3310 list can be found in the
3311 @uref{https://www.raspberrypi.org/documentation/hardware/raspberrypi/peripheral_addresses.md, official guide}.
3316 @deffn {Interface Driver} {imx_gpio}
3317 i.MX SoC is present in many community boards. Wandboard is an example
3318 of the one which is most popular.
3320 This driver is mostly the same as bcm2835gpio.
3322 See @file{interface/imx-native.cfg} for a sample config and
3328 @deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
3329 Black and BeagleBone Green single-board computers which expose some of the GPIOs
3330 on the two expansion headers.
3332 For maximum performance the driver accesses memory-mapped GPIO peripheral
3333 registers directly. The memory mapping requires read and write permission to
3334 kernel memory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
3335 be used. The driver restores the GPIO state on exit.
3337 All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO port
3338 0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on.
3340 See @file{interface/beaglebone-swd-native.cfg} for a sample configuration file.
3342 @deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3343 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
3344 Must be specified to enable JTAG transport. These pins can also be specified
3348 @deffn {Config Command} {am335xgpio tck_num} @var{tck}
3349 Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
3350 specified using the configuration command @command{am335xgpio jtag_nums}.
3353 @deffn {Config Command} {am335xgpio tms_num} @var{tms}
3354 Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
3355 specified using the configuration command @command{am335xgpio jtag_nums}.
3358 @deffn {Config Command} {am335xgpio tdo_num} @var{tdo}
3359 Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
3360 specified using the configuration command @command{am335xgpio jtag_nums}.
3363 @deffn {Config Command} {am335xgpio tdi_num} @var{tdi}
3364 Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
3365 specified using the configuration command @command{am335xgpio jtag_nums}.
3368 @deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio}
3369 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3370 specified to enable SWD transport. These pins can also be specified individually.
3373 @deffn {Config Command} {am335xgpio swclk_num} @var{swclk}
3374 Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
3375 specified using the configuration command @command{am335xgpio swd_nums}.
3378 @deffn {Config Command} {am335xgpio swdio_num} @var{swdio}
3379 Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
3380 specified using the configuration command @command{am335xgpio swd_nums}.
3383 @deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio_dir}
3384 Set SWDIO direction control pin GPIO number. If specified, this pin can be used
3385 to control the direction of an external buffer on the SWDIO pin. The direction
3386 control state can be set with the command @command{am335xgpio
3387 swdio_dir_output_state}. If not specified this feature is disabled.
3390 @deffn {Config Command} {am335xgpio swdio_dir_output_state} @var{output_state}
3391 Set the state required for an external SWDIO buffer to be an output. Valid
3392 values are @option{on} (default) and @option{off}.
3395 @deffn {Config Command} {am335xgpio srst_num} @var{srst}
3396 Set SRST GPIO number. Must be specified to enable SRST.
3399 @deffn {Config Command} {am335xgpio trst_num} @var{trst}
3400 Set TRST GPIO number. Must be specified to enable TRST.
3403 @deffn {Config Command} {am335xgpio led_num} @var{led}
3404 Set activity LED GPIO number. If not specified an activity LED is not enabled.
3407 @deffn {Config Command} {am335xgpio led_on_state} @var{on_state}
3408 Set required logic level for the LED to be on. Valid values are @option{on}
3409 (default) and @option{off}.
3412 @deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff} @var{speed_offset}
3413 Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
3414 speed_coeff defaults to 600000 and speed_offset defaults to 575.
3420 @deffn {Interface Driver} {linuxgpiod}
3421 Linux provides userspace access to GPIO through libgpiod since Linux kernel version v4.6.
3422 The driver emulates either JTAG or SWD transport through bitbanging.
3424 See @file{interface/dln-2-gpiod.cfg} for a sample config.
3426 @deffn {Config Command} {linuxgpiod gpiochip} @var{chip}
3427 Set the GPIO chip number for all GPIOs used by linuxgpiod. If GPIOs use
3428 different GPIO chips then the individual GPIO configuration commands (i.e., not
3429 @command{linuxgpiod jtag_nums} or @command{linuxgpiod swd_nums}) can be used to
3430 set chip numbers independently for each GPIO.
3433 @deffn {Config Command} {linuxgpiod jtag_nums} @var{tck} @var{tms} @var{tdi} @var{tdo}
3434 Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order). Must
3435 be specified to enable JTAG transport. These pins can also be specified
3439 @deffn {Config Command} {linuxgpiod tck_num} [@var{chip}] @var{tck}
3440 Set TCK GPIO number, and optionally TCK chip number. Must be specified to enable
3441 JTAG transport. Can also be specified using the configuration command
3442 @command{linuxgpiod jtag_nums}.
3445 @deffn {Config Command} {linuxgpiod tms_num} [@var{chip}] @var{tms}
3446 Set TMS GPIO number, and optionally TMS chip number. Must be specified to enable
3447 JTAG transport. Can also be specified using the configuration command
3448 @command{linuxgpiod jtag_nums}.
3451 @deffn {Config Command} {linuxgpiod tdo_num} [@var{chip}] @var{tdo}
3452 Set TDO GPIO number, and optionally TDO chip number. Must be specified to enable
3453 JTAG transport. Can also be specified using the configuration command
3454 @command{linuxgpiod jtag_nums}.
3457 @deffn {Config Command} {linuxgpiod tdi_num} [@var{chip}] @var{tdi}
3458 Set TDI GPIO number, and optionally TDI chip number. Must be specified to enable
3459 JTAG transport. Can also be specified using the configuration command
3460 @command{linuxgpiod jtag_nums}.
3463 @deffn {Config Command} {linuxgpiod trst_num} [@var{chip}] @var{trst}
3464 Set TRST GPIO number, and optionally TRST chip number. Must be specified to
3468 @deffn {Config Command} {linuxgpiod swd_nums} @var{swclk} @var{swdio}
3469 Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
3470 specified to enable SWD transport. These pins can also be specified
3474 @deffn {Config Command} {linuxgpiod swclk_num} [@var{chip}] @var{swclk}
3475 Set SWCLK GPIO number, and optionally SWCLK chip number. Must be specified to
3476 enable SWD transport. Can also be specified using the configuration command
3477 @command{linuxgpiod swd_nums}.
3480 @deffn {Config Command} {linuxgpiod swdio_num} [@var{chip}] @var{swdio}
3481 Set SWDIO GPIO number, and optionally SWDIO chip number. Must be specified to
3482 enable SWD transport. Can also be specified using the configuration command
3483 @command{linuxgpiod swd_nums}.
3486 @deffn {Config Command} {linuxgpiod swdio_dir_num} [@var{chip}] @var{swdio_dir}
3487 Set SWDIO direction control GPIO number, and optionally SWDIO direction control
3488 chip number. If specified, this GPIO can be used to control the direction of an
3489 external buffer connected to the SWDIO GPIO (set=output mode, clear=input mode).
3492 @deffn {Config Command} {linuxgpiod srst_num} [@var{chip}] @var{srst}
3493 Set SRST GPIO number, and optionally SRST chip number. Must be specified to
3497 @deffn {Config Command} {linuxgpiod led_num} [@var{chip}] @var{led}
3498 Set activity LED GPIO number, and optionally activity LED chip number. If not
3499 specified an activity LED is not enabled.
3505 @deffn {Interface Driver} {sysfsgpio}
3506 Linux legacy userspace access to GPIO through sysfs is deprecated from Linux kernel version v5.3.
3507 Prefer using @b{linuxgpiod}, instead.
3509 See @file{interface/sysfsgpio-raspberrypi.cfg} for a sample config.
3513 @deffn {Interface Driver} {openjtag}
3514 OpenJTAG compatible USB adapter.
3515 This defines some driver-specific commands:
3517 @deffn {Config Command} {openjtag variant} variant
3518 Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}).
3519 Currently valid @var{variant} values include:
3522 @item @b{standard} Standard variant (default).
3523 @item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller
3524 (see @uref{http://www.cypress.com/?rID=82870}).
3528 @deffn {Config Command} {openjtag device_desc} string
3529 The USB device description string of the adapter.
3530 This value is only used with the standard variant.
3535 @deffn {Interface Driver} {vdebug}
3536 Cadence Virtual Debug Interface driver.
3538 @deffn {Config Command} {vdebug server} host:port
3539 Specifies the host and TCP port number where the vdebug server runs.
3542 @deffn {Config Command} {vdebug batching} value
3543 Specifies the batching method for the vdebug request. Possible values are
3545 1 or wr to batch write transactions together (default)
3546 2 or rw to batch both read and write transactions
3549 @deffn {Config Command} {vdebug polling} min max
3550 Takes two values, representing the polling interval in ms. Lower values mean faster
3551 debugger responsiveness, but lower emulation performance. The minimum should be
3552 around 10, maximum should not exceed 1000, which is the default gdb and keepalive
3556 @deffn {Config Command} {vdebug bfm_path} path clk_period
3557 Specifies the hierarchical path and input clk period of the vdebug BFM in the design.
3558 The hierarchical path uses Verilog notation top.inst.inst
3559 The clock period must include the unit, for instance 40ns.
3562 @deffn {Config Command} {vdebug mem_path} path base size
3563 Specifies the hierarchical path to the design memory instance for backdoor access.
3564 Up to 4 memories can be specified. The hierarchical path uses Verilog notation.
3565 The base specifies start address in the design address space, size its size in bytes.
3566 Both values can use hexadecimal notation with prefix 0x.
3570 @deffn {Interface Driver} {jtag_dpi}
3571 SystemVerilog Direct Programming Interface (DPI) compatible driver for
3572 JTAG devices in emulation. The driver acts as a client for the SystemVerilog
3573 DPI server interface.
3575 @deffn {Config Command} {jtag_dpi set_port} port
3576 Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
3579 @deffn {Config Command} {jtag_dpi set_address} address
3580 Specifies the TCP/IP address of the SystemVerilog DPI server interface.
3585 @deffn {Interface Driver} {buspirate}
3587 This driver is for the Bus Pirate (see @url{http://dangerousprototypes.com/docs/Bus_Pirate}) and compatible devices.
3588 It uses a simple data protocol over a serial port connection.
3590 Most hardware development boards have a UART, a real serial port, or a virtual USB serial device, so this driver
3591 allows you to start building your own JTAG adapter without the complexity of a custom USB connection.
3593 @deffn {Config Command} {buspirate port} serial_port
3594 Specify the serial port's filename. For example:
3596 buspirate port /dev/ttyUSB0
3600 @deffn {Config Command} {buspirate speed} (normal|fast)
3601 Set the communication speed to 115k (normal) or 1M (fast). For example:
3603 buspirate speed normal
3607 @deffn {Config Command} {buspirate mode} (normal|open-drain)
3608 Set the Bus Pirate output mode.
3610 @item In normal mode (push/pull), do not enable the pull-ups, and do not connect I/O header pin VPU to JTAG VREF.
3611 @item In open drain mode, you will then need to enable the pull-ups.
3615 buspirate mode normal
3619 @deffn {Config Command} {buspirate pullup} (0|1)
3620 Whether to connect (1) or not (0) the I/O header pin VPU (JTAG VREF)
3621 to the pull-up/pull-down resistors on MOSI (JTAG TDI), CLK (JTAG TCK), MISO (JTAG TDO) and CS (JTAG TMS).
3628 @deffn {Config Command} {buspirate vreg} (0|1)
3629 Whether to enable (1) or disable (0) the built-in voltage regulator,
3630 which can be used to supply power to a test circuit through
3631 I/O header pins +3V3 and +5V. For example:
3637 @deffn {Command} {buspirate led} (0|1)
3638 Turns the Bus Pirate's LED on (1) or off (0). For example:
3647 @section Transport Configuration
3649 As noted earlier, depending on the version of OpenOCD you use,
3650 and the debug adapter you are using,
3651 several transports may be available to
3652 communicate with debug targets (or perhaps to program flash memory).
3653 @deffn {Command} {transport list}
3654 displays the names of the transports supported by this
3658 @deffn {Command} {transport select} @option{transport_name}
3659 Select which of the supported transports to use in this OpenOCD session.
3661 When invoked with @option{transport_name}, attempts to select the named
3662 transport. The transport must be supported by the debug adapter
3663 hardware and by the version of OpenOCD you are using (including the
3666 If no transport has been selected and no @option{transport_name} is
3667 provided, @command{transport select} auto-selects the first transport
3668 supported by the debug adapter.
3670 @command{transport select} always returns the name of the session's selected
3674 @subsection JTAG Transport
3676 JTAG is the original transport supported by OpenOCD, and most
3677 of the OpenOCD commands support it.
3678 JTAG transports expose a chain of one or more Test Access Points (TAPs),
3679 each of which must be explicitly declared.
3680 JTAG supports both debugging and boundary scan testing.
3681 Flash programming support is built on top of debug support.
3683 JTAG transport is selected with the command @command{transport select
3684 jtag}. Unless your adapter uses either @ref{hla_interface,the hla interface
3685 driver} (in which case the command is @command{transport select hla_jtag})
3686 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3687 the command is @command{transport select dapdirect_jtag}).
3689 @subsection SWD Transport
3691 @cindex Serial Wire Debug
3692 SWD (Serial Wire Debug) is an ARM-specific transport which exposes one
3693 Debug Access Point (DAP, which must be explicitly declared.
3694 (SWD uses fewer signal wires than JTAG.)
3695 SWD is debug-oriented, and does not support boundary scan testing.
3696 Flash programming support is built on top of debug support.
3697 (Some processors support both JTAG and SWD.)
3699 SWD transport is selected with the command @command{transport select
3700 swd}. Unless your adapter uses either @ref{hla_interface,the hla interface
3701 driver} (in which case the command is @command{transport select hla_swd})
3702 or @ref{st_link_dap_interface,the st-link interface driver} (in which case
3703 the command is @command{transport select dapdirect_swd}).
3705 @deffn {Config Command} {swd newdap} ...
3706 Declares a single DAP which uses SWD transport.
3707 Parameters are currently the same as "jtag newtap" but this is
3711 @cindex SWD multi-drop
3712 The newer SWD devices (SW-DP v2 or SWJ-DP v2) support the multi-drop extension
3713 of SWD protocol: two or more devices can be connected to one SWD adapter.
3714 SWD transport works in multi-drop mode if @ref{dap_create,DAP} is configured
3715 with both @code{-dp-id} and @code{-instance-id} parameters regardless how many
3718 Not all adapters and adapter drivers support SWD multi-drop. Only the following
3719 adapter drivers are SWD multi-drop capable:
3720 cmsis_dap (use an adapter with CMSIS-DAP version 2.0), ftdi, all bitbang based.
3722 @subsection SPI Transport
3724 @cindex Serial Peripheral Interface
3725 The Serial Peripheral Interface (SPI) is a general purpose transport
3726 which uses four wire signaling. Some processors use it as part of a
3727 solution for flash programming.
3729 @anchor{swimtransport}
3730 @subsection SWIM Transport
3732 @cindex Single Wire Interface Module
3733 The Single Wire Interface Module (SWIM) is a low-pin-count debug protocol used
3734 by the STMicroelectronics MCU family STM8 and documented in the
3735 @uref{https://www.st.com/resource/en/user_manual/cd00173911.pdf, User Manual UM470}.
3737 SWIM does not support boundary scan testing nor multiple cores.
3739 The SWIM transport is selected with the command @command{transport select swim}.
3741 The concept of TAPs does not fit in the protocol since SWIM does not implement
3742 a scan chain. Nevertheless, the current SW model of OpenOCD requires defining a
3743 virtual SWIM TAP through the command @command{swim newtap basename tap_type}.
3744 The TAP definition must precede the target definition command
3745 @command{target create target_name stm8 -chain-position basename.tap_type}.
3749 JTAG clock setup is part of system setup.
3750 It @emph{does not belong with interface setup} since any interface
3751 only knows a few of the constraints for the JTAG clock speed.
3752 Sometimes the JTAG speed is
3753 changed during the target initialization process: (1) slow at
3754 reset, (2) program the CPU clocks, (3) run fast.
3755 Both the "slow" and "fast" clock rates are functions of the
3756 oscillators used, the chip, the board design, and sometimes
3757 power management software that may be active.
3759 The speed used during reset, and the scan chain verification which
3760 follows reset, can be adjusted using a @code{reset-start}
3761 target event handler.
3762 It can then be reconfigured to a faster speed by a
3763 @code{reset-init} target event handler after it reprograms those
3764 CPU clocks, or manually (if something else, such as a boot loader,
3765 sets up those clocks).
3766 @xref{targetevents,,Target Events}.
3767 When the initial low JTAG speed is a chip characteristic, perhaps
3768 because of a required oscillator speed, provide such a handler
3769 in the target config file.
3770 When that speed is a function of a board-specific characteristic
3771 such as which speed oscillator is used, it belongs in the board
3772 config file instead.
3773 In both cases it's safest to also set the initial JTAG clock rate
3774 to that same slow speed, so that OpenOCD never starts up using a
3775 clock speed that's faster than the scan chain can support.
3779 $_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
3782 If your system supports adaptive clocking (RTCK), configuring
3783 JTAG to use that is probably the most robust approach.
3784 However, it introduces delays to synchronize clocks; so it
3785 may not be the fastest solution.
3787 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
3788 instead of @command{adapter speed}, but only for (ARM) cores and boards
3789 which support adaptive clocking.
3791 @deffn {Command} {adapter speed} max_speed_kHz
3792 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
3793 JTAG interfaces usually support a limited number of
3794 speeds. The speed actually used won't be faster
3795 than the speed specified.
3797 Chip data sheets generally include a top JTAG clock rate.
3798 The actual rate is often a function of a CPU core clock,
3799 and is normally less than that peak rate.
3800 For example, most ARM cores accept at most one sixth of the CPU clock.
3802 Speed 0 (khz) selects RTCK method.
3803 @xref{faqrtck,,FAQ RTCK}.
3804 If your system uses RTCK, you won't need to change the
3805 JTAG clocking after setup.
3806 Not all interfaces, boards, or targets support ``rtck''.
3807 If the interface device can not
3808 support it, an error is returned when you try to use RTCK.
3811 @defun jtag_rclk fallback_speed_kHz
3812 @cindex adaptive clocking
3814 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
3815 If that fails (maybe the interface, board, or target doesn't
3816 support it), falls back to the specified frequency.
3818 # Fall back to 3mhz if RTCK is not supported
3823 @node Reset Configuration
3824 @chapter Reset Configuration
3825 @cindex Reset Configuration
3827 Every system configuration may require a different reset
3828 configuration. This can also be quite confusing.
3829 Resets also interact with @var{reset-init} event handlers,
3830 which do things like setting up clocks and DRAM, and
3831 JTAG clock rates. (@xref{jtagspeed,,JTAG Speed}.)
3832 They can also interact with JTAG routers.
3833 Please see the various board files for examples.
3836 To maintainers and integrators:
3837 Reset configuration touches several things at once.
3838 Normally the board configuration file
3839 should define it and assume that the JTAG adapter supports
3840 everything that's wired up to the board's JTAG connector.
3842 However, the target configuration file could also make note
3843 of something the silicon vendor has done inside the chip,
3844 which will be true for most (or all) boards using that chip.
3845 And when the JTAG adapter doesn't support everything, the
3846 user configuration file will need to override parts of
3847 the reset configuration provided by other files.
3850 @section Types of Reset
3852 There are many kinds of reset possible through JTAG, but
3853 they may not all work with a given board and adapter.
3854 That's part of why reset configuration can be error prone.
3858 @emph{System Reset} ... the @emph{SRST} hardware signal
3859 resets all chips connected to the JTAG adapter, such as processors,
3860 power management chips, and I/O controllers. Normally resets triggered
3861 with this signal behave exactly like pressing a RESET button.
3863 @emph{JTAG TAP Reset} ... the @emph{TRST} hardware signal resets
3864 just the TAP controllers connected to the JTAG adapter.
3865 Such resets should not be visible to the rest of the system; resetting a
3866 device's TAP controller just puts that controller into a known state.
3868 @emph{Emulation Reset} ... many devices can be reset through JTAG
3869 commands. These resets are often distinguishable from system
3870 resets, either explicitly (a "reset reason" register says so)
3871 or implicitly (not all parts of the chip get reset).
3873 @emph{Other Resets} ... system-on-chip devices often support
3874 several other types of reset.
3875 You may need to arrange that a watchdog timer stops
3876 while debugging, preventing a watchdog reset.
3877 There may be individual module resets.
3880 In the best case, OpenOCD can hold SRST, then reset
3881 the TAPs via TRST and send commands through JTAG to halt the
3882 CPU at the reset vector before the 1st instruction is executed.
3883 Then when it finally releases the SRST signal, the system is
3884 halted under debugger control before any code has executed.
3885 This is the behavior required to support the @command{reset halt}
3886 and @command{reset init} commands; after @command{reset init} a
3887 board-specific script might do things like setting up DRAM.
3888 (@xref{resetcommand,,Reset Command}.)
3890 @anchor{srstandtrstissues}
3891 @section SRST and TRST Issues
3893 Because SRST and TRST are hardware signals, they can have a
3894 variety of system-specific constraints. Some of the most
3899 @item @emph{Signal not available} ... Some boards don't wire
3900 SRST or TRST to the JTAG connector. Some JTAG adapters don't
3901 support such signals even if they are wired up.
3902 Use the @command{reset_config} @var{signals} options to say
3903 when either of those signals is not connected.
3904 When SRST is not available, your code might not be able to rely
3905 on controllers having been fully reset during code startup.
3906 Missing TRST is not a problem, since JTAG-level resets can
3907 be triggered using with TMS signaling.
3909 @item @emph{Signals shorted} ... Sometimes a chip, board, or
3910 adapter will connect SRST to TRST, instead of keeping them separate.
3911 Use the @command{reset_config} @var{combination} options to say
3912 when those signals aren't properly independent.
3914 @item @emph{Timing} ... Reset circuitry like a resistor/capacitor
3915 delay circuit, reset supervisor, or on-chip features can extend
3916 the effect of a JTAG adapter's reset for some time after the adapter
3917 stops issuing the reset. For example, there may be chip or board
3918 requirements that all reset pulses last for at least a
3919 certain amount of time; and reset buttons commonly have
3920 hardware debouncing.
3921 Use the @command{adapter srst delay} and @command{jtag_ntrst_delay}
3922 commands to say when extra delays are needed.
3924 @item @emph{Drive type} ... Reset lines often have a pullup
3925 resistor, letting the JTAG interface treat them as open-drain
3926 signals. But that's not a requirement, so the adapter may need
3927 to use push/pull output drivers.
3928 Also, with weak pullups it may be advisable to drive
3929 signals to both levels (push/pull) to minimize rise times.
3930 Use the @command{reset_config} @var{trst_type} and
3931 @var{srst_type} parameters to say how to drive reset signals.
3933 @item @emph{Special initialization} ... Targets sometimes need
3934 special JTAG initialization sequences to handle chip-specific
3935 issues (not limited to errata).
3936 For example, certain JTAG commands might need to be issued while
3937 the system as a whole is in a reset state (SRST active)
3938 but the JTAG scan chain is usable (TRST inactive).
3939 Many systems treat combined assertion of SRST and TRST as a
3940 trigger for a harder reset than SRST alone.
3941 Such custom reset handling is discussed later in this chapter.
3944 There can also be other issues.
3945 Some devices don't fully conform to the JTAG specifications.
3946 Trivial system-specific differences are common, such as
3947 SRST and TRST using slightly different names.
3948 There are also vendors who distribute key JTAG documentation for
3949 their chips only to developers who have signed a Non-Disclosure
3952 Sometimes there are chip-specific extensions like a requirement to use
3953 the normally-optional TRST signal (precluding use of JTAG adapters which
3954 don't pass TRST through), or needing extra steps to complete a TAP reset.
3956 In short, SRST and especially TRST handling may be very finicky,
3957 needing to cope with both architecture and board specific constraints.
3959 @section Commands for Handling Resets
3961 @deffn {Command} {adapter srst pulse_width} milliseconds
3962 Minimum amount of time (in milliseconds) OpenOCD should wait
3963 after asserting nSRST (active-low system reset) before
3964 allowing it to be deasserted.
3967 @deffn {Command} {adapter srst delay} milliseconds
3968 How long (in milliseconds) OpenOCD should wait after deasserting
3969 nSRST (active-low system reset) before starting new JTAG operations.
3970 When a board has a reset button connected to SRST line it will
3971 probably have hardware debouncing, implying you should use this.
3974 @deffn {Command} {jtag_ntrst_assert_width} milliseconds
3975 Minimum amount of time (in milliseconds) OpenOCD should wait
3976 after asserting nTRST (active-low JTAG TAP reset) before
3977 allowing it to be deasserted.
3980 @deffn {Command} {jtag_ntrst_delay} milliseconds
3981 How long (in milliseconds) OpenOCD should wait after deasserting
3982 nTRST (active-low JTAG TAP reset) before starting new JTAG operations.
3985 @anchor{reset_config}
3986 @deffn {Command} {reset_config} mode_flag ...
3987 This command displays or modifies the reset configuration
3988 of your combination of JTAG board and target in target
3989 configuration scripts.
3991 Information earlier in this section describes the kind of problems
3992 the command is intended to address (@pxref{srstandtrstissues,,SRST and TRST Issues}).
3993 As a rule this command belongs only in board config files,
3994 describing issues like @emph{board doesn't connect TRST};
3995 or in user config files, addressing limitations derived
3996 from a particular combination of interface and board.
3997 (An unlikely example would be using a TRST-only adapter
3998 with a board that only wires up SRST.)
4000 The @var{mode_flag} options can be specified in any order, but only one
4001 of each type -- @var{signals}, @var{combination}, @var{gates},
4002 @var{trst_type}, @var{srst_type} and @var{connect_type}
4003 -- may be specified at a time.
4004 If you don't provide a new value for a given type, its previous
4005 value (perhaps the default) is unchanged.
4006 For example, this means that you don't need to say anything at all about
4007 TRST just to declare that if the JTAG adapter should want to drive SRST,
4008 it must explicitly be driven high (@option{srst_push_pull}).
4012 @var{signals} can specify which of the reset signals are connected.
4013 For example, If the JTAG interface provides SRST, but the board doesn't
4014 connect that signal properly, then OpenOCD can't use it.
4015 Possible values are @option{none} (the default), @option{trst_only},
4016 @option{srst_only} and @option{trst_and_srst}.
4019 If your board provides SRST and/or TRST through the JTAG connector,
4020 you must declare that so those signals can be used.
4024 The @var{combination} is an optional value specifying broken reset
4025 signal implementations.
4026 The default behaviour if no option given is @option{separate},
4027 indicating everything behaves normally.
4028 @option{srst_pulls_trst} states that the
4029 test logic is reset together with the reset of the system (e.g. NXP
4030 LPC2000, "broken" board layout), @option{trst_pulls_srst} says that
4031 the system is reset together with the test logic (only hypothetical, I
4032 haven't seen hardware with such a bug, and can be worked around).
4033 @option{combined} implies both @option{srst_pulls_trst} and
4034 @option{trst_pulls_srst}.
4037 The @var{gates} tokens control flags that describe some cases where
4038 JTAG may be unavailable during reset.
4039 @option{srst_gates_jtag} (default)
4040 indicates that asserting SRST gates the
4041 JTAG clock. This means that no communication can happen on JTAG
4042 while SRST is asserted.
4043 Its converse is @option{srst_nogate}, indicating that JTAG commands
4044 can safely be issued while SRST is active.
4047 The @var{connect_type} tokens control flags that describe some cases where
4048 SRST is asserted while connecting to the target. @option{srst_nogate}
4049 is required to use this option.
4050 @option{connect_deassert_srst} (default)
4051 indicates that SRST will not be asserted while connecting to the target.
4052 Its converse is @option{connect_assert_srst}, indicating that SRST will
4053 be asserted before any target connection.
4054 Only some targets support this feature, STM32 and STR9 are examples.
4055 This feature is useful if you are unable to connect to your target due
4056 to incorrect options byte config or illegal program execution.
4059 The optional @var{trst_type} and @var{srst_type} parameters allow the
4060 driver mode of each reset line to be specified. These values only affect
4061 JTAG interfaces with support for different driver modes, like the Amontec
4062 JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
4063 relevant signal (TRST or SRST) is not connected.
4067 Possible @var{trst_type} driver modes for the test reset signal (TRST)
4068 are the default @option{trst_push_pull}, and @option{trst_open_drain}.
4069 Most boards connect this signal to a pulldown, so the JTAG TAPs
4070 never leave reset unless they are hooked up to a JTAG adapter.
4073 Possible @var{srst_type} driver modes for the system reset signal (SRST)
4074 are the default @option{srst_open_drain}, and @option{srst_push_pull}.
4075 Most boards connect this signal to a pullup, and allow the
4076 signal to be pulled low by various events including system
4077 power-up and pressing a reset button.
4081 @section Custom Reset Handling
4084 OpenOCD has several ways to help support the various reset
4085 mechanisms provided by chip and board vendors.
4086 The commands shown in the previous section give standard parameters.
4087 There are also @emph{event handlers} associated with TAPs or Targets.
4088 Those handlers are Tcl procedures you can provide, which are invoked
4089 at particular points in the reset sequence.
4091 @emph{When SRST is not an option} you must set
4092 up a @code{reset-assert} event handler for your target.
4093 For example, some JTAG adapters don't include the SRST signal;
4094 and some boards have multiple targets, and you won't always
4095 want to reset everything at once.
4097 After configuring those mechanisms, you might still
4098 find your board doesn't start up or reset correctly.
4099 For example, maybe it needs a slightly different sequence
4100 of SRST and/or TRST manipulations, because of quirks that
4101 the @command{reset_config} mechanism doesn't address;
4102 or asserting both might trigger a stronger reset, which
4103 needs special attention.
4105 Experiment with lower level operations, such as
4106 @command{adapter assert}, @command{adapter deassert}
4107 and the @command{jtag arp_*} operations shown here,
4108 to find a sequence of operations that works.
4109 @xref{JTAG Commands}.
4110 When you find a working sequence, it can be used to override
4111 @command{jtag_init}, which fires during OpenOCD startup
4112 (@pxref{configurationstage,,Configuration Stage});
4113 or @command{init_reset}, which fires during reset processing.
4115 You might also want to provide some project-specific reset
4116 schemes. For example, on a multi-target board the standard
4117 @command{reset} command would reset all targets, but you
4118 may need the ability to reset only one target at time and
4119 thus want to avoid using the board-wide SRST signal.
4121 @deffn {Overridable Procedure} {init_reset} mode
4122 This is invoked near the beginning of the @command{reset} command,
4123 usually to provide as much of a cold (power-up) reset as practical.
4124 By default it is also invoked from @command{jtag_init} if
4125 the scan chain does not respond to pure JTAG operations.
4126 The @var{mode} parameter is the parameter given to the
4127 low level reset command (@option{halt},
4128 @option{init}, or @option{run}), @option{setup},
4129 or potentially some other value.
4131 The default implementation just invokes @command{jtag arp_init-reset}.
4132 Replacements will normally build on low level JTAG
4133 operations such as @command{adapter assert} and @command{adapter deassert}.
4134 Operations here must not address individual TAPs
4135 (or their associated targets)
4136 until the JTAG scan chain has first been verified to work.
4138 Implementations must have verified the JTAG scan chain before
4140 This is done by calling @command{jtag arp_init}
4141 (or @command{jtag arp_init-reset}).
4144 @deffn {Command} {jtag arp_init}
4145 This validates the scan chain using just the four
4146 standard JTAG signals (TMS, TCK, TDI, TDO).
4147 It starts by issuing a JTAG-only reset.
4148 Then it performs checks to verify that the scan chain configuration
4149 matches the TAPs it can observe.
4150 Those checks include checking IDCODE values for each active TAP,
4151 and verifying the length of their instruction registers using
4152 TAP @code{-ircapture} and @code{-irmask} values.
4153 If these tests all pass, TAP @code{setup} events are
4154 issued to all TAPs with handlers for that event.
4157 @deffn {Command} {jtag arp_init-reset}
4158 This uses TRST and SRST to try resetting
4159 everything on the JTAG scan chain
4160 (and anything else connected to SRST).
4161 It then invokes the logic of @command{jtag arp_init}.
4165 @node TAP Declaration
4166 @chapter TAP Declaration
4167 @cindex TAP declaration
4168 @cindex TAP configuration
4170 @emph{Test Access Ports} (TAPs) are the core of JTAG.
4171 TAPs serve many roles, including:
4174 @item @b{Debug Target} A CPU TAP can be used as a GDB debug target.
4175 @item @b{Flash Programming} Some chips program the flash directly via JTAG.
4176 Others do it indirectly, making a CPU do it.
4177 @item @b{Program Download} Using the same CPU support GDB uses,
4178 you can initialize a DRAM controller, download code to DRAM, and then
4179 start running that code.
4180 @item @b{Boundary Scan} Most chips support boundary scan, which
4181 helps test for board assembly problems like solder bridges
4182 and missing connections.
4185 OpenOCD must know about the active TAPs on your board(s).
4186 Setting up the TAPs is the core task of your configuration files.
4187 Once those TAPs are set up, you can pass their names to code
4188 which sets up CPUs and exports them as GDB targets,
4189 probes flash memory, performs low-level JTAG operations, and more.
4191 @section Scan Chains
4194 TAPs are part of a hardware @dfn{scan chain},
4195 which is a daisy chain of TAPs.
4196 They also need to be added to
4197 OpenOCD's software mirror of that hardware list,
4198 giving each member a name and associating other data with it.
4199 Simple scan chains, with a single TAP, are common in
4200 systems with a single microcontroller or microprocessor.
4201 More complex chips may have several TAPs internally.
4202 Very complex scan chains might have a dozen or more TAPs:
4203 several in one chip, more in the next, and connecting
4204 to other boards with their own chips and TAPs.
4206 You can display the list with the @command{scan_chain} command.
4207 (Don't confuse this with the list displayed by the @command{targets}
4208 command, presented in the next chapter.
4209 That only displays TAPs for CPUs which are configured as
4211 Here's what the scan chain might look like for a chip more than one TAP:
4214 TapName Enabled IdCode Expected IrLen IrCap IrMask
4215 -- ------------------ ------- ---------- ---------- ----- ----- ------
4216 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
4217 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
4218 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
4221 OpenOCD can detect some of that information, but not all
4222 of it. @xref{autoprobing,,Autoprobing}.
4223 Unfortunately, those TAPs can't always be autoconfigured,
4224 because not all devices provide good support for that.
4225 JTAG doesn't require supporting IDCODE instructions, and
4226 chips with JTAG routers may not link TAPs into the chain
4227 until they are told to do so.
4229 The configuration mechanism currently supported by OpenOCD
4230 requires explicit configuration of all TAP devices using
4231 @command{jtag newtap} commands, as detailed later in this chapter.
4232 A command like this would declare one tap and name it @code{chip1.cpu}:
4235 jtag newtap chip1 cpu -irlen 4 -expected-id 0x3ba00477
4238 Each target configuration file lists the TAPs provided
4240 Board configuration files combine all the targets on a board,
4242 Note that @emph{the order in which TAPs are declared is very important.}
4243 That declaration order must match the order in the JTAG scan chain,
4244 both inside a single chip and between them.
4245 @xref{faqtaporder,,FAQ TAP Order}.
4247 For example, the STMicroelectronics STR912 chip has
4248 three separate TAPs@footnote{See the ST
4249 document titled: @emph{STR91xFAxxx, Section 3.15 Jtag Interface, Page:
4250 28/102, Figure 3: JTAG chaining inside the STR91xFA}.
4251 @url{http://eu.st.com/stonline/products/literature/ds/13495.pdf}}.
4252 To configure those taps, @file{target/str912.cfg}
4253 includes commands something like this:
4256 jtag newtap str912 flash ... params ...
4257 jtag newtap str912 cpu ... params ...
4258 jtag newtap str912 bs ... params ...
4261 Actual config files typically use a variable such as @code{$_CHIPNAME}
4262 instead of literals like @option{str912}, to support more than one chip
4263 of each type. @xref{Config File Guidelines}.
4265 @deffn {Command} {jtag names}
4266 Returns the names of all current TAPs in the scan chain.
4267 Use @command{jtag cget} or @command{jtag tapisenabled}
4268 to examine attributes and state of each TAP.
4270 foreach t [jtag names] @{
4271 puts [format "TAP: %s\n" $t]
4276 @deffn {Command} {scan_chain}
4277 Displays the TAPs in the scan chain configuration,
4279 The set of TAPs listed by this command is fixed by
4280 exiting the OpenOCD configuration stage,
4281 but systems with a JTAG router can
4282 enable or disable TAPs dynamically.
4285 @c FIXME! "jtag cget" should be able to return all TAP
4286 @c attributes, like "$target_name cget" does for targets.
4288 @c Probably want "jtag eventlist", and a "tap-reset" event
4289 @c (on entry to RESET state).
4294 When TAP objects are declared with @command{jtag newtap},
4295 a @dfn{dotted.name} is created for the TAP, combining the
4296 name of a module (usually a chip) and a label for the TAP.
4297 For example: @code{xilinx.tap}, @code{str912.flash},
4298 @code{omap3530.jrc}, @code{dm6446.dsp}, or @code{stm32.cpu}.
4299 Many other commands use that dotted.name to manipulate or
4300 refer to the TAP. For example, CPU configuration uses the
4301 name, as does declaration of NAND or NOR flash banks.
4303 The components of a dotted name should follow ``C'' symbol
4304 name rules: start with an alphabetic character, then numbers
4305 and underscores are OK; while others (including dots!) are not.
4307 @section TAP Declaration Commands
4309 @deffn {Config Command} {jtag newtap} chipname tapname configparams...
4310 Declares a new TAP with the dotted name @var{chipname}.@var{tapname},
4311 and configured according to the various @var{configparams}.
4313 The @var{chipname} is a symbolic name for the chip.
4314 Conventionally target config files use @code{$_CHIPNAME},
4315 defaulting to the model name given by the chip vendor but
4318 @cindex TAP naming convention
4319 The @var{tapname} reflects the role of that TAP,
4320 and should follow this convention:
4323 @item @code{bs} -- For boundary scan if this is a separate TAP;
4324 @item @code{cpu} -- The main CPU of the chip, alternatively
4325 @code{arm} and @code{dsp} on chips with both ARM and DSP CPUs,
4326 @code{arm1} and @code{arm2} on chips with two ARMs, and so forth;
4327 @item @code{etb} -- For an embedded trace buffer (example: an ARM ETB11);
4328 @item @code{flash} -- If the chip has a flash TAP, like the str912;
4329 @item @code{jrc} -- For JTAG route controller (example: the ICEPick modules
4330 on many Texas Instruments chips, like the OMAP3530 on Beagleboards);
4331 @item @code{tap} -- Should be used only for FPGA- or CPLD-like devices
4333 @item @code{unknownN} -- If you have no idea what the TAP is for (N is a number);
4334 @item @emph{when in doubt} -- Use the chip maker's name in their data sheet.
4335 For example, the Freescale i.MX31 has a SDMA (Smart DMA) with
4336 a JTAG TAP; that TAP should be named @code{sdma}.
4339 Every TAP requires at least the following @var{configparams}:
4342 @item @code{-irlen} @var{NUMBER}
4343 @*The length in bits of the
4344 instruction register, such as 4 or 5 bits.
4347 A TAP may also provide optional @var{configparams}:
4350 @item @code{-disable} (or @code{-enable})
4351 @*Use the @code{-disable} parameter to flag a TAP which is not
4352 linked into the scan chain after a reset using either TRST
4353 or the JTAG state machine's @sc{reset} state.
4354 You may use @code{-enable} to highlight the default state
4355 (the TAP is linked in).
4356 @xref{enablinganddisablingtaps,,Enabling and Disabling TAPs}.
4357 @item @code{-expected-id} @var{NUMBER}
4358 @*A non-zero @var{number} represents a 32-bit IDCODE
4359 which you expect to find when the scan chain is examined.
4360 These codes are not required by all JTAG devices.
4361 @emph{Repeat the option} as many times as required if more than one
4362 ID code could appear (for example, multiple versions).
4363 Specify @var{number} as zero to suppress warnings about IDCODE
4364 values that were found but not included in the list.
4366 Provide this value if at all possible, since it lets OpenOCD
4367 tell when the scan chain it sees isn't right. These values
4368 are provided in vendors' chip documentation, usually a technical
4369 reference manual. Sometimes you may need to probe the JTAG
4370 hardware to find these values.
4371 @xref{autoprobing,,Autoprobing}.
4372 @item @code{-ignore-version}
4373 @*Specify this to ignore the JTAG version field in the @code{-expected-id}
4374 option. When vendors put out multiple versions of a chip, or use the same
4375 JTAG-level ID for several largely-compatible chips, it may be more practical
4376 to ignore the version field than to update config files to handle all of
4377 the various chip IDs. The version field is defined as bit 28-31 of the IDCODE.
4378 @item @code{-ignore-bypass}
4379 @*Specify this to ignore the 'bypass' bit of the idcode. Some vendor put
4380 an invalid idcode regarding this bit. Specify this to ignore this bit and
4381 to not consider this tap in bypass mode.
4382 @item @code{-ircapture} @var{NUMBER}
4383 @*The bit pattern loaded by the TAP into the JTAG shift register
4384 on entry to the @sc{ircapture} state, such as 0x01.
4385 JTAG requires the two LSBs of this value to be 01.
4386 By default, @code{-ircapture} and @code{-irmask} are set
4387 up to verify that two-bit value. You may provide
4388 additional bits if you know them, or indicate that
4389 a TAP doesn't conform to the JTAG specification.
4390 @item @code{-irmask} @var{NUMBER}
4391 @*A mask used with @code{-ircapture}
4392 to verify that instruction scans work correctly.
4393 Such scans are not used by OpenOCD except to verify that
4394 there seems to be no problems with JTAG scan chain operations.
4395 @item @code{-ignore-syspwrupack}
4396 @*Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4397 register during initial examination and when checking the sticky error bit.
4398 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4399 devices do not set the ack bit until sometime later.
4403 @section Other TAP commands
4405 @deffn {Command} {jtag cget} dotted.name @option{-idcode}
4406 Get the value of the IDCODE found in hardware.
4409 @deffn {Command} {jtag cget} dotted.name @option{-event} event_name
4410 @deffnx {Command} {jtag configure} dotted.name @option{-event} event_name handler
4411 At this writing this TAP attribute
4412 mechanism is limited and used mostly for event handling.
4413 (It is not a direct analogue of the @code{cget}/@code{configure}
4414 mechanism for debugger targets.)
4415 See the next section for information about the available events.
4417 The @code{configure} subcommand assigns an event handler,
4418 a TCL string which is evaluated when the event is triggered.
4419 The @code{cget} subcommand returns that handler.
4426 OpenOCD includes two event mechanisms.
4427 The one presented here applies to all JTAG TAPs.
4428 The other applies to debugger targets,
4429 which are associated with certain TAPs.
4431 The TAP events currently defined are:
4434 @item @b{post-reset}
4435 @* The TAP has just completed a JTAG reset.
4436 The tap may still be in the JTAG @sc{reset} state.
4437 Handlers for these events might perform initialization sequences
4438 such as issuing TCK cycles, TMS sequences to ensure
4439 exit from the ARM SWD mode, and more.
4441 Because the scan chain has not yet been verified, handlers for these events
4442 @emph{should not issue commands which scan the JTAG IR or DR registers}
4443 of any particular target.
4444 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
4446 @* The scan chain has been reset and verified.
4447 This handler may enable TAPs as needed.
4448 @item @b{tap-disable}
4449 @* The TAP needs to be disabled. This handler should
4450 implement @command{jtag tapdisable}
4451 by issuing the relevant JTAG commands.
4452 @item @b{tap-enable}
4453 @* The TAP needs to be enabled. This handler should
4454 implement @command{jtag tapenable}
4455 by issuing the relevant JTAG commands.
4458 If you need some action after each JTAG reset which isn't actually
4459 specific to any TAP (since you can't yet trust the scan chain's
4460 contents to be accurate), you might:
4463 jtag configure CHIP.jrc -event post-reset @{
4464 echo "JTAG Reset done"
4465 ... non-scan jtag operations to be done after reset
4470 @anchor{enablinganddisablingtaps}
4471 @section Enabling and Disabling TAPs
4472 @cindex JTAG Route Controller
4475 In some systems, a @dfn{JTAG Route Controller} (JRC)
4476 is used to enable and/or disable specific JTAG TAPs.
4477 Many ARM-based chips from Texas Instruments include
4478 an ``ICEPick'' module, which is a JRC.
4479 Such chips include DaVinci and OMAP3 processors.
4481 A given TAP may not be visible until the JRC has been
4482 told to link it into the scan chain; and if the JRC
4483 has been told to unlink that TAP, it will no longer
4485 Such routers address problems that JTAG ``bypass mode''
4489 @item The scan chain can only go as fast as its slowest TAP.
4490 @item Having many TAPs slows instruction scans, since all
4491 TAPs receive new instructions.
4492 @item TAPs in the scan chain must be powered up, which wastes
4493 power and prevents debugging some power management mechanisms.
4496 The IEEE 1149.1 JTAG standard has no concept of a ``disabled'' tap,
4497 as implied by the existence of JTAG routers.
4498 However, the upcoming IEEE 1149.7 framework (layered on top of JTAG)
4499 does include a kind of JTAG router functionality.
4501 @c (a) currently the event handlers don't seem to be able to
4502 @c fail in a way that could lead to no-change-of-state.
4504 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
4505 shown below, and is implemented using TAP event handlers.
4506 So for example, when defining a TAP for a CPU connected to
4507 a JTAG router, your @file{target.cfg} file
4508 should define TAP event handlers using
4509 code that looks something like this:
4512 jtag configure CHIP.cpu -event tap-enable @{
4513 ... jtag operations using CHIP.jrc
4515 jtag configure CHIP.cpu -event tap-disable @{
4516 ... jtag operations using CHIP.jrc
4520 Then you might want that CPU's TAP enabled almost all the time:
4523 jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
4526 Note how that particular setup event handler declaration
4527 uses quotes to evaluate @code{$CHIP} when the event is configured.
4528 Using brackets @{ @} would cause it to be evaluated later,
4529 at runtime, when it might have a different value.
4531 @deffn {Command} {jtag tapdisable} dotted.name
4532 If necessary, disables the tap
4533 by sending it a @option{tap-disable} event.
4534 Returns the string "1" if the tap
4535 specified by @var{dotted.name} is enabled,
4536 and "0" if it is disabled.
4539 @deffn {Command} {jtag tapenable} dotted.name
4540 If necessary, enables the tap
4541 by sending it a @option{tap-enable} event.
4542 Returns the string "1" if the tap
4543 specified by @var{dotted.name} is enabled,
4544 and "0" if it is disabled.
4547 @deffn {Command} {jtag tapisenabled} dotted.name
4548 Returns the string "1" if the tap
4549 specified by @var{dotted.name} is enabled,
4550 and "0" if it is disabled.
4553 Humans will find the @command{scan_chain} command more helpful
4554 for querying the state of the JTAG taps.
4558 @anchor{autoprobing}
4559 @section Autoprobing
4561 @cindex JTAG autoprobe
4563 TAP configuration is the first thing that needs to be done
4564 after interface and reset configuration. Sometimes it's
4565 hard finding out what TAPs exist, or how they are identified.
4566 Vendor documentation is not always easy to find and use.
4568 To help you get past such problems, OpenOCD has a limited
4569 @emph{autoprobing} ability to look at the scan chain, doing
4570 a @dfn{blind interrogation} and then reporting the TAPs it finds.
4571 To use this mechanism, start the OpenOCD server with only data
4572 that configures your JTAG interface, and arranges to come up
4573 with a slow clock (many devices don't support fast JTAG clocks
4574 right when they come out of reset).
4576 For example, your @file{openocd.cfg} file might have:
4579 source [find interface/olimex-arm-usb-tiny-h.cfg]
4580 reset_config trst_and_srst
4584 When you start the server without any TAPs configured, it will
4585 attempt to autoconfigure the TAPs. There are two parts to this:
4588 @item @emph{TAP discovery} ...
4589 After a JTAG reset (sometimes a system reset may be needed too),
4590 each TAP's data registers will hold the contents of either the
4591 IDCODE or BYPASS register.
4592 If JTAG communication is working, OpenOCD will see each TAP,
4593 and report what @option{-expected-id} to use with it.
4594 @item @emph{IR Length discovery} ...
4595 Unfortunately JTAG does not provide a reliable way to find out
4596 the value of the @option{-irlen} parameter to use with a TAP
4598 If OpenOCD can discover the length of a TAP's instruction
4599 register, it will report it.
4600 Otherwise you may need to consult vendor documentation, such
4601 as chip data sheets or BSDL files.
4604 In many cases your board will have a simple scan chain with just
4605 a single device. Here's what OpenOCD reported with one board
4606 that's a bit more complex:
4610 There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
4611 AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
4612 AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
4613 AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
4614 AUTO auto0.tap - use "... -irlen 4"
4615 AUTO auto1.tap - use "... -irlen 4"
4616 AUTO auto2.tap - use "... -irlen 6"
4617 no gdb ports allocated as no target has been specified
4620 Given that information, you should be able to either find some existing
4621 config files to use, or create your own. If you create your own, you
4622 would configure from the bottom up: first a @file{target.cfg} file
4623 with these TAPs, any targets associated with them, and any on-chip
4624 resources; then a @file{board.cfg} with off-chip resources, clocking,
4627 @anchor{dapdeclaration}
4628 @section DAP declaration (ARMv6-M, ARMv7 and ARMv8 targets)
4629 @cindex DAP declaration
4631 Since OpenOCD version 0.11.0, the Debug Access Port (DAP) is
4632 no longer implicitly created together with the target. It must be
4633 explicitly declared using the @command{dap create} command. For all ARMv6-M, ARMv7
4634 and ARMv8 targets, the option "@option{-dap} @var{dap_name}" has to be used
4635 instead of "@option{-chain-position} @var{dotted.name}" when the target is created.
4637 The @command{dap} command group supports the following sub-commands:
4640 @deffn {Command} {dap create} dap_name @option{-chain-position} dotted.name configparams...
4641 Declare a DAP instance named @var{dap_name} linked to the JTAG tap
4642 @var{dotted.name}. This also creates a new command (@command{dap_name})
4643 which is used for various purposes including additional configuration.
4644 There can only be one DAP for each JTAG tap in the system.
4646 A DAP may also provide optional @var{configparams}:
4650 Specify that it's an ADIv5 DAP. This is the default if not specified.
4652 Specify that it's an ADIv6 DAP.
4653 @item @code{-ignore-syspwrupack}
4654 Specify this to ignore the CSYSPWRUPACK bit in the ARM DAP DP CTRL/STAT
4655 register during initial examination and when checking the sticky error bit.
4656 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
4657 devices do not set the ack bit until sometime later.
4659 @item @code{-dp-id} @var{number}
4660 @*Debug port identification number for SWD DPv2 multidrop.
4661 The @var{number} is written to bits 0..27 of DP TARGETSEL during DP selection.
4662 To find the id number of a single connected device read DP TARGETID:
4663 @code{device.dap dpreg 0x24}
4664 Use bits 0..27 of TARGETID.
4666 @item @code{-instance-id} @var{number}
4667 @*Instance identification number for SWD DPv2 multidrop.
4668 The @var{number} is written to bits 28..31 of DP TARGETSEL during DP selection.
4669 To find the instance number of a single connected device read DP DLPIDR:
4670 @code{device.dap dpreg 0x34}
4671 The instance number is in bits 28..31 of DLPIDR value.
4675 @deffn {Command} {dap names}
4676 This command returns a list of all registered DAP objects. It it useful mainly
4680 @deffn {Command} {dap info} [@var{num}|@option{root}]
4681 Displays the ROM table for MEM-AP @var{num},
4682 defaulting to the currently selected AP of the currently selected target.
4683 On ADIv5 DAP @var{num} is the numeric index of the AP.
4684 On ADIv6 DAP @var{num} is the base address of the AP.
4685 With ADIv6 only, @option{root} specifies the root ROM table.
4688 @deffn {Command} {dap init}
4689 Initialize all registered DAPs. This command is used internally
4690 during initialization. It can be issued at any time after the
4691 initialization, too.
4694 The following commands exist as subcommands of DAP instances:
4696 @deffn {Command} {$dap_name info} [@var{num}|@option{root}]
4697 Displays the ROM table for MEM-AP @var{num},
4698 defaulting to the currently selected AP.
4699 On ADIv5 DAP @var{num} is the numeric index of the AP.
4700 On ADIv6 DAP @var{num} is the base address of the AP.
4701 With ADIv6 only, @option{root} specifies the root ROM table.
4704 @deffn {Command} {$dap_name apid} [num]
4705 Displays ID register from AP @var{num}, defaulting to the currently selected AP.
4706 On ADIv5 DAP @var{num} is the numeric index of the AP.
4707 On ADIv6 DAP @var{num} is the base address of the AP.
4710 @anchor{DAP subcommand apreg}
4711 @deffn {Command} {$dap_name apreg} ap_num reg [value]
4712 Displays content of a register @var{reg} from AP @var{ap_num}
4713 or set a new value @var{value}.
4714 On ADIv5 DAP @var{ap_num} is the numeric index of the AP.
4715 On ADIv6 DAP @var{ap_num} is the base address of the AP.
4716 @var{reg} is byte address of a word register, 0, 4, 8 ... 0xfc.
4719 @deffn {Command} {$dap_name apsel} [num]
4720 Select AP @var{num}, defaulting to 0.
4721 On ADIv5 DAP @var{num} is the numeric index of the AP.
4722 On ADIv6 DAP @var{num} is the base address of the AP.
4725 @deffn {Command} {$dap_name dpreg} reg [value]
4726 Displays the content of DP register at address @var{reg}, or set it to a new
4729 In case of SWD, @var{reg} is a value in packed format
4730 @math{dpbanksel << 4 | addr} and assumes values 0, 4, 8 ... 0xfc.
4731 In case of JTAG it only assumes values 0, 4, 8 and 0xc.
4733 @emph{Note:} Consider using @command{poll off} to avoid any disturbing
4734 background activity by OpenOCD while you are operating at such low-level.
4737 @deffn {Command} {$dap_name baseaddr} [num]
4738 Displays debug base address from MEM-AP @var{num},
4739 defaulting to the currently selected AP.
4740 On ADIv5 DAP @var{num} is the numeric index of the AP.
4741 On ADIv6 DAP @var{num} is the base address of the AP.
4744 @deffn {Command} {$dap_name memaccess} [value]
4745 Displays the number of extra tck cycles in the JTAG idle to use for MEM-AP
4746 memory bus access [0-255], giving additional time to respond to reads.
4747 If @var{value} is defined, first assigns that.
4750 @deffn {Command} {$dap_name apcsw} [value [mask]]
4751 Displays or changes CSW bit pattern for MEM-AP transfers.
4753 At the begin of each memory access the CSW pattern is extended (bitwise or-ed)
4754 by @dfn{Size} and @dfn{AddrInc} bit-fields according to transfer requirements
4755 and the result is written to the real CSW register. All bits except dynamically
4756 updated fields @dfn{Size} and @dfn{AddrInc} can be changed by changing
4757 the CSW pattern. Refer to ARM ADI v5 manual chapter 7.6.4 and appendix A
4760 Use @var{value} only syntax if you want to set the new CSW pattern as a whole.
4761 The example sets HPROT1 bit (required by Cortex-M) and clears the rest of
4764 kx.dap apcsw 0x2000000
4767 If @var{mask} is also used, the CSW pattern is changed only on bit positions
4768 where the mask bit is 1. The following example sets HPROT3 (cacheable)
4769 and leaves the rest of the pattern intact. It configures memory access through
4770 DCache on Cortex-M7.
4772 set CSW_HPROT3_CACHEABLE [expr @{1 << 27@}]
4773 samv.dap apcsw $CSW_HPROT3_CACHEABLE $CSW_HPROT3_CACHEABLE
4776 Another example clears SPROT bit and leaves the rest of pattern intact:
4778 set CSW_SPROT [expr @{1 << 30@}]
4779 samv.dap apcsw 0 $CSW_SPROT
4782 @emph{Note:} If you want to check the real value of CSW, not CSW pattern, use
4783 @code{xxx.dap apreg 0}. @xref{DAP subcommand apreg,,}.
4785 @emph{Warning:} Some of the CSW bits are vital for working memory transfer.
4786 If you set a wrong CSW pattern and MEM-AP stopped working, use the following
4787 example with a proper dap name:
4789 xxx.dap apcsw default
4793 @deffn {Config Command} {$dap_name ti_be_32_quirks} [@option{enable}]
4794 Set/get quirks mode for TI TMS450/TMS570 processors
4799 @node CPU Configuration
4800 @chapter CPU Configuration
4803 This chapter discusses how to set up GDB debug targets for CPUs.
4804 You can also access these targets without GDB
4805 (@pxref{Architecture and Core Commands},
4806 and @ref{targetstatehandling,,Target State handling}) and
4807 through various kinds of NAND and NOR flash commands.
4808 If you have multiple CPUs you can have multiple such targets.
4810 We'll start by looking at how to examine the targets you have,
4811 then look at how to add one more target and how to configure it.
4813 @section Target List
4814 @cindex target, current
4815 @cindex target, list
4817 All targets that have been set up are part of a list,
4818 where each member has a name.
4819 That name should normally be the same as the TAP name.
4820 You can display the list with the @command{targets}
4822 This display often has only one CPU; here's what it might
4823 look like with more than one:
4825 TargetName Type Endian TapName State
4826 -- ------------------ ---------- ------ ------------------ ------------
4827 0* at91rm9200.cpu arm920t little at91rm9200.cpu running
4828 1 MyTarget cortex_m little mychip.foo tap-disabled
4831 One member of that list is the @dfn{current target}, which
4832 is implicitly referenced by many commands.
4833 It's the one marked with a @code{*} near the target name.
4834 In particular, memory addresses often refer to the address
4835 space seen by that current target.
4836 Commands like @command{mdw} (memory display words)
4837 and @command{flash erase_address} (erase NOR flash blocks)
4838 are examples; and there are many more.
4840 Several commands let you examine the list of targets:
4842 @deffn {Command} {target current}
4843 Returns the name of the current target.
4846 @deffn {Command} {target names}
4847 Lists the names of all current targets in the list.
4849 foreach t [target names] @{
4850 puts [format "Target: %s\n" $t]
4855 @c yep, "target list" would have been better.
4856 @c plus maybe "target setdefault".
4858 @deffn {Command} {targets} [name]
4859 @emph{Note: the name of this command is plural. Other target
4860 command names are singular.}
4862 With no parameter, this command displays a table of all known
4863 targets in a user friendly form.
4865 With a parameter, this command sets the current target to
4866 the given target with the given @var{name}; this is
4867 only relevant on boards which have more than one target.
4870 @section Target CPU Types
4874 Each target has a @dfn{CPU type}, as shown in the output of
4875 the @command{targets} command. You need to specify that type
4876 when calling @command{target create}.
4877 The CPU type indicates more than just the instruction set.
4878 It also indicates how that instruction set is implemented,
4879 what kind of debug support it integrates,
4880 whether it has an MMU (and if so, what kind),
4881 what core-specific commands may be available
4882 (@pxref{Architecture and Core Commands}),
4885 It's easy to see what target types are supported,
4886 since there's a command to list them.
4888 @anchor{targettypes}
4889 @deffn {Command} {target types}
4890 Lists all supported target types.
4891 At this writing, the supported CPU types are:
4894 @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
4895 @item @code{arm11} -- this is a generation of ARMv6 cores.
4896 @item @code{arm720t} -- this is an ARMv4 core with an MMU.
4897 @item @code{arm7tdmi} -- this is an ARMv4 core.
4898 @item @code{arm920t} -- this is an ARMv4 core with an MMU.
4899 @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
4900 @item @code{arm946e} -- this is an ARMv5 core with an MMU.
4901 @item @code{arm966e} -- this is an ARMv5 core.
4902 @item @code{arm9tdmi} -- this is an ARMv4 core.
4903 @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
4904 (Support for this is preliminary and incomplete.)
4905 @item @code{avr32_ap7k} -- this an AVR32 core.
4906 @item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
4907 @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
4908 compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
4909 @item @code{cortex_r4} -- this is an ARMv7-R core.
4910 @item @code{dragonite} -- resembles arm966e.
4911 @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
4912 (Support for this is still incomplete.)
4913 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
4914 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
4915 The current implementation supports eSi-32xx cores.
4916 @item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
4917 @item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
4918 @item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
4919 @item @code{fa526} -- resembles arm920 (w/o Thumb).
4920 @item @code{feroceon} -- resembles arm926.
4921 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
4922 @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
4923 allowing access to physical memory addresses independently of CPU cores.
4924 @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without
4925 a CPU, through which bus read and write cycles can be generated; it may be
4926 useful for working with non-CPU hardware behind an AP or during development of
4927 support for new CPUs.
4928 It's possible to connect a GDB client to this target (the GDB port has to be
4929 specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
4930 be emulated to comply to GDB remote protocol.
4931 @item @code{mips_m4k} -- a MIPS core.
4932 @item @code{mips_mips64} -- a MIPS64 core.
4933 @item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
4934 @item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
4935 @item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
4936 @item @code{or1k} -- this is an OpenRISC 1000 core.
4937 The current implementation supports three JTAG TAP cores:
4939 @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag})
4940 @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
4941 @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf})
4943 And two debug interfaces cores:
4945 @item @code{Advanced debug interface}
4946 @*(See: @url{http://opencores.org/project@comma{}adv_debug_sys})
4947 @item @code{SoC Debug Interface}
4948 @*(See: @url{http://opencores.org/project@comma{}dbg_interface})
4950 @item @code{quark_d20xx} -- an Intel Quark D20xx core.
4951 @item @code{quark_x10xx} -- an Intel Quark X10xx core.
4952 @item @code{riscv} -- a RISC-V core.
4953 @item @code{stm8} -- implements an STM8 core.
4954 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
4955 @item @code{xscale} -- this is actually an architecture,
4956 not a CPU type. It is based on the ARMv5 architecture.
4960 To avoid being confused by the variety of ARM based cores, remember
4961 this key point: @emph{ARM is a technology licencing company}.
4962 (See: @url{http://www.arm.com}.)
4963 The CPU name used by OpenOCD will reflect the CPU design that was
4964 licensed, not a vendor brand which incorporates that design.
4965 Name prefixes like arm7, arm9, arm11, and cortex
4966 reflect design generations;
4967 while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8
4968 reflect an architecture version implemented by a CPU design.
4970 @anchor{targetconfiguration}
4971 @section Target Configuration
4973 Before creating a ``target'', you must have added its TAP to the scan chain.
4974 When you've added that TAP, you will have a @code{dotted.name}
4975 which is used to set up the CPU support.
4976 The chip-specific configuration file will normally configure its CPU(s)
4977 right after it adds all of the chip's TAPs to the scan chain.
4979 Although you can set up a target in one step, it's often clearer if you
4980 use shorter commands and do it in two steps: create it, then configure
4982 All operations on the target after it's created will use a new
4983 command, created as part of target creation.
4985 The two main things to configure after target creation are
4986 a work area, which usually has target-specific defaults even
4987 if the board setup code overrides them later;
4988 and event handlers (@pxref{targetevents,,Target Events}), which tend
4989 to be much more board-specific.
4990 The key steps you use might look something like this
4993 dap create mychip.dap -chain-position mychip.cpu
4994 target create MyTarget cortex_m -dap mychip.dap
4995 MyTarget configure -work-area-phys 0x08000 -work-area-size 8096
4996 MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}
4997 MyTarget configure -event reset-init @{ myboard_reinit @}
5000 You should specify a working area if you can; typically it uses some
5002 Such a working area can speed up many things, including bulk
5003 writes to target memory;
5004 flash operations like checking to see if memory needs to be erased;
5005 GDB memory checksumming;
5009 On more complex chips, the work area can become
5010 inaccessible when application code
5011 (such as an operating system)
5012 enables or disables the MMU.
5013 For example, the particular MMU context used to access the virtual
5014 address will probably matter ... and that context might not have
5015 easy access to other addresses needed.
5016 At this writing, OpenOCD doesn't have much MMU intelligence.
5019 It's often very useful to define a @code{reset-init} event handler.
5020 For systems that are normally used with a boot loader,
5021 common tasks include updating clocks and initializing memory
5023 That may be needed to let you write the boot loader into flash,
5024 in order to ``de-brick'' your board; or to load programs into
5025 external DDR memory without having run the boot loader.
5027 @deffn {Config Command} {target create} target_name type configparams...
5028 This command creates a GDB debug target that refers to a specific JTAG tap.
5029 It enters that target into a list, and creates a new
5030 command (@command{@var{target_name}}) which is used for various
5031 purposes including additional configuration.
5034 @item @var{target_name} ... is the name of the debug target.
5035 By convention this should be the same as the @emph{dotted.name}
5036 of the TAP associated with this target, which must be specified here
5037 using the @code{-chain-position @var{dotted.name}} configparam.
5039 This name is also used to create the target object command,
5040 referred to here as @command{$target_name},
5041 and in other places the target needs to be identified.
5042 @item @var{type} ... specifies the target type. @xref{targettypes,,target types}.
5043 @item @var{configparams} ... all parameters accepted by
5044 @command{$target_name configure} are permitted.
5045 If the target is big-endian, set it here with @code{-endian big}.
5047 You @emph{must} set the @code{-chain-position @var{dotted.name}} or
5048 @code{-dap @var{dap_name}} here.
5052 @deffn {Command} {$target_name configure} configparams...
5053 The options accepted by this command may also be
5054 specified as parameters to @command{target create}.
5055 Their values can later be queried one at a time by
5056 using the @command{$target_name cget} command.
5058 @emph{Warning:} changing some of these after setup is dangerous.
5059 For example, moving a target from one TAP to another;
5060 and changing its endianness.
5064 @item @code{-chain-position} @var{dotted.name} -- names the TAP
5065 used to access this target.
5067 @item @code{-dap} @var{dap_name} -- names the DAP used to access
5068 this target. @xref{dapdeclaration,,DAP declaration}, on how to
5069 create and manage DAP instances.
5071 @item @code{-endian} (@option{big}|@option{little}) -- specifies
5072 whether the CPU uses big or little endian conventions
5074 @item @code{-event} @var{event_name} @var{event_body} --
5075 @xref{targetevents,,Target Events}.
5076 Note that this updates a list of named event handlers.
5077 Calling this twice with two different event names assigns
5078 two different handlers, but calling it twice with the
5079 same event name assigns only one handler.
5081 Current target is temporarily overridden to the event issuing target
5082 before handler code starts and switched back after handler is done.
5084 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
5085 whether the work area gets backed up; by default,
5086 @emph{it is not backed up.}
5087 When possible, use a working_area that doesn't need to be backed up,
5088 since performing a backup slows down operations.
5089 For example, the beginning of an SRAM block is likely to
5090 be used by most build systems, but the end is often unused.
5092 @item @code{-work-area-size} @var{size} -- specify work are size,
5093 in bytes. The same size applies regardless of whether its physical
5094 or virtual address is being used.
5096 @item @code{-work-area-phys} @var{address} -- set the work area
5097 base @var{address} to be used when no MMU is active.
5099 @item @code{-work-area-virt} @var{address} -- set the work area
5100 base @var{address} to be used when an MMU is active.
5101 @emph{Do not specify a value for this except on targets with an MMU.}
5102 The value should normally correspond to a static mapping for the
5103 @code{-work-area-phys} address, set up by the current operating system.
5106 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
5107 @var{rtos_type} can be one of @option{auto}, @option{eCos},
5108 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
5109 @option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
5110 @option{RIOT}, @option{Zephyr}
5111 @xref{gdbrtossupport,,RTOS Support}.
5113 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
5114 scan and after a reset. A manual call to arp_examine is required to
5115 access the target for debugging.
5117 @item @code{-ap-num} @var{ap_number} -- set DAP access port for target.
5118 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the target is connected to.
5119 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the target is connected to.
5120 Use this option with systems where multiple, independent cores are connected
5121 to separate access ports of the same DAP.
5123 @item @code{-cti} @var{cti_name} -- set Cross-Trigger Interface (CTI) connected
5124 to the target. Currently, only the @code{aarch64} target makes use of this option,
5125 where it is a mandatory configuration for the target run control.
5126 @xref{armcrosstrigger,,ARM Cross-Trigger Interface},
5127 for instruction on how to declare and control a CTI instance.
5129 @anchor{gdbportoverride}
5130 @item @code{-gdb-port} @var{number} -- see command @command{gdb_port} for the
5131 possible values of the parameter @var{number}, which are not only numeric values.
5132 Use this option to override, for this target only, the global parameter set with
5133 command @command{gdb_port}.
5134 @xref{gdb_port,,command gdb_port}.
5136 @item @code{-gdb-max-connections} @var{number} -- EXPERIMENTAL: set the maximum
5137 number of GDB connections that are allowed for the target. Default is 1.
5138 A negative value for @var{number} means unlimited connections.
5139 See @xref{gdbmeminspect,,Using GDB as a non-intrusive memory inspector}.
5143 @section Other $target_name Commands
5144 @cindex object command
5146 The Tcl/Tk language has the concept of object commands,
5147 and OpenOCD adopts that same model for targets.
5149 A good Tk example is a on screen button.
5150 Once a button is created a button
5151 has a name (a path in Tk terms) and that name is useable as a first
5152 class command. For example in Tk, one can create a button and later
5153 configure it like this:
5157 button .foobar -background red -command @{ foo @}
5159 .foobar configure -foreground blue
5161 set x [.foobar cget -background]
5163 puts [format "The button is %s" $x]
5166 In OpenOCD's terms, the ``target'' is an object just like a Tcl/Tk
5167 button, and its object commands are invoked the same way.
5170 str912.cpu mww 0x1234 0x42
5171 omap3530.cpu mww 0x5555 123
5174 The commands supported by OpenOCD target objects are:
5176 @deffn {Command} {$target_name arp_examine} @option{allow-defer}
5177 @deffnx {Command} {$target_name arp_halt}
5178 @deffnx {Command} {$target_name arp_poll}
5179 @deffnx {Command} {$target_name arp_reset}
5180 @deffnx {Command} {$target_name arp_waitstate}
5181 Internal OpenOCD scripts (most notably @file{startup.tcl})
5182 use these to deal with specific reset cases.
5183 They are not otherwise documented here.
5186 @deffn {Command} {$target_name set_reg} dict
5187 Set register values of the target.
5190 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
5193 For example, the following command sets the value 0 to the program counter (pc)
5194 register and 0x1000 to the stack pointer (sp) register:
5197 set_reg @{pc 0 sp 0x1000@}
5201 @deffn {Command} {$target_name get_reg} [-force] list
5202 Get register values from the target and return them as Tcl dictionary with pairs
5203 of register names and values.
5204 If option "-force" is set, the register values are read directly from the
5205 target, bypassing any caching.
5208 @item @var{list} ... List of register names
5211 For example, the following command retrieves the values from the program
5212 counter (pc) and stack pointer (sp) register:
5219 @deffn {Command} {$target_name write_memory} address width data ['phys']
5220 This function provides an efficient way to write to the target memory from a Tcl
5224 @item @var{address} ... target memory address
5225 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5226 @item @var{data} ... Tcl list with the elements to write
5227 @item ['phys'] ... treat the memory address as physical instead of virtual address
5230 For example, the following command writes two 32 bit words into the target
5231 memory at address 0x20000000:
5234 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
5238 @deffn {Command} {$target_name read_memory} address width count ['phys']
5239 This function provides an efficient way to read the target memory from a Tcl
5241 A Tcl list containing the requested memory elements is returned by this function.
5244 @item @var{address} ... target memory address
5245 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
5246 @item @var{count} ... number of elements to read
5247 @item ['phys'] ... treat the memory address as physical instead of virtual address
5250 For example, the following command reads two 32 bit words from the target
5251 memory at address 0x20000000:
5254 read_memory 0x20000000 32 2
5258 @deffn {Command} {$target_name cget} queryparm
5259 Each configuration parameter accepted by
5260 @command{$target_name configure}
5261 can be individually queried, to return its current value.
5262 The @var{queryparm} is a parameter name
5263 accepted by that command, such as @code{-work-area-phys}.
5264 There are a few special cases:
5267 @item @code{-event} @var{event_name} -- returns the handler for the
5268 event named @var{event_name}.
5269 This is a special case because setting a handler requires
5271 @item @code{-type} -- returns the target type.
5272 This is a special case because this is set using
5273 @command{target create} and can't be changed
5274 using @command{$target_name configure}.
5277 For example, if you wanted to summarize information about
5278 all the targets you might use something like this:
5281 foreach name [target names] @{
5282 set y [$name cget -endian]
5283 set z [$name cget -type]
5284 puts [format "Chip %d is %s, Endian: %s, type: %s" \
5290 @anchor{targetcurstate}
5291 @deffn {Command} {$target_name curstate}
5292 Displays the current target state:
5293 @code{debug-running},
5296 @code{running}, or @code{unknown}.
5297 (Also, @pxref{eventpolling,,Event Polling}.)
5300 @deffn {Command} {$target_name eventlist}
5301 Displays a table listing all event handlers
5302 currently associated with this target.
5303 @xref{targetevents,,Target Events}.
5306 @deffn {Command} {$target_name invoke-event} event_name
5307 Invokes the handler for the event named @var{event_name}.
5308 (This is primarily intended for use by OpenOCD framework
5309 code, for example by the reset code in @file{startup.tcl}.)
5312 @deffn {Command} {$target_name mdd} [phys] addr [count]
5313 @deffnx {Command} {$target_name mdw} [phys] addr [count]
5314 @deffnx {Command} {$target_name mdh} [phys] addr [count]
5315 @deffnx {Command} {$target_name mdb} [phys] addr [count]
5316 Display contents of address @var{addr}, as
5317 64-bit doublewords (@command{mdd}),
5318 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5319 or 8-bit bytes (@command{mdb}).
5320 When the current target has an MMU which is present and active,
5321 @var{addr} is interpreted as a virtual address.
5322 Otherwise, or if the optional @var{phys} flag is specified,
5323 @var{addr} is interpreted as a physical address.
5324 If @var{count} is specified, displays that many units.
5325 (If you want to process the data instead of displaying it,
5326 see the @code{read_memory} primitives.)
5329 @deffn {Command} {$target_name mwd} [phys] addr doubleword [count]
5330 @deffnx {Command} {$target_name mww} [phys] addr word [count]
5331 @deffnx {Command} {$target_name mwh} [phys] addr halfword [count]
5332 @deffnx {Command} {$target_name mwb} [phys] addr byte [count]
5333 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
5334 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
5335 at the specified address @var{addr}.
5336 When the current target has an MMU which is present and active,
5337 @var{addr} is interpreted as a virtual address.
5338 Otherwise, or if the optional @var{phys} flag is specified,
5339 @var{addr} is interpreted as a physical address.
5340 If @var{count} is specified, fills that many units of consecutive address.
5343 @anchor{targetevents}
5344 @section Target Events
5345 @cindex target events
5347 At various times, certain things can happen, or you want them to happen.
5350 @item What should happen when GDB connects? Should your target reset?
5351 @item When GDB tries to flash the target, do you need to enable the flash via a special command?
5352 @item Is using SRST appropriate (and possible) on your system?
5353 Or instead of that, do you need to issue JTAG commands to trigger reset?
5354 SRST usually resets everything on the scan chain, which can be inappropriate.
5355 @item During reset, do you need to write to certain memory locations
5356 to set up system clocks or
5357 to reconfigure the SDRAM?
5358 How about configuring the watchdog timer, or other peripherals,
5359 to stop running while you hold the core stopped for debugging?
5362 All of the above items can be addressed by target event handlers.
5363 These are set up by @command{$target_name configure -event} or
5364 @command{target create ... -event}.
5366 The programmer's model matches the @code{-command} option used in Tcl/Tk
5367 buttons and events. The two examples below act the same, but one creates
5368 and invokes a small procedure while the other inlines it.
5371 proc my_init_proc @{ @} @{
5372 echo "Disabling watchdog..."
5373 mww 0xfffffd44 0x00008000
5375 mychip.cpu configure -event reset-init my_init_proc
5376 mychip.cpu configure -event reset-init @{
5377 echo "Disabling watchdog..."
5378 mww 0xfffffd44 0x00008000
5382 The following target events are defined:
5385 @item @b{debug-halted}
5386 @* The target has halted for debug reasons (i.e.: breakpoint)
5387 @item @b{debug-resumed}
5388 @* The target has resumed (i.e.: GDB said run)
5389 @item @b{early-halted}
5390 @* Occurs early in the halt process
5391 @item @b{examine-start}
5392 @* Before target examine is called.
5393 @item @b{examine-end}
5394 @* After target examine is called with no errors.
5395 @item @b{examine-fail}
5396 @* After target examine fails.
5397 @item @b{gdb-attach}
5398 @* When GDB connects. Issued before any GDB communication with the target
5399 starts. GDB expects the target is halted during attachment.
5400 @xref{gdbmeminspect,,GDB as a non-intrusive memory inspector}, how to
5401 connect GDB to running target.
5402 The event can be also used to set up the target so it is possible to probe flash.
5403 Probing flash is necessary during GDB connect if you want to use
5404 @pxref{programmingusinggdb,,programming using GDB}.
5405 Another use of the flash memory map is for GDB to automatically choose
5406 hardware or software breakpoints depending on whether the breakpoint
5407 is in RAM or read only memory.
5408 Default is @code{halt}
5409 @item @b{gdb-detach}
5410 @* When GDB disconnects
5412 @* When the target has halted and GDB is not doing anything (see early halt)
5413 @item @b{gdb-flash-erase-start}
5414 @* Before the GDB flash process tries to erase the flash (default is
5416 @item @b{gdb-flash-erase-end}
5417 @* After the GDB flash process has finished erasing the flash
5418 @item @b{gdb-flash-write-start}
5419 @* Before GDB writes to the flash
5420 @item @b{gdb-flash-write-end}
5421 @* After GDB writes to the flash (default is @code{reset halt})
5423 @* Before the target steps, GDB is trying to start/resume the target
5425 @* The target has halted
5426 @item @b{reset-assert-pre}
5427 @* Issued as part of @command{reset} processing
5428 after @command{reset-start} was triggered
5429 but before either SRST alone is asserted on the scan chain,
5430 or @code{reset-assert} is triggered.
5431 @item @b{reset-assert}
5432 @* Issued as part of @command{reset} processing
5433 after @command{reset-assert-pre} was triggered.
5434 When such a handler is present, cores which support this event will use
5435 it instead of asserting SRST.
5436 This support is essential for debugging with JTAG interfaces which
5437 don't include an SRST line (JTAG doesn't require SRST), and for
5438 selective reset on scan chains that have multiple targets.
5439 @item @b{reset-assert-post}
5440 @* Issued as part of @command{reset} processing
5441 after @code{reset-assert} has been triggered.
5442 or the target asserted SRST on the entire scan chain.
5443 @item @b{reset-deassert-pre}
5444 @* Issued as part of @command{reset} processing
5445 after @code{reset-assert-post} has been triggered.
5446 @item @b{reset-deassert-post}
5447 @* Issued as part of @command{reset} processing
5448 after @code{reset-deassert-pre} has been triggered
5449 and (if the target is using it) after SRST has been
5450 released on the scan chain.
5452 @* Issued as the final step in @command{reset} processing.
5453 @item @b{reset-init}
5454 @* Used by @b{reset init} command for board-specific initialization.
5455 This event fires after @emph{reset-deassert-post}.
5457 This is where you would configure PLLs and clocking, set up DRAM so
5458 you can download programs that don't fit in on-chip SRAM, set up pin
5459 multiplexing, and so on.
5460 (You may be able to switch to a fast JTAG clock rate here, after
5461 the target clocks are fully set up.)
5462 @item @b{reset-start}
5463 @* Issued as the first step in @command{reset} processing
5464 before @command{reset-assert-pre} is called.
5466 This is the most robust place to use @command{jtag_rclk}
5467 or @command{adapter speed} to switch to a low JTAG clock rate,
5468 when reset disables PLLs needed to use a fast clock.
5469 @item @b{resume-start}
5470 @* Before any target is resumed
5471 @item @b{resume-end}
5472 @* After all targets have resumed
5474 @* Target has resumed
5475 @item @b{step-start}
5476 @* Before a target is single-stepped
5478 @* After single-step has completed
5479 @item @b{trace-config}
5480 @* After target hardware trace configuration was changed
5481 @item @b{semihosting-user-cmd-0x100}
5482 @* The target made a semihosting call with user-defined operation number 0x100
5483 @item @b{semihosting-user-cmd-0x101}
5484 @* The target made a semihosting call with user-defined operation number 0x101
5485 @item @b{semihosting-user-cmd-0x102}
5486 @* The target made a semihosting call with user-defined operation number 0x102
5487 @item @b{semihosting-user-cmd-0x103}
5488 @* The target made a semihosting call with user-defined operation number 0x103
5489 @item @b{semihosting-user-cmd-0x104}
5490 @* The target made a semihosting call with user-defined operation number 0x104
5491 @item @b{semihosting-user-cmd-0x105}
5492 @* The target made a semihosting call with user-defined operation number 0x105
5493 @item @b{semihosting-user-cmd-0x106}
5494 @* The target made a semihosting call with user-defined operation number 0x106
5495 @item @b{semihosting-user-cmd-0x107}
5496 @* The target made a semihosting call with user-defined operation number 0x107
5500 OpenOCD events are not supposed to be preempt by another event, but this
5501 is not enforced in current code. Only the target event @b{resumed} is
5502 executed with polling disabled; this avoids polling to trigger the event
5503 @b{halted}, reversing the logical order of execution of their handlers.
5504 Future versions of OpenOCD will prevent the event preemption and will
5505 disable the schedule of polling during the event execution. Do not rely
5506 on polling in any event handler; this means, don't expect the status of
5507 a core to change during the execution of the handler. The event handler
5508 will have to enable polling or use @command{$target_name arp_poll} to
5509 check if the core has changed status.
5512 @node Flash Commands
5513 @chapter Flash Commands
5515 OpenOCD has different commands for NOR and NAND flash;
5516 the ``flash'' command works with NOR flash, while
5517 the ``nand'' command works with NAND flash.
5518 This partially reflects different hardware technologies:
5519 NOR flash usually supports direct CPU instruction and data bus access,
5520 while data from a NAND flash must be copied to memory before it can be
5521 used. (SPI flash must also be copied to memory before use.)
5522 However, the documentation also uses ``flash'' as a generic term;
5523 for example, ``Put flash configuration in board-specific files''.
5527 @item Configure via the command @command{flash bank}
5528 @* Do this in a board-specific configuration file,
5529 passing parameters as needed by the driver.
5530 @item Operate on the flash via @command{flash subcommand}
5531 @* Often commands to manipulate the flash are typed by a human, or run
5532 via a script in some automated way. Common tasks include writing a
5533 boot loader, operating system, or other data.
5535 @* Flashing via GDB requires the flash be configured via ``flash
5536 bank'', and the GDB flash features be enabled.
5537 @xref{gdbconfiguration,,GDB Configuration}.
5540 Many CPUs have the ability to ``boot'' from the first flash bank.
5541 This means that misprogramming that bank can ``brick'' a system,
5542 so that it can't boot.
5543 JTAG tools, like OpenOCD, are often then used to ``de-brick'' the
5544 board by (re)installing working boot firmware.
5546 @anchor{norconfiguration}
5547 @section Flash Configuration Commands
5548 @cindex flash configuration
5550 @deffn {Config Command} {flash bank} name driver base size chip_width bus_width target [driver_options]
5551 Configures a flash bank which provides persistent storage
5552 for addresses from @math{base} to @math{base + size - 1}.
5553 These banks will often be visible to GDB through the target's memory map.
5554 In some cases, configuring a flash bank will activate extra commands;
5555 see the driver-specific documentation.
5558 @item @var{name} ... may be used to reference the flash bank
5559 in other flash commands. A number is also available.
5560 @item @var{driver} ... identifies the controller driver
5561 associated with the flash bank being declared.
5562 This is usually @code{cfi} for external flash, or else
5563 the name of a microcontroller with embedded flash memory.
5564 @xref{flashdriverlist,,Flash Driver List}.
5565 @item @var{base} ... Base address of the flash chip.
5566 @item @var{size} ... Size of the chip, in bytes.
5567 For some drivers, this value is detected from the hardware.
5568 @item @var{chip_width} ... Width of the flash chip, in bytes;
5569 ignored for most microcontroller drivers.
5570 @item @var{bus_width} ... Width of the data bus used to access the
5571 chip, in bytes; ignored for most microcontroller drivers.
5572 @item @var{target} ... Names the target used to issue
5573 commands to the flash controller.
5574 @comment Actually, it's currently a controller-specific parameter...
5575 @item @var{driver_options} ... drivers may support, or require,
5576 additional parameters. See the driver-specific documentation
5577 for more information.
5580 This command is not available after OpenOCD initialization has completed.
5581 Use it in board specific configuration files, not interactively.
5585 @comment less confusing would be: "flash list" (like "nand list")
5586 @deffn {Command} {flash banks}
5587 Prints a one-line summary of each device that was
5588 declared using @command{flash bank}, numbered from zero.
5589 Note that this is the @emph{plural} form;
5590 the @emph{singular} form is a very different command.
5593 @deffn {Command} {flash list}
5594 Retrieves a list of associative arrays for each device that was
5595 declared using @command{flash bank}, numbered from zero.
5596 This returned list can be manipulated easily from within scripts.
5599 @deffn {Command} {flash probe} num
5600 Identify the flash, or validate the parameters of the configured flash. Operation
5601 depends on the flash type.
5602 The @var{num} parameter is a value shown by @command{flash banks}.
5603 Most flash commands will implicitly @emph{autoprobe} the bank;
5604 flash drivers can distinguish between probing and autoprobing,
5605 but most don't bother.
5608 @section Preparing a Target before Flash Programming
5610 The target device should be in well defined state before the flash programming
5613 @emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}.
5614 Do not issue another @command{reset} or @command{reset halt} or @command{resume}
5615 until the programming session is finished.
5617 If you use @ref{programmingusinggdb,,Programming using GDB},
5618 the target is prepared automatically in the event gdb-flash-erase-start
5620 The jimtcl script @command{program} calls @command{reset init} explicitly.
5622 @section Erasing, Reading, Writing to Flash
5623 @cindex flash erasing
5624 @cindex flash reading
5625 @cindex flash writing
5626 @cindex flash programming
5627 @anchor{flashprogrammingcommands}
5629 One feature distinguishing NOR flash from NAND or serial flash technologies
5630 is that for read access, it acts exactly like any other addressable memory.
5631 This means you can use normal memory read commands like @command{mdw} or
5632 @command{dump_image} with it, with no special @command{flash} subcommands.
5633 @xref{memoryaccess,,Memory access}, and @ref{imageaccess,,Image access}.
5635 Write access works differently. Flash memory normally needs to be erased
5636 before it's written. Erasing a sector turns all of its bits to ones, and
5637 writing can turn ones into zeroes. This is why there are special commands
5638 for interactive erasing and writing, and why GDB needs to know which parts
5639 of the address space hold NOR flash memory.
5642 Most of these erase and write commands leverage the fact that NOR flash
5643 chips consume target address space. They implicitly refer to the current
5644 JTAG target, and map from an address in that target's address space
5645 back to a flash bank.
5646 @comment In May 2009, those mappings may fail if any bank associated
5647 @comment with that target doesn't successfully autoprobe ... bug worth fixing?
5648 A few commands use abstract addressing based on bank and sector numbers,
5649 and don't depend on searching the current target and its address space.
5650 Avoid confusing the two command models.
5653 Some flash chips implement software protection against accidental writes,
5654 since such buggy writes could in some cases ``brick'' a system.
5655 For such systems, erasing and writing may require sector protection to be
5657 Examples include CFI flash such as ``Intel Advanced Bootblock flash'',
5658 and AT91SAM7 on-chip flash.
5659 @xref{flashprotect,,flash protect}.
5661 @deffn {Command} {flash erase_sector} num first last
5662 Erase sectors in bank @var{num}, starting at sector @var{first}
5663 up to and including @var{last}.
5664 Sector numbering starts at 0.
5665 Providing a @var{last} sector of @option{last}
5666 specifies "to the end of the flash bank".
5667 The @var{num} parameter is a value shown by @command{flash banks}.
5670 @deffn {Command} {flash erase_address} [@option{pad}] [@option{unlock}] address length
5671 Erase sectors starting at @var{address} for @var{length} bytes.
5672 Unless @option{pad} is specified, @math{address} must begin a
5673 flash sector, and @math{address + length - 1} must end a sector.
5674 Specifying @option{pad} erases extra data at the beginning and/or
5675 end of the specified region, as needed to erase only full sectors.
5676 The flash bank to use is inferred from the @var{address}, and
5677 the specified length must stay within that bank.
5678 As a special case, when @var{length} is zero and @var{address} is
5679 the start of the bank, the whole flash is erased.
5680 If @option{unlock} is specified, then the flash is unprotected
5681 before erase starts.
5684 @deffn {Command} {flash filld} address double-word length
5685 @deffnx {Command} {flash fillw} address word length
5686 @deffnx {Command} {flash fillh} address halfword length
5687 @deffnx {Command} {flash fillb} address byte length
5688 Fills flash memory with the specified @var{double-word} (64 bits), @var{word} (32 bits),
5689 @var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
5690 starting at @var{address} and continuing
5691 for @var{length} units (word/halfword/byte).
5692 No erasure is done before writing; when needed, that must be done
5693 before issuing this command.
5694 Writes are done in blocks of up to 1024 bytes, and each write is
5695 verified by reading back the data and comparing it to what was written.
5696 The flash bank to use is inferred from the @var{address} of
5697 each block, and the specified length must stay within that bank.
5699 @comment no current checks for errors if fill blocks touch multiple banks!
5701 @deffn {Command} {flash mdw} addr [count]
5702 @deffnx {Command} {flash mdh} addr [count]
5703 @deffnx {Command} {flash mdb} addr [count]
5704 Display contents of address @var{addr}, as
5705 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
5706 or 8-bit bytes (@command{mdb}).
5707 If @var{count} is specified, displays that many units.
5708 Reads from flash using the flash driver, therefore it enables reading
5709 from a bank not mapped in target address space.
5710 The flash bank to use is inferred from the @var{address} of
5711 each block, and the specified length must stay within that bank.
5714 @deffn {Command} {flash write_bank} num filename [offset]
5715 Write the binary @file{filename} to flash bank @var{num},
5716 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
5717 is omitted, start at the beginning of the flash bank.
5718 The @var{num} parameter is a value shown by @command{flash banks}.
5721 @deffn {Command} {flash read_bank} num filename [offset [length]]
5722 Read @var{length} bytes from the flash bank @var{num} starting at @var{offset}
5723 and write the contents to the binary @file{filename}. If @var{offset} is
5724 omitted, start at the beginning of the flash bank. If @var{length} is omitted,
5725 read the remaining bytes from the flash bank.
5726 The @var{num} parameter is a value shown by @command{flash banks}.
5729 @deffn {Command} {flash verify_bank} num filename [offset]
5730 Compare the contents of the binary file @var{filename} with the contents of the
5731 flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted,
5732 start at the beginning of the flash bank. Fail if the contents do not match.
5733 The @var{num} parameter is a value shown by @command{flash banks}.
5736 @deffn {Command} {flash write_image} [erase] [unlock] filename [offset] [type]
5737 Write the image @file{filename} to the current target's flash bank(s).
5738 Only loadable sections from the image are written.
5739 A relocation @var{offset} may be specified, in which case it is added
5740 to the base address for each section in the image.
5741 The file [@var{type}] can be specified
5742 explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
5743 @option{elf} (ELF file), @option{s19} (Motorola s19).
5744 @option{mem}, or @option{builder}.
5745 The relevant flash sectors will be erased prior to programming
5746 if the @option{erase} parameter is given. If @option{unlock} is
5747 provided, then the flash banks are unlocked before erase and
5748 program. The flash bank to use is inferred from the address of
5752 Be careful using the @option{erase} flag when the flash is holding
5753 data you want to preserve.
5754 Portions of the flash outside those described in the image's
5755 sections might be erased with no notice.
5758 When a section of the image being written does not fill out all the
5759 sectors it uses, the unwritten parts of those sectors are necessarily
5760 also erased, because sectors can't be partially erased.
5762 Data stored in sector "holes" between image sections are also affected.
5763 For example, "@command{flash write_image erase ...}" of an image with
5764 one byte at the beginning of a flash bank and one byte at the end
5765 erases the entire bank -- not just the two sectors being written.
5767 Also, when flash protection is important, you must re-apply it after
5768 it has been removed by the @option{unlock} flag.
5773 @deffn {Command} {flash verify_image} filename [offset] [type]
5774 Verify the image @file{filename} to the current target's flash bank(s).
5775 Parameters follow the description of 'flash write_image'.
5776 In contrast to the 'verify_image' command, for banks with specific
5777 verify method, that one is used instead of the usual target's read
5778 memory methods. This is necessary for flash banks not readable by
5779 ordinary memory reads.
5780 This command gives only an overall good/bad result for each bank, not
5781 addresses of individual failed bytes as it's intended only as quick
5782 check for successful programming.
5785 @section Other Flash commands
5786 @cindex flash protection
5788 @deffn {Command} {flash erase_check} num
5789 Check erase state of sectors in flash bank @var{num},
5790 and display that status.
5791 The @var{num} parameter is a value shown by @command{flash banks}.
5794 @deffn {Command} {flash info} num [sectors]
5795 Print info about flash bank @var{num}, a list of protection blocks
5796 and their status. Use @option{sectors} to show a list of sectors instead.
5798 The @var{num} parameter is a value shown by @command{flash banks}.
5799 This command will first query the hardware, it does not print cached
5800 and possibly stale information.
5803 @anchor{flashprotect}
5804 @deffn {Command} {flash protect} num first last (@option{on}|@option{off})
5805 Enable (@option{on}) or disable (@option{off}) protection of flash blocks
5806 in flash bank @var{num}, starting at protection block @var{first}
5807 and continuing up to and including @var{last}.
5808 Providing a @var{last} block of @option{last}
5809 specifies "to the end of the flash bank".
5810 The @var{num} parameter is a value shown by @command{flash banks}.
5811 The protection block is usually identical to a flash sector.
5812 Some devices may utilize a protection block distinct from flash sector.
5813 See @command{flash info} for a list of protection blocks.
5816 @deffn {Command} {flash padded_value} num value
5817 Sets the default value used for padding any image sections, This should
5818 normally match the flash bank erased value. If not specified by this
5819 command or the flash driver then it defaults to 0xff.
5823 @deffn {Command} {program} filename [preverify] [verify] [reset] [exit] [offset]
5824 This is a helper script that simplifies using OpenOCD as a standalone
5825 programmer. The only required parameter is @option{filename}, the others are optional.
5826 @xref{Flash Programming}.
5829 @anchor{flashdriverlist}
5830 @section Flash Driver List
5831 As noted above, the @command{flash bank} command requires a driver name,
5832 and allows driver-specific options and behaviors.
5833 Some drivers also activate driver-specific commands.
5835 @deffn {Flash Driver} {virtual}
5836 This is a special driver that maps a previously defined bank to another
5837 address. All bank settings will be copied from the master physical bank.
5839 The @var{virtual} driver defines one mandatory parameters,
5842 @item @var{master_bank} The bank that this virtual address refers to.
5845 So in the following example addresses 0xbfc00000 and 0x9fc00000 refer to
5846 the flash bank defined at address 0x1fc00000. Any command executed on
5847 the virtual banks is actually performed on the physical banks.
5849 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
5850 flash bank vbank0 virtual 0xbfc00000 0 0 0 \
5851 $_TARGETNAME $_FLASHNAME
5852 flash bank vbank1 virtual 0x9fc00000 0 0 0 \
5853 $_TARGETNAME $_FLASHNAME
5857 @subsection External Flash
5859 @deffn {Flash Driver} {cfi}
5860 @cindex Common Flash Interface
5862 The ``Common Flash Interface'' (CFI) is the main standard for
5863 external NOR flash chips, each of which connects to a
5864 specific external chip select on the CPU.
5865 Frequently the first such chip is used to boot the system.
5866 Your board's @code{reset-init} handler might need to
5867 configure additional chip selects using other commands (like: @command{mww} to
5868 configure a bus and its timings), or
5869 perhaps configure a GPIO pin that controls the ``write protect'' pin
5871 The CFI driver can use a target-specific working area to significantly
5874 The CFI driver can accept the following optional parameters, in any order:
5877 @item @var{jedec_probe} ... is used to detect certain non-CFI flash ROMs,
5878 like AM29LV010 and similar types.
5879 @item @var{x16_as_x8} ... when a 16-bit flash is hooked up to an 8-bit bus.
5880 @item @var{bus_swap} ... when data bytes in a 16-bit flash needs to be swapped.
5881 @item @var{data_swap} ... when data bytes in a 16-bit flash needs to be
5882 swapped when writing data values (i.e. not CFI commands).
5885 To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
5886 wide on a sixteen bit bus:
5889 flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
5890 flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
5893 To configure one bank of 32 MBytes
5894 built from two sixteen bit (two byte) wide parts wired in parallel
5895 to create a thirty-two bit (four byte) bus with doubled throughput:
5898 flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
5901 @c "cfi part_id" disabled
5904 @deffn {Flash Driver} {jtagspi}
5905 @cindex Generic JTAG2SPI driver
5909 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
5910 SPI flash connected to them. To access this flash from the host, the device
5911 is first programmed with a special proxy bitstream that
5912 exposes the SPI flash on the device's JTAG interface. The flash can then be
5913 accessed through JTAG.
5915 Since signaling between JTAG and SPI is compatible, all that is required for
5916 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
5917 the flash chip select when the JTAG state machine is in SHIFT-DR. Such
5918 a bitstream for several Xilinx FPGAs can be found in
5919 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
5920 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
5922 This flash bank driver requires a target on a JTAG tap and will access that
5923 tap directly. Since no support from the target is needed, the target can be a
5924 "testee" dummy. Since the target does not expose the flash memory
5925 mapping, target commands that would otherwise be expected to access the flash
5926 will not work. These include all @command{*_image} and
5927 @command{$target_name m*} commands as well as @command{program}. Equivalent
5928 functionality is available through the @command{flash write_bank},
5929 @command{flash read_bank}, and @command{flash verify_bank} commands.
5931 According to device size, 1- to 4-byte addresses are sent. However, some
5932 flash chips additionally have to be switched to 4-byte addresses by an extra
5936 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
5937 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
5938 @var{USER1} instruction.
5942 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
5943 set _XILINX_USER1 0x02
5944 flash bank $_FLASHNAME spi 0x0 0 0 0 \
5945 $_TARGETNAME $_XILINX_USER1
5948 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
5949 Sets flash parameters: @var{name} human readable string, @var{total_size}
5950 size in bytes, @var{page_size} is write page size. @var{read_cmd} and @var{pprg_cmd}
5951 are commands for read and page program, respectively. @var{mass_erase_cmd},
5952 @var{sector_size} and @var{sector_erase_cmd} are optional.
5954 jtagspi set 0 w25q128 0x1000000 0x100 0x03 0 0x02 0xC7 0x10000 0xD8
5958 @deffn Command {jtagspi cmd} bank_id resp_num cmd_byte ...
5959 Sends command @var{cmd_byte} and at most 20 following bytes and reads
5960 @var{resp_num} bytes afterwards. E.g. for 'Enter 4-byte address mode'
5962 jtagspi cmd 0 0 0xB7
5966 @deffn Command {jtagspi always_4byte} bank_id [ on | off ]
5967 Some devices use 4-byte addresses for all commands except the legacy 0x03 read
5968 regardless of device size. This command controls the corresponding hack.
5972 @deffn {Flash Driver} {xcf}
5973 @cindex Xilinx Platform flash driver
5975 Xilinx FPGAs can be configured from specialized flash ICs named Platform Flash.
5976 It is (almost) regular NOR flash with erase sectors, program pages, etc. The
5977 only difference is special registers controlling its FPGA specific behavior.
5978 They must be properly configured for successful FPGA loading using
5979 additional @var{xcf} driver command:
5981 @deffn {Command} {xcf ccb} <bank_id>
5982 command accepts additional parameters:
5984 @item @var{external|internal} ... selects clock source.
5985 @item @var{serial|parallel} ... selects serial or parallel data bus mode.
5986 @item @var{slave|master} ... selects slave of master mode for flash device.
5987 @item @var{40|20} ... selects clock frequency in MHz for internal clock
5991 xcf ccb 0 external parallel slave 40
5993 All of them must be specified even if clock frequency is pointless
5994 in slave mode. If only bank id specified than command prints current
5995 CCB register value. Note: there is no need to write this register
5996 every time you erase/program data sectors because it stores in
6000 @deffn {Command} {xcf configure} <bank_id>
6001 Initiates FPGA loading procedure. Useful if your board has no "configure"
6008 Additional driver notes:
6010 @item Only single revision supported.
6011 @item Driver automatically detects need of bit reverse, but
6012 only "bin" (raw binary, do not confuse it with "bit") and "mcs"
6013 (Intel hex) file types supported.
6014 @item For additional info check xapp972.pdf and ug380.pdf.
6018 @deffn {Flash Driver} {lpcspifi}
6019 @cindex NXP SPI Flash Interface
6022 NXP's LPC43xx and LPC18xx families include a proprietary SPI
6023 Flash Interface (SPIFI) peripheral that can drive and provide
6024 memory mapped access to external SPI flash devices.
6026 The lpcspifi driver initializes this interface and provides
6027 program and erase functionality for these serial flash devices.
6028 Use of this driver @b{requires} a working area of at least 1kB
6029 to be configured on the target device; more than this will
6030 significantly reduce flash programming times.
6032 The setup command only requires the @var{base} parameter. All
6033 other parameters are ignored, and the flash size and layout
6034 are configured by the driver.
6037 flash bank $_FLASHNAME lpcspifi 0x14000000 0 0 0 $_TARGETNAME
6042 @deffn {Flash Driver} {stmsmi}
6043 @cindex STMicroelectronics Serial Memory Interface
6046 Some devices from STMicroelectronics (e.g. STR75x MCU family,
6047 SPEAr MPU family) include a proprietary
6048 ``Serial Memory Interface'' (SMI) controller able to drive external
6050 Depending on specific device and board configuration, up to 4 external
6051 flash devices can be connected.
6053 SMI makes the flash content directly accessible in the CPU address
6054 space; each external device is mapped in a memory bank.
6055 CPU can directly read data, execute code and boot from SMI banks.
6056 Normal OpenOCD commands like @command{mdw} can be used to display
6059 The setup command only requires the @var{base} parameter in order
6060 to identify the memory bank.
6061 All other parameters are ignored. Additional information, like
6062 flash size, are detected automatically.
6065 flash bank $_FLASHNAME stmsmi 0xf8000000 0 0 0 $_TARGETNAME
6070 @deffn {Flash Driver} {stmqspi}
6071 @cindex STMicroelectronics QuadSPI/OctoSPI Interface
6075 Some devices from STMicroelectronics include a proprietary ``QuadSPI Interface''
6076 (e.g. STM32F4, STM32F7, STM32L4) or ``OctoSPI Interface'' (e.g. STM32L4+)
6077 controller able to drive one or even two (dual mode) external SPI flash devices.
6078 The OctoSPI is a superset of QuadSPI, its presence is detected automatically.
6079 Currently only the regular command mode is supported, whereas the HyperFlash
6082 QuadSPI/OctoSPI makes the flash contents directly accessible in the CPU address
6083 space; in case of dual mode both devices must be of the same type and are
6084 mapped in the same memory bank (even and odd addresses interleaved).
6085 CPU can directly read data, execute code (but not boot) from QuadSPI bank.
6087 The 'flash bank' command only requires the @var{base} parameter and the extra
6088 parameter @var{io_base} in order to identify the memory bank. Both are fixed
6089 by hardware, see datasheet or RM. All other parameters are ignored.
6091 The controller must be initialized after each reset and properly configured
6092 for memory-mapped read operation for the particular flash chip(s), for the full
6093 list of available register settings cf. the controller's RM. This setup is quite
6094 board specific (that's why booting from this memory is not possible). The
6095 flash driver infers all parameters from current controller register values when
6096 'flash probe @var{bank_id}' is executed.
6098 Normal OpenOCD commands like @command{mdw} can be used to display the flash content,
6099 but only after proper controller initialization as described above. However,
6100 due to a silicon bug in some devices, attempting to access the very last word
6103 It is possible to use two (even different) flash chips alternatingly, if individual
6104 bank chip selects are available. For some package variants, this is not the case
6105 due to limited pin count. To switch from one to another, adjust FSEL bit accordingly
6106 and re-issue 'flash probe bank_id'. Note that the bank base address will @emph{not}
6107 change, so the address spaces of both devices will overlap. In dual flash mode
6108 both chips must be identical regarding size and most other properties.
6110 Block or sector protection internal to the flash chip is not handled by this
6111 driver at all, but can be dealt with manually by the 'cmd' command, see below.
6112 The sector protection via 'flash protect' command etc. is completely internal to
6113 openocd, intended only to prevent accidental erase or overwrite and it does not
6114 persist across openocd invocations.
6116 OpenOCD contains a hardcoded list of flash devices with their properties,
6117 these are auto-detected. If a device is not included in this list, SFDP discovery
6118 is attempted. If this fails or gives inappropriate results, manual setting is
6119 required (see 'set' command).
6122 flash bank $_FLASHNAME stmqspi 0x90000000 0 0 0 \
6123 $_TARGETNAME 0xA0001000
6124 flash bank $_FLASHNAME stmqspi 0x70000000 0 0 0 \
6125 $_TARGETNAME 0xA0001400
6128 There are three specific commands
6129 @deffn {Command} {stmqspi mass_erase} bank_id
6130 Clears sector protections and performs a mass erase. Works only if there is no
6131 chip specific write protection engaged.
6134 @deffn {Command} {stmqspi set} bank_id name total_size page_size read_cmd fread_cmd pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
6135 Set flash parameters: @var{name} human readable string, @var{total_size} size
6136 in bytes, @var{page_size} is write page size. @var{read_cmd}, @var{fread_cmd} and @var{pprg_cmd}
6137 are commands for reading and page programming. @var{fread_cmd} is used in DPI and QPI modes,
6138 @var{read_cmd} in normal SPI (single line) mode. @var{mass_erase_cmd}, @var{sector_size}
6139 and @var{sector_erase_cmd} are optional.
6141 This command is required if chip id is not hardcoded yet and e.g. for EEPROMs or FRAMs
6142 which don't support an id command.
6144 In dual mode parameters of both chips are set identically. The parameters refer to
6145 a single chip, so the whole bank gets twice the specified capacity etc.
6148 @deffn {Command} {stmqspi cmd} bank_id resp_num cmd_byte ...
6149 If @var{resp_num} is zero, sends command @var{cmd_byte} and following data
6150 bytes. In dual mode command byte is sent to @emph{both} chips but data bytes are
6151 sent @emph{alternatingly} to chip 1 and 2, first to flash 1, second to flash 2, etc.,
6152 i.e. the total number of bytes (including cmd_byte) must be odd.
6154 If @var{resp_num} is not zero, cmd and at most four following data bytes are
6155 sent, in dual mode @emph{simultaneously} to both chips. Then @var{resp_num} bytes
6156 are read interleaved from both chips starting with chip 1. In this case
6157 @var{resp_num} must be even.
6159 Note the hardware dictated subtle difference of those two cases in dual-flash mode.
6161 To check basic communication settings, issue
6163 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 1 0x05
6164 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 1 0x05
6166 for single flash mode or
6168 stmqspi cmd bank_id 0 0x04; stmqspi cmd bank_id 2 0x05
6169 stmqspi cmd bank_id 0 0x06; stmqspi cmd bank_id 2 0x05
6171 for dual flash mode. This should return the status register contents.
6173 In 8-line mode, @var{cmd_byte} is sent twice - first time as given, second time
6174 complemented. Additionally, in 8-line mode only, some commands (e.g. Read Status)
6175 need a dummy address, e.g.
6177 stmqspi cmd bank_id 1 0x05 0x00 0x00 0x00 0x00
6179 should return the status register contents.
6185 @deffn {Flash Driver} {mrvlqspi}
6186 This driver supports QSPI flash controller of Marvell's Wireless
6187 Microcontroller platform.
6189 The flash size is autodetected based on the table of known JEDEC IDs
6190 hardcoded in the OpenOCD sources.
6193 flash bank $_FLASHNAME mrvlqspi 0x0 0 0 0 $_TARGETNAME 0x46010000
6198 @deffn {Flash Driver} {ath79}
6199 @cindex Atheros ath79 SPI driver
6201 Members of ATH79 SoC family from Atheros include a SPI interface with 3
6203 On reset a SPI flash connected to the first chip select (CS0) is made
6204 directly read-accessible in the CPU address space (up to 16MBytes)
6205 and is usually used to store the bootloader and operating system.
6206 Normal OpenOCD commands like @command{mdw} can be used to display
6207 the flash content while it is in memory-mapped mode (only the first
6208 4MBytes are accessible without additional configuration on reset).
6210 The setup command only requires the @var{base} parameter in order
6211 to identify the memory bank. The actual value for the base address
6212 is not otherwise used by the driver. However the mapping is passed
6213 to gdb. Thus for the memory mapped flash (chipselect CS0) the base
6214 address should be the actual memory mapped base address. For unmapped
6215 chipselects (CS1 and CS2) care should be taken to use a base address
6216 that does not overlap with real memory regions.
6217 Additional information, like flash size, are detected automatically.
6218 An optional additional parameter sets the chipselect for the bank,
6219 with the default CS0.
6220 CS1 and CS2 require additional GPIO setup before they can be used
6221 since the alternate function must be enabled on the GPIO pin
6222 CS1/CS2 is routed to on the given SoC.
6225 flash bank $_FLASHNAME ath79 0xbf000000 0 0 0 $_TARGETNAME
6227 # When using multiple chipselects the base should be different
6228 # for each, otherwise the write_image command is not able to
6229 # distinguish the banks.
6230 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0
6231 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1
6232 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2
6237 @deffn {Flash Driver} {fespi}
6238 @cindex Freedom E SPI
6241 SiFive's Freedom E SPI controller, used in HiFive and other boards.
6244 flash bank $_FLASHNAME fespi 0x20000000 0 0 0 $_TARGETNAME
6248 @subsection Internal Flash (Microcontrollers)
6250 @deffn {Flash Driver} {aduc702x}
6251 The ADUC702x analog microcontrollers from Analog Devices
6252 include internal flash and use ARM7TDMI cores.
6253 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
6254 The setup command only requires the @var{target} argument
6255 since all devices in this family have the same memory layout.
6258 flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
6262 @deffn {Flash Driver} {ambiqmicro}
6265 All members of the Apollo microcontroller family from
6266 Ambiq Micro include internal flash and use ARM's Cortex-M4 core.
6267 The host connects over USB to an FTDI interface that communicates
6268 with the target using SWD.
6270 The @var{ambiqmicro} driver reads the Chip Information Register detect
6271 the device class of the MCU.
6272 The Flash and SRAM sizes directly follow device class, and are used
6273 to set up the flash banks.
6274 If this fails, the driver will use default values set to the minimum
6275 sizes of an Apollo chip.
6277 All Apollo chips have two flash banks of the same size.
6278 In all cases the first flash bank starts at location 0,
6279 and the second bank starts after the first.
6283 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME
6284 # Flash bank 1 - same size as bank0, starts after bank 0.
6285 flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \
6289 Flash is programmed using custom entry points into the bootloader.
6290 This is the only way to program the flash as no flash control registers
6291 are available to the user.
6293 The @var{ambiqmicro} driver adds some additional commands:
6295 @deffn {Command} {ambiqmicro mass_erase} <bank>
6298 @deffn {Command} {ambiqmicro page_erase} <bank> <first> <last>
6301 @deffn {Command} {ambiqmicro program_otp} <bank> <offset> <count>
6302 Program OTP is a one time operation to create write protected flash.
6303 The user writes sectors to SRAM starting at 0x10000010.
6304 Program OTP will write these sectors from SRAM to flash, and write protect
6310 @deffn {Flash Driver} {at91samd}
6312 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
6313 families from Atmel include internal flash and use ARM's Cortex-M0+ core.
6315 Do not use for ATSAM D51 and E5x: use @xref{atsame5}.
6317 The devices have one flash bank:
6320 flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
6323 @deffn {Command} {at91samd chip-erase}
6324 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6325 used to erase a chip back to its factory state and does not require the
6326 processor to be halted.
6329 @deffn {Command} {at91samd set-security}
6330 Secures the Flash via the Set Security Bit (SSB) command. This prevents access
6331 to the Flash and can only be undone by using the chip-erase command which
6332 erases the Flash contents and turns off the security bit. Warning: at this
6333 time, openocd will not be able to communicate with a secured chip and it is
6334 therefore not possible to chip-erase it without using another tool.
6337 at91samd set-security enable
6341 @deffn {Command} {at91samd eeprom}
6342 Shows or sets the EEPROM emulation size configuration, stored in the User Row
6343 of the Flash. When setting, the EEPROM size must be specified in bytes and it
6344 must be one of the permitted sizes according to the datasheet. Settings are
6345 written immediately but only take effect on MCU reset. EEPROM emulation
6346 requires additional firmware support and the minimum EEPROM size may not be
6347 the same as the minimum that the hardware supports. Set the EEPROM size to 0
6348 in order to disable this feature.
6352 at91samd eeprom 1024
6356 @deffn {Command} {at91samd bootloader}
6357 Shows or sets the bootloader size configuration, stored in the User Row of the
6358 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6359 must be specified in bytes and it must be one of the permitted sizes according
6360 to the datasheet. Settings are written immediately but only take effect on
6361 MCU reset. Setting the bootloader size to 0 disables bootloader protection.
6365 at91samd bootloader 16384
6369 @deffn {Command} {at91samd dsu_reset_deassert}
6370 This command releases internal reset held by DSU
6371 and prepares reset vector catch in case of reset halt.
6372 Command is used internally in event reset-deassert-post.
6375 @deffn {Command} {at91samd nvmuserrow}
6376 Writes or reads the entire 64 bit wide NVM user row register which is located at
6377 0x804000. This register includes various fuses lock-bits and factory calibration
6378 data. Reading the register is done by invoking this command without any
6379 arguments. Writing is possible by giving 1 or 2 hex values. The first argument
6380 is the register value to be written and the second one is an optional changemask.
6381 Every bit which value in changemask is 0 will stay unchanged. The lock- and
6382 reserved-bits are masked out and cannot be changed.
6386 >at91samd nvmuserrow
6387 NVMUSERROW: 0xFFFFFC5DD8E0C788
6388 # Write 0xFFFFFC5DD8E0C788 to user row
6389 >at91samd nvmuserrow 0xFFFFFC5DD8E0C788
6390 # Write 0x12300 to user row but leave other bits and low
6392 >at91samd nvmuserrow 0x12345 0xFFF00
6399 @deffn {Flash Driver} {at91sam3}
6401 All members of the AT91SAM3 microcontroller family from
6402 Atmel include internal flash and use ARM's Cortex-M3 core. The driver
6403 currently (6/22/09) recognizes the AT91SAM3U[1/2/4][C/E] chips. Note
6404 that the driver was orginaly developed and tested using the
6405 AT91SAM3U4E, using a SAM3U-EK eval board. Support for other chips in
6406 the family was cribbed from the data sheet. @emph{Note to future
6407 readers/updaters: Please remove this worrisome comment after other
6408 chips are confirmed.}
6410 The AT91SAM3U4[E/C] (256K) chips have two flash banks; most other chips
6411 have one flash bank. In all cases the flash banks are at
6412 the following fixed locations:
6415 # Flash bank 0 - all chips
6416 flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
6417 # Flash bank 1 - only 256K chips
6418 flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
6421 Internally, the AT91SAM3 flash memory is organized as follows.
6422 Unlike the AT91SAM7 chips, these are not used as parameters
6423 to the @command{flash bank} command:
6426 @item @emph{N-Banks:} 256K chips have 2 banks, others have 1 bank.
6427 @item @emph{Bank Size:} 128K/64K Per flash bank
6428 @item @emph{Sectors:} 16 or 8 per bank
6429 @item @emph{SectorSize:} 8K Per Sector
6430 @item @emph{PageSize:} 256 bytes per page. Note that OpenOCD operates on 'sector' sizes, not page sizes.
6433 The AT91SAM3 driver adds some additional commands:
6435 @deffn {Command} {at91sam3 gpnvm}
6436 @deffnx {Command} {at91sam3 gpnvm clear} number
6437 @deffnx {Command} {at91sam3 gpnvm set} number
6438 @deffnx {Command} {at91sam3 gpnvm show} [@option{all}|number]
6439 With no parameters, @command{show} or @command{show all},
6440 shows the status of all GPNVM bits.
6441 With @command{show} @var{number}, displays that bit.
6443 With @command{set} @var{number} or @command{clear} @var{number},
6444 modifies that GPNVM bit.
6447 @deffn {Command} {at91sam3 info}
6448 This command attempts to display information about the AT91SAM3
6449 chip. @emph{First} it read the @code{CHIPID_CIDR} [address 0x400e0740, see
6450 Section 28.2.1, page 505 of the AT91SAM3U 29/may/2009 datasheet,
6451 document id: doc6430A] and decodes the values. @emph{Second} it reads the
6452 various clock configuration registers and attempts to display how it
6453 believes the chip is configured. By default, the SLOWCLK is assumed to
6454 be 32768 Hz, see the command @command{at91sam3 slowclk}.
6457 @deffn {Command} {at91sam3 slowclk} [value]
6458 This command shows/sets the slow clock frequency used in the
6459 @command{at91sam3 info} command calculations above.
6463 @deffn {Flash Driver} {at91sam4}
6465 All members of the AT91SAM4 microcontroller family from
6466 Atmel include internal flash and use ARM's Cortex-M4 core.
6467 This driver uses the same command names/syntax as @xref{at91sam3}.
6470 @deffn {Flash Driver} {at91sam4l}
6472 All members of the AT91SAM4L microcontroller family from
6473 Atmel include internal flash and use ARM's Cortex-M4 core.
6474 This driver uses the same command names/syntax as @xref{at91sam3}.
6476 The AT91SAM4L driver adds some additional commands:
6477 @deffn {Command} {at91sam4l smap_reset_deassert}
6478 This command releases internal reset held by SMAP
6479 and prepares reset vector catch in case of reset halt.
6480 Command is used internally in event reset-deassert-post.
6485 @deffn {Flash Driver} {atsame5}
6487 All members of the SAM E54, E53, E51 and D51 microcontroller
6488 families from Microchip (former Atmel) include internal flash
6489 and use ARM's Cortex-M4 core.
6491 The devices have two ECC flash banks with a swapping feature.
6492 This driver handles both banks together as it were one.
6493 Bank swapping is not supported yet.
6496 flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME
6499 @deffn {Command} {atsame5 bootloader}
6500 Shows or sets the bootloader size configuration, stored in the User Page of the
6501 Flash. This is called the BOOTPROT region. When setting, the bootloader size
6502 must be specified in bytes. The nearest bigger protection size is used.
6503 Settings are written immediately but only take effect on MCU reset.
6504 Setting the bootloader size to 0 disables bootloader protection.
6508 atsame5 bootloader 16384
6512 @deffn {Command} {atsame5 chip-erase}
6513 Issues a complete Flash erase via the Device Service Unit (DSU). This can be
6514 used to erase a chip back to its factory state and does not require the
6515 processor to be halted.
6518 @deffn {Command} {atsame5 dsu_reset_deassert}
6519 This command releases internal reset held by DSU
6520 and prepares reset vector catch in case of reset halt.
6521 Command is used internally in event reset-deassert-post.
6524 @deffn {Command} {atsame5 userpage}
6525 Writes or reads the first 64 bits of NVM User Page which is located at
6526 0x804000. This field includes various fuses.
6527 Reading is done by invoking this command without any arguments.
6528 Writing is possible by giving 1 or 2 hex values. The first argument
6529 is the value to be written and the second one is an optional bit mask
6530 (a zero bit in the mask means the bit stays unchanged).
6531 The reserved fields are always masked out and cannot be changed.
6536 USER PAGE: 0xAEECFF80FE9A9239
6538 >atsame5 userpage 0xAEECFF80FE9A9239
6539 # Write 2 to SEESBLK and 4 to SEEPSZ fields but leave other
6540 # bits unchanged (setup SmartEEPROM of virtual size 8192
6542 >atsame5 userpage 0x4200000000 0x7f00000000
6548 @deffn {Flash Driver} {atsamv}
6550 All members of the ATSAMV7x, ATSAMS70, and ATSAME70 families from
6551 Atmel include internal flash and use ARM's Cortex-M7 core.
6552 This driver uses the same command names/syntax as @xref{at91sam3}.
6555 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
6558 @deffn {Command} {atsamv gpnvm} [@option{show} [@option{all}|number]]
6559 @deffnx {Command} {atsamv gpnvm} (@option{clr}|@option{set}) number
6560 With no parameters, @option{show} or @option{show all},
6561 shows the status of all GPNVM bits.
6562 With @option{show} @var{number}, displays that bit.
6564 With @option{set} @var{number} or @option{clear} @var{number},
6565 modifies that GPNVM bit.
6570 @deffn {Flash Driver} {at91sam7}
6571 All members of the AT91SAM7 microcontroller family from Atmel include
6572 internal flash and use ARM7TDMI cores. The driver automatically
6573 recognizes a number of these chips using the chip identification
6574 register, and autoconfigures itself.
6577 flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
6580 For chips which are not recognized by the controller driver, you must
6581 provide additional parameters in the following order:
6584 @item @var{chip_model} ... label used with @command{flash info}
6586 @item @var{sectors_per_bank}
6587 @item @var{pages_per_sector}
6588 @item @var{pages_size}
6589 @item @var{num_nvm_bits}
6590 @item @var{freq_khz} ... required if an external clock is provided,
6591 optional (but recommended) when the oscillator frequency is known
6594 It is recommended that you provide zeroes for all of those values
6595 except the clock frequency, so that everything except that frequency
6596 will be autoconfigured.
6597 Knowing the frequency helps ensure correct timings for flash access.
6599 The flash controller handles erases automatically on a page (128/256 byte)
6600 basis, so explicit erase commands are not necessary for flash programming.
6601 However, there is an ``EraseAll`` command that can erase an entire flash
6602 plane (of up to 256KB), and it will be used automatically when you issue
6603 @command{flash erase_sector} or @command{flash erase_address} commands.
6605 @deffn {Command} {at91sam7 gpnvm} bitnum (@option{set}|@option{clear})
6606 Set or clear a ``General Purpose Non-Volatile Memory'' (GPNVM)
6607 bit for the processor. Each processor has a number of such bits,
6608 used for controlling features such as brownout detection (so they
6609 are not truly general purpose).
6611 This assumes that the first flash bank (number 0) is associated with
6612 the appropriate at91sam7 target.
6617 @deffn {Flash Driver} {avr}
6618 The AVR 8-bit microcontrollers from Atmel integrate flash memory.
6619 @emph{The current implementation is incomplete.}
6620 @comment - defines mass_erase ... pointless given flash_erase_address
6623 @deffn {Flash Driver} {bluenrg-x}
6624 STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP/LPS Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
6625 The driver automatically recognizes these chips using
6626 the chip identification registers, and autoconfigures itself.
6629 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
6632 Note that when users ask to erase all the sectors of the flash, a mass erase command is used which is faster than erasing
6633 each single sector one by one.
6636 flash erase_sector 0 0 last # It will perform a mass erase
6639 Triggering a mass erase is also useful when users want to disable readout protection.
6642 @deffn {Flash Driver} {cc26xx}
6643 All versions of the SimpleLink CC13xx and CC26xx microcontrollers from Texas
6644 Instruments include internal flash. The cc26xx flash driver supports both the
6645 CC13xx and CC26xx family of devices. The driver automatically recognizes the
6646 specific version's flash parameters and autoconfigures itself. The flash bank
6647 starts at address 0.
6650 flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
6654 @deffn {Flash Driver} {cc3220sf}
6655 The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
6656 Instruments includes 1MB of internal flash. The cc3220sf flash driver only
6657 supports the internal flash. The serial flash on SimpleLink boards is
6658 programmed via the bootloader over a UART connection. Security features of
6659 the CC3220SF may erase the internal flash during power on reset. Refer to
6660 documentation at @url{www.ti.com/cc3220sf} for details on security features
6661 and programming the serial flash.
6664 flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
6668 @deffn {Flash Driver} {efm32}
6669 All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
6670 include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
6671 recognizes a number of these chips using the chip identification register, and
6672 autoconfigures itself.
6674 flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
6676 It supports writing to the user data page, as well as the portion of the lockbits page
6677 past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
6678 bootloader/AppLoader system for encryption keys. Setting protection on these pages is
6679 currently not supported.
6681 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
6682 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
6685 A special feature of efm32 controllers is that it is possible to completely disable the
6686 debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
6687 this via the following command:
6691 The @var{num} parameter is a value shown by @command{flash banks}.
6692 Note that in order for this command to take effect, the target needs to be reset.
6693 @emph{The current implementation is incomplete. Unprotecting flash pages is not
6697 @deffn {Flash Driver} {esirisc}
6698 Members of the eSi-RISC family may optionally include internal flash programmed
6699 via the eSi-TSMC Flash interface. Additional parameters are required to
6700 configure the driver: @option{cfg_address} is the base address of the
6701 configuration register interface, @option{clock_hz} is the expected clock
6702 frequency, and @option{wait_states} is the number of configured read wait states.
6705 flash bank $_FLASHNAME esirisc base_address size_bytes 0 0 \
6706 $_TARGETNAME cfg_address clock_hz wait_states
6709 @deffn {Command} {esirisc flash mass_erase} bank_id
6710 Erase all pages in data memory for the bank identified by @option{bank_id}.
6713 @deffn {Command} {esirisc flash ref_erase} bank_id
6714 Erase the reference cell for the bank identified by @option{bank_id}. @emph{This
6715 is an uncommon operation.}
6719 @deffn {Flash Driver} {fm3}
6720 All members of the FM3 microcontroller family from Fujitsu
6721 include internal flash and use ARM Cortex-M3 cores.
6722 The @var{fm3} driver uses the @var{target} parameter to select the
6723 correct bank config, it can currently be one of the following:
6724 @code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
6725 @code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}.
6728 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
6732 @deffn {Flash Driver} {fm4}
6733 All members of the FM4 microcontroller family from Spansion (formerly Fujitsu)
6734 include internal flash and use ARM Cortex-M4 cores.
6735 The @var{fm4} driver uses a @var{family} parameter to select the
6736 correct bank config, it can currently be one of the following:
6737 @code{MB9BFx64}, @code{MB9BFx65}, @code{MB9BFx66}, @code{MB9BFx67}, @code{MB9BFx68},
6738 @code{S6E2Cx8}, @code{S6E2Cx9}, @code{S6E2CxA} or @code{S6E2Dx},
6739 with @code{x} treated as wildcard and otherwise case (and any trailing
6740 characters) ignored.
6743 flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \
6744 $_TARGETNAME S6E2CCAJ0A
6745 flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \
6746 $_TARGETNAME S6E2CCAJ0A
6748 @emph{The current implementation is incomplete. Protection is not supported,
6749 nor is Chip Erase (only Sector Erase is implemented).}
6752 @deffn {Flash Driver} {kinetis}
6754 Kx, KLx, KVx and KE1x members of the Kinetis microcontroller family
6755 from NXP (former Freescale) include
6756 internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
6757 recognizes flash size and a number of flash banks (1-4) using the chip
6758 identification register, and autoconfigures itself.
6759 Use kinetis_ke driver for KE0x and KEAx devices.
6761 The @var{kinetis} driver defines option:
6763 @item -sim-base @var{addr} ... base of System Integration Module where chip identification resides. Driver tries two known locations if option is omitted.
6767 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
6770 @deffn {Config Command} {kinetis create_banks}
6771 Configuration command enables automatic creation of additional flash banks
6772 based on real flash layout of device. Banks are created during device probe.
6773 Use 'flash probe 0' to force probe.
6776 @deffn {Command} {kinetis fcf_source} [protection|write]
6777 Select what source is used when writing to a Flash Configuration Field.
6778 @option{protection} mode builds FCF content from protection bits previously
6779 set by 'flash protect' command.
6780 This mode is default. MCU is protected from unwanted locking by immediate
6781 writing FCF after erase of relevant sector.
6782 @option{write} mode enables direct write to FCF.
6783 Protection cannot be set by 'flash protect' command. FCF is written along
6784 with the rest of a flash image.
6785 @emph{BEWARE: Incorrect flash configuration may permanently lock the device!}
6788 @deffn {Command} {kinetis fopt} [num]
6789 Set value to write to FOPT byte of Flash Configuration Field.
6790 Used in kinetis 'fcf_source protection' mode only.
6793 @deffn {Command} {kinetis mdm check_security}
6794 Checks status of device security lock. Used internally in examine-end
6795 and examine-fail event.
6798 @deffn {Command} {kinetis mdm halt}
6799 Issues a halt via the MDM-AP. This command can be used to break a watchdog reset
6800 loop when connecting to an unsecured target.
6803 @deffn {Command} {kinetis mdm mass_erase}
6804 Issues a complete flash erase via the MDM-AP. This can be used to erase a chip
6805 back to its factory state, removing security. It does not require the processor
6806 to be halted, however the target will remain in a halted state after this
6810 @deffn {Command} {kinetis nvm_partition}
6811 For FlexNVM devices only (KxxDX and KxxFX).
6812 Command shows or sets data flash or EEPROM backup size in kilobytes,
6813 sets two EEPROM blocks sizes in bytes and enables/disables loading
6814 of EEPROM contents to FlexRAM during reset.
6816 For details see device reference manual, Flash Memory Module,
6817 Program Partition command.
6819 Setting is possible only once after mass_erase.
6820 Reset the device after partition setting.
6822 Show partition size:
6824 kinetis nvm_partition info
6827 Set 32 KB data flash, rest of FlexNVM is EEPROM backup. EEPROM has two blocks
6828 of 512 and 1536 bytes and its contents is loaded to FlexRAM during reset:
6830 kinetis nvm_partition dataflash 32 512 1536 on
6833 Set 16 KB EEPROM backup, rest of FlexNVM is a data flash. EEPROM has two blocks
6834 of 1024 bytes and its contents is not loaded to FlexRAM during reset:
6836 kinetis nvm_partition eebkp 16 1024 1024 off
6840 @deffn {Command} {kinetis mdm reset}
6841 Issues a reset via the MDM-AP. This causes the MCU to output a low pulse on the
6842 RESET pin, which can be used to reset other hardware on board.
6845 @deffn {Command} {kinetis disable_wdog}
6846 For Kx devices only (KLx has different COP watchdog, it is not supported).
6847 Command disables watchdog timer.
6851 @deffn {Flash Driver} {kinetis_ke}
6853 KE0x and KEAx members of the Kinetis microcontroller family from NXP include
6854 internal flash and use ARM Cortex-M0+. The driver automatically recognizes
6855 the KE0x sub-family using the chip identification register, and
6856 autoconfigures itself.
6857 Use kinetis (not kinetis_ke) driver for KE1x devices.
6860 flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
6863 @deffn {Command} {kinetis_ke mdm check_security}
6864 Checks status of device security lock. Used internally in examine-end event.
6867 @deffn {Command} {kinetis_ke mdm mass_erase}
6868 Issues a complete Flash erase via the MDM-AP.
6869 This can be used to erase a chip back to its factory state.
6870 Command removes security lock from a device (use of SRST highly recommended).
6871 It does not require the processor to be halted.
6874 @deffn {Command} {kinetis_ke disable_wdog}
6875 Command disables watchdog timer.
6879 @deffn {Flash Driver} {lpc2000}
6880 This is the driver to support internal flash of all members of the
6881 LPC11(x)00 and LPC1300 microcontroller families and most members of
6882 the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100,
6883 LPC8Nxx and NHS31xx microcontroller families from NXP.
6886 There are LPC2000 devices which are not supported by the @var{lpc2000}
6888 The LPC2888 is supported by the @var{lpc288x} driver.
6889 The LPC29xx family is supported by the @var{lpc2900} driver.
6892 The @var{lpc2000} driver defines two mandatory and two optional parameters,
6893 which must appear in the following order:
6896 @item @var{variant} ... required, may be
6897 @option{lpc2000_v1} (older LPC21xx and LPC22xx)
6898 @option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
6899 @option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
6900 @option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
6902 @option{lpc800} (LPC8xx)
6903 @option{lpc1100} (LPC11(x)xx and LPC13xx)
6904 @option{lpc1500} (LPC15xx)
6905 @option{lpc54100} (LPC541xx)
6906 @option{lpc4000} (LPC40xx)
6907 or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
6908 LPC8xx, LPC13xx, LPC17xx, LPC40xx, LPC8Nxx and NHS31xx
6909 @item @var{clock_kHz} ... the frequency, in kiloHertz,
6910 at which the core is running
6911 @item @option{calc_checksum} ... optional (but you probably want to provide this!),
6912 telling the driver to calculate a valid checksum for the exception vector table.
6914 If you don't provide @option{calc_checksum} when you're writing the vector
6915 table, the boot ROM will almost certainly ignore your flash image.
6916 However, if you do provide it,
6917 with most tool chains @command{verify_image} will fail.
6919 @item @option{iap_entry} ... optional telling the driver to use a different
6920 ROM IAP entry point.
6923 LPC flashes don't require the chip and bus width to be specified.
6926 flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
6927 lpc2000_v2 14765 calc_checksum
6930 @deffn {Command} {lpc2000 part_id} bank
6931 Displays the four byte part identifier associated with
6932 the specified flash @var{bank}.
6936 @deffn {Flash Driver} {lpc288x}
6937 The LPC2888 microcontroller from NXP needs slightly different flash
6938 support from its lpc2000 siblings.
6939 The @var{lpc288x} driver defines one mandatory parameter,
6940 the programming clock rate in Hz.
6941 LPC flashes don't require the chip and bus width to be specified.
6944 flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
6948 @deffn {Flash Driver} {lpc2900}
6949 This driver supports the LPC29xx ARM968E based microcontroller family
6952 The predefined parameters @var{base}, @var{size}, @var{chip_width} and
6953 @var{bus_width} of the @code{flash bank} command are ignored. Flash size and
6954 sector layout are auto-configured by the driver.
6955 The driver has one additional mandatory parameter: The CPU clock rate
6956 (in kHz) at the time the flash operations will take place. Most of the time this
6957 will not be the crystal frequency, but a higher PLL frequency. The
6958 @code{reset-init} event handler in the board script is usually the place where
6961 The driver rejects flashless devices (currently the LPC2930).
6963 The EEPROM in LPC2900 devices is not mapped directly into the address space.
6964 It must be handled much more like NAND flash memory, and will therefore be
6965 handled by a separate @code{lpc2900_eeprom} driver (not yet available).
6967 Sector protection in terms of the LPC2900 is handled transparently. Every time a
6968 sector needs to be erased or programmed, it is automatically unprotected.
6969 What is shown as protection status in the @code{flash info} command, is
6970 actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
6971 sector from ever being erased or programmed again. As this is an irreversible
6972 mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
6973 and not by the standard @code{flash protect} command.
6975 Example for a 125 MHz clock frequency:
6977 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
6980 Some @code{lpc2900}-specific commands are defined. In the following command list,
6981 the @var{bank} parameter is the bank number as obtained by the
6982 @code{flash banks} command.
6984 @deffn {Command} {lpc2900 signature} bank
6985 Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
6986 content. This is a hardware feature of the flash block, hence the calculation is
6987 very fast. You may use this to verify the content of a programmed device against
6992 signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
6996 @deffn {Command} {lpc2900 read_custom} bank filename
6997 Reads the 912 bytes of customer information from the flash index sector, and
6998 saves it to a file in binary format.
7001 lpc2900 read_custom 0 /path_to/customer_info.bin
7005 The index sector of the flash is a @emph{write-only} sector. It cannot be
7006 erased! In order to guard against unintentional write access, all following
7007 commands need to be preceded by a successful call to the @code{password}
7010 @deffn {Command} {lpc2900 password} bank password
7011 You need to use this command right before each of the following commands:
7012 @code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
7013 @code{lpc2900 secure_jtag}.
7015 The password string is fixed to "I_know_what_I_am_doing".
7018 lpc2900 password 0 I_know_what_I_am_doing
7019 Potentially dangerous operation allowed in next command!
7023 @deffn {Command} {lpc2900 write_custom} bank filename type
7024 Writes the content of the file into the customer info space of the flash index
7025 sector. The filetype can be specified with the @var{type} field. Possible values
7026 for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
7027 @var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
7028 contain a single section, and the contained data length must be exactly
7030 @quotation Attention
7031 This cannot be reverted! Be careful!
7035 lpc2900 write_custom 0 /path_to/customer_info.bin bin
7039 @deffn {Command} {lpc2900 secure_sector} bank first last
7040 Secures the sector range from @var{first} to @var{last} (including) against
7041 further program and erase operations. The sector security will be effective
7042 after the next power cycle.
7043 @quotation Attention
7044 This cannot be reverted! Be careful!
7046 Secured sectors appear as @emph{protected} in the @code{flash info} command.
7049 lpc2900 secure_sector 0 1 1
7051 #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
7052 # 0: 0x00000000 (0x2000 8kB) not protected
7053 # 1: 0x00002000 (0x2000 8kB) protected
7054 # 2: 0x00004000 (0x2000 8kB) not protected
7058 @deffn {Command} {lpc2900 secure_jtag} bank
7059 Irreversibly disable the JTAG port. The new JTAG security setting will be
7060 effective after the next power cycle.
7061 @quotation Attention
7062 This cannot be reverted! Be careful!
7066 lpc2900 secure_jtag 0
7071 @deffn {Flash Driver} {mdr}
7072 This drivers handles the integrated NOR flash on Milandr Cortex-M
7073 based controllers. A known limitation is that the Info memory can't be
7074 read or verified as it's not memory mapped.
7077 flash bank <name> mdr <base> <size> \
7078 0 0 <target#> @var{type} @var{page_count} @var{sec_count}
7082 @item @var{type} - 0 for main memory, 1 for info memory
7083 @item @var{page_count} - total number of pages
7084 @item @var{sec_count} - number of sector per page count
7089 if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
7090 flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \
7091 0 0 $_TARGETNAME 1 1 4
7093 flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \
7094 0 0 $_TARGETNAME 0 32 4
7099 @deffn {Flash Driver} {msp432}
7100 All versions of the SimpleLink MSP432 microcontrollers from Texas
7101 Instruments include internal flash. The msp432 flash driver automatically
7102 recognizes the specific version's flash parameters and autoconfigures itself.
7103 Main program flash starts at address 0. The information flash region on
7104 MSP432P4 versions starts at address 0x200000.
7107 flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
7110 @deffn {Command} {msp432 mass_erase} bank_id [main|all]
7111 Performs a complete erase of flash. By default, @command{mass_erase} will erase
7112 only the main program flash.
7114 On MSP432P4 versions, using @command{mass_erase all} will erase both the
7115 main program and information flash regions. To also erase the BSL in information
7116 flash, the user must first use the @command{bsl} command.
7119 @deffn {Command} {msp432 bsl} bank_id [unlock|lock]
7120 On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
7121 region in information flash so that flash commands can erase or write the BSL.
7122 Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
7124 To erase and program the BSL:
7127 flash erase_address 0x202000 0x2000
7128 flash write_image bsl.bin 0x202000
7134 @deffn {Flash Driver} {niietcm4}
7135 This drivers handles the integrated NOR flash on NIIET Cortex-M4
7136 based controllers. Flash size and sector layout are auto-configured by the driver.
7137 Main flash memory is called "Bootflash" and has main region and info region.
7138 Info region is NOT memory mapped by default,
7139 but it can replace first part of main region if needed.
7140 Full erase, single and block writes are supported for both main and info regions.
7141 There is additional not memory mapped flash called "Userflash", which
7142 also have division into regions: main and info.
7143 Purpose of userflash - to store system and user settings.
7144 Driver has special commands to perform operations with this memory.
7147 flash bank $_FLASHNAME niietcm4 0 0 0 0 $_TARGETNAME
7150 Some niietcm4-specific commands are defined:
7152 @deffn {Command} {niietcm4 uflash_read_byte} bank ('main'|'info') address
7153 Read byte from main or info userflash region.
7156 @deffn {Command} {niietcm4 uflash_write_byte} bank ('main'|'info') address value
7157 Write byte to main or info userflash region.
7160 @deffn {Command} {niietcm4 uflash_full_erase} bank
7161 Erase all userflash including info region.
7164 @deffn {Command} {niietcm4 uflash_erase} bank ('main'|'info') first_sector last_sector
7165 Erase sectors of main or info userflash region, starting at sector first up to and including last.
7168 @deffn {Command} {niietcm4 uflash_protect_check} bank ('main'|'info')
7169 Check sectors protect.
7172 @deffn {Command} {niietcm4 uflash_protect} bank ('main'|'info') first_sector last_sector ('on'|'off')
7173 Protect sectors of main or info userflash region, starting at sector first up to and including last.
7176 @deffn {Command} {niietcm4 bflash_info_remap} bank ('on'|'off')
7177 Enable remapping bootflash info region to 0x00000000 (or 0x40000000 if external memory boot used).
7180 @deffn {Command} {niietcm4 extmem_cfg} bank ('gpioa'|'gpiob'|'gpioc'|'gpiod'|'gpioe'|'gpiof'|'gpiog'|'gpioh') pin_num ('func1'|'func3')
7181 Configure external memory interface for boot.
7184 @deffn {Command} {niietcm4 service_mode_erase} bank
7185 Perform emergency erase of all flash (bootflash and userflash).
7188 @deffn {Command} {niietcm4 driver_info} bank
7189 Show information about flash driver.
7194 @deffn {Flash Driver} {npcx}
7195 All versions of the NPCX microcontroller families from Nuvoton include internal
7196 flash. The NPCX flash driver supports the NPCX family of devices. The driver
7197 automatically recognizes the specific version's flash parameters and
7198 autoconfigures itself. The flash bank starts at address 0x64000000.
7201 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
7205 @deffn {Flash Driver} {nrf5}
7206 All members of the nRF51 microcontroller families from Nordic Semiconductor
7207 include internal flash and use ARM Cortex-M0 core. nRF52 family powered
7208 by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
7209 including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
7210 supported with the exception of security extensions (flash access control list
7214 flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
7217 Some nrf5-specific commands are defined:
7219 @deffn {Command} {nrf5 mass_erase}
7220 Erases the contents of the code memory and user information
7221 configuration registers as well. It must be noted that this command
7222 works only for chips that do not have factory pre-programmed region 0
7226 @deffn {Command} {nrf5 info}
7227 Decodes and shows information from FICR and UICR registers.
7232 @deffn {Flash Driver} {ocl}
7233 This driver is an implementation of the ``on chip flash loader''
7234 protocol proposed by Pavel Chromy.
7236 It is a minimalistic command-response protocol intended to be used
7237 over a DCC when communicating with an internal or external flash
7238 loader running from RAM. An example implementation for AT91SAM7x is
7239 available in @file{contrib/loaders/flash/at91sam7x/}.
7242 flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
7246 @deffn {Flash Driver} {pic32mx}
7247 The PIC32MX microcontrollers are based on the MIPS 4K cores,
7248 and integrate flash memory.
7251 flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
7252 flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
7255 @comment numerous *disabled* commands are defined:
7256 @comment - chip_erase ... pointless given flash_erase_address
7257 @comment - lock, unlock ... pointless given protect on/off (yes?)
7258 @comment - pgm_word ... shouldn't bank be deduced from address??
7259 Some pic32mx-specific commands are defined:
7260 @deffn {Command} {pic32mx pgm_word} address value bank
7261 Programs the specified 32-bit @var{value} at the given @var{address}
7262 in the specified chip @var{bank}.
7264 @deffn {Command} {pic32mx unlock} bank
7265 Unlock and erase specified chip @var{bank}.
7266 This will remove any Code Protection.
7270 @deffn {Flash Driver} {psoc4}
7271 All members of the PSoC 41xx/42xx microcontroller family from Cypress
7272 include internal flash and use ARM Cortex-M0 cores.
7273 The driver automatically recognizes a number of these chips using
7274 the chip identification register, and autoconfigures itself.
7276 Note: Erased internal flash reads as 00.
7277 System ROM of PSoC 4 does not implement erase of a flash sector.
7280 flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
7283 psoc4-specific commands
7284 @deffn {Command} {psoc4 flash_autoerase} num (on|off)
7285 Enables or disables autoerase mode for a flash bank.
7287 If flash_autoerase is off, use mass_erase before flash programming.
7288 Flash erase command fails if region to erase is not whole flash memory.
7290 If flash_autoerase is on, a sector is both erased and programmed in one
7291 system ROM call. Flash erase command is ignored.
7292 This mode is suitable for gdb load.
7294 The @var{num} parameter is a value shown by @command{flash banks}.
7297 @deffn {Command} {psoc4 mass_erase} num
7298 Erases the contents of the flash memory, protection and security lock.
7300 The @var{num} parameter is a value shown by @command{flash banks}.
7304 @deffn {Flash Driver} {psoc5lp}
7305 All members of the PSoC 5LP microcontroller family from Cypress
7306 include internal program flash and use ARM Cortex-M3 cores.
7307 The driver probes for a number of these chips and autoconfigures itself,
7308 apart from the base address.
7311 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
7314 @b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
7315 @quotation Attention
7316 If flash operations are performed in ECC-disabled mode, they will also affect
7317 the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
7318 then also erase the corresponding 2k data bytes in the 0x48000000 area.
7319 Writing to the ECC data bytes in ECC-disabled mode is not implemented.
7322 Commands defined in the @var{psoc5lp} driver:
7324 @deffn {Command} {psoc5lp mass_erase}
7325 Erases all flash data and ECC/configuration bytes, all flash protection rows,
7326 and all row latches in all flash arrays on the device.
7330 @deffn {Flash Driver} {psoc5lp_eeprom}
7331 All members of the PSoC 5LP microcontroller family from Cypress
7332 include internal EEPROM and use ARM Cortex-M3 cores.
7333 The driver probes for a number of these chips and autoconfigures itself,
7334 apart from the base address.
7337 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 \
7342 @deffn {Flash Driver} {psoc5lp_nvl}
7343 All members of the PSoC 5LP microcontroller family from Cypress
7344 include internal Nonvolatile Latches and use ARM Cortex-M3 cores.
7345 The driver probes for a number of these chips and autoconfigures itself.
7348 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
7351 PSoC 5LP chips have multiple NV Latches:
7354 @item Device Configuration NV Latch - 4 bytes
7355 @item Write Once (WO) NV Latch - 4 bytes
7358 @b{Note:} This driver only implements the Device Configuration NVL.
7360 The @var{psoc5lp} driver reads the ECC mode from Device Configuration NVL.
7361 @quotation Attention
7362 Switching ECC mode via write to Device Configuration NVL will require a reset
7363 after successful write.
7367 @deffn {Flash Driver} {psoc6}
7368 Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
7369 PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
7370 the same Flash/RAM/MMIO address space.
7372 Flash in PSoC6 is split into three regions:
7374 @item Main Flash - this is the main storage for user application.
7375 Total size varies among devices, sector size: 256 kBytes, row size:
7376 512 bytes. Supports erase operation on individual rows.
7377 @item Work Flash - intended to be used as storage for user data
7378 (e.g. EEPROM emulation). Total size: 32 KBytes, sector size: 32 KBytes,
7379 row size: 512 bytes.
7380 @item Supervisory Flash - special region which contains device-specific
7381 service data. This region does not support erase operation. Only few rows can
7382 be programmed by the user, most of the rows are read only. Programming
7383 operation will erase row automatically.
7386 All three flash regions are supported by the driver. Flash geometry is detected
7387 automatically by parsing data in SPCIF_GEOMETRY register.
7389 PSoC6 is equipped with NOR Flash so erased Flash reads as 0x00.
7392 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 \
7394 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 \
7396 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 \
7398 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 \
7400 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 \
7402 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 \
7405 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 \
7407 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 \
7409 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 \
7411 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 \
7413 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 \
7415 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 \
7419 psoc6-specific commands
7420 @deffn {Command} {psoc6 reset_halt}
7421 Command can be used to simulate broken Vector Catch from gdbinit or tcl scripts.
7422 When invoked for CM0+ target, it will set break point at application entry point
7423 and issue SYSRESETREQ. This will reset both cores and all peripherals. CM0+ will
7424 reset CM4 during boot anyway so this is safe. On CM4 target, VECTRESET is used
7425 instead of SYSRESETREQ to avoid unwanted reset of CM0+;
7428 @deffn {Command} {psoc6 mass_erase} num
7429 Erases the contents given flash bank. The @var{num} parameter is a value shown
7430 by @command{flash banks}.
7431 Note: only Main and Work flash regions support Erase operation.
7435 @deffn {Flash Driver} {rp2040}
7436 Supports RP2040 "Raspberry Pi Pico" microcontroller.
7437 RP2040 is a dual-core device with two CM0+ cores. Both cores share the same
7438 Flash/RAM/MMIO address space. Non-volatile storage is achieved with an
7439 external QSPI flash; a Boot ROM provides helper functions.
7442 flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
7446 @deffn {Flash Driver} {sim3x}
7447 All members of the SiM3 microcontroller family from Silicon Laboratories
7448 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
7450 The @var{sim3x} driver tries to probe the device to auto detect the MCU.
7451 If this fails, it will use the @var{size} parameter as the size of flash bank.
7454 flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
7457 There are 2 commands defined in the @var{sim3x} driver:
7459 @deffn {Command} {sim3x mass_erase}
7460 Erases the complete flash. This is used to unlock the flash.
7461 And this command is only possible when using the SWD interface.
7464 @deffn {Command} {sim3x lock}
7465 Lock the flash. To unlock use the @command{sim3x mass_erase} command.
7469 @deffn {Flash Driver} {stellaris}
7470 All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
7471 families from Texas Instruments include internal flash. The driver
7472 automatically recognizes a number of these chips using the chip
7473 identification register, and autoconfigures itself.
7476 flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
7479 @deffn {Command} {stellaris recover}
7480 Performs the @emph{Recovering a "Locked" Device} procedure to restore
7481 the flash and its associated nonvolatile registers to their factory
7482 default values (erased). This is the only way to remove flash
7483 protection or re-enable debugging if that capability has been
7486 Note that the final "power cycle the chip" step in this procedure
7487 must be performed by hand, since OpenOCD can't do it.
7489 if more than one Stellaris chip is connected, the procedure is
7490 applied to all of them.
7495 @deffn {Flash Driver} {stm32f1x}
7496 All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
7497 from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
7498 families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
7499 The driver also works with GD32VF103 powered by RISC-V core.
7500 The driver automatically recognizes a number of these chips using
7501 the chip identification register, and autoconfigures itself.
7504 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
7507 Note that some devices have been found that have a flash size register that contains
7508 an invalid value, to workaround this issue you can override the probed value used by
7512 flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME
7515 If you have a target with dual flash banks then define the second bank
7516 as per the following example.
7518 flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
7521 Some stm32f1x-specific commands are defined:
7523 @deffn {Command} {stm32f1x lock} num
7524 Locks the entire stm32 device against reading.
7525 The @var{num} parameter is a value shown by @command{flash banks}.
7528 @deffn {Command} {stm32f1x unlock} num
7529 Unlocks the entire stm32 device for reading. This command will cause
7530 a mass erase of the entire stm32 device if previously locked.
7531 The @var{num} parameter is a value shown by @command{flash banks}.
7534 @deffn {Command} {stm32f1x mass_erase} num
7535 Mass erases the entire stm32 device.
7536 The @var{num} parameter is a value shown by @command{flash banks}.
7539 @deffn {Command} {stm32f1x options_read} num
7540 Reads and displays active stm32 option bytes loaded during POR
7541 or upon executing the @command{stm32f1x options_load} command.
7542 The @var{num} parameter is a value shown by @command{flash banks}.
7545 @deffn {Command} {stm32f1x options_write} num (@option{SWWDG}|@option{HWWDG}) (@option{RSTSTNDBY}|@option{NORSTSTNDBY}) (@option{RSTSTOP}|@option{NORSTSTOP}) (@option{USEROPT} user_data)
7546 Writes the stm32 option byte with the specified values.
7547 The @var{num} parameter is a value shown by @command{flash banks}.
7548 The @var{user_data} parameter is content of higher 16 bits of the option byte register (Data0 and Data1 as one 16bit number).
7551 @deffn {Command} {stm32f1x options_load} num
7552 Generates a special kind of reset to re-load the stm32 option bytes written
7553 by the @command{stm32f1x options_write} or @command{flash protect} commands
7554 without having to power cycle the target. Not applicable to stm32f1x devices.
7555 The @var{num} parameter is a value shown by @command{flash banks}.
7559 @deffn {Flash Driver} {stm32f2x}
7560 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
7561 include internal flash and use ARM Cortex-M3/M4/M7 cores.
7562 The driver automatically recognizes a number of these chips using
7563 the chip identification register, and autoconfigures itself.
7566 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
7569 If you use OTP (One-Time Programmable) memory define it as a second bank
7570 as per the following example.
7572 flash bank $_FLASHNAME stm32f2x 0x1FFF7800 0 0 0 $_TARGETNAME
7575 @deffn {Command} {stm32f2x otp} num (@option{enable}|@option{disable}|@option{show})
7576 Enables or disables OTP write commands for bank @var{num}.
7577 The @var{num} parameter is a value shown by @command{flash banks}.
7580 Note that some devices have been found that have a flash size register that contains
7581 an invalid value, to workaround this issue you can override the probed value used by
7585 flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME
7588 Some stm32f2x-specific commands are defined:
7590 @deffn {Command} {stm32f2x lock} num
7591 Locks the entire stm32 device.
7592 The @var{num} parameter is a value shown by @command{flash banks}.
7595 @deffn {Command} {stm32f2x unlock} num
7596 Unlocks the entire stm32 device.
7597 The @var{num} parameter is a value shown by @command{flash banks}.
7600 @deffn {Command} {stm32f2x mass_erase} num
7601 Mass erases the entire stm32f2x device.
7602 The @var{num} parameter is a value shown by @command{flash banks}.
7605 @deffn {Command} {stm32f2x options_read} num
7606 Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
7607 The @var{num} parameter is a value shown by @command{flash banks}.
7610 @deffn {Command} {stm32f2x options_write} num user_options boot_addr0 boot_addr1
7611 Writes user options and (where implemented) boot_addr0 and boot_addr1 in raw format.
7612 Warning: The meaning of the various bits depends on the device, always check datasheet!
7613 The @var{num} parameter is a value shown by @command{flash banks}, @var{user_options} a
7614 12 bit value, consisting of bits 31-28 and 7-0 of FLASH_OPTCR, @var{boot_addr0} and
7615 @var{boot_addr1} two halfwords (of FLASH_OPTCR1).
7618 @deffn {Command} {stm32f2x optcr2_write} num optcr2
7619 Writes FLASH_OPTCR2 options. Warning: Clearing PCROPi bits requires a full mass erase!
7620 The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2} a 32-bit word.
7624 @deffn {Flash Driver} {stm32h7x}
7625 All members of the STM32H7 microcontroller families from STMicroelectronics
7626 include internal flash and use ARM Cortex-M7 core.
7627 The driver automatically recognizes a number of these chips using
7628 the chip identification register, and autoconfigures itself.
7631 flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
7634 Note that some devices have been found that have a flash size register that contains
7635 an invalid value, to workaround this issue you can override the probed value used by
7639 flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
7642 Some stm32h7x-specific commands are defined:
7644 @deffn {Command} {stm32h7x lock} num
7645 Locks the entire stm32 device.
7646 The @var{num} parameter is a value shown by @command{flash banks}.
7649 @deffn {Command} {stm32h7x unlock} num
7650 Unlocks the entire stm32 device.
7651 The @var{num} parameter is a value shown by @command{flash banks}.
7654 @deffn {Command} {stm32h7x mass_erase} num
7655 Mass erases the entire stm32h7x device.
7656 The @var{num} parameter is a value shown by @command{flash banks}.
7659 @deffn {Command} {stm32h7x option_read} num reg_offset
7660 Reads an option byte register from the stm32h7x device.
7661 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7662 is the register offset of the option byte to read from the used bank registers' base.
7663 For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2.
7668 stm32h7x option_read 0 0x1c
7670 stm32h7x option_read 0 0x38
7672 stm32h7x option_read 1 0x38
7676 @deffn {Command} {stm32h7x option_write} num reg_offset value [reg_mask]
7677 Writes an option byte register of the stm32h7x device.
7678 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7679 is the register offset of the option byte to write from the used bank register base,
7680 and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1'
7685 # swap bank 1 and bank 2 in dual bank devices
7686 # by setting SWAP_BANK_OPT bit in OPTSR_PRG
7687 stm32h7x option_write 0 0x20 0x8000000 0x8000000
7692 @deffn {Flash Driver} {stm32lx}
7693 All members of the STM32L0 and STM32L1 microcontroller families from STMicroelectronics
7694 include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
7695 The driver automatically recognizes a number of these chips using
7696 the chip identification register, and autoconfigures itself.
7699 flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
7702 Note that some devices have been found that have a flash size register that contains
7703 an invalid value, to workaround this issue you can override the probed value used by
7704 the flash driver. If you use 0 as the bank base address, it tells the
7705 driver to autodetect the bank location assuming you're configuring the
7709 flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
7712 Some stm32lx-specific commands are defined:
7714 @deffn {Command} {stm32lx lock} num
7715 Locks the entire stm32 device.
7716 The @var{num} parameter is a value shown by @command{flash banks}.
7719 @deffn {Command} {stm32lx unlock} num
7720 Unlocks the entire stm32 device.
7721 The @var{num} parameter is a value shown by @command{flash banks}.
7724 @deffn {Command} {stm32lx mass_erase} num
7725 Mass erases the entire stm32lx device (all flash banks and EEPROM
7726 data). This is the only way to unlock a protected flash (unless RDP
7727 Level is 2 which can't be unlocked at all).
7728 The @var{num} parameter is a value shown by @command{flash banks}.
7732 @deffn {Flash Driver} {stm32l4x}
7733 All members of the STM32 G0, G4, L4, L4+, L5, U5, WB and WL
7734 microcontroller families from STMicroelectronics include internal flash
7735 and use ARM Cortex-M0+, M4 and M33 cores.
7736 The driver automatically recognizes a number of these chips using
7737 the chip identification register, and autoconfigures itself.
7740 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
7743 If you use OTP (One-Time Programmable) memory define it as a second bank
7744 as per the following example.
7746 flash bank $_FLASHNAME stm32l4x 0x1FFF7000 0 0 0 $_TARGETNAME
7749 @deffn {Command} {stm32l4x otp} num (@option{enable}|@option{disable}|@option{show})
7750 Enables or disables OTP write commands for bank @var{num}.
7751 The @var{num} parameter is a value shown by @command{flash banks}.
7754 Note that some devices have been found that have a flash size register that contains
7755 an invalid value, to workaround this issue you can override the probed value used by
7756 the flash driver. However, specifying a wrong value might lead to a completely
7757 wrong flash layout, so this feature must be used carefully.
7760 flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
7763 Some stm32l4x-specific commands are defined:
7765 @deffn {Command} {stm32l4x lock} num
7766 Locks the entire stm32 device.
7767 The @var{num} parameter is a value shown by @command{flash banks}.
7769 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7772 @deffn {Command} {stm32l4x unlock} num
7773 Unlocks the entire stm32 device.
7774 The @var{num} parameter is a value shown by @command{flash banks}.
7776 @emph{Note:} To apply the protection change immediately, use @command{stm32l4x option_load}.
7779 @deffn {Command} {stm32l4x mass_erase} num
7780 Mass erases the entire stm32l4x device.
7781 The @var{num} parameter is a value shown by @command{flash banks}.
7784 @deffn {Command} {stm32l4x option_read} num reg_offset
7785 Reads an option byte register from the stm32l4x device.
7786 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7787 is the register offset of the Option byte to read.
7789 For example to read the FLASH_OPTR register:
7791 stm32l4x option_read 0 0x20
7792 # Option Register (for STM32L4x): <0x40022020> = 0xffeff8aa
7793 # Option Register (for STM32WBx): <0x58004020> = ...
7794 # The correct flash base address will be used automatically
7797 The above example will read out the FLASH_OPTR register which contains the RDP
7798 option byte, Watchdog configuration, BOR level etc.
7801 @deffn {Command} {stm32l4x option_write} num reg_offset reg_mask
7802 Write an option byte register of the stm32l4x device.
7803 The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset}
7804 is the register offset of the Option byte to write, and @var{reg_mask} is the mask
7805 to apply when writing the register (only bits with a '1' will be touched).
7807 @emph{Note:} To apply the option bytes change immediately, use @command{stm32l4x option_load}.
7809 For example to write the WRP1AR option bytes:
7811 stm32l4x option_write 0 0x28 0x00FF0000 0x00FF00FF
7814 The above example will write the WRP1AR option register configuring the Write protection
7815 Area A for bank 1. The above example set WRP1AR_END=255, WRP1AR_START=0.
7816 This will effectively write protect all sectors in flash bank 1.
7819 @deffn {Command} {stm32l4x wrp_info} num [device_bank]
7820 List the protected areas using WRP.
7821 The @var{num} parameter is a value shown by @command{flash banks}.
7822 @var{device_bank} parameter is optional, possible values 'bank1' or 'bank2',
7823 if not specified, the command will display the whole flash protected areas.
7825 @b{Note:} @var{device_bank} is different from banks created using @code{flash bank}.
7826 Devices supported in this flash driver, can have main flash memory organized
7827 in single or dual-banks mode.
7828 Thus the usage of @var{device_bank} is meaningful only in dual-bank mode, to get
7829 write protected areas in a specific @var{device_bank}
7833 @deffn {Command} {stm32l4x option_load} num
7834 Forces a re-load of the option byte registers. Will cause a system reset of the device.
7835 The @var{num} parameter is a value shown by @command{flash banks}.
7838 @deffn Command {stm32l4x trustzone} num [@option{enable} | @option{disable}]
7839 Enables or disables Global TrustZone Security, using the TZEN option bit.
7840 If neither @option{enabled} nor @option{disable} are specified, the command will display
7841 the TrustZone status.
7842 @emph{Note:} This command works only with devices with TrustZone, eg. STM32L5.
7843 @emph{Note:} This command will perform an OBL_Launch after modifying the TZEN.
7847 @deffn {Flash Driver} {str7x}
7848 All members of the STR7 microcontroller family from STMicroelectronics
7849 include internal flash and use ARM7TDMI cores.
7850 The @var{str7x} driver defines one mandatory parameter, @var{variant},
7851 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
7854 flash bank $_FLASHNAME str7x \
7855 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
7858 @deffn {Command} {str7x disable_jtag} bank
7859 Activate the Debug/Readout protection mechanism
7860 for the specified flash bank.
7864 @deffn {Flash Driver} {str9x}
7865 Most members of the STR9 microcontroller family from STMicroelectronics
7866 include internal flash and use ARM966E cores.
7867 The str9 needs the flash controller to be configured using
7868 the @command{str9x flash_config} command prior to Flash programming.
7871 flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
7872 str9x flash_config 0 4 2 0 0x80000
7875 @deffn {Command} {str9x flash_config} num bbsr nbbsr bbadr nbbadr
7876 Configures the str9 flash controller.
7877 The @var{num} parameter is a value shown by @command{flash banks}.
7880 @item @var{bbsr} - Boot Bank Size register
7881 @item @var{nbbsr} - Non Boot Bank Size register
7882 @item @var{bbadr} - Boot Bank Start Address register
7883 @item @var{nbbadr} - Boot Bank Start Address register
7889 @deffn {Flash Driver} {str9xpec}
7892 Only use this driver for locking/unlocking the device or configuring the option bytes.
7893 Use the standard str9 driver for programming.
7894 Before using the flash commands the turbo mode must be enabled using the
7895 @command{str9xpec enable_turbo} command.
7897 Here is some background info to help
7898 you better understand how this driver works. OpenOCD has two flash drivers for
7902 Standard driver @option{str9x} programmed via the str9 core. Normally used for
7903 flash programming as it is faster than the @option{str9xpec} driver.
7905 Direct programming @option{str9xpec} using the flash controller. This is an
7906 ISC compliant (IEEE 1532) tap connected in series with the str9 core. The str9
7907 core does not need to be running to program using this flash driver. Typical use
7908 for this driver is locking/unlocking the target and programming the option bytes.
7911 Before we run any commands using the @option{str9xpec} driver we must first disable
7912 the str9 core. This example assumes the @option{str9xpec} driver has been
7913 configured for flash bank 0.
7915 # assert srst, we do not want core running
7916 # while accessing str9xpec flash driver
7918 # turn off target polling
7921 str9xpec enable_turbo 0
7923 str9xpec options_read 0
7924 # re-enable str9 core
7925 str9xpec disable_turbo 0
7929 The above example will read the str9 option bytes.
7930 When performing a unlock remember that you will not be able to halt the str9 - it
7931 has been locked. Halting the core is not required for the @option{str9xpec} driver
7932 as mentioned above, just issue the commands above manually or from a telnet prompt.
7934 Several str9xpec-specific commands are defined:
7936 @deffn {Command} {str9xpec disable_turbo} num
7937 Restore the str9 into JTAG chain.
7940 @deffn {Command} {str9xpec enable_turbo} num
7941 Enable turbo mode, will simply remove the str9 from the chain and talk
7942 directly to the embedded flash controller.
7945 @deffn {Command} {str9xpec lock} num
7946 Lock str9 device. The str9 will only respond to an unlock command that will
7950 @deffn {Command} {str9xpec part_id} num
7951 Prints the part identifier for bank @var{num}.
7954 @deffn {Command} {str9xpec options_cmap} num (@option{bank0}|@option{bank1})
7955 Configure str9 boot bank.
7958 @deffn {Command} {str9xpec options_lvdsel} num (@option{vdd}|@option{vdd_vddq})
7959 Configure str9 lvd source.
7962 @deffn {Command} {str9xpec options_lvdthd} num (@option{2.4v}|@option{2.7v})
7963 Configure str9 lvd threshold.
7966 @deffn {Command} {str9xpec options_lvdwarn} bank (@option{vdd}|@option{vdd_vddq})
7967 Configure str9 lvd reset warning source.
7970 @deffn {Command} {str9xpec options_read} num
7971 Read str9 option bytes.
7974 @deffn {Command} {str9xpec options_write} num
7975 Write str9 option bytes.
7978 @deffn {Command} {str9xpec unlock} num
7984 @deffn {Flash Driver} {swm050}
7986 All members of the swm050 microcontroller family from Foshan Synwit Tech.
7989 flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME
7992 One swm050-specific command is defined:
7994 @deffn {Command} {swm050 mass_erase} bank_id
7995 Erases the entire flash bank.
8001 @deffn {Flash Driver} {tms470}
8002 Most members of the TMS470 microcontroller family from Texas Instruments
8003 include internal flash and use ARM7TDMI cores.
8004 This driver doesn't require the chip and bus width to be specified.
8006 Some tms470-specific commands are defined:
8008 @deffn {Command} {tms470 flash_keyset} key0 key1 key2 key3
8009 Saves programming keys in a register, to enable flash erase and write commands.
8012 @deffn {Command} {tms470 osc_megahertz} clock_mhz
8013 Reports the clock speed, which is used to calculate timings.
8016 @deffn {Command} {tms470 plldis} (0|1)
8017 Disables (@var{1}) or enables (@var{0}) use of the PLL to speed up
8022 @deffn {Flash Driver} {w600}
8023 W60x series Wi-Fi SoC from WinnerMicro
8024 are designed with ARM Cortex-M3 and have 1M Byte QFLASH inside.
8025 The @var{w600} driver uses the @var{target} parameter to select the
8026 correct bank config.
8029 flash bank $_FLASHNAME w600 0x08000000 0 0 0 $_TARGETNAMEs
8033 @deffn {Flash Driver} {xmc1xxx}
8034 All members of the XMC1xxx microcontroller family from Infineon.
8035 This driver does not require the chip and bus width to be specified.
8038 @deffn {Flash Driver} {xmc4xxx}
8039 All members of the XMC4xxx microcontroller family from Infineon.
8040 This driver does not require the chip and bus width to be specified.
8042 Some xmc4xxx-specific commands are defined:
8044 @deffn {Command} {xmc4xxx flash_password} bank_id passwd1 passwd2
8045 Saves flash protection passwords which are used to lock the user flash
8048 @deffn {Command} {xmc4xxx flash_unprotect} bank_id user_level[0-1]
8049 Removes Flash write protection from the selected user bank
8054 @section NAND Flash Commands
8057 Compared to NOR or SPI flash, NAND devices are inexpensive
8058 and high density. Today's NAND chips, and multi-chip modules,
8059 commonly hold multiple GigaBytes of data.
8061 NAND chips consist of a number of ``erase blocks'' of a given
8062 size (such as 128 KBytes), each of which is divided into a
8063 number of pages (of perhaps 512 or 2048 bytes each). Each
8064 page of a NAND flash has an ``out of band'' (OOB) area to hold
8065 Error Correcting Code (ECC) and other metadata, usually 16 bytes
8066 of OOB for every 512 bytes of page data.
8068 One key characteristic of NAND flash is that its error rate
8069 is higher than that of NOR flash. In normal operation, that
8070 ECC is used to correct and detect errors. However, NAND
8071 blocks can also wear out and become unusable; those blocks
8072 are then marked "bad". NAND chips are even shipped from the
8073 manufacturer with a few bad blocks. The highest density chips
8074 use a technology (MLC) that wears out more quickly, so ECC
8075 support is increasingly important as a way to detect blocks
8076 that have begun to fail, and help to preserve data integrity
8077 with techniques such as wear leveling.
8079 Software is used to manage the ECC. Some controllers don't
8080 support ECC directly; in those cases, software ECC is used.
8081 Other controllers speed up the ECC calculations with hardware.
8082 Single-bit error correction hardware is routine. Controllers
8083 geared for newer MLC chips may correct 4 or more errors for
8084 every 512 bytes of data.
8086 You will need to make sure that any data you write using
8087 OpenOCD includes the appropriate kind of ECC. For example,
8088 that may mean passing the @code{oob_softecc} flag when
8089 writing NAND data, or ensuring that the correct hardware
8092 The basic steps for using NAND devices include:
8094 @item Declare via the command @command{nand device}
8095 @* Do this in a board-specific configuration file,
8096 passing parameters as needed by the controller.
8097 @item Configure each device using @command{nand probe}.
8098 @* Do this only after the associated target is set up,
8099 such as in its reset-init script or in procures defined
8100 to access that device.
8101 @item Operate on the flash via @command{nand subcommand}
8102 @* Often commands to manipulate the flash are typed by a human, or run
8103 via a script in some automated way. Common task include writing a
8104 boot loader, operating system, or other data needed to initialize or
8108 @b{NOTE:} At the time this text was written, the largest NAND
8109 flash fully supported by OpenOCD is 2 GiBytes (16 GiBits).
8110 This is because the variables used to hold offsets and lengths
8111 are only 32 bits wide.
8112 (Larger chips may work in some cases, unless an offset or length
8113 is larger than 0xffffffff, the largest 32-bit unsigned integer.)
8114 Some larger devices will work, since they are actually multi-chip
8115 modules with two smaller chips and individual chipselect lines.
8117 @anchor{nandconfiguration}
8118 @subsection NAND Configuration Commands
8119 @cindex NAND configuration
8121 NAND chips must be declared in configuration scripts,
8122 plus some additional configuration that's done after
8123 OpenOCD has initialized.
8125 @deffn {Config Command} {nand device} name driver target [configparams...]
8126 Declares a NAND device, which can be read and written to
8127 after it has been configured through @command{nand probe}.
8128 In OpenOCD, devices are single chips; this is unlike some
8129 operating systems, which may manage multiple chips as if
8130 they were a single (larger) device.
8131 In some cases, configuring a device will activate extra
8132 commands; see the controller-specific documentation.
8134 @b{NOTE:} This command is not available after OpenOCD
8135 initialization has completed. Use it in board specific
8136 configuration files, not interactively.
8139 @item @var{name} ... may be used to reference the NAND bank
8140 in most other NAND commands. A number is also available.
8141 @item @var{driver} ... identifies the NAND controller driver
8142 associated with the NAND device being declared.
8143 @xref{nanddriverlist,,NAND Driver List}.
8144 @item @var{target} ... names the target used when issuing
8145 commands to the NAND controller.
8146 @comment Actually, it's currently a controller-specific parameter...
8147 @item @var{configparams} ... controllers may support, or require,
8148 additional parameters. See the controller-specific documentation
8149 for more information.
8153 @deffn {Command} {nand list}
8154 Prints a summary of each device declared
8155 using @command{nand device}, numbered from zero.
8156 Note that un-probed devices show no details.
8159 #0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8160 blocksize: 131072, blocks: 8192
8161 #1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
8162 blocksize: 131072, blocks: 8192
8167 @deffn {Command} {nand probe} num
8168 Probes the specified device to determine key characteristics
8169 like its page and block sizes, and how many blocks it has.
8170 The @var{num} parameter is the value shown by @command{nand list}.
8171 You must (successfully) probe a device before you can use
8172 it with most other NAND commands.
8175 @subsection Erasing, Reading, Writing to NAND Flash
8177 @deffn {Command} {nand dump} num filename offset length [oob_option]
8178 @cindex NAND reading
8179 Reads binary data from the NAND device and writes it to the file,
8180 starting at the specified offset.
8181 The @var{num} parameter is the value shown by @command{nand list}.
8183 Use a complete path name for @var{filename}, so you don't depend
8184 on the directory used to start the OpenOCD server.
8186 The @var{offset} and @var{length} must be exact multiples of the
8187 device's page size. They describe a data region; the OOB data
8188 associated with each such page may also be accessed.
8190 @b{NOTE:} At the time this text was written, no error correction
8191 was done on the data that's read, unless raw access was disabled
8192 and the underlying NAND controller driver had a @code{read_page}
8193 method which handled that error correction.
8195 By default, only page data is saved to the specified file.
8196 Use an @var{oob_option} parameter to save OOB data:
8198 @item no oob_* parameter
8199 @*Output file holds only page data; OOB is discarded.
8200 @item @code{oob_raw}
8201 @*Output file interleaves page data and OOB data;
8202 the file will be longer than "length" by the size of the
8203 spare areas associated with each data page.
8204 Note that this kind of "raw" access is different from
8205 what's implied by @command{nand raw_access}, which just
8206 controls whether a hardware-aware access method is used.
8207 @item @code{oob_only}
8208 @*Output file has only raw OOB data, and will
8209 be smaller than "length" since it will contain only the
8210 spare areas associated with each data page.
8214 @deffn {Command} {nand erase} num [offset length]
8215 @cindex NAND erasing
8216 @cindex NAND programming
8217 Erases blocks on the specified NAND device, starting at the
8218 specified @var{offset} and continuing for @var{length} bytes.
8219 Both of those values must be exact multiples of the device's
8220 block size, and the region they specify must fit entirely in the chip.
8221 If those parameters are not specified,
8222 the whole NAND chip will be erased.
8223 The @var{num} parameter is the value shown by @command{nand list}.
8225 @b{NOTE:} This command will try to erase bad blocks, when told
8226 to do so, which will probably invalidate the manufacturer's bad
8228 For the remainder of the current server session, @command{nand info}
8229 will still report that the block ``is'' bad.
8232 @deffn {Command} {nand write} num filename offset [option...]
8233 @cindex NAND writing
8234 @cindex NAND programming
8235 Writes binary data from the file into the specified NAND device,
8236 starting at the specified offset. Those pages should already
8237 have been erased; you can't change zero bits to one bits.
8238 The @var{num} parameter is the value shown by @command{nand list}.
8240 Use a complete path name for @var{filename}, so you don't depend
8241 on the directory used to start the OpenOCD server.
8243 The @var{offset} must be an exact multiple of the device's page size.
8244 All data in the file will be written, assuming it doesn't run
8245 past the end of the device.
8246 Only full pages are written, and any extra space in the last
8247 page will be filled with 0xff bytes. (That includes OOB data,
8248 if that's being written.)
8250 @b{NOTE:} At the time this text was written, bad blocks are
8251 ignored. That is, this routine will not skip bad blocks,
8252 but will instead try to write them. This can cause problems.
8254 Provide at most one @var{option} parameter. With some
8255 NAND drivers, the meanings of these parameters may change
8256 if @command{nand raw_access} was used to disable hardware ECC.
8258 @item no oob_* parameter
8259 @*File has only page data, which is written.
8260 If raw access is in use, the OOB area will not be written.
8261 Otherwise, if the underlying NAND controller driver has
8262 a @code{write_page} routine, that routine may write the OOB
8263 with hardware-computed ECC data.
8264 @item @code{oob_only}
8265 @*File has only raw OOB data, which is written to the OOB area.
8266 Each page's data area stays untouched. @i{This can be a dangerous
8267 option}, since it can invalidate the ECC data.
8268 You may need to force raw access to use this mode.
8269 @item @code{oob_raw}
8270 @*File interleaves data and OOB data, both of which are written
8271 If raw access is enabled, the data is written first, then the
8273 Otherwise, if the underlying NAND controller driver has
8274 a @code{write_page} routine, that routine may modify the OOB
8275 before it's written, to include hardware-computed ECC data.
8276 @item @code{oob_softecc}
8277 @*File has only page data, which is written.
8278 The OOB area is filled with 0xff, except for a standard 1-bit
8279 software ECC code stored in conventional locations.
8280 You might need to force raw access to use this mode, to prevent
8281 the underlying driver from applying hardware ECC.
8282 @item @code{oob_softecc_kw}
8283 @*File has only page data, which is written.
8284 The OOB area is filled with 0xff, except for a 4-bit software ECC
8285 specific to the boot ROM in Marvell Kirkwood SoCs.
8286 You might need to force raw access to use this mode, to prevent
8287 the underlying driver from applying hardware ECC.
8291 @deffn {Command} {nand verify} num filename offset [option...]
8292 @cindex NAND verification
8293 @cindex NAND programming
8294 Verify the binary data in the file has been programmed to the
8295 specified NAND device, starting at the specified offset.
8296 The @var{num} parameter is the value shown by @command{nand list}.
8298 Use a complete path name for @var{filename}, so you don't depend
8299 on the directory used to start the OpenOCD server.
8301 The @var{offset} must be an exact multiple of the device's page size.
8302 All data in the file will be read and compared to the contents of the
8303 flash, assuming it doesn't run past the end of the device.
8304 As with @command{nand write}, only full pages are verified, so any extra
8305 space in the last page will be filled with 0xff bytes.
8307 The same @var{options} accepted by @command{nand write},
8308 and the file will be processed similarly to produce the buffers that
8309 can be compared against the contents produced from @command{nand dump}.
8311 @b{NOTE:} This will not work when the underlying NAND controller
8312 driver's @code{write_page} routine must update the OOB with a
8313 hardware-computed ECC before the data is written. This limitation may
8314 be removed in a future release.
8317 @subsection Other NAND commands
8318 @cindex NAND other commands
8320 @deffn {Command} {nand check_bad_blocks} num [offset length]
8321 Checks for manufacturer bad block markers on the specified NAND
8322 device. If no parameters are provided, checks the whole
8323 device; otherwise, starts at the specified @var{offset} and
8324 continues for @var{length} bytes.
8325 Both of those values must be exact multiples of the device's
8326 block size, and the region they specify must fit entirely in the chip.
8327 The @var{num} parameter is the value shown by @command{nand list}.
8329 @b{NOTE:} Before using this command you should force raw access
8330 with @command{nand raw_access enable} to ensure that the underlying
8331 driver will not try to apply hardware ECC.
8334 @deffn {Command} {nand info} num
8335 The @var{num} parameter is the value shown by @command{nand list}.
8336 This prints the one-line summary from "nand list", plus for
8337 devices which have been probed this also prints any known
8338 status for each block.
8341 @deffn {Command} {nand raw_access} num (@option{enable}|@option{disable})
8342 Sets or clears an flag affecting how page I/O is done.
8343 The @var{num} parameter is the value shown by @command{nand list}.
8345 This flag is cleared (disabled) by default, but changing that
8346 value won't affect all NAND devices. The key factor is whether
8347 the underlying driver provides @code{read_page} or @code{write_page}
8348 methods. If it doesn't provide those methods, the setting of
8349 this flag is irrelevant; all access is effectively ``raw''.
8351 When those methods exist, they are normally used when reading
8352 data (@command{nand dump} or reading bad block markers) or
8353 writing it (@command{nand write}). However, enabling
8354 raw access (setting the flag) prevents use of those methods,
8355 bypassing hardware ECC logic.
8356 @i{This can be a dangerous option}, since writing blocks
8357 with the wrong ECC data can cause them to be marked as bad.
8360 @anchor{nanddriverlist}
8361 @subsection NAND Driver List
8362 As noted above, the @command{nand device} command allows
8363 driver-specific options and behaviors.
8364 Some controllers also activate controller-specific commands.
8366 @deffn {NAND Driver} {at91sam9}
8367 This driver handles the NAND controllers found on AT91SAM9 family chips from
8368 Atmel. It takes two extra parameters: address of the NAND chip;
8369 address of the ECC controller.
8371 nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
8373 AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
8374 @code{read_page} methods are used to utilize the ECC hardware unless they are
8375 disabled by using the @command{nand raw_access} command. There are four
8376 additional commands that are needed to fully configure the AT91SAM9 NAND
8377 controller. Two are optional; most boards use the same wiring for ALE/CLE:
8378 @deffn {Config Command} {at91sam9 cle} num addr_line
8379 Configure the address line used for latching commands. The @var{num}
8380 parameter is the value shown by @command{nand list}.
8382 @deffn {Config Command} {at91sam9 ale} num addr_line
8383 Configure the address line used for latching addresses. The @var{num}
8384 parameter is the value shown by @command{nand list}.
8387 For the next two commands, it is assumed that the pins have already been
8388 properly configured for input or output.
8389 @deffn {Config Command} {at91sam9 rdy_busy} num pio_base_addr pin
8390 Configure the RDY/nBUSY input from the NAND device. The @var{num}
8391 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8392 is the base address of the PIO controller and @var{pin} is the pin number.
8394 @deffn {Config Command} {at91sam9 ce} num pio_base_addr pin
8395 Configure the chip enable input to the NAND device. The @var{num}
8396 parameter is the value shown by @command{nand list}. @var{pio_base_addr}
8397 is the base address of the PIO controller and @var{pin} is the pin number.
8401 @deffn {NAND Driver} {davinci}
8402 This driver handles the NAND controllers found on DaVinci family
8403 chips from Texas Instruments.
8404 It takes three extra parameters:
8405 address of the NAND chip;
8406 hardware ECC mode to use (@option{hwecc1},
8407 @option{hwecc4}, @option{hwecc4_infix});
8408 address of the AEMIF controller on this processor.
8410 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
8412 All DaVinci processors support the single-bit ECC hardware,
8413 and newer ones also support the four-bit ECC hardware.
8414 The @code{write_page} and @code{read_page} methods are used
8415 to implement those ECC modes, unless they are disabled using
8416 the @command{nand raw_access} command.
8419 @deffn {NAND Driver} {lpc3180}
8420 These controllers require an extra @command{nand device}
8421 parameter: the clock rate used by the controller.
8422 @deffn {Command} {lpc3180 select} num [mlc|slc]
8423 Configures use of the MLC or SLC controller mode.
8424 MLC implies use of hardware ECC.
8425 The @var{num} parameter is the value shown by @command{nand list}.
8428 At this writing, this driver includes @code{write_page}
8429 and @code{read_page} methods. Using @command{nand raw_access}
8430 to disable those methods will prevent use of hardware ECC
8431 in the MLC controller mode, but won't change SLC behavior.
8433 @comment current lpc3180 code won't issue 5-byte address cycles
8435 @deffn {NAND Driver} {mx3}
8436 This driver handles the NAND controller in i.MX31. The mxc driver
8437 should work for this chip as well.
8440 @deffn {NAND Driver} {mxc}
8441 This driver handles the NAND controller found in Freescale i.MX
8442 chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
8443 The driver takes 3 extra arguments, chip (@option{mx27},
8444 @option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
8445 and optionally if bad block information should be swapped between
8446 main area and spare area (@option{biswap}), defaults to off.
8448 nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
8450 @deffn {Command} {mxc biswap} bank_num [enable|disable]
8451 Turns on/off bad block information swapping from main area,
8452 without parameter query status.
8456 @deffn {NAND Driver} {orion}
8457 These controllers require an extra @command{nand device}
8458 parameter: the address of the controller.
8460 nand device orion 0xd8000000
8462 These controllers don't define any specialized commands.
8463 At this writing, their drivers don't include @code{write_page}
8464 or @code{read_page} methods, so @command{nand raw_access} won't
8465 change any behavior.
8468 @deffn {NAND Driver} {s3c2410}
8469 @deffnx {NAND Driver} {s3c2412}
8470 @deffnx {NAND Driver} {s3c2440}
8471 @deffnx {NAND Driver} {s3c2443}
8472 @deffnx {NAND Driver} {s3c6400}
8473 These S3C family controllers don't have any special
8474 @command{nand device} options, and don't define any
8475 specialized commands.
8476 At this writing, their drivers don't include @code{write_page}
8477 or @code{read_page} methods, so @command{nand raw_access} won't
8478 change any behavior.
8481 @node Flash Programming
8482 @chapter Flash Programming
8484 OpenOCD implements numerous ways to program the target flash, whether internal or external.
8485 Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB},
8486 or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}.
8488 @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage.
8489 OpenOCD will program/verify/reset the target and optionally shutdown.
8491 The script is executed as follows and by default the following actions will be performed.
8493 @item 'init' is executed.
8494 @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed.
8495 @item @code{flash write_image} is called to erase and write any flash using the filename given.
8496 @item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails.
8497 @item @code{verify_image} is called if @option{verify} parameter is given.
8498 @item @code{reset run} is called if @option{reset} parameter is given.
8499 @item OpenOCD is shutdown if @option{exit} parameter is given.
8502 An example of usage is given below. @xref{program}.
8505 # program and verify using elf/hex/s19. verify and reset
8506 # are optional parameters
8507 openocd -f board/stm32f3discovery.cfg \
8508 -c "program filename.elf verify reset exit"
8510 # binary files need the flash address passing
8511 openocd -f board/stm32f3discovery.cfg \
8512 -c "program filename.bin exit 0x08000000"
8515 @node PLD/FPGA Commands
8516 @chapter PLD/FPGA Commands
8520 Programmable Logic Devices (PLDs) and the more flexible
8521 Field Programmable Gate Arrays (FPGAs) are both types of programmable hardware.
8522 OpenOCD can support programming them.
8523 Although PLDs are generally restrictive (cells are less functional, and
8524 there are no special purpose cells for memory or computational tasks),
8525 they share the same OpenOCD infrastructure.
8526 Accordingly, both are called PLDs here.
8528 @section PLD/FPGA Configuration and Commands
8530 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
8531 OpenOCD maintains a list of PLDs available for use in various commands.
8532 Also, each such PLD requires a driver.
8534 They are referenced by the number shown by the @command{pld devices} command,
8535 and new PLDs are defined by @command{pld device driver_name}.
8537 @deffn {Config Command} {pld device} driver_name tap_name [driver_options]
8538 Defines a new PLD device, supported by driver @var{driver_name},
8539 using the TAP named @var{tap_name}.
8540 The driver may make use of any @var{driver_options} to configure its
8544 @deffn {Command} {pld devices}
8545 Lists the PLDs and their numbers.
8548 @deffn {Command} {pld load} num filename
8549 Loads the file @file{filename} into the PLD identified by @var{num}.
8550 The file format must be inferred by the driver.
8553 @section PLD/FPGA Drivers, Options, and Commands
8555 Drivers may support PLD-specific options to the @command{pld device}
8556 definition command, and may also define commands usable only with
8557 that particular type of PLD.
8559 @deffn {FPGA Driver} {virtex2} [no_jstart]
8560 Virtex-II is a family of FPGAs sold by Xilinx.
8561 It supports the IEEE 1532 standard for In-System Configuration (ISC).
8563 If @var{no_jstart} is non-zero, the JSTART instruction is not used after
8564 loading the bitstream. While required for Series2, Series3, and Series6, it
8565 breaks bitstream loading on Series7.
8567 @deffn {Command} {virtex2 read_stat} num
8568 Reads and displays the Virtex-II status register (STAT)
8573 @node General Commands
8574 @chapter General Commands
8577 The commands documented in this chapter here are common commands that
8578 you, as a human, may want to type and see the output of. Configuration type
8579 commands are documented elsewhere.
8583 @item @b{Source Of Commands}
8584 @* OpenOCD commands can occur in a configuration script (discussed
8585 elsewhere) or typed manually by a human or supplied programmatically,
8586 or via one of several TCP/IP Ports.
8588 @item @b{From the human}
8589 @* A human should interact with the telnet interface (default port: 4444)
8590 or via GDB (default port 3333).
8592 To issue commands from within a GDB session, use the @option{monitor}
8593 command, e.g. use @option{monitor poll} to issue the @option{poll}
8594 command. All output is relayed through the GDB session.
8596 @item @b{Machine Interface}
8597 The Tcl interface's intent is to be a machine interface. The default Tcl
8602 @section Server Commands
8604 @deffn {Command} {exit}
8605 Exits the current telnet session.
8608 @deffn {Command} {help} [string]
8609 With no parameters, prints help text for all commands.
8610 Otherwise, prints each helptext containing @var{string}.
8611 Not every command provides helptext.
8613 Configuration commands, and commands valid at any time, are
8614 explicitly noted in parenthesis.
8615 In most cases, no such restriction is listed; this indicates commands
8616 which are only available after the configuration stage has completed.
8619 @deffn {Command} {usage} [string]
8620 With no parameters, prints usage text for all commands. Otherwise,
8621 prints all usage text of which command, help text, and usage text
8622 containing @var{string}.
8623 Not every command provides helptext.
8626 @deffn {Command} {sleep} msec [@option{busy}]
8627 Wait for at least @var{msec} milliseconds before resuming.
8628 If @option{busy} is passed, busy-wait instead of sleeping.
8629 (This option is strongly discouraged.)
8630 Useful in connection with script files
8631 (@command{script} command and @command{target_name} configuration).
8634 @deffn {Command} {shutdown} [@option{error}]
8635 Close the OpenOCD server, disconnecting all clients (GDB, telnet,
8636 other). If option @option{error} is used, OpenOCD will return a
8637 non-zero exit code to the parent process.
8639 If user types CTRL-C or kills OpenOCD, the command @command{shutdown}
8640 will be automatically executed to cause OpenOCD to exit.
8642 It is possible to specify, in the TCL list @var{pre_shutdown_commands} , a
8643 set of commands to be automatically executed before @command{shutdown} , e.g.:
8645 lappend pre_shutdown_commands @{echo "Goodbye, my friend ..."@}
8646 lappend pre_shutdown_commands @{echo "see you soon !"@}
8648 The commands in the list will be executed (in the same order they occupy
8649 in the list) before OpenOCD exits. If one of the commands in the list
8650 fails, then the remaining commands are not executed anymore while OpenOCD
8651 will proceed to quit.
8655 @deffn {Command} {debug_level} [n]
8656 @cindex message level
8657 Display debug level.
8658 If @var{n} (from 0..4) is provided, then set it to that level.
8659 This affects the kind of messages sent to the server log.
8660 Level 0 is error messages only;
8661 level 1 adds warnings;
8662 level 2 adds informational messages;
8663 level 3 adds debugging messages;
8664 and level 4 adds verbose low-level debug messages.
8665 The default is level 2, but that can be overridden on
8666 the command line along with the location of that log
8667 file (which is normally the server's standard output).
8671 @deffn {Command} {echo} [-n] message
8672 Logs a message at "user" priority.
8673 Option "-n" suppresses trailing newline.
8675 echo "Downloading kernel -- please wait"
8679 @deffn {Command} {log_output} [filename | "default"]
8680 Redirect logging to @var{filename} or set it back to default output;
8681 the default log output channel is stderr.
8684 @deffn {Command} {add_script_search_dir} [directory]
8685 Add @var{directory} to the file/script search path.
8688 @deffn {Config Command} {bindto} [@var{name}]
8689 Specify hostname or IPv4 address on which to listen for incoming
8690 TCP/IP connections. By default, OpenOCD will listen on the loopback
8691 interface only. If your network environment is safe, @code{bindto
8692 0.0.0.0} can be used to cover all available interfaces.
8695 @anchor{targetstatehandling}
8696 @section Target State handling
8699 @cindex target initialization
8701 In this section ``target'' refers to a CPU configured as
8702 shown earlier (@pxref{CPU Configuration}).
8703 These commands, like many, implicitly refer to
8704 a current target which is used to perform the
8705 various operations. The current target may be changed
8706 by using @command{targets} command with the name of the
8707 target which should become current.
8709 @deffn {Command} {reg} [(number|name) [(value|'force')]]
8710 Access a single register by @var{number} or by its @var{name}.
8711 The target must generally be halted before access to CPU core
8712 registers is allowed. Depending on the hardware, some other
8713 registers may be accessible while the target is running.
8715 @emph{With no arguments}:
8716 list all available registers for the current target,
8717 showing number, name, size, value, and cache status.
8718 For valid entries, a value is shown; valid entries
8719 which are also dirty (and will be written back later)
8720 are flagged as such.
8722 @emph{With number/name}: display that register's value.
8723 Use @var{force} argument to read directly from the target,
8724 bypassing any internal cache.
8726 @emph{With both number/name and value}: set register's value.
8727 Writes may be held in a writeback cache internal to OpenOCD,
8728 so that setting the value marks the register as dirty instead
8729 of immediately flushing that value. Resuming CPU execution
8730 (including by single stepping) or otherwise activating the
8731 relevant module will flush such values.
8733 Cores may have surprisingly many registers in their
8734 Debug and trace infrastructure:
8739 (0) r0 (/32): 0x0000D3C2 (dirty)
8740 (1) r1 (/32): 0xFD61F31C
8743 (164) ETM_contextid_comparator_mask (/32)
8748 @deffn {Command} {set_reg} dict
8749 Set register values of the target.
8752 @item @var{dict} ... Tcl dictionary with pairs of register names and values.
8755 For example, the following command sets the value 0 to the program counter (pc)
8756 register and 0x1000 to the stack pointer (sp) register:
8759 set_reg @{pc 0 sp 0x1000@}
8763 @deffn {Command} {get_reg} [-force] list
8764 Get register values from the target and return them as Tcl dictionary with pairs
8765 of register names and values.
8766 If option "-force" is set, the register values are read directly from the
8767 target, bypassing any caching.
8770 @item @var{list} ... List of register names
8773 For example, the following command retrieves the values from the program
8774 counter (pc) and stack pointer (sp) register:
8781 @deffn {Command} {write_memory} address width data ['phys']
8782 This function provides an efficient way to write to the target memory from a Tcl
8786 @item @var{address} ... target memory address
8787 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8788 @item @var{data} ... Tcl list with the elements to write
8789 @item ['phys'] ... treat the memory address as physical instead of virtual address
8792 For example, the following command writes two 32 bit words into the target
8793 memory at address 0x20000000:
8796 write_memory 0x20000000 32 @{0xdeadbeef 0x00230500@}
8800 @deffn {Command} {read_memory} address width count ['phys']
8801 This function provides an efficient way to read the target memory from a Tcl
8803 A Tcl list containing the requested memory elements is returned by this function.
8806 @item @var{address} ... target memory address
8807 @item @var{width} ... memory access bit size, can be 8, 16, 32 or 64
8808 @item @var{count} ... number of elements to read
8809 @item ['phys'] ... treat the memory address as physical instead of virtual address
8812 For example, the following command reads two 32 bit words from the target
8813 memory at address 0x20000000:
8816 read_memory 0x20000000 32 2
8820 @deffn {Command} {halt} [ms]
8821 @deffnx {Command} {wait_halt} [ms]
8822 The @command{halt} command first sends a halt request to the target,
8823 which @command{wait_halt} doesn't.
8824 Otherwise these behave the same: wait up to @var{ms} milliseconds,
8825 or 5 seconds if there is no parameter, for the target to halt
8826 (and enter debug mode).
8827 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
8830 On ARM cores, software using the @emph{wait for interrupt} operation
8831 often blocks the JTAG access needed by a @command{halt} command.
8832 This is because that operation also puts the core into a low
8833 power mode by gating the core clock;
8834 but the core clock is needed to detect JTAG clock transitions.
8836 One partial workaround uses adaptive clocking: when the core is
8837 interrupted the operation completes, then JTAG clocks are accepted
8838 at least until the interrupt handler completes.
8839 However, this workaround is often unusable since the processor, board,
8840 and JTAG adapter must all support adaptive JTAG clocking.
8841 Also, it can't work until an interrupt is issued.
8843 A more complete workaround is to not use that operation while you
8844 work with a JTAG debugger.
8845 Tasking environments generally have idle loops where the body is the
8846 @emph{wait for interrupt} operation.
8847 (On older cores, it is a coprocessor action;
8848 newer cores have a @option{wfi} instruction.)
8849 Such loops can just remove that operation, at the cost of higher
8850 power consumption (because the CPU is needlessly clocked).
8855 @deffn {Command} {resume} [address]
8856 Resume the target at its current code position,
8857 or the optional @var{address} if it is provided.
8858 OpenOCD will wait 5 seconds for the target to resume.
8861 @deffn {Command} {step} [address]
8862 Single-step the target at its current code position,
8863 or the optional @var{address} if it is provided.
8866 @anchor{resetcommand}
8867 @deffn {Command} {reset}
8868 @deffnx {Command} {reset run}
8869 @deffnx {Command} {reset halt}
8870 @deffnx {Command} {reset init}
8871 Perform as hard a reset as possible, using SRST if possible.
8872 @emph{All defined targets will be reset, and target
8873 events will fire during the reset sequence.}
8875 The optional parameter specifies what should
8876 happen after the reset.
8877 If there is no parameter, a @command{reset run} is executed.
8878 The other options will not work on all systems.
8879 @xref{Reset Configuration}.
8882 @item @b{run} Let the target run
8883 @item @b{halt} Immediately halt the target
8884 @item @b{init} Immediately halt the target, and execute the reset-init script
8888 @deffn {Command} {soft_reset_halt}
8889 Requesting target halt and executing a soft reset. This is often used
8890 when a target cannot be reset and halted. The target, after reset is
8891 released begins to execute code. OpenOCD attempts to stop the CPU and
8892 then sets the program counter back to the reset vector. Unfortunately
8893 the code that was executed may have left the hardware in an unknown
8897 @deffn {Command} {adapter assert} [signal [assert|deassert signal]]
8898 @deffnx {Command} {adapter deassert} [signal [assert|deassert signal]]
8899 Set values of reset signals.
8900 Without parameters returns current status of the signals.
8901 The @var{signal} parameter values may be
8902 @option{srst}, indicating that srst signal is to be asserted or deasserted,
8903 @option{trst}, indicating that trst signal is to be asserted or deasserted.
8905 The @command{reset_config} command should already have been used
8906 to configure how the board and the adapter treat these two
8907 signals, and to say if either signal is even present.
8908 @xref{Reset Configuration}.
8909 Trying to assert a signal that is not present triggers an error.
8910 If a signal is present on the adapter and not specified in the command,
8911 the signal will not be modified.
8914 TRST is specially handled.
8915 It actually signifies JTAG's @sc{reset} state.
8916 So if the board doesn't support the optional TRST signal,
8917 or it doesn't support it along with the specified SRST value,
8918 JTAG reset is triggered with TMS and TCK signals
8919 instead of the TRST signal.
8920 And no matter how that JTAG reset is triggered, once
8921 the scan chain enters @sc{reset} with TRST inactive,
8922 TAP @code{post-reset} events are delivered to all TAPs
8923 with handlers for that event.
8927 @anchor{memoryaccess}
8928 @section Memory access commands
8929 @cindex memory access
8931 These commands allow accesses of a specific size to the memory
8932 system. Often these are used to configure the current target in some
8933 special way. For example - one may need to write certain values to the
8934 SDRAM controller to enable SDRAM.
8937 @item Use the @command{targets} (plural) command
8938 to change the current target.
8939 @item In system level scripts these commands are deprecated.
8940 Please use their TARGET object siblings to avoid making assumptions
8941 about what TAP is the current target, or about MMU configuration.
8944 @deffn {Command} {mdd} [phys] addr [count]
8945 @deffnx {Command} {mdw} [phys] addr [count]
8946 @deffnx {Command} {mdh} [phys] addr [count]
8947 @deffnx {Command} {mdb} [phys] addr [count]
8948 Display contents of address @var{addr}, as
8949 64-bit doublewords (@command{mdd}),
8950 32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
8951 or 8-bit bytes (@command{mdb}).
8952 When the current target has an MMU which is present and active,
8953 @var{addr} is interpreted as a virtual address.
8954 Otherwise, or if the optional @var{phys} flag is specified,
8955 @var{addr} is interpreted as a physical address.
8956 If @var{count} is specified, displays that many units.
8957 (If you want to process the data instead of displaying it,
8958 see the @code{read_memory} primitives.)
8961 @deffn {Command} {mwd} [phys] addr doubleword [count]
8962 @deffnx {Command} {mww} [phys] addr word [count]
8963 @deffnx {Command} {mwh} [phys] addr halfword [count]
8964 @deffnx {Command} {mwb} [phys] addr byte [count]
8965 Writes the specified @var{doubleword} (64 bits), @var{word} (32 bits),
8966 @var{halfword} (16 bits), or @var{byte} (8-bit) value,
8967 at the specified address @var{addr}.
8968 When the current target has an MMU which is present and active,
8969 @var{addr} is interpreted as a virtual address.
8970 Otherwise, or if the optional @var{phys} flag is specified,
8971 @var{addr} is interpreted as a physical address.
8972 If @var{count} is specified, fills that many units of consecutive address.
8975 @anchor{imageaccess}
8976 @section Image loading commands
8977 @cindex image loading
8978 @cindex image dumping
8980 @deffn {Command} {dump_image} filename address size
8981 Dump @var{size} bytes of target memory starting at @var{address} to the
8982 binary file named @var{filename}.
8985 @deffn {Command} {fast_load}
8986 Loads an image stored in memory by @command{fast_load_image} to the
8987 current target. Must be preceded by fast_load_image.
8990 @deffn {Command} {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
8991 Normally you should be using @command{load_image} or GDB load. However, for
8992 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
8993 host), storing the image in memory and uploading the image to the target
8994 can be a way to upload e.g. multiple debug sessions when the binary does not change.
8995 Arguments are the same as @command{load_image}, but the image is stored in OpenOCD host
8996 memory, i.e. does not affect target. This approach is also useful when profiling
8997 target programming performance as I/O and target programming can easily be profiled
9001 @deffn {Command} {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
9002 Load image from file @var{filename} to target memory offset by @var{address} from its load address.
9003 The file format may optionally be specified
9004 (@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
9005 In addition the following arguments may be specified:
9006 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
9007 @var{max_length} - maximum number of bytes to load.
9009 proc load_image_bin @{fname foffset address length @} @{
9010 # Load data from fname filename at foffset offset to
9011 # target at address. Load at most length bytes.
9012 load_image $fname [expr @{$address - $foffset@}] bin \
9018 @deffn {Command} {test_image} filename [address [@option{bin}|@option{ihex}|@option{elf}]]
9019 Displays image section sizes and addresses
9020 as if @var{filename} were loaded into target memory
9021 starting at @var{address} (defaults to zero).
9022 The file format may optionally be specified
9023 (@option{bin}, @option{ihex}, or @option{elf})
9026 @deffn {Command} {verify_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
9027 Verify @var{filename} against target memory starting at @var{address}.
9028 The file format may optionally be specified
9029 (@option{bin}, @option{ihex}, or @option{elf})
9030 This will first attempt a comparison using a CRC checksum, if this fails it will try a binary compare.
9033 @deffn {Command} {verify_image_checksum} filename address [@option{bin}|@option{ihex}|@option{elf}]
9034 Verify @var{filename} against target memory starting at @var{address}.
9035 The file format may optionally be specified
9036 (@option{bin}, @option{ihex}, or @option{elf})
9037 This perform a comparison using a CRC checksum only
9041 @section Breakpoint and Watchpoint commands
9045 CPUs often make debug modules accessible through JTAG, with
9046 hardware support for a handful of code breakpoints and data
9048 In addition, CPUs almost always support software breakpoints.
9050 @deffn {Command} {bp} [address len [@option{hw}]]
9051 With no parameters, lists all active breakpoints.
9052 Else sets a breakpoint on code execution starting
9053 at @var{address} for @var{length} bytes.
9054 This is a software breakpoint, unless @option{hw} is specified
9055 in which case it will be a hardware breakpoint.
9057 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
9058 for similar mechanisms that do not consume hardware breakpoints.)
9061 @deffn {Command} {rbp} @option{all} | address
9062 Remove the breakpoint at @var{address} or all breakpoints.
9065 @deffn {Command} {rwp} address
9066 Remove data watchpoint on @var{address}
9069 @deffn {Command} {wp} [address len [(@option{r}|@option{w}|@option{a}) [value [mask]]]]
9070 With no parameters, lists all active watchpoints.
9071 Else sets a data watchpoint on data from @var{address} for @var{length} bytes.
9072 The watch point is an "access" watchpoint unless
9073 the @option{r} or @option{w} parameter is provided,
9074 defining it as respectively a read or write watchpoint.
9075 If a @var{value} is provided, that value is used when determining if
9076 the watchpoint should trigger. The value may be first be masked
9077 using @var{mask} to mark ``don't care'' fields.
9081 @section Real Time Transfer (RTT)
9083 Real Time Transfer (RTT) is an interface specified by SEGGER based on basic
9084 memory reads and writes to transfer data bidirectionally between target and host.
9085 The specification is independent of the target architecture.
9086 Every target that supports so called "background memory access", which means
9087 that the target memory can be accessed by the debugger while the target is
9088 running, can be used.
9089 This interface is especially of interest for targets without
9090 Serial Wire Output (SWO), such as ARM Cortex-M0, or where semihosting is not
9091 applicable because of real-time constraints.
9094 The current implementation supports only single target devices.
9097 The data transfer between host and target device is organized through
9098 unidirectional up/down-channels for target-to-host and host-to-target
9099 communication, respectively.
9102 The current implementation does not respect channel buffer flags.
9103 They are used to determine what happens when writing to a full buffer, for
9107 Channels are exposed via raw TCP/IP connections. One or more RTT servers can be
9108 assigned to each channel to make them accessible to an unlimited number
9109 of TCP/IP connections.
9111 @deffn {Command} {rtt setup} address size ID
9112 Configure RTT for the currently selected target.
9113 Once RTT is started, OpenOCD searches for a control block with the
9114 identifier @var{ID} starting at the memory address @var{address} within the next
9118 @deffn {Command} {rtt start}
9120 If the control block location is not known, OpenOCD starts searching for it.
9123 @deffn {Command} {rtt stop}
9127 @deffn {Command} {rtt polling_interval} [interval]
9128 Display the polling interval.
9129 If @var{interval} is provided, set the polling interval.
9130 The polling interval determines (in milliseconds) how often the up-channels are
9131 checked for new data.
9134 @deffn {Command} {rtt channels}
9135 Display a list of all channels and their properties.
9138 @deffn {Command} {rtt channellist}
9139 Return a list of all channels and their properties as Tcl list.
9140 The list can be manipulated easily from within scripts.
9143 @deffn {Command} {rtt server start} port channel
9144 Start a TCP server on @var{port} for the channel @var{channel}.
9147 @deffn {Command} {rtt server stop} port
9148 Stop the TCP sever with port @var{port}.
9151 The following example shows how to setup RTT using the SEGGER RTT implementation
9152 on the target device.
9157 rtt setup 0x20000000 2048 "SEGGER RTT"
9160 rtt server start 9090 0
9163 In this example, OpenOCD searches the control block with the ID "SEGGER RTT"
9164 starting at 0x20000000 for 2048 bytes. The RTT channel 0 is exposed through the
9168 @section Misc Commands
9171 @deffn {Command} {profile} seconds filename [start end]
9172 Profiling samples the CPU's program counter as quickly as possible,
9173 which is useful for non-intrusive stochastic profiling.
9174 Saves up to 10000 samples in @file{filename} using ``gmon.out''
9175 format. Optional @option{start} and @option{end} parameters allow to
9176 limit the address range.
9179 @deffn {Command} {version}
9180 Displays a string identifying the version of this OpenOCD server.
9183 @deffn {Command} {virt2phys} virtual_address
9184 Requests the current target to map the specified @var{virtual_address}
9185 to its corresponding physical address, and displays the result.
9188 @deffn {Command} {add_help_text} 'command_name' 'help-string'
9189 Add or replace help text on the given @var{command_name}.
9192 @deffn {Command} {add_usage_text} 'command_name' 'help-string'
9193 Add or replace usage text on the given @var{command_name}.
9196 @node Architecture and Core Commands
9197 @chapter Architecture and Core Commands
9198 @cindex Architecture Specific Commands
9199 @cindex Core Specific Commands
9201 Most CPUs have specialized JTAG operations to support debugging.
9202 OpenOCD packages most such operations in its standard command framework.
9203 Some of those operations don't fit well in that framework, so they are
9204 exposed here as architecture or implementation (core) specific commands.
9206 @anchor{armhardwaretracing}
9207 @section ARM Hardware Tracing
9212 CPUs based on ARM cores may include standard tracing interfaces,
9213 based on an ``Embedded Trace Module'' (ETM) which sends voluminous
9214 address and data bus trace records to a ``Trace Port''.
9218 Development-oriented boards will sometimes provide a high speed
9219 trace connector for collecting that data, when the particular CPU
9220 supports such an interface.
9221 (The standard connector is a 38-pin Mictor, with both JTAG
9222 and trace port support.)
9223 Those trace connectors are supported by higher end JTAG adapters
9224 and some logic analyzer modules; frequently those modules can
9225 buffer several megabytes of trace data.
9226 Configuring an ETM coupled to such an external trace port belongs
9227 in the board-specific configuration file.
9229 If the CPU doesn't provide an external interface, it probably
9230 has an ``Embedded Trace Buffer'' (ETB) on the chip, which is a
9231 dedicated SRAM. 4KBytes is one common ETB size.
9232 Configuring an ETM coupled only to an ETB belongs in the CPU-specific
9233 (target) configuration file, since it works the same on all boards.
9236 ETM support in OpenOCD doesn't seem to be widely used yet.
9239 ETM support may be buggy, and at least some @command{etm config}
9240 parameters should be detected by asking the ETM for them.
9242 ETM trigger events could also implement a kind of complex
9243 hardware breakpoint, much more powerful than the simple
9244 watchpoint hardware exported by EmbeddedICE modules.
9245 @emph{Such breakpoints can be triggered even when using the
9246 dummy trace port driver}.
9248 It seems like a GDB hookup should be possible,
9249 as well as tracing only during specific states
9250 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
9252 There should be GUI tools to manipulate saved trace data and help
9253 analyse it in conjunction with the source code.
9254 It's unclear how much of a common interface is shared
9255 with the current XScale trace support, or should be
9256 shared with eventual Nexus-style trace module support.
9258 At this writing (November 2009) only ARM7, ARM9, and ARM11 support
9259 for ETM modules is available. The code should be able to
9260 work with some newer cores; but not all of them support
9261 this original style of JTAG access.
9264 @subsection ETM Configuration
9265 ETM setup is coupled with the trace port driver configuration.
9267 @deffn {Config Command} {etm config} target width mode clocking driver
9268 Declares the ETM associated with @var{target}, and associates it
9269 with a given trace port @var{driver}. @xref{traceportdrivers,,Trace Port Drivers}.
9271 Several of the parameters must reflect the trace port capabilities,
9272 which are a function of silicon capabilities (exposed later
9273 using @command{etm info}) and of what hardware is connected to
9274 that port (such as an external pod, or ETB).
9275 The @var{width} must be either 4, 8, or 16,
9276 except with ETMv3.0 and newer modules which may also
9277 support 1, 2, 24, 32, 48, and 64 bit widths.
9278 (With those versions, @command{etm info} also shows whether
9279 the selected port width and mode are supported.)
9281 The @var{mode} must be @option{normal}, @option{multiplexed},
9282 or @option{demultiplexed}.
9283 The @var{clocking} must be @option{half} or @option{full}.
9286 With ETMv3.0 and newer, the bits set with the @var{mode} and
9287 @var{clocking} parameters both control the mode.
9288 This modified mode does not map to the values supported by
9289 previous ETM modules, so this syntax is subject to change.
9293 You can see the ETM registers using the @command{reg} command.
9294 Not all possible registers are present in every ETM.
9295 Most of the registers are write-only, and are used to configure
9296 what CPU activities are traced.
9300 @deffn {Command} {etm info}
9301 Displays information about the current target's ETM.
9302 This includes resource counts from the @code{ETM_CONFIG} register,
9303 as well as silicon capabilities (except on rather old modules).
9304 from the @code{ETM_SYS_CONFIG} register.
9307 @deffn {Command} {etm status}
9308 Displays status of the current target's ETM and trace port driver:
9309 is the ETM idle, or is it collecting data?
9310 Did trace data overflow?
9314 @deffn {Command} {etm tracemode} [type context_id_bits cycle_accurate branch_output]
9315 Displays what data that ETM will collect.
9316 If arguments are provided, first configures that data.
9317 When the configuration changes, tracing is stopped
9318 and any buffered trace data is invalidated.
9321 @item @var{type} ... describing how data accesses are traced,
9322 when they pass any ViewData filtering that was set up.
9324 @option{none} (save nothing),
9325 @option{data} (save data),
9326 @option{address} (save addresses),
9327 @option{all} (save data and addresses)
9328 @item @var{context_id_bits} ... 0, 8, 16, or 32
9329 @item @var{cycle_accurate} ... @option{enable} or @option{disable}
9330 cycle-accurate instruction tracing.
9331 Before ETMv3, enabling this causes much extra data to be recorded.
9332 @item @var{branch_output} ... @option{enable} or @option{disable}.
9333 Disable this unless you need to try reconstructing the instruction
9334 trace stream without an image of the code.
9338 @deffn {Command} {etm trigger_debug} (@option{enable}|@option{disable})
9339 Displays whether ETM triggering debug entry (like a breakpoint) is
9340 enabled or disabled, after optionally modifying that configuration.
9341 The default behaviour is @option{disable}.
9342 Any change takes effect after the next @command{etm start}.
9344 By using script commands to configure ETM registers, you can make the
9345 processor enter debug state automatically when certain conditions,
9346 more complex than supported by the breakpoint hardware, happen.
9349 @subsection ETM Trace Operation
9351 After setting up the ETM, you can use it to collect data.
9352 That data can be exported to files for later analysis.
9353 It can also be parsed with OpenOCD, for basic sanity checking.
9355 To configure what is being traced, you will need to write
9356 various trace registers using @command{reg ETM_*} commands.
9357 For the definitions of these registers, read ARM publication
9358 @emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
9359 Be aware that most of the relevant registers are write-only,
9360 and that ETM resources are limited. There are only a handful
9361 of address comparators, data comparators, counters, and so on.
9363 Examples of scenarios you might arrange to trace include:
9366 @item Code flow within a function, @emph{excluding} subroutines
9367 it calls. Use address range comparators to enable tracing
9368 for instruction access within that function's body.
9369 @item Code flow within a function, @emph{including} subroutines
9370 it calls. Use the sequencer and address comparators to activate
9371 tracing on an ``entered function'' state, then deactivate it by
9372 exiting that state when the function's exit code is invoked.
9373 @item Code flow starting at the fifth invocation of a function,
9374 combining one of the above models with a counter.
9375 @item CPU data accesses to the registers for a particular device,
9376 using address range comparators and the ViewData logic.
9377 @item Such data accesses only during IRQ handling, combining the above
9378 model with sequencer triggers which on entry and exit to the IRQ handler.
9379 @item @emph{... more}
9382 At this writing, September 2009, there are no Tcl utility
9383 procedures to help set up any common tracing scenarios.
9385 @deffn {Command} {etm analyze}
9386 Reads trace data into memory, if it wasn't already present.
9387 Decodes and prints the data that was collected.
9390 @deffn {Command} {etm dump} filename
9391 Stores the captured trace data in @file{filename}.
9394 @deffn {Command} {etm image} filename [base_address] [type]
9395 Opens an image file.
9398 @deffn {Command} {etm load} filename
9399 Loads captured trace data from @file{filename}.
9402 @deffn {Command} {etm start}
9403 Starts trace data collection.
9406 @deffn {Command} {etm stop}
9407 Stops trace data collection.
9410 @anchor{traceportdrivers}
9411 @subsection Trace Port Drivers
9413 To use an ETM trace port it must be associated with a driver.
9415 @deffn {Trace Port Driver} {dummy}
9416 Use the @option{dummy} driver if you are configuring an ETM that's
9417 not connected to anything (on-chip ETB or off-chip trace connector).
9418 @emph{This driver lets OpenOCD talk to the ETM, but it does not expose
9419 any trace data collection.}
9420 @deffn {Config Command} {etm_dummy config} target
9421 Associates the ETM for @var{target} with a dummy driver.
9425 @deffn {Trace Port Driver} {etb}
9426 Use the @option{etb} driver if you are configuring an ETM
9427 to use on-chip ETB memory.
9428 @deffn {Config Command} {etb config} target etb_tap
9429 Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
9430 You can see the ETB registers using the @command{reg} command.
9432 @deffn {Command} {etb trigger_percent} [percent]
9433 This displays, or optionally changes, ETB behavior after the
9434 ETM's configured @emph{trigger} event fires.
9435 It controls how much more trace data is saved after the (single)
9436 trace trigger becomes active.
9439 @item The default corresponds to @emph{trace around} usage,
9440 recording 50 percent data before the event and the rest
9442 @item The minimum value of @var{percent} is 2 percent,
9443 recording almost exclusively data before the trigger.
9444 Such extreme @emph{trace before} usage can help figure out
9445 what caused that event to happen.
9446 @item The maximum value of @var{percent} is 100 percent,
9447 recording data almost exclusively after the event.
9448 This extreme @emph{trace after} usage might help sort out
9449 how the event caused trouble.
9451 @c REVISIT allow "break" too -- enter debug mode.
9456 @anchor{armcrosstrigger}
9457 @section ARM Cross-Trigger Interface
9460 The ARM Cross-Trigger Interface (CTI) is a generic CoreSight component
9461 that connects event sources like tracing components or CPU cores with each
9462 other through a common trigger matrix (CTM). For ARMv8 architecture, a
9463 CTI is mandatory for core run control and each core has an individual
9464 CTI instance attached to it. OpenOCD has limited support for CTI using
9465 the @emph{cti} group of commands.
9467 @deffn {Command} {cti create} cti_name @option{-dap} dap_name @option{-ap-num} apn @option{-baseaddr} base_address
9468 Creates a CTI instance @var{cti_name} on the DAP instance @var{dap_name} on MEM-AP
9470 On ADIv5 DAP @var{apn} is the numeric index of the DAP AP the CTI is connected to.
9471 On ADIv6 DAP @var{apn} is the base address of the DAP AP the CTI is connected to.
9472 The @var{base_address} must match the base address of the CTI
9473 on the respective MEM-AP. All arguments are mandatory. This creates a
9474 new command @command{$cti_name} which is used for various purposes
9475 including additional configuration.
9478 @deffn {Command} {$cti_name enable} @option{on|off}
9479 Enable (@option{on}) or disable (@option{off}) the CTI.
9482 @deffn {Command} {$cti_name dump}
9483 Displays a register dump of the CTI.
9486 @deffn {Command} {$cti_name write} @var{reg_name} @var{value}
9487 Write @var{value} to the CTI register with the symbolic name @var{reg_name}.
9490 @deffn {Command} {$cti_name read} @var{reg_name}
9491 Print the value read from the CTI register with the symbolic name @var{reg_name}.
9494 @deffn {Command} {$cti_name ack} @var{event}
9495 Acknowledge a CTI @var{event}.
9498 @deffn {Command} {$cti_name channel} @var{channel_number} @var{operation}
9499 Perform a specific channel operation, the possible operations are:
9500 gate, ungate, set, clear and pulse
9503 @deffn {Command} {$cti_name testmode} @option{on|off}
9504 Enable (@option{on}) or disable (@option{off}) the integration test mode
9508 @deffn {Command} {cti names}
9509 Prints a list of names of all CTI objects created. This command is mainly
9510 useful in TCL scripting.
9513 @section Generic ARM
9516 These commands should be available on all ARM processors.
9517 They are available in addition to other core-specific
9518 commands that may be available.
9520 @deffn {Command} {arm core_state} [@option{arm}|@option{thumb}]
9521 Displays the core_state, optionally changing it to process
9522 either @option{arm} or @option{thumb} instructions.
9523 The target may later be resumed in the currently set core_state.
9524 (Processors may also support the Jazelle state, but
9525 that is not currently supported in OpenOCD.)
9528 @deffn {Command} {arm disassemble} address [count [@option{thumb}]]
9530 Disassembles @var{count} instructions starting at @var{address}.
9531 If @var{count} is not specified, a single instruction is disassembled.
9532 If @option{thumb} is specified, or the low bit of the address is set,
9533 Thumb2 (mixed 16/32-bit) instructions are used;
9534 else ARM (32-bit) instructions are used.
9535 (Processors may also support the Jazelle state, but
9536 those instructions are not currently understood by OpenOCD.)
9538 Note that all Thumb instructions are Thumb2 instructions,
9539 so older processors (without Thumb2 support) will still
9540 see correct disassembly of Thumb code.
9541 Also, ThumbEE opcodes are the same as Thumb2,
9542 with a handful of exceptions.
9543 ThumbEE disassembly currently has no explicit support.
9546 @deffn {Command} {arm mcr} pX op1 CRn CRm op2 value
9547 Write @var{value} to a coprocessor @var{pX} register
9548 passing parameters @var{CRn},
9549 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9550 and using the MCR instruction.
9551 (Parameter sequence matches the ARM instruction, but omits
9555 @deffn {Command} {arm mrc} pX coproc op1 CRn CRm op2
9556 Read a coprocessor @var{pX} register passing parameters @var{CRn},
9557 @var{CRm}, opcodes @var{opc1} and @var{opc2},
9558 and the MRC instruction.
9559 Returns the result so it can be manipulated by Jim scripts.
9560 (Parameter sequence matches the ARM instruction, but omits
9564 @deffn {Command} {arm reg}
9565 Display a table of all banked core registers, fetching the current value from every
9566 core mode if necessary.
9569 @deffn {Command} {arm semihosting} [@option{enable}|@option{disable}]
9570 @cindex ARM semihosting
9571 Display status of semihosting, after optionally changing that status.
9573 Semihosting allows for code executing on an ARM target to use the
9574 I/O facilities on the host computer i.e. the system where OpenOCD
9575 is running. The target application must be linked against a library
9576 implementing the ARM semihosting convention that forwards operation
9577 requests by using a special SVC instruction that is trapped at the
9578 Supervisor Call vector by OpenOCD.
9581 @deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
9582 [@option{debug}|@option{stdio}|@option{all})
9583 @cindex ARM semihosting
9584 Redirect semihosting messages to a specified TCP port.
9586 This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
9587 semihosting operations to the specified TCP port.
9588 The command allows to select which type of operations to redirect (debug, stdio, all (default)).
9589 Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
9592 @deffn {Command} {arm semihosting_cmdline} [@option{enable}|@option{disable}]
9593 @cindex ARM semihosting
9594 Set the command line to be passed to the debugger.
9597 arm semihosting_cmdline argv0 argv1 argv2 ...
9600 This option lets one set the command line arguments to be passed to
9601 the program. The first argument (argv0) is the program name in a
9602 standard C environment (argv[0]). Depending on the program (not much
9603 programs look at argv[0]), argv0 is ignored and can be any string.
9606 @deffn {Command} {arm semihosting_fileio} [@option{enable}|@option{disable}]
9607 @cindex ARM semihosting
9608 Display status of semihosting fileio, after optionally changing that
9611 Enabling this option forwards semihosting I/O to GDB process using the
9612 File-I/O remote protocol extension. This is especially useful for
9613 interacting with remote files or displaying console messages in the
9617 @deffn {Command} {arm semihosting_resexit} [@option{enable}|@option{disable}]
9618 @cindex ARM semihosting
9619 Enable resumable SEMIHOSTING_SYS_EXIT.
9621 When SEMIHOSTING_SYS_EXIT is called outside a debug session,
9622 things are simple, the openocd process calls exit() and passes
9623 the value returned by the target.
9625 When SEMIHOSTING_SYS_EXIT is called during a debug session,
9626 by default execution returns to the debugger, leaving the
9627 debugger in a HALT state, similar to the state entered when
9628 encountering a break.
9630 In some use cases, it is useful to have SEMIHOSTING_SYS_EXIT
9631 return normally, as any semihosting call, and do not break
9633 The standard allows this to happen, but the condition
9634 to trigger it is a bit obscure ("by performing an RDI_Execute
9635 request or equivalent").
9637 To make the SEMIHOSTING_SYS_EXIT call return normally, enable
9638 this option (default: disabled).
9641 @deffn {Command} {arm semihosting_read_user_param}
9642 @cindex ARM semihosting
9643 Read parameter of the semihosting call from the target. Usable in
9644 semihosting-user-cmd-0x10* event handlers, returning a string.
9646 When the target makes semihosting call with operation number from range 0x100-
9647 0x107, an optional string parameter can be passed to the server. This parameter
9648 is valid during the run of the event handlers and is accessible with this
9652 @deffn {Command} {arm semihosting_basedir} [dir]
9653 @cindex ARM semihosting
9654 Set the base directory for semihosting I/O, either an absolute path or a path relative to OpenOCD working directory.
9655 Use "." for the current directory.
9658 @section ARMv4 and ARMv5 Architecture
9662 The ARMv4 and ARMv5 architectures are widely used in embedded systems,
9663 and introduced core parts of the instruction set in use today.
9664 That includes the Thumb instruction set, introduced in the ARMv4T
9667 @subsection ARM7 and ARM9 specific commands
9671 These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
9672 ARM9TDMI, ARM920T or ARM926EJ-S.
9673 They are available in addition to the ARM commands,
9674 and any other core-specific commands that may be available.
9676 @deffn {Command} {arm7_9 dbgrq} [@option{enable}|@option{disable}]
9677 Displays the value of the flag controlling use of the
9678 EmbeddedIce DBGRQ signal to force entry into debug mode,
9679 instead of breakpoints.
9680 If a boolean parameter is provided, first assigns that flag.
9683 safe for all but ARM7TDMI-S cores (like NXP LPC).
9684 This feature is enabled by default on most ARM9 cores,
9685 including ARM9TDMI, ARM920T, and ARM926EJ-S.
9688 @deffn {Command} {arm7_9 dcc_downloads} [@option{enable}|@option{disable}]
9690 Displays the value of the flag controlling use of the debug communications
9691 channel (DCC) to write larger (>128 byte) amounts of memory.
9692 If a boolean parameter is provided, first assigns that flag.
9694 DCC downloads offer a huge speed increase, but might be
9695 unsafe, especially with targets running at very low speeds. This command was introduced
9696 with OpenOCD rev. 60, and requires a few bytes of working area.
9699 @deffn {Command} {arm7_9 fast_memory_access} [@option{enable}|@option{disable}]
9700 Displays the value of the flag controlling use of memory writes and reads
9701 that don't check completion of the operation.
9702 If a boolean parameter is provided, first assigns that flag.
9704 This provides a huge speed increase, especially with USB JTAG
9705 cables (FT2232), but might be unsafe if used with targets running at very low
9706 speeds, like the 32kHz startup clock of an AT91RM9200.
9709 @subsection ARM9 specific commands
9712 ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
9714 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
9716 @c 9-june-2009: tried this on arm920t, it didn't work.
9717 @c no-params always lists nothing caught, and that's how it acts.
9718 @c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
9719 @c versions have different rules about when they commit writes.
9721 @anchor{arm9vectorcatch}
9722 @deffn {Command} {arm9 vector_catch} [@option{all}|@option{none}|list]
9723 @cindex vector_catch
9724 Vector Catch hardware provides a sort of dedicated breakpoint
9725 for hardware events such as reset, interrupt, and abort.
9726 You can use this to conserve normal breakpoint resources,
9727 so long as you're not concerned with code that branches directly
9728 to those hardware vectors.
9730 This always finishes by listing the current configuration.
9731 If parameters are provided, it first reconfigures the
9732 vector catch hardware to intercept
9733 @option{all} of the hardware vectors,
9734 @option{none} of them,
9735 or a list with one or more of the following:
9736 @option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
9737 @option{irq} @option{fiq}.
9740 @subsection ARM920T specific commands
9743 These commands are available to ARM920T based CPUs,
9744 which are implementations of the ARMv4T architecture
9745 built using the ARM9TDMI integer core.
9746 They are available in addition to the ARM, ARM7/ARM9,
9749 @deffn {Command} {arm920t cache_info}
9750 Print information about the caches found. This allows to see whether your target
9751 is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
9754 @deffn {Command} {arm920t cp15} regnum [value]
9755 Display cp15 register @var{regnum};
9756 else if a @var{value} is provided, that value is written to that register.
9757 This uses "physical access" and the register number is as
9758 shown in bits 38..33 of table 9-9 in the ARM920T TRM.
9759 (Not all registers can be written.)
9762 @deffn {Command} {arm920t read_cache} filename
9763 Dump the content of ICache and DCache to a file named @file{filename}.
9766 @deffn {Command} {arm920t read_mmu} filename
9767 Dump the content of the ITLB and DTLB to a file named @file{filename}.
9770 @subsection ARM926ej-s specific commands
9773 These commands are available to ARM926ej-s based CPUs,
9774 which are implementations of the ARMv5TEJ architecture
9775 based on the ARM9EJ-S integer core.
9776 They are available in addition to the ARM, ARM7/ARM9,
9779 The Feroceon cores also support these commands, although
9780 they are not built from ARM926ej-s designs.
9782 @deffn {Command} {arm926ejs cache_info}
9783 Print information about the caches found.
9786 @subsection ARM966E specific commands
9789 These commands are available to ARM966 based CPUs,
9790 which are implementations of the ARMv5TE architecture.
9791 They are available in addition to the ARM, ARM7/ARM9,
9794 @deffn {Command} {arm966e cp15} regnum [value]
9795 Display cp15 register @var{regnum};
9796 else if a @var{value} is provided, that value is written to that register.
9797 The six bit @var{regnum} values are bits 37..32 from table 7-2 of the
9799 There is no current control over bits 31..30 from that table,
9800 as required for BIST support.
9803 @subsection XScale specific commands
9806 Some notes about the debug implementation on the XScale CPUs:
9808 The XScale CPU provides a special debug-only mini-instruction cache
9809 (mini-IC) in which exception vectors and target-resident debug handler
9810 code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
9811 must point vector 0 (the reset vector) to the entry of the debug
9812 handler. However, this means that the complete first cacheline in the
9813 mini-IC is marked valid, which makes the CPU fetch all exception
9814 handlers from the mini-IC, ignoring the code in RAM.
9816 To address this situation, OpenOCD provides the @code{xscale
9817 vector_table} command, which allows the user to explicitly write
9818 individual entries to either the high or low vector table stored in
9821 It is recommended to place a pc-relative indirect branch in the vector
9822 table, and put the branch destination somewhere in memory. Doing so
9823 makes sure the code in the vector table stays constant regardless of
9824 code layout in memory:
9827 ldr pc,[pc,#0x100-8]
9828 ldr pc,[pc,#0x100-8]
9829 ldr pc,[pc,#0x100-8]
9830 ldr pc,[pc,#0x100-8]
9831 ldr pc,[pc,#0x100-8]
9832 ldr pc,[pc,#0x100-8]
9833 ldr pc,[pc,#0x100-8]
9834 ldr pc,[pc,#0x100-8]
9836 .long real_reset_vector
9837 .long real_ui_handler
9838 .long real_swi_handler
9840 .long real_data_abort
9841 .long 0 /* unused */
9842 .long real_irq_handler
9843 .long real_fiq_handler
9846 Alternatively, you may choose to keep some or all of the mini-IC
9847 vector table entries synced with those written to memory by your
9848 system software. The mini-IC can not be modified while the processor
9849 is executing, but for each vector table entry not previously defined
9850 using the @code{xscale vector_table} command, OpenOCD will copy the
9851 value from memory to the mini-IC every time execution resumes from a
9852 halt. This is done for both high and low vector tables (although the
9853 table not in use may not be mapped to valid memory, and in this case
9854 that copy operation will silently fail). This means that you will
9855 need to briefly halt execution at some strategic point during system
9856 start-up; e.g., after the software has initialized the vector table,
9857 but before exceptions are enabled. A breakpoint can be used to
9858 accomplish this once the appropriate location in the start-up code has
9859 been identified. A watchpoint over the vector table region is helpful
9860 in finding the location if you're not sure. Note that the same
9861 situation exists any time the vector table is modified by the system
9864 The debug handler must be placed somewhere in the address space using
9865 the @code{xscale debug_handler} command. The allowed locations for the
9866 debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
9867 0xfffff800). The default value is 0xfe000800.
9869 XScale has resources to support two hardware breakpoints and two
9870 watchpoints. However, the following restrictions on watchpoint
9871 functionality apply: (1) the value and mask arguments to the @code{wp}
9872 command are not supported, (2) the watchpoint length must be a
9873 power of two and not less than four, and can not be greater than the
9874 watchpoint address, and (3) a watchpoint with a length greater than
9875 four consumes all the watchpoint hardware resources. This means that
9876 at any one time, you can have enabled either two watchpoints with a
9877 length of four, or one watchpoint with a length greater than four.
9879 These commands are available to XScale based CPUs,
9880 which are implementations of the ARMv5TE architecture.
9882 @deffn {Command} {xscale analyze_trace}
9883 Displays the contents of the trace buffer.
9886 @deffn {Command} {xscale cache_clean_address} address
9887 Changes the address used when cleaning the data cache.
9890 @deffn {Command} {xscale cache_info}
9891 Displays information about the CPU caches.
9894 @deffn {Command} {xscale cp15} regnum [value]
9895 Display cp15 register @var{regnum};
9896 else if a @var{value} is provided, that value is written to that register.
9899 @deffn {Command} {xscale debug_handler} target address
9900 Changes the address used for the specified target's debug handler.
9903 @deffn {Command} {xscale dcache} [@option{enable}|@option{disable}]
9904 Enables or disable the CPU's data cache.
9907 @deffn {Command} {xscale dump_trace} filename
9908 Dumps the raw contents of the trace buffer to @file{filename}.
9911 @deffn {Command} {xscale icache} [@option{enable}|@option{disable}]
9912 Enables or disable the CPU's instruction cache.
9915 @deffn {Command} {xscale mmu} [@option{enable}|@option{disable}]
9916 Enables or disable the CPU's memory management unit.
9919 @deffn {Command} {xscale trace_buffer} [@option{enable}|@option{disable} [@option{fill} [n] | @option{wrap}]]
9920 Displays the trace buffer status, after optionally
9921 enabling or disabling the trace buffer
9922 and modifying how it is emptied.
9925 @deffn {Command} {xscale trace_image} filename [offset [type]]
9926 Opens a trace image from @file{filename}, optionally rebasing
9927 its segment addresses by @var{offset}.
9928 The image @var{type} may be one of
9929 @option{bin} (binary), @option{ihex} (Intel hex),
9930 @option{elf} (ELF file), @option{s19} (Motorola s19),
9931 @option{mem}, or @option{builder}.
9934 @anchor{xscalevectorcatch}
9935 @deffn {Command} {xscale vector_catch} [mask]
9936 @cindex vector_catch
9937 Display a bitmask showing the hardware vectors to catch.
9938 If the optional parameter is provided, first set the bitmask to that value.
9940 The mask bits correspond with bit 16..23 in the DCSR:
9943 0x02 Trap Undefined Instructions
9944 0x04 Trap Software Interrupt
9945 0x08 Trap Prefetch Abort
9946 0x10 Trap Data Abort
9953 @deffn {Command} {xscale vector_table} [(@option{low}|@option{high}) index value]
9954 @cindex vector_table
9956 Set an entry in the mini-IC vector table. There are two tables: one for
9957 low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
9958 holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
9959 points to the debug handler entry and can not be overwritten.
9960 @var{value} holds the 32-bit opcode that is placed in the mini-IC.
9962 Without arguments, the current settings are displayed.
9966 @section ARMv6 Architecture
9969 @subsection ARM11 specific commands
9972 @deffn {Command} {arm11 memwrite burst} [@option{enable}|@option{disable}]
9973 Displays the value of the memwrite burst-enable flag,
9974 which is enabled by default.
9975 If a boolean parameter is provided, first assigns that flag.
9976 Burst writes are only used for memory writes larger than 1 word.
9977 They improve performance by assuming that the CPU has read each data
9978 word over JTAG and completed its write before the next word arrives,
9979 instead of polling for a status flag to verify that completion.
9980 This is usually safe, because JTAG runs much slower than the CPU.
9983 @deffn {Command} {arm11 memwrite error_fatal} [@option{enable}|@option{disable}]
9984 Displays the value of the memwrite error_fatal flag,
9985 which is enabled by default.
9986 If a boolean parameter is provided, first assigns that flag.
9987 When set, certain memory write errors cause earlier transfer termination.
9990 @deffn {Command} {arm11 step_irq_enable} [@option{enable}|@option{disable}]
9991 Displays the value of the flag controlling whether
9992 IRQs are enabled during single stepping;
9993 they are disabled by default.
9994 If a boolean parameter is provided, first assigns that.
9997 @deffn {Command} {arm11 vcr} [value]
9998 @cindex vector_catch
9999 Displays the value of the @emph{Vector Catch Register (VCR)},
10000 coprocessor 14 register 7.
10001 If @var{value} is defined, first assigns that.
10003 Vector Catch hardware provides dedicated breakpoints
10004 for certain hardware events.
10005 The specific bit values are core-specific (as in fact is using
10006 coprocessor 14 register 7 itself) but all current ARM11
10007 cores @emph{except the ARM1176} use the same six bits.
10010 @section ARMv7 and ARMv8 Architecture
10014 @subsection ARMv7-A specific commands
10017 @deffn {Command} {cortex_a cache_info}
10018 display information about target caches
10021 @deffn {Command} {cortex_a dacrfixup} [@option{on}|@option{off}]
10022 Work around issues with software breakpoints when the program text is
10023 mapped read-only by the operating system. This option sets the CP15 DACR
10024 to "all-manager" to bypass MMU permission checks on memory access.
10028 @deffn {Command} {cortex_a dbginit}
10029 Initialize core debug
10030 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10033 @deffn {Command} {cortex_a smp} [on|off]
10034 Display/set the current SMP mode
10037 @deffn {Command} {cortex_a smp_gdb} [core_id]
10038 Display/set the current core displayed in GDB
10041 @deffn {Command} {cortex_a maskisr} [@option{on}|@option{off}]
10042 Selects whether interrupts will be processed when single stepping
10045 @deffn {Command} {cache_config l2x} [base way]
10046 configure l2x cache
10049 @deffn {Command} {cortex_a mmu dump} [@option{0}|@option{1}|@option{addr} address [@option{num_entries}]]
10050 Dump the MMU translation table from TTB0 or TTB1 register, or from physical
10051 memory location @var{address}. When dumping the table from @var{address}, print at most
10052 @var{num_entries} page table entries. @var{num_entries} is optional, if omitted, the maximum
10053 possible (4096) entries are printed.
10056 @subsection ARMv7-R specific commands
10059 @deffn {Command} {cortex_r4 dbginit}
10060 Initialize core debug
10061 Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
10064 @deffn {Command} {cortex_r4 maskisr} [@option{on}|@option{off}]
10065 Selects whether interrupts will be processed when single stepping
10069 @subsection ARM CoreSight TPIU and SWO specific commands
10075 ARM CoreSight provides several modules to generate debugging
10076 information internally (ITM, DWT and ETM). Their output is directed
10077 through TPIU or SWO modules to be captured externally either on an SWO pin (this
10078 configuration is called SWV) or on a synchronous parallel trace port.
10080 ARM CoreSight provides independent HW blocks named TPIU and SWO each with its
10081 own functionality. Embedded in Cortex-M3 and M4, ARM provides an optional HW
10082 block that includes both TPIU and SWO functionalities and is again named TPIU,
10083 which causes quite some confusion.
10084 The registers map of all the TPIU and SWO implementations allows using a single
10085 driver that detects at runtime the features available.
10087 The @command{tpiu} is used for either TPIU or SWO.
10088 A convenient alias @command{swo} is available to help distinguish, in scripts,
10089 the commands for SWO from the commands for TPIU.
10091 @deffn {Command} {swo} ...
10092 Alias of @command{tpiu ...}. Can be used in scripts to distinguish the commands
10093 for SWO from the commands for TPIU.
10096 @deffn {Command} {tpiu create} tpiu_name configparams...
10097 Creates a TPIU or a SWO object. The two commands are equivalent.
10098 Add the object in a list and add new commands (@command{@var{tpiu_name}})
10099 which are used for various purposes including additional configuration.
10102 @item @var{tpiu_name} -- the name of the TPIU or SWO object.
10103 This name is also used to create the object's command, referred to here
10104 as @command{$tpiu_name}, and in other places where the TPIU or SWO needs to be identified.
10105 @item @var{configparams} -- all parameters accepted by @command{$tpiu_name configure} are permitted.
10107 You @emph{must} set here the AP and MEM_AP base_address through @code{-dap @var{dap_name}},
10108 @code{-ap-num @var{ap_number}} and @code{-baseaddr @var{base_address}}.
10112 @deffn {Command} {tpiu names}
10113 Lists all the TPIU or SWO objects created so far. The two commands are equivalent.
10116 @deffn {Command} {tpiu init}
10117 Initialize all registered TPIU and SWO. The two commands are equivalent.
10118 These commands are used internally during initialization. They can be issued
10119 at any time after the initialization, too.
10122 @deffn {Command} {$tpiu_name cget} queryparm
10123 Each configuration parameter accepted by @command{$tpiu_name configure} can be
10124 individually queried, to return its current value.
10125 The @var{queryparm} is a parameter name accepted by that command, such as @code{-dap}.
10128 @deffn {Command} {$tpiu_name configure} configparams...
10129 The options accepted by this command may also be specified as parameters
10130 to @command{tpiu create}. Their values can later be queried one at a time by
10131 using the @command{$tpiu_name cget} command.
10134 @item @code{-dap} @var{dap_name} -- names the DAP used to access this
10135 TPIU. @xref{dapdeclaration,,DAP declaration}, on how to create and manage DAP instances.
10137 @item @code{-ap-num} @var{ap_number} -- sets DAP access port for TPIU.
10138 On ADIv5 DAP @var{ap_number} is the numeric index of the DAP AP the TPIU is connected to.
10139 On ADIv6 DAP @var{ap_number} is the base address of the DAP AP the TPIU is connected to.
10141 @item @code{-baseaddr} @var{base_address} -- sets the TPIU @var{base_address} where
10142 to access the TPIU in the DAP AP memory space.
10144 @item @code{-protocol} (@option{sync}|@option{uart}|@option{manchester}) -- sets the
10145 protocol used for trace data:
10147 @item @option{sync} -- synchronous parallel trace output mode, using @var{port_width}
10148 data bits (default);
10149 @item @option{uart} -- use asynchronous SWO mode with NRZ (same as regular UART 8N1) coding;
10150 @item @option{manchester} -- use asynchronous SWO mode with Manchester coding.
10153 @item @code{-event} @var{event_name} @var{event_body} -- assigns an event handler,
10154 a TCL string which is evaluated when the event is triggered. The events
10155 @code{pre-enable}, @code{post-enable}, @code{pre-disable} and @code{post-disable}
10156 are defined for TPIU/SWO.
10157 A typical use case for the event @code{pre-enable} is to enable the trace clock
10160 @item @code{-output} (@option{external}|@option{:}@var{port}|@var{filename}|@option{-}) -- specifies
10161 the destination of the trace data:
10163 @item @option{external} -- configure TPIU/SWO to let user capture trace
10164 output externally, either with an additional UART or with a logic analyzer (default);
10165 @item @option{-} -- configure TPIU/SWO and debug adapter to gather trace data
10166 and forward it to @command{tcl_trace} command;
10167 @item @option{:}@var{port} -- configure TPIU/SWO and debug adapter to gather
10168 trace data, open a TCP server at port @var{port} and send the trace data to
10169 each connected client;
10170 @item @var{filename} -- configure TPIU/SWO and debug adapter to
10171 gather trace data and append it to @var{filename}, which can be
10172 either a regular file or a named pipe.
10175 @item @code{-traceclk} @var{TRACECLKIN_freq} -- mandatory parameter.
10176 Specifies the frequency in Hz of the trace clock. For the TPIU embedded in
10177 Cortex-M3 or M4, this is usually the same frequency as HCLK. For protocol
10178 @option{sync} this is twice the frequency of the pin data rate.
10180 @item @code{-pin-freq} @var{trace_freq} -- specifies the expected data rate
10181 in Hz of the SWO pin. Parameter used only on protocols @option{uart} and
10182 @option{manchester}. Can be omitted to let the adapter driver select the
10183 maximum supported rate automatically.
10185 @item @code{-port-width} @var{port_width} -- sets to @var{port_width} the width
10186 of the synchronous parallel port used for trace output. Parameter used only on
10187 protocol @option{sync}. If not specified, default value is @var{1}.
10189 @item @code{-formatter} (@option{0}|@option{1}) -- specifies if the formatter
10190 should be enabled. Parameter used only on protocol @option{sync}. If not specified,
10191 default value is @var{0}.
10195 @deffn {Command} {$tpiu_name enable}
10196 Uses the parameters specified by the previous @command{$tpiu_name configure}
10197 to configure and enable the TPIU or the SWO.
10198 If required, the adapter is also configured and enabled to receive the trace
10200 This command can be used before @command{init}, but it will take effect only
10201 after the @command{init}.
10204 @deffn {Command} {$tpiu_name disable}
10205 Disable the TPIU or the SWO, terminating the receiving of the trace data.
10212 @item STM32L152 board is programmed with an application that configures
10213 PLL to provide core clock with 24MHz frequency; to use ITM output it's
10216 #include <libopencm3/cm3/itm.h>
10221 (the most obvious way is to use the first stimulus port for printf,
10222 for that this ITM_STIM8 assignment can be used inside _write(); to make it
10223 blocking to avoid data loss, add @code{while (!(ITM_STIM8(0) &
10224 ITM_STIM_FIFOREADY));});
10225 @item An FT2232H UART is connected to the SWO pin of the board;
10226 @item Commands to configure UART for 12MHz baud rate:
10228 $ setserial /dev/ttyUSB1 spd_cust divisor 5
10229 $ stty -F /dev/ttyUSB1 38400
10231 (FT2232H's base frequency is 60MHz, spd_cust allows to alias 38400
10232 baud with our custom divisor to get 12MHz)
10233 @item @code{itmdump -f /dev/ttyUSB1 -d1}
10234 @item OpenOCD invocation line:
10236 openocd -f interface/stlink.cfg \
10237 -c "transport select hla_swd" \
10238 -f target/stm32l1.cfg \
10239 -c "stm32l1.tpiu configure -protocol uart" \
10240 -c "stm32l1.tpiu configure -traceclk 24000000 -pin-freq 12000000" \
10241 -c "stm32l1.tpiu enable"
10245 @subsection ARMv7-M specific commands
10252 @deffn {Command} {itm port} @var{port} (@option{0}|@option{1}|@option{on}|@option{off})
10253 Enable or disable trace output for ITM stimulus @var{port} (counting
10254 from 0). Port 0 is enabled on target creation automatically.
10257 @deffn {Command} {itm ports} (@option{0}|@option{1}|@option{on}|@option{off})
10258 Enable or disable trace output for all ITM stimulus ports.
10261 @subsection Cortex-M specific commands
10264 @deffn {Command} {cortex_m maskisr} (@option{auto}|@option{on}|@option{off}|@option{steponly})
10265 Control masking (disabling) interrupts during target step/resume.
10267 The @option{auto} option handles interrupts during stepping in a way that they
10268 get served but don't disturb the program flow. The step command first allows
10269 pending interrupt handlers to execute, then disables interrupts and steps over
10270 the next instruction where the core was halted. After the step interrupts
10271 are enabled again. If the interrupt handlers don't complete within 500ms,
10272 the step command leaves with the core running.
10274 The @option{steponly} option disables interrupts during single-stepping but
10275 enables them during normal execution. This can be used as a partial workaround
10276 for 702596 erratum in Cortex-M7 r0p1. See "Cortex-M7 (AT610) and Cortex-M7 with
10277 FPU (AT611) Software Developer Errata Notice" from ARM for further details.
10279 Note that a free hardware (FPB) breakpoint is required for the @option{auto}
10280 option. If no breakpoint is available at the time of the step, then the step
10281 is taken with interrupts enabled, i.e. the same way the @option{off} option
10284 Default is @option{auto}.
10287 @deffn {Command} {cortex_m vector_catch} [@option{all}|@option{none}|list]
10288 @cindex vector_catch
10289 Vector Catch hardware provides dedicated breakpoints
10290 for certain hardware events.
10292 Parameters request interception of
10293 @option{all} of these hardware event vectors,
10294 @option{none} of them,
10295 or one or more of the following:
10296 @option{hard_err} for a HardFault exception;
10297 @option{mm_err} for a MemManage exception;
10298 @option{bus_err} for a BusFault exception;
10300 @option{state_err},
10301 @option{chk_err}, or
10302 @option{nocp_err} for various UsageFault exceptions; or
10304 If NVIC setup code does not enable them,
10305 MemManage, BusFault, and UsageFault exceptions
10306 are mapped to HardFault.
10307 UsageFault checks for
10308 divide-by-zero and unaligned access
10309 must also be explicitly enabled.
10311 This finishes by listing the current vector catch configuration.
10314 @deffn {Command} {cortex_m reset_config} (@option{sysresetreq}|@option{vectreset})
10315 Control reset handling if hardware srst is not fitted
10316 @xref{reset_config,,reset_config}.
10319 @item @option{sysresetreq} use AIRCR SYSRESETREQ to reset system.
10320 @item @option{vectreset} use AIRCR VECTRESET to reset system (default).
10323 Using @option{vectreset} is a safe option for Cortex-M3, M4 and M7 cores.
10324 This however has the disadvantage of only resetting the core, all peripherals
10325 are unaffected. A solution would be to use a @code{reset-init} event handler
10326 to manually reset the peripherals.
10327 @xref{targetevents,,Target Events}.
10329 Cortex-M0, M0+ and M1 do not support @option{vectreset}, use @option{sysresetreq}
10333 @subsection ARMv8-A specific commands
10337 @deffn {Command} {aarch64 cache_info}
10338 Display information about target caches
10341 @deffn {Command} {aarch64 dbginit}
10342 This command enables debugging by clearing the OS Lock and sticky power-down and reset
10343 indications. It also establishes the expected, basic cross-trigger configuration the aarch64
10344 target code relies on. In a configuration file, the command would typically be called from a
10345 @code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset.
10346 However, normally it is not necessary to use the command at all.
10349 @deffn {Command} {aarch64 disassemble} address [count]
10350 @cindex disassemble
10351 Disassembles @var{count} instructions starting at @var{address}.
10352 If @var{count} is not specified, a single instruction is disassembled.
10355 @deffn {Command} {aarch64 smp} [on|off]
10356 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
10357 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
10358 halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP
10359 group. With SMP handling disabled, all targets need to be treated individually.
10362 @deffn {Command} {aarch64 maskisr} [@option{on}|@option{off}]
10363 Selects whether interrupts will be processed when single stepping. The default configuration is
10367 @deffn {Command} {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
10368 Cause @command{$target_name} to halt when an exception is taken. Any combination of
10369 Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
10370 @command{$target_name} will halt before taking the exception. In order to resume
10371 the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
10372 Issuing the command without options prints the current configuration.
10375 @section EnSilica eSi-RISC Architecture
10377 eSi-RISC is a highly configurable microprocessor architecture for embedded systems
10378 provided by EnSilica. (See: @url{http://www.ensilica.com/risc-ip/}.)
10380 @subsection eSi-RISC Configuration
10382 @deffn {Command} {esirisc cache_arch} (@option{harvard}|@option{von_neumann})
10383 Configure the caching architecture. Targets with the @code{UNIFIED_ADDRESS_SPACE}
10384 option disabled employ a Harvard architecture. By default, @option{von_neumann} is assumed.
10387 @deffn {Command} {esirisc hwdc} (@option{all}|@option{none}|mask ...)
10388 Configure hardware debug control. The HWDC register controls which exceptions return
10389 control back to the debugger. Possible masks are @option{all}, @option{none},
10390 @option{reset}, @option{interrupt}, @option{syscall}, @option{error}, and @option{debug}.
10391 By default, @option{reset}, @option{error}, and @option{debug} are enabled.
10394 @subsection eSi-RISC Operation
10396 @deffn {Command} {esirisc flush_caches}
10397 Flush instruction and data caches. This command requires that the target is halted
10398 when the command is issued and configured with an instruction or data cache.
10401 @subsection eSi-Trace Configuration
10403 eSi-RISC targets may be configured with support for instruction tracing. Trace
10404 data may be written to an in-memory buffer or FIFO. If a FIFO is configured, DMA
10405 is typically employed to move trace data off-device using a high-speed
10406 peripheral (eg. SPI). Collected trace data is encoded in one of three different
10407 formats. At a minimum, @command{esirisc trace buffer} or @command{esirisc trace
10408 fifo} must be issued along with @command{esirisc trace format} before trace data
10411 OpenOCD provides rudimentary analysis of collected trace data. If more detail is
10412 needed, collected trace data can be dumped to a file and processed by external
10416 OpenOCD is unable to process trace data sent to a FIFO. A potential workaround
10417 for this issue is to configure DMA to copy trace data to an in-memory buffer,
10418 which can then be passed to the @command{esirisc trace analyze} and
10419 @command{esirisc trace dump} commands.
10421 It is possible to corrupt trace data when using a FIFO if the peripheral
10422 responsible for draining data from the FIFO is not fast enough. This can be
10423 managed by enabling flow control, however this can impact timing-sensitive
10424 software operation on the CPU.
10427 @deffn {Command} {esirisc trace buffer} address size [@option{wrap}]
10428 Configure trace buffer using the provided address and size. If the @option{wrap}
10429 option is specified, trace collection will continue once the end of the buffer
10430 is reached. By default, wrap is disabled.
10433 @deffn {Command} {esirisc trace fifo} address
10434 Configure trace FIFO using the provided address.
10437 @deffn {Command} {esirisc trace flow_control} (@option{enable}|@option{disable})
10438 Enable or disable stalling the CPU to collect trace data. By default, flow
10439 control is disabled.
10442 @deffn {Command} {esirisc trace format} (@option{full}|@option{branch}|@option{icache}) pc_bits
10443 Configure trace format and number of PC bits to be captured. @option{pc_bits}
10444 must be within 1 and 31 as the LSB is not collected. If external tooling is used
10445 to analyze collected trace data, these values must match.
10447 Supported trace formats:
10449 @item @option{full} capture full trace data, allowing execution history and
10450 timing to be determined.
10451 @item @option{branch} capture taken branch instructions and branch target
10453 @item @option{icache} capture instruction cache misses.
10457 @deffn {Command} {esirisc trace trigger start} (@option{condition}) [start_data start_mask]
10458 Configure trigger start condition using the provided start data and mask. A
10459 brief description of each condition is provided below; for more detail on how
10460 these values are used, see the eSi-RISC Architecture Manual.
10462 Supported conditions:
10464 @item @option{none} manual tracing (see @command{esirisc trace start}).
10465 @item @option{pc} start tracing if the PC matches start data and mask.
10466 @item @option{load} start tracing if the effective address of a load
10467 instruction matches start data and mask.
10468 @item @option{store} start tracing if the effective address of a store
10469 instruction matches start data and mask.
10470 @item @option{exception} start tracing if the EID of an exception matches start
10472 @item @option{eret} start tracing when an @code{ERET} instruction is executed.
10473 @item @option{wait} start tracing when a @code{WAIT} instruction is executed.
10474 @item @option{stop} start tracing when a @code{STOP} instruction is executed.
10475 @item @option{high} start tracing when an external signal is a logical high.
10476 @item @option{low} start tracing when an external signal is a logical low.
10480 @deffn {Command} {esirisc trace trigger stop} (@option{condition}) [stop_data stop_mask]
10481 Configure trigger stop condition using the provided stop data and mask. A brief
10482 description of each condition is provided below; for more detail on how these
10483 values are used, see the eSi-RISC Architecture Manual.
10485 Supported conditions:
10487 @item @option{none} manual tracing (see @command{esirisc trace stop}).
10488 @item @option{pc} stop tracing if the PC matches stop data and mask.
10489 @item @option{load} stop tracing if the effective address of a load
10490 instruction matches stop data and mask.
10491 @item @option{store} stop tracing if the effective address of a store
10492 instruction matches stop data and mask.
10493 @item @option{exception} stop tracing if the EID of an exception matches stop
10495 @item @option{eret} stop tracing when an @code{ERET} instruction is executed.
10496 @item @option{wait} stop tracing when a @code{WAIT} instruction is executed.
10497 @item @option{stop} stop tracing when a @code{STOP} instruction is executed.
10501 @deffn {Command} {esirisc trace trigger delay} (@option{trigger}) [cycles]
10502 Configure trigger start/stop delay in clock cycles.
10504 Supported triggers:
10506 @item @option{none} no delay to start or stop collection.
10507 @item @option{start} delay @option{cycles} after trigger to start collection.
10508 @item @option{stop} delay @option{cycles} after trigger to stop collection.
10509 @item @option{both} delay @option{cycles} after both triggers to start or stop
10514 @subsection eSi-Trace Operation
10516 @deffn {Command} {esirisc trace init}
10517 Initialize trace collection. This command must be called any time the
10518 configuration changes. If a trace buffer has been configured, the contents will
10519 be overwritten when trace collection starts.
10522 @deffn {Command} {esirisc trace info}
10523 Display trace configuration.
10526 @deffn {Command} {esirisc trace status}
10527 Display trace collection status.
10530 @deffn {Command} {esirisc trace start}
10531 Start manual trace collection.
10534 @deffn {Command} {esirisc trace stop}
10535 Stop manual trace collection.
10538 @deffn {Command} {esirisc trace analyze} [address size]
10539 Analyze collected trace data. This command may only be used if a trace buffer
10540 has been configured. If a trace FIFO has been configured, trace data must be
10541 copied to an in-memory buffer identified by the @option{address} and
10542 @option{size} options using DMA.
10545 @deffn {Command} {esirisc trace dump} [address size] @file{filename}
10546 Dump collected trace data to file. This command may only be used if a trace
10547 buffer has been configured. If a trace FIFO has been configured, trace data must
10548 be copied to an in-memory buffer identified by the @option{address} and
10549 @option{size} options using DMA.
10552 @section Intel Architecture
10554 Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
10555 (Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
10556 Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
10557 software debug and the CLTAP is used for SoC level operations.
10558 Useful docs are here: https://communities.intel.com/community/makers/documentation
10560 @item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
10561 @item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
10562 @item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
10565 @subsection x86 32-bit specific commands
10566 The three main address spaces for x86 are memory, I/O and configuration space.
10567 These commands allow a user to read and write to the 64Kbyte I/O address space.
10569 @deffn {Command} {x86_32 idw} address
10570 Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
10573 @deffn {Command} {x86_32 idh} address
10574 Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
10577 @deffn {Command} {x86_32 idb} address
10578 Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
10581 @deffn {Command} {x86_32 iww} address
10582 Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
10585 @deffn {Command} {x86_32 iwh} address
10586 Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
10589 @deffn {Command} {x86_32 iwb} address
10590 Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
10593 @section OpenRISC Architecture
10595 The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
10596 configured with any of the TAP / Debug Unit available.
10598 @subsection TAP and Debug Unit selection commands
10599 @deffn {Command} {tap_select} (@option{vjtag}|@option{mohor}|@option{xilinx_bscan})
10600 Select between the Altera Virtual JTAG , Xilinx Virtual JTAG and Mohor TAP.
10602 @deffn {Command} {du_select} (@option{adv}|@option{mohor}) [option]
10603 Select between the Advanced Debug Interface and the classic one.
10605 An option can be passed as a second argument to the debug unit.
10607 When using the Advanced Debug Interface, option = 1 means the RTL core is
10608 configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
10609 between bytes while doing read or write bursts.
10612 @subsection Registers commands
10613 @deffn {Command} {addreg} [name] [address] [feature] [reg_group]
10614 Add a new register in the cpu register list. This register will be
10615 included in the generated target descriptor file.
10617 @strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
10619 @strong{[reg_group]} can be anything. The default register list defines "system",
10620 "dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
10621 and "timer" groups.
10625 addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
10630 @section RISC-V Architecture
10632 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
10633 debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
10634 harts. (It's possible to increase this limit to 1024 by changing
10635 RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
10636 Debug Specification, but there is also support for legacy targets that
10637 implement version 0.11.
10639 @subsection RISC-V Terminology
10641 A @emph{hart} is a hardware thread. A hart may share resources (eg. FPU) with
10642 another hart, or may be a separate core. RISC-V treats those the same, and
10643 OpenOCD exposes each hart as a separate core.
10645 @subsection Vector Registers
10647 For harts that implement the vector extension, OpenOCD provides access to the
10648 relevant CSRs, as well as the vector registers (v0-v31). The size of each
10649 vector register is dependent on the value of vlenb. RISC-V allows each vector
10650 register to be divided into selected-width elements, and this division can be
10651 changed at run-time. Because OpenOCD cannot update register definitions at
10652 run-time, it exposes each vector register to gdb as a union of fields of
10653 vectors so that users can easily access individual bytes, shorts, words,
10654 longs, and quads inside each vector register. It is left to gdb or
10655 higher-level debuggers to present this data in a more intuitive format.
10657 In the XML register description, the vector registers (when vlenb=16) look as
10661 <feature name="org.gnu.gdb.riscv.vector">
10662 <vector id="bytes" type="uint8" count="16"/>
10663 <vector id="shorts" type="uint16" count="8"/>
10664 <vector id="words" type="uint32" count="4"/>
10665 <vector id="longs" type="uint64" count="2"/>
10666 <vector id="quads" type="uint128" count="1"/>
10667 <union id="riscv_vector">
10668 <field name="b" type="bytes"/>
10669 <field name="s" type="shorts"/>
10670 <field name="w" type="words"/>
10671 <field name="l" type="longs"/>
10672 <field name="q" type="quads"/>
10674 <reg name="v0" bitsize="128" regnum="4162" save-restore="no"
10675 type="riscv_vector" group="vector"/>
10677 <reg name="v31" bitsize="128" regnum="4193" save-restore="no"
10678 type="riscv_vector" group="vector"/>
10682 @subsection RISC-V Debug Configuration Commands
10684 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
10685 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
10686 can be specified as individual register numbers or register ranges (inclusive). For the
10687 individually listed CSRs, a human-readable name can optionally be set using the @code{n=name}
10688 syntax, which will get @code{csr_} prepended to it. If no name is provided, the register will be
10689 named @code{csr<n>}.
10691 By default OpenOCD attempts to expose only CSRs that are mentioned in a spec,
10692 and then only if the corresponding extension appears to be implemented. This
10693 command can be used if OpenOCD gets this wrong, or if the target implements custom
10697 # Expose a single RISC-V CSR number 128 under the name "csr128":
10698 $_TARGETNAME expose_csrs 128
10700 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
10701 $_TARGETNAME expose_csrs 128-132
10703 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
10704 $_TARGETNAME expose_csrs 1996=myregister
10708 @deffn {Config Command} {riscv expose_custom} n[-m|=name] [...]
10709 The RISC-V Debug Specification allows targets to expose custom registers
10710 through abstract commands. (See Section 3.5.1.1 in that document.) This command
10711 configures individual registers or register ranges (inclusive) that shall be exposed.
10712 Number 0 indicates the first custom register, whose abstract command number is 0xc000.
10713 For individually listed registers, a human-readable name can be optionally provided
10714 using the @code{n=name} syntax, which will get @code{custom_} prepended to it. If no
10715 name is provided, the register will be named @code{custom<n>}.
10718 # Expose one RISC-V custom register with number 0xc010 (0xc000 + 16)
10719 # under the name "custom16":
10720 $_TARGETNAME expose_custom 16
10722 # Expose a range of RISC-V custom registers with numbers 0xc010 .. 0xc018
10723 # (0xc000+16 .. 0xc000+24) under the names "custom16" through "custom24":
10724 $_TARGETNAME expose_custom 16-24
10726 # Expose one RISC-V custom register with number 0xc020 (0xc000 + 32) under
10727 # user-defined name "custom_myregister":
10728 $_TARGETNAME expose_custom 32=myregister
10732 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
10733 Set the wall-clock timeout (in seconds) for individual commands. The default
10734 should work fine for all but the slowest targets (eg. simulators).
10737 @deffn {Command} {riscv set_reset_timeout_sec} [seconds]
10738 Set the maximum time to wait for a hart to come out of reset after reset is
10742 @deffn {Command} {riscv set_scratch_ram} none|[address]
10743 Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
10744 This is used to access 64-bit floating point registers on 32-bit targets.
10747 @deffn Command {riscv set_mem_access} method1 [method2] [method3]
10748 Specify which RISC-V memory access method(s) shall be used, and in which order
10749 of priority. At least one method must be specified.
10751 Available methods are:
10753 @item @code{progbuf} - Use RISC-V Debug Program Buffer to access memory.
10754 @item @code{sysbus} - Access memory via RISC-V Debug System Bus interface.
10755 @item @code{abstract} - Access memory via RISC-V Debug abstract commands.
10758 By default, all memory access methods are enabled in the following order:
10759 @code{progbuf sysbus abstract}.
10761 This command can be used to change the memory access methods if the default
10762 behavior is not suitable for a particular target.
10765 @deffn {Command} {riscv set_enable_virtual} on|off
10766 When on, memory accesses are performed on physical or virtual memory depending
10767 on the current system configuration. When off (default), all memory accessses are performed
10768 on physical memory.
10771 @deffn {Command} {riscv set_enable_virt2phys} on|off
10772 When on (default), memory accesses are performed on physical or virtual memory
10773 depending on the current satp configuration. When off, all memory accessses are
10774 performed on physical memory.
10777 @deffn {Command} {riscv resume_order} normal|reversed
10778 Some software assumes all harts are executing nearly continuously. Such
10779 software may be sensitive to the order that harts are resumed in. On harts
10780 that don't support hasel, this option allows the user to choose the order the
10781 harts are resumed in. If you are using this option, it's probably masking a
10782 race condition problem in your code.
10784 Normal order is from lowest hart index to highest. This is the default
10785 behavior. Reversed order is from highest hart index to lowest.
10788 @deffn {Command} {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
10789 Set the IR value for the specified JTAG register. This is useful, for
10790 example, when using the existing JTAG interface on a Xilinx FPGA by
10791 way of BSCANE2 primitives that only permit a limited selection of IR
10794 When utilizing version 0.11 of the RISC-V Debug Specification,
10795 @option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL
10796 and DBUS registers, respectively.
10799 @deffn {Command} {riscv use_bscan_tunnel} value
10800 Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
10801 the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
10804 @deffn {Command} {riscv set_ebreakm} on|off
10805 Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
10806 OpenOCD. When off, they generate a breakpoint exception handled internally.
10809 @deffn {Command} {riscv set_ebreaks} on|off
10810 Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
10811 OpenOCD. When off, they generate a breakpoint exception handled internally.
10814 @deffn {Command} {riscv set_ebreaku} on|off
10815 Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
10816 OpenOCD. When off, they generate a breakpoint exception handled internally.
10819 @subsection RISC-V Authentication Commands
10821 The following commands can be used to authenticate to a RISC-V system. Eg. a
10822 trivial challenge-response protocol could be implemented as follows in a
10823 configuration file, immediately following @command{init}:
10825 set challenge [riscv authdata_read]
10826 riscv authdata_write [expr @{$challenge + 1@}]
10829 @deffn {Command} {riscv authdata_read}
10830 Return the 32-bit value read from authdata.
10833 @deffn {Command} {riscv authdata_write} value
10834 Write the 32-bit value to authdata.
10837 @subsection RISC-V DMI Commands
10839 The following commands allow direct access to the Debug Module Interface, which
10840 can be used to interact with custom debug features.
10842 @deffn {Command} {riscv dmi_read} address
10843 Perform a 32-bit DMI read at address, returning the value.
10846 @deffn {Command} {riscv dmi_write} address value
10847 Perform a 32-bit DMI write of value at address.
10850 @section ARC Architecture
10853 Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
10854 designers can optimize for a wide range of uses, from deeply embedded to
10855 high-performance host applications in a variety of market segments. See more
10856 at: @url{http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx}.
10857 OpenOCD currently supports ARC EM processors.
10858 There is a set ARC-specific OpenOCD commands that allow low-level
10859 access to the core and provide necessary support for ARC extensibility and
10860 configurability capabilities. ARC processors has much more configuration
10861 capabilities than most of the other processors and in addition there is an
10862 extension interface that allows SoC designers to add custom registers and
10863 instructions. For the OpenOCD that mostly means that set of core and AUX
10864 registers in target will vary and is not fixed for a particular processor
10865 model. To enable extensibility several TCL commands are provided that allow to
10866 describe those optional registers in OpenOCD configuration files. Moreover
10867 those commands allow for a dynamic target features discovery.
10870 @subsection General ARC commands
10872 @deffn {Config Command} {arc add-reg} configparams
10874 Add a new register to processor target. By default newly created register is
10875 marked as not existing. @var{configparams} must have following required
10880 @item @code{-name} name
10881 @*Name of a register.
10883 @item @code{-num} number
10884 @*Architectural register number: core register number or AUX register number.
10886 @item @code{-feature} XML_feature
10887 @*Name of GDB XML target description feature.
10891 @var{configparams} may have following optional arguments:
10895 @item @code{-gdbnum} number
10896 @*GDB register number. It is recommended to not assign GDB register number
10897 manually, because there would be a risk that two register will have same
10898 number. When register GDB number is not set with this option, then register
10899 will get a previous register number + 1. This option is required only for those
10900 registers that must be at particular address expected by GDB.
10903 @*This option specifies that register is a core registers. If not - this is an
10904 AUX register. AUX registers and core registers reside in different address
10908 @*This options specifies that register is a BCR register. BCR means Build
10909 Configuration Registers - this is a special type of AUX registers that are read
10910 only and non-volatile, that is - they never change their value. Therefore OpenOCD
10911 never invalidates values of those registers in internal caches. Because BCR is a
10912 type of AUX registers, this option cannot be used with @code{-core}.
10914 @item @code{-type} type_name
10915 @*Name of type of this register. This can be either one of the basic GDB types,
10916 or a custom types described with @command{arc add-reg-type-[flags|struct]}.
10919 @* If specified then this is a "general" register. General registers are always
10920 read by OpenOCD on context save (when core has just been halted) and is always
10921 transferred to GDB client in a response to g-packet. Contrary to this,
10922 non-general registers are read and sent to GDB client on-demand. In general it
10923 is not recommended to apply this option to custom registers.
10929 @deffn {Config Command} {arc add-reg-type-flags} -name name flags...
10930 Adds new register type of ``flags'' class. ``Flags'' types can contain only
10931 one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
10934 @anchor{add-reg-type-struct}
10935 @deffn {Config Command} {arc add-reg-type-struct} -name name structs...
10936 Adds new register type of ``struct'' class. ``Struct'' types can contain either
10937 bit-fields or fields of other types, however at the moment only bit fields are
10938 supported. Structure bit field definition looks like @code{-bitfield name
10942 @deffn {Command} {arc get-reg-field} reg-name field-name
10943 Returns value of bit-field in a register. Register must be ``struct'' register
10944 type, @xref{add-reg-type-struct}. command definition.
10947 @deffn {Command} {arc set-reg-exists} reg-names...
10948 Specify that some register exists. Any amount of names can be passed
10949 as an argument for a single command invocation.
10952 @subsection ARC JTAG commands
10954 @deffn {Command} {arc jtag set-aux-reg} regnum value
10955 This command writes value to AUX register via its number. This command access
10956 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10957 therefore it is unsafe to use if that register can be operated by other means.
10961 @deffn {Command} {arc jtag set-core-reg} regnum value
10962 This command is similar to @command{arc jtag set-aux-reg} but is for core
10966 @deffn {Command} {arc jtag get-aux-reg} regnum
10967 This command returns the value storded in AUX register via its number. This commands access
10968 register in target directly via JTAG, bypassing any OpenOCD internal caches,
10969 therefore it is unsafe to use if that register can be operated by other means.
10973 @deffn {Command} {arc jtag get-core-reg} regnum
10974 This command is similar to @command{arc jtag get-aux-reg} but is for core
10978 @section STM8 Architecture
10979 @uref{http://st.com/stm8/, STM8} is a 8-bit microcontroller platform from
10980 STMicroelectronics, based on a proprietary 8-bit core architecture.
10982 OpenOCD supports debugging STM8 through the STMicroelectronics debug
10983 protocol SWIM, @pxref{swimtransport,,SWIM}.
10985 @section Xtensa Architecture
10986 Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
10987 that can easily scale from a tiny, cache-less controller or task engine to a high-performance
10988 SIMD/VLIW DSP provided by Cadence.
10989 @url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
10991 OpenOCD supports generic Xtensa processors implementation which can be customized by
10992 simply providing vendor-specific core configuration which controls every configurable
10993 Xtensa architecture option, e.g. number of address registers, exceptions, reduced
10994 size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
10995 configurations for Xtensa processors with any number of cores and allows to configure
10996 their debug signals interconnection (so-called "break/stall networks") which control how
10997 debug signals are distributed among cores. Xtensa "break networks" are compatible with
10998 ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
10999 uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
11000 @uref{https://www.espressif.com/en/products/socs, ESP32 family}.
11002 @subsection General Xtensa Commands
11004 @deffn {Command} {xtensa set_permissive} (0|1)
11005 By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
11006 When set to (1), skips access controls and address range check before read/write memory.
11009 @deffn {Command} {xtensa maskisr} (on|off)
11010 Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
11013 @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
11014 Configures debug signals connection ("break network") for currently selected core.
11016 @item @code{none} - Core's "break/stall network" is disconnected. Core is not affected by any debug
11017 signal from other cores.
11018 @item @code{breakinout} - Core's "break network" is fully connected (break inputs and outputs are enabled).
11019 Core will receive debug break signals from other cores and send such signals to them. For example when another core
11020 is stopped due to breakpoint hit this core will be stopped too and vice versa.
11021 @item @code{runstall} - Core's "stall network" is fully connected (stall inputs and outputs are enabled).
11022 This feature is not well implemented and tested yet.
11023 @item @code{BreakIn} - Core's "break-in" signal is enabled.
11024 Core will receive debug break signals from other cores. For example when another core is
11025 stopped due to breakpoint hit this core will be stopped too.
11026 @item @code{BreakOut} - Core's "break-out" signal is enabled.
11027 Core will send debug break signal to other cores. For example when this core is
11028 stopped due to breakpoint hit other cores with enabled break-in signals will be stopped too.
11029 @item @code{RunStallIn} - Core's "runstall-in" signal is enabled.
11030 This feature is not well implemented and tested yet.
11031 @item @code{DebugModeOut} - Core's "debugmode-out" signal is enabled.
11032 This feature is not well implemented and tested yet.
11036 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
11037 Enable and start performance counter.
11039 @item @code{counter_id} - Counter ID (0-1).
11040 @item @code{select} - Selects performance metric to be counted by the counter,
11041 e.g. 0 - CPU cycles, 2 - retired instructions.
11042 @item @code{mask} - Selects input subsets to be counted (counter will
11043 increment only once even if more than one condition corresponding to a mask bit occurs).
11044 @item @code{kernelcnt} - 0 - count events with "CINTLEVEL <= tracelevel",
11045 1 - count events with "CINTLEVEL > tracelevel".
11046 @item @code{tracelevel} - Compares this value to "CINTLEVEL" when deciding
11051 @deffn {Command} {xtensa perfmon_dump} (counter_id)
11052 Dump performance counter value. If no argument specified, dumps all counters.
11055 @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
11056 Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
11057 This command also allows to specify the amount of data to capture after stop trigger activation.
11059 @item @code{pcval} - PC value which will trigger trace data collection stop.
11060 @item @code{maskbitcount} - PC value mask.
11061 @item @code{n} - Maximum number of instructions/words to capture after trace stop trigger.
11065 @deffn {Command} {xtensa tracestop}
11066 Stop current trace as started by the tracestart command.
11069 @deffn {Command} {xtensa tracedump} <outfile>
11070 Dump trace memory to a file.
11073 @anchor{softwaredebugmessagesandtracing}
11074 @section Software Debug Messages and Tracing
11075 @cindex Linux-ARM DCC support
11079 OpenOCD can process certain requests from target software, when
11080 the target uses appropriate libraries.
11081 The most powerful mechanism is semihosting, but there is also
11082 a lighter weight mechanism using only the DCC channel.
11084 Currently @command{target_request debugmsgs}
11085 is supported only for @option{arm7_9} and @option{cortex_m} cores.
11086 These messages are received as part of target polling, so
11087 you need to have @command{poll on} active to receive them.
11088 They are intrusive in that they will affect program execution
11089 times. If that is a problem, @pxref{armhardwaretracing,,ARM Hardware Tracing}.
11091 See @file{libdcc} in the contrib dir for more details.
11092 In addition to sending strings, characters, and
11093 arrays of various size integers from the target,
11094 @file{libdcc} also exports a software trace point mechanism.
11095 The target being debugged may
11096 issue trace messages which include a 24-bit @dfn{trace point} number.
11097 Trace point support includes two distinct mechanisms,
11098 each supported by a command:
11101 @item @emph{History} ... A circular buffer of trace points
11102 can be set up, and then displayed at any time.
11103 This tracks where code has been, which can be invaluable in
11104 finding out how some fault was triggered.
11106 The buffer may overflow, since it collects records continuously.
11107 It may be useful to use some of the 24 bits to represent a
11108 particular event, and other bits to hold data.
11110 @item @emph{Counting} ... An array of counters can be set up,
11111 and then displayed at any time.
11112 This can help establish code coverage and identify hot spots.
11114 The array of counters is directly indexed by the trace point
11115 number, so trace points with higher numbers are not counted.
11118 Linux-ARM kernels have a ``Kernel low-level debugging
11119 via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
11120 depends on CONFIG_DEBUG_LL) which uses this mechanism to
11121 deliver messages before a serial console can be activated.
11122 This is not the same format used by @file{libdcc}.
11123 Other software, such as the U-Boot boot loader, sometimes
11124 does the same thing.
11126 @deffn {Command} {target_request debugmsgs} [@option{enable}|@option{disable}|@option{charmsg}]
11127 Displays current handling of target DCC message requests.
11128 These messages may be sent to the debugger while the target is running.
11129 The optional @option{enable} and @option{charmsg} parameters
11130 both enable the messages, while @option{disable} disables them.
11132 With @option{charmsg} the DCC words each contain one character,
11133 as used by Linux with CONFIG_DEBUG_ICEDCC;
11134 otherwise the libdcc format is used.
11137 @deffn {Command} {trace history} [@option{clear}|count]
11138 With no parameter, displays all the trace points that have triggered
11139 in the order they triggered.
11140 With the parameter @option{clear}, erases all current trace history records.
11141 With a @var{count} parameter, allocates space for that many
11145 @deffn {Command} {trace point} [@option{clear}|identifier]
11146 With no parameter, displays all trace point identifiers and how many times
11147 they have been triggered.
11148 With the parameter @option{clear}, erases all current trace point counters.
11149 With a numeric @var{identifier} parameter, creates a new a trace point counter
11150 and associates it with that identifier.
11152 @emph{Important:} The identifier and the trace point number
11153 are not related except by this command.
11154 These trace point numbers always start at zero (from server startup,
11155 or after @command{trace point clear}) and count up from there.
11159 @node JTAG Commands
11160 @chapter JTAG Commands
11161 @cindex JTAG Commands
11162 Most general purpose JTAG commands have been presented earlier.
11163 (@xref{jtagspeed,,JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Declaration}.)
11164 Lower level JTAG commands, as presented here,
11165 may be needed to work with targets which require special
11166 attention during operations such as reset or initialization.
11168 To use these commands you will need to understand some
11169 of the basics of JTAG, including:
11172 @item A JTAG scan chain consists of a sequence of individual TAP
11173 devices such as a CPUs.
11174 @item Control operations involve moving each TAP through the same
11175 standard state machine (in parallel)
11176 using their shared TMS and clock signals.
11177 @item Data transfer involves shifting data through the chain of
11178 instruction or data registers of each TAP, writing new register values
11179 while the reading previous ones.
11180 @item Data register sizes are a function of the instruction active in
11181 a given TAP, while instruction register sizes are fixed for each TAP.
11182 All TAPs support a BYPASS instruction with a single bit data register.
11183 @item The way OpenOCD differentiates between TAP devices is by
11184 shifting different instructions into (and out of) their instruction
11188 @section Low Level JTAG Commands
11190 These commands are used by developers who need to access
11191 JTAG instruction or data registers, possibly controlling
11192 the order of TAP state transitions.
11193 If you're not debugging OpenOCD internals, or bringing up a
11194 new JTAG adapter or a new type of TAP device (like a CPU or
11195 JTAG router), you probably won't need to use these commands.
11196 In a debug session that doesn't use JTAG for its transport protocol,
11197 these commands are not available.
11199 @deffn {Command} {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
11200 Loads the data register of @var{tap} with a series of bit fields
11201 that specify the entire register.
11202 Each field is @var{numbits} bits long with
11203 a numeric @var{value} (hexadecimal encouraged).
11204 The return value holds the original value of each
11207 For example, a 38 bit number might be specified as one
11208 field of 32 bits then one of 6 bits.
11209 @emph{For portability, never pass fields which are more
11210 than 32 bits long. Many OpenOCD implementations do not
11211 support 64-bit (or larger) integer values.}
11213 All TAPs other than @var{tap} must be in BYPASS mode.
11214 The single bit in their data registers does not matter.
11216 When @var{tap_state} is specified, the JTAG state machine is left
11218 For example @sc{drpause} might be specified, so that more
11219 instructions can be issued before re-entering the @sc{run/idle} state.
11220 If the end state is not specified, the @sc{run/idle} state is entered.
11223 OpenOCD does not record information about data register lengths,
11224 so @emph{it is important that you get the bit field lengths right}.
11225 Remember that different JTAG instructions refer to different
11226 data registers, which may have different lengths.
11227 Moreover, those lengths may not be fixed;
11228 the SCAN_N instruction can change the length of
11229 the register accessed by the INTEST instruction
11230 (by connecting a different scan chain).
11234 @deffn {Command} {flush_count}
11235 Returns the number of times the JTAG queue has been flushed.
11236 This may be used for performance tuning.
11238 For example, flushing a queue over USB involves a
11239 minimum latency, often several milliseconds, which does
11240 not change with the amount of data which is written.
11241 You may be able to identify performance problems by finding
11242 tasks which waste bandwidth by flushing small transfers too often,
11243 instead of batching them into larger operations.
11246 @deffn {Command} {irscan} [tap instruction]+ [@option{-endstate} tap_state]
11247 For each @var{tap} listed, loads the instruction register
11248 with its associated numeric @var{instruction}.
11249 (The number of bits in that instruction may be displayed
11250 using the @command{scan_chain} command.)
11251 For other TAPs, a BYPASS instruction is loaded.
11253 When @var{tap_state} is specified, the JTAG state machine is left
11255 For example @sc{irpause} might be specified, so the data register
11256 can be loaded before re-entering the @sc{run/idle} state.
11257 If the end state is not specified, the @sc{run/idle} state is entered.
11260 OpenOCD currently supports only a single field for instruction
11261 register values, unlike data register values.
11262 For TAPs where the instruction register length is more than 32 bits,
11263 portable scripts currently must issue only BYPASS instructions.
11267 @deffn {Command} {pathmove} start_state [next_state ...]
11268 Start by moving to @var{start_state}, which
11269 must be one of the @emph{stable} states.
11270 Unless it is the only state given, this will often be the
11271 current state, so that no TCK transitions are needed.
11272 Then, in a series of single state transitions
11273 (conforming to the JTAG state machine) shift to
11274 each @var{next_state} in sequence, one per TCK cycle.
11275 The final state must also be stable.
11278 @deffn {Command} {runtest} @var{num_cycles}
11279 Move to the @sc{run/idle} state, and execute at least
11280 @var{num_cycles} of the JTAG clock (TCK).
11281 Instructions often need some time
11282 to execute before they take effect.
11285 @c tms_sequence (short|long)
11286 @c ... temporary, debug-only, other than USBprog bug workaround...
11288 @deffn {Command} {verify_ircapture} (@option{enable}|@option{disable})
11289 Verify values captured during @sc{ircapture} and returned
11290 during IR scans. Default is enabled, but this can be
11291 overridden by @command{verify_jtag}.
11292 This flag is ignored when validating JTAG chain configuration.
11295 @deffn {Command} {verify_jtag} (@option{enable}|@option{disable})
11296 Enables verification of DR and IR scans, to help detect
11297 programming errors. For IR scans, @command{verify_ircapture}
11298 must also be enabled.
11299 Default is enabled.
11302 @section TAP state names
11303 @cindex TAP state names
11305 The @var{tap_state} names used by OpenOCD in the @command{drscan},
11306 @command{irscan}, and @command{pathmove} commands are the same
11307 as those used in SVF boundary scan documents, except that
11308 SVF uses @sc{idle} instead of @sc{run/idle}.
11311 @item @b{RESET} ... @emph{stable} (with TMS high);
11312 acts as if TRST were pulsed
11313 @item @b{RUN/IDLE} ... @emph{stable}; don't assume this always means IDLE
11315 @item @b{DRCAPTURE}
11316 @item @b{DRSHIFT} ... @emph{stable}; TDI/TDO shifting
11317 through the data register
11319 @item @b{DRPAUSE} ... @emph{stable}; data register ready
11320 for update or more shifting
11324 @item @b{IRCAPTURE}
11325 @item @b{IRSHIFT} ... @emph{stable}; TDI/TDO shifting
11326 through the instruction register
11328 @item @b{IRPAUSE} ... @emph{stable}; instruction register ready
11329 for update or more shifting
11334 Note that only six of those states are fully ``stable'' in the
11335 face of TMS fixed (low except for @sc{reset})
11336 and a free-running JTAG clock. For all the
11337 others, the next TCK transition changes to a new state.
11340 @item From @sc{drshift} and @sc{irshift}, clock transitions will
11341 produce side effects by changing register contents. The values
11342 to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
11343 may not be as expected.
11344 @item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
11345 choices after @command{drscan} or @command{irscan} commands,
11346 since they are free of JTAG side effects.
11347 @item @sc{run/idle} may have side effects that appear at non-JTAG
11348 levels, such as advancing the ARM9E-S instruction pipeline.
11349 Consult the documentation for the TAP(s) you are working with.
11352 @node Boundary Scan Commands
11353 @chapter Boundary Scan Commands
11355 One of the original purposes of JTAG was to support
11356 boundary scan based hardware testing.
11357 Although its primary focus is to support On-Chip Debugging,
11358 OpenOCD also includes some boundary scan commands.
11360 @section SVF: Serial Vector Format
11361 @cindex Serial Vector Format
11364 The Serial Vector Format, better known as @dfn{SVF}, is a
11365 way to represent JTAG test patterns in text files.
11366 In a debug session using JTAG for its transport protocol,
11367 OpenOCD supports running such test files.
11369 @deffn {Command} {svf} @file{filename} [@option{-tap @var{tapname}}] [@option{[-]quiet}] @
11370 [@option{[-]nil}] [@option{[-]progress}] [@option{[-]ignore_error}]
11371 This issues a JTAG reset (Test-Logic-Reset) and then
11372 runs the SVF script from @file{filename}.
11374 Arguments can be specified in any order; the optional dash doesn't
11375 affect their semantics.
11379 @item @option{-tap @var{tapname}} ignore IR and DR headers and footers
11380 specified by the SVF file with HIR, TIR, HDR and TDR commands;
11381 instead, calculate them automatically according to the current JTAG
11382 chain configuration, targeting @var{tapname};
11383 @item @option{[-]quiet} do not log every command before execution;
11384 @item @option{[-]nil} ``dry run'', i.e., do not perform any operations
11385 on the real interface;
11386 @item @option{[-]progress} enable progress indication;
11387 @item @option{[-]ignore_error} continue execution despite TDO check
11392 @section XSVF: Xilinx Serial Vector Format
11393 @cindex Xilinx Serial Vector Format
11396 The Xilinx Serial Vector Format, better known as @dfn{XSVF}, is a
11397 binary representation of SVF which is optimized for use with
11399 In a debug session using JTAG for its transport protocol,
11400 OpenOCD supports running such test files.
11402 @quotation Important
11403 Not all XSVF commands are supported.
11406 @deffn {Command} {xsvf} (tapname|@option{plain}) filename [@option{virt2}] [@option{quiet}]
11407 This issues a JTAG reset (Test-Logic-Reset) and then
11408 runs the XSVF script from @file{filename}.
11409 When a @var{tapname} is specified, the commands are directed at
11411 When @option{virt2} is specified, the @sc{xruntest} command counts
11412 are interpreted as TCK cycles instead of microseconds.
11413 Unless the @option{quiet} option is specified,
11414 messages are logged for comments and some retries.
11417 The OpenOCD sources also include two utility scripts
11418 for working with XSVF; they are not currently installed
11419 after building the software.
11420 You may find them useful:
11423 @item @emph{svf2xsvf} ... converts SVF files into the extended XSVF
11424 syntax understood by the @command{xsvf} command; see notes below.
11425 @item @emph{xsvfdump} ... converts XSVF files into a text output format;
11426 understands the OpenOCD extensions.
11429 The input format accepts a handful of non-standard extensions.
11430 These include three opcodes corresponding to SVF extensions
11431 from Lattice Semiconductor (LCOUNT, LDELAY, LDSR), and
11432 two opcodes supporting a more accurate translation of SVF
11433 (XTRST, XWAITSTATE).
11434 If @emph{xsvfdump} shows a file is using those opcodes, it
11435 probably will not be usable with other XSVF tools.
11438 @section IPDBG: JTAG-Host server
11439 @cindex IPDBG JTAG-Host server
11442 IPDBG is a set of tools to debug IP-Cores. It comprises, among others, a logic analyzer and an arbitrary
11443 waveform generator. These are synthesize-able hardware descriptions of
11444 logic circuits in addition to software for control, visualization and further analysis.
11445 In a session using JTAG for its transport protocol, OpenOCD supports the function
11446 of a JTAG-Host. The JTAG-Host is needed to connect the circuit over JTAG to the
11447 control-software. For more details see @url{http://ipdbg.org}.
11449 @deffn {Command} {ipdbg} [@option{-start|-stop}] @option{-tap @var{tapname}} @option{-hub @var{ir_value} [@var{dr_length}]} [@option{-port @var{number}}] [@option{-tool @var{number}}] [@option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]}]
11450 Starts or stops a IPDBG JTAG-Host server. Arguments can be specified in any order.
11454 @item @option{-start|-stop} starts or stops a IPDBG JTAG-Host server (default: start).
11455 @item @option{-tap @var{tapname}} targeting the TAP @var{tapname}.
11456 @item @option{-hub @var{ir_value}} states that the JTAG hub is
11457 reachable with dr-scans while the JTAG instruction register has the value @var{ir_value}.
11458 @item @option{-port @var{number}} tcp port number where the JTAG-Host is listening.
11459 @item @option{-tool @var{number}} number of the tool/feature. These corresponds to the ports "data_(up/down)_(0..6)" at the JtagHub.
11460 @item @option{-vir [@var{vir_value} [@var{length} [@var{instr_code}]]]} On some devices, the user data-register is only reachable if there is a
11461 specific value in a second dr. This second dr is called vir (virtual ir). With this parameter given, the IPDBG satisfies this condition prior an
11462 access to the IPDBG-Hub. The value shifted into the vir is given by the first parameter @var{vir_value} (default: 0x11). The second
11463 parameter @var{length} is the length of the vir data register (default: 5). With the @var{instr_code} (default: 0x00e) parameter the ir value to
11464 shift data through vir can be configured.
11470 ipdbg -start -tap xc6s.tap -hub 0x02 -port 4242 -tool 4
11472 Starts a server listening on tcp-port 4242 which connects to tool 4.
11473 The connection is through the TAP of a Xilinx Spartan 6 on USER1 instruction (tested with a papillion pro board).
11476 ipdbg -start -tap 10m50.tap -hub 0x00C -vir -port 60000 -tool 1
11478 Starts a server listening on tcp-port 60000 which connects to tool 1 (data_up_1/data_down_1).
11479 The connection is through the TAP of a Intel MAX10 virtual jtag component (sld_instance_index is 0; sld_ir_width is smaller than 5).
11481 @node Utility Commands
11482 @chapter Utility Commands
11483 @cindex Utility Commands
11485 @section RAM testing
11486 @cindex RAM testing
11488 There is often a need to stress-test random access memory (RAM) for
11489 errors. OpenOCD comes with a Tcl implementation of well-known memory
11490 testing procedures allowing the detection of all sorts of issues with
11491 electrical wiring, defective chips, PCB layout and other common
11494 To use them, you usually need to initialise your RAM controller first;
11495 consult your SoC's documentation to get the recommended list of
11496 register operations and translate them to the corresponding
11497 @command{mww}/@command{mwb} commands.
11499 Load the memory testing functions with
11502 source [find tools/memtest.tcl]
11505 to get access to the following facilities:
11507 @deffn {Command} {memTestDataBus} address
11508 Test the data bus wiring in a memory region by performing a walking
11509 1's test at a fixed address within that region.
11512 @deffn {Command} {memTestAddressBus} baseaddress size
11513 Perform a walking 1's test on the relevant bits of the address and
11514 check for aliasing. This test will find single-bit address failures
11515 such as stuck-high, stuck-low, and shorted pins.
11518 @deffn {Command} {memTestDevice} baseaddress size
11519 Test the integrity of a physical memory device by performing an
11520 increment/decrement test over the entire region. In the process every
11521 storage bit in the device is tested as zero and as one.
11524 @deffn {Command} {runAllMemTests} baseaddress size
11525 Run all of the above tests over a specified memory region.
11528 @section Firmware recovery helpers
11529 @cindex Firmware recovery
11531 OpenOCD includes an easy-to-use script to facilitate mass-market
11532 devices recovery with JTAG.
11534 For quickstart instructions run:
11536 openocd -f tools/firmware-recovery.tcl -c firmware_help
11539 @node GDB and OpenOCD
11540 @chapter GDB and OpenOCD
11542 OpenOCD complies with the remote gdbserver protocol and, as such, can be used
11543 to debug remote targets.
11544 Setting up GDB to work with OpenOCD can involve several components:
11547 @item The OpenOCD server support for GDB may need to be configured.
11548 @xref{gdbconfiguration,,GDB Configuration}.
11549 @item GDB's support for OpenOCD may need configuration,
11550 as shown in this chapter.
11551 @item If you have a GUI environment like Eclipse,
11552 that also will probably need to be configured.
11555 Of course, the version of GDB you use will need to be one which has
11556 been built to know about the target CPU you're using. It's probably
11557 part of the tool chain you're using. For example, if you are doing
11558 cross-development for ARM on an x86 PC, instead of using the native
11559 x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
11560 if that's the tool chain used to compile your code.
11562 @section Connecting to GDB
11563 @cindex Connecting to GDB
11564 Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
11565 instance GDB 6.3 has a known bug that produces bogus memory access
11566 errors, which has since been fixed; see
11567 @url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
11569 OpenOCD can communicate with GDB in two ways:
11573 A socket (TCP/IP) connection is typically started as follows:
11575 target extended-remote localhost:3333
11577 This would cause GDB to connect to the gdbserver on the local pc using port 3333.
11579 The extended remote protocol is a super-set of the remote protocol and should
11580 be the preferred choice. More details are available in GDB documentation
11581 @url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
11583 To speed-up typing, any GDB command can be abbreviated, including the extended
11584 remote command above that becomes:
11589 @b{Note:} If any backward compatibility issue requires using the old remote
11590 protocol in place of the extended remote one, the former protocol is still
11591 available through the command:
11593 target remote localhost:3333
11597 A pipe connection is typically started as follows:
11599 target extended-remote | \
11600 openocd -c "gdb_port pipe; log_output openocd.log"
11602 This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
11603 Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
11604 session. log_output sends the log output to a file to ensure that the pipe is
11605 not saturated when using higher debug level outputs.
11608 To list the available OpenOCD commands type @command{monitor help} on the
11611 @section Sample GDB session startup
11613 With the remote protocol, GDB sessions start a little differently
11614 than they do when you're debugging locally.
11615 Here's an example showing how to start a debug session with a
11617 In this case the program was linked to be loaded into SRAM on a Cortex-M3.
11618 Most programs would be written into flash (address 0) and run from there.
11621 $ arm-none-eabi-gdb example.elf
11622 (gdb) target extended-remote localhost:3333
11623 Remote debugging using localhost:3333
11625 (gdb) monitor reset halt
11628 Loading section .vectors, size 0x100 lma 0x20000000
11629 Loading section .text, size 0x5a0 lma 0x20000100
11630 Loading section .data, size 0x18 lma 0x200006a0
11631 Start address 0x2000061c, load size 1720
11632 Transfer rate: 22 KB/sec, 573 bytes/write.
11638 You could then interrupt the GDB session to make the program break,
11639 type @command{where} to show the stack, @command{list} to show the
11640 code around the program counter, @command{step} through code,
11641 set breakpoints or watchpoints, and so on.
11643 @section Configuring GDB for OpenOCD
11645 OpenOCD supports the gdb @option{qSupported} packet, this enables information
11646 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
11647 packet size and the device's memory map.
11648 You do not need to configure the packet size by hand,
11649 and the relevant parts of the memory map should be automatically
11650 set up when you declare (NOR) flash banks.
11652 However, there are other things which GDB can't currently query.
11653 You may need to set those up by hand.
11654 As OpenOCD starts up, you will often see a line reporting
11658 Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
11661 You can pass that information to GDB with these commands:
11664 set remote hardware-breakpoint-limit 6
11665 set remote hardware-watchpoint-limit 4
11668 With that particular hardware (Cortex-M3) the hardware breakpoints
11669 only work for code running from flash memory. Most other ARM systems
11670 do not have such restrictions.
11672 Rather than typing such commands interactively, you may prefer to
11673 save them in a file and have GDB execute them as it starts, perhaps
11674 using a @file{.gdbinit} in your project directory or starting GDB
11675 using @command{gdb -x filename}.
11677 @section Programming using GDB
11678 @cindex Programming using GDB
11679 @anchor{programmingusinggdb}
11681 By default the target memory map is sent to GDB. This can be disabled by
11682 the following OpenOCD configuration option:
11684 gdb_memory_map disable
11686 For this to function correctly a valid flash configuration must also be set
11687 in OpenOCD. For faster performance you should also configure a valid
11690 Informing GDB of the memory map of the target will enable GDB to protect any
11691 flash areas of the target and use hardware breakpoints by default. This means
11692 that the OpenOCD option @command{gdb_breakpoint_override} is not required when
11693 using a memory map. @xref{gdbbreakpointoverride,,gdb_breakpoint_override}.
11695 To view the configured memory map in GDB, use the GDB command @option{info mem}.
11696 All other unassigned addresses within GDB are treated as RAM.
11698 GDB 6.8 and higher set any memory area not in the memory map as inaccessible.
11699 This can be changed to the old behaviour by using the following GDB command
11701 set mem inaccessible-by-default off
11704 If @command{gdb_flash_program enable} is also used, GDB will be able to
11705 program any flash memory using the vFlash interface.
11707 GDB will look at the target memory map when a load command is given, if any
11708 areas to be programmed lie within the target flash area the vFlash packets
11711 If the target needs configuring before GDB programming, set target
11712 event gdb-flash-erase-start:
11714 $_TARGETNAME configure -event gdb-flash-erase-start BODY
11716 @xref{targetevents,,Target Events}, for other GDB programming related events.
11718 To verify any flash programming the GDB command @option{compare-sections}
11721 @section Using GDB as a non-intrusive memory inspector
11722 @cindex Using GDB as a non-intrusive memory inspector
11723 @anchor{gdbmeminspect}
11725 If your project controls more than a blinking LED, let's say a heavy industrial
11726 robot or an experimental nuclear reactor, stopping the controlling process
11727 just because you want to attach GDB is not a good option.
11729 OpenOCD does not support GDB non-stop mode (might be implemented in the future).
11730 Though there is a possible setup where the target does not get stopped
11731 and GDB treats it as it were running.
11732 If the target supports background access to memory while it is running,
11733 you can use GDB in this mode to inspect memory (mainly global variables)
11734 without any intrusion of the target process.
11736 Remove default setting of gdb-attach event. @xref{targetevents,,Target Events}.
11737 Place following command after target configuration:
11739 $_TARGETNAME configure -event gdb-attach @{@}
11742 If any of installed flash banks does not support probe on running target,
11743 switch off gdb_memory_map:
11745 gdb_memory_map disable
11748 Ensure GDB is configured without interrupt-on-connect.
11749 Some GDB versions set it by default, some does not.
11751 set remote interrupt-on-connect off
11754 If you switched gdb_memory_map off, you may want to setup GDB memory map
11755 manually or issue @command{set mem inaccessible-by-default off}
11757 Now you can issue GDB command @command{target extended-remote ...} and inspect memory
11758 of a running target. Do not use GDB commands @command{continue},
11759 @command{step} or @command{next} as they synchronize GDB with your target
11760 and GDB would require stopping the target to get the prompt back.
11762 Do not use this mode under an IDE like Eclipse as it caches values of
11763 previously shown variables.
11765 It's also possible to connect more than one GDB to the same target by the
11766 target's configuration option @code{-gdb-max-connections}. This allows, for
11767 example, one GDB to run a script that continuously polls a set of variables
11768 while other GDB can be used interactively. Be extremely careful in this case,
11769 because the two GDB can easily get out-of-sync.
11771 @section RTOS Support
11772 @cindex RTOS Support
11773 @anchor{gdbrtossupport}
11775 OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled.
11776 It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}.
11778 @xref{Threads, Debugging Programs with Multiple Threads,
11779 Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant
11782 @* An example setup is below:
11785 $_TARGETNAME configure -rtos auto
11788 This will attempt to auto detect the RTOS within your application.
11790 Currently supported rtos's include:
11792 @item @option{eCos}
11793 @item @option{ThreadX}
11794 @item @option{FreeRTOS}
11795 @item @option{linux}
11796 @item @option{ChibiOS}
11797 @item @option{embKernel}
11799 @item @option{uCOS-III}
11800 @item @option{nuttx}
11801 @item @option{RIOT}
11802 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
11803 @item @option{Zephyr}
11806 Before an RTOS can be detected, it must export certain symbols; otherwise, it cannot
11807 be used by OpenOCD. Below is a list of the required symbols for each supported RTOS.
11811 Cyg_Thread::thread_list, Cyg_Scheduler_Base::current_thread.
11812 @item ThreadX symbols
11813 _tx_thread_current_ptr, _tx_thread_created_ptr, _tx_thread_created_count.
11814 @item FreeRTOS symbols
11816 pxCurrentTCB, pxReadyTasksLists, xDelayedTaskList1, xDelayedTaskList2,
11817 pxDelayedTaskList, pxOverflowDelayedTaskList, xPendingReadyList,
11818 uxCurrentNumberOfTasks, uxTopUsedPriority.
11820 @item linux symbols
11822 @item ChibiOS symbols
11823 rlist, ch_debug, chSysInit.
11824 @item embKernel symbols
11825 Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep,
11826 Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount.
11828 _mqx_kernel_data, MQX_init_struct.
11829 @item uC/OS-III symbols
11830 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty.
11831 @item nuttx symbols
11832 g_readytorun, g_tasklisttable.
11835 sched_threads, sched_num_threads, sched_active_pid, max_threads,
11838 @item Zephyr symbols
11839 _kernel, _kernel_openocd_offsets, _kernel_openocd_size_t_size
11842 For most RTOS supported the above symbols will be exported by default. However for
11843 some, eg. FreeRTOS, uC/OS-III and Zephyr, extra steps must be taken.
11845 Zephyr must be compiled with the DEBUG_THREAD_INFO option. This will generate some symbols
11846 with information needed in order to build the list of threads.
11848 FreeRTOS and uC/OS-III RTOSes may require additional OpenOCD-specific file to be linked
11849 along with the project:
11853 contrib/rtos-helpers/FreeRTOS-openocd.c
11855 contrib/rtos-helpers/uCOS-III-openocd.c
11858 @anchor{usingopenocdsmpwithgdb}
11859 @section Using OpenOCD SMP with GDB
11863 OpenOCD includes a pseudo RTOS called @emph{hwthread} that presents CPU cores
11864 ("hardware threads") in an SMP system as threads to GDB. With this extension,
11865 GDB can be used to inspect the state of an SMP system in a natural way.
11866 After halting the system, using the GDB command @command{info threads} will
11867 list the context of each active CPU core in the system. GDB's @command{thread}
11868 command can be used to switch the view to a different CPU core.
11869 The @command{step} and @command{stepi} commands can be used to step a specific core
11870 while other cores are free-running or remain halted, depending on the
11871 scheduler-locking mode configured in GDB.
11873 @node Tcl Scripting API
11874 @chapter Tcl Scripting API
11875 @cindex Tcl Scripting API
11876 @cindex Tcl scripts
11879 Tcl commands are stateless; e.g. the @command{telnet} command has
11880 a concept of currently active target, the Tcl API proc's take this sort
11881 of state information as an argument to each proc.
11883 There are three main types of return values: single value, name value
11884 pair list and lists.
11886 Name value pair. The proc 'foo' below returns a name/value pair
11890 > set foo(me) Duane
11891 > set foo(you) Oyvind
11892 > set foo(mouse) Micky
11893 > set foo(duck) Donald
11905 me Duane you Oyvind mouse Micky duck Donald
11908 Thus, to get the names of the associative array is easy:
11911 foreach { name value } [set foo] {
11912 puts "Name: $name, Value: $value"
11916 Lists returned should be relatively small. Otherwise, a range
11917 should be passed in to the proc in question.
11919 @section Internal low-level Commands
11921 By "low-level", we mean commands that a human would typically not
11925 @item @b{flash banks} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}> <@var{target}> [@option{driver options} ...]
11927 Return information about the flash banks
11929 @item @b{capture} <@var{command}>
11931 Run <@var{command}> and return full log output that was produced during
11932 its execution. Example:
11935 > capture "reset init"
11940 OpenOCD commands can consist of two words, e.g. "flash banks". The
11941 @file{startup.tcl} "unknown" proc will translate this into a Tcl proc
11942 called "flash_banks".
11944 @section Tcl RPC server
11947 OpenOCD provides a simple RPC server that allows to run arbitrary Tcl
11948 commands and receive the results.
11950 To access it, your application needs to connect to a configured TCP port
11951 (see @command{tcl_port}). Then it can pass any string to the
11952 interpreter terminating it with @code{0x1a} and wait for the return
11953 value (it will be terminated with @code{0x1a} as well). This can be
11954 repeated as many times as desired without reopening the connection.
11956 It is not needed anymore to prefix the OpenOCD commands with
11957 @code{ocd_} to get the results back. But sometimes you might need the
11958 @command{capture} command.
11960 See @file{contrib/rpc_examples/} for specific client implementations.
11962 @section Tcl RPC server notifications
11963 @cindex RPC Notifications
11965 Notifications are sent asynchronously to other commands being executed over
11966 the RPC server, so the port must be polled continuously.
11968 Target event, state and reset notifications are emitted as Tcl associative arrays
11969 in the following format.
11972 type target_event event [event-name]
11973 type target_state state [state-name]
11974 type target_reset mode [reset-mode]
11977 @deffn {Command} {tcl_notifications} [on/off]
11978 Toggle output of target notifications to the current Tcl RPC server.
11979 Only available from the Tcl RPC server.
11984 @section Tcl RPC server trace output
11985 @cindex RPC trace output
11987 Trace data is sent asynchronously to other commands being executed over
11988 the RPC server, so the port must be polled continuously.
11990 Target trace data is emitted as a Tcl associative array in the following format.
11993 type target_trace data [trace-data-hex-encoded]
11996 @deffn {Command} {tcl_trace} [on/off]
11997 Toggle output of target trace data to the current Tcl RPC server.
11998 Only available from the Tcl RPC server.
12001 See an example application here:
12002 @url{https://github.com/apmorton/OpenOcdTraceUtil} [OpenOcdTraceUtil]
12011 @item @b{RTCK, also known as: Adaptive Clocking - What is it?}
12013 @cindex adaptive clocking
12016 In digital circuit design it is often referred to as ``clock
12017 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
12018 operating at some speed, your CPU target is operating at another.
12019 The two clocks are not synchronised, they are ``asynchronous''
12021 In order for the two to work together they must be synchronised
12022 well enough to work; JTAG can't go ten times faster than the CPU,
12023 for example. There are 2 basic options:
12026 Use a special "adaptive clocking" circuit to change the JTAG
12027 clock rate to match what the CPU currently supports.
12029 The JTAG clock must be fixed at some speed that's enough slower than
12030 the CPU clock that all TMS and TDI transitions can be detected.
12033 @b{Does this really matter?} For some chips and some situations, this
12034 is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
12035 the CPU has no difficulty keeping up with JTAG.
12036 Startup sequences are often problematic though, as are other
12037 situations where the CPU clock rate changes (perhaps to save
12040 For example, Atmel AT91SAM chips start operation from reset with
12041 a 32kHz system clock. Boot firmware may activate the main oscillator
12042 and PLL before switching to a faster clock (perhaps that 500 MHz
12044 If you're using JTAG to debug that startup sequence, you must slow
12045 the JTAG clock to sometimes 1 to 4kHz. After startup completes,
12046 JTAG can use a faster clock.
12048 Consider also debugging a 500MHz ARM926 hand held battery powered
12049 device that enters a low power ``deep sleep'' mode, at 32kHz CPU
12050 clock, between keystrokes unless it has work to do. When would
12051 that 5 MHz JTAG clock be usable?
12053 @b{Solution #1 - A special circuit}
12055 In order to make use of this,
12056 your CPU, board, and JTAG adapter must all support the RTCK
12057 feature. Not all of them support this; keep reading!
12059 The RTCK ("Return TCK") signal in some ARM chips is used to help with
12060 this problem. ARM has a good description of the problem described at
12061 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
12062 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
12063 work? / how does adaptive clocking work?''.
12065 The nice thing about adaptive clocking is that ``battery powered hand
12066 held device example'' - the adaptiveness works perfectly all the
12067 time. One can set a break point or halt the system in the deep power
12068 down code, slow step out until the system speeds up.
12070 Note that adaptive clocking may also need to work at the board level,
12071 when a board-level scan chain has multiple chips.
12072 Parallel clock voting schemes are good way to implement this,
12073 both within and between chips, and can easily be implemented
12075 It's not difficult to have logic fan a module's input TCK signal out
12076 to each TAP in the scan chain, and then wait until each TAP's RTCK comes
12077 back with the right polarity before changing the output RTCK signal.
12078 Texas Instruments makes some clock voting logic available
12079 for free (with no support) in VHDL form; see
12080 @url{http://tiexpressdsp.com/index.php/Adaptive_Clocking}
12082 @b{Solution #2 - Always works - but may be slower}
12084 Often this is a perfectly acceptable solution.
12086 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
12087 the target clock speed. But what that ``magic division'' is varies
12088 depending on the chips on your board.
12089 @b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
12090 ARM11 cores use an 8:1 division.
12091 @b{Xilinx rule of thumb} is 1/12 the clock speed.
12093 Note: most full speed FT2232 based JTAG adapters are limited to a
12094 maximum of 6MHz. The ones using USB high speed chips (FT2232H)
12095 often support faster clock rates (and adaptive clocking).
12097 You can still debug the 'low power' situations - you just need to
12098 either use a fixed and very slow JTAG clock rate ... or else
12099 manually adjust the clock speed at every step. (Adjusting is painful
12100 and tedious, and is not always practical.)
12102 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
12103 have a special debug mode in your application that does a ``high power
12104 sleep''. If you are careful - 98% of your problems can be debugged
12107 Note that on ARM you may need to avoid using the @emph{wait for interrupt}
12108 operation in your idle loops even if you don't otherwise change the CPU
12110 That operation gates the CPU clock, and thus the JTAG clock; which
12111 prevents JTAG access. One consequence is not being able to @command{halt}
12112 cores which are executing that @emph{wait for interrupt} operation.
12114 To set the JTAG frequency use the command:
12117 # Example: 1.234MHz
12122 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
12124 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
12125 around Windows filenames.
12138 @item @b{Missing: cygwin1.dll} OpenOCD complains about a missing cygwin1.dll.
12140 Make sure you have Cygwin installed, or at least a version of OpenOCD that
12141 claims to come with all the necessary DLLs. When using Cygwin, try launching
12142 OpenOCD from the Cygwin shell.
12144 @item @b{Breakpoint Issue} I'm trying to set a breakpoint using GDB (or a front-end like Insight or
12145 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
12146 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
12148 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
12149 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720T or ARM920T,
12150 software breakpoints consume one of the two available hardware breakpoints.
12152 @item @b{LPC2000 Flash} When erasing or writing LPC2000 on-chip flash, the operation fails at random.
12154 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
12155 clock at the time you're programming the flash. If you've specified the crystal's
12156 frequency, make sure the PLL is disabled. If you've specified the full core speed
12157 (e.g. 60MHz), make sure the PLL is enabled.
12159 @item @b{Amontec Chameleon} When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
12160 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
12161 out while waiting for end of scan, rtck was disabled".
12163 Make sure your PC's parallel port operates in EPP mode. You might have to try several
12164 settings in your PC BIOS (ECP, EPP, and different versions of those).
12166 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
12167 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
12168 memory read caused data abort".
12170 The errors are non-fatal, and are the result of GDB trying to trace stack frames
12171 beyond the last valid frame. It might be possible to prevent this by setting up
12172 a proper "initial" stack frame, if you happen to know what exactly has to
12173 be done, feel free to add this here.
12175 @b{Simple:} In your startup code - push 8 registers of zeros onto the
12176 stack before calling main(). What GDB is doing is ``climbing'' the run
12177 time stack by reading various values on the stack using the standard
12178 call frame for the target. GDB keeps going - until one of 2 things
12179 happen @b{#1} an invalid frame is found, or @b{#2} some huge number of
12180 stackframes have been processed. By pushing zeros on the stack, GDB
12183 @b{Debugging Interrupt Service Routines} - In your ISR before you call
12184 your C code, do the same - artificially push some zeros onto the stack,
12185 remember to pop them off when the ISR is done.
12187 @b{Also note:} If you have a multi-threaded operating system, they
12188 often do not @b{in the interest of saving memory} waste these few
12192 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
12193 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
12195 This warning doesn't indicate any serious problem, as long as you don't want to
12196 debug your core right out of reset. Your .cfg file specified @option{reset_config
12197 trst_and_srst srst_pulls_trst} to tell OpenOCD that either your board,
12198 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
12199 independently. With this setup, it's not possible to halt the core right out of
12200 reset, everything else should work fine.
12202 @item @b{USB Power} When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
12203 toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
12204 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
12205 quit with an error message. Is there a stability issue with OpenOCD?
12207 No, this is not a stability issue concerning OpenOCD. Most users have solved
12208 this issue by simply using a self-powered USB hub, which they connect their
12209 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
12210 supply stable enough for the Amontec JTAGkey to be operated.
12212 @b{Laptops running on battery have this problem too...}
12214 @item @b{GDB Disconnects} When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
12215 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
12216 What does that mean and what might be the reason for this?
12218 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
12219 has closed the connection to OpenOCD. This might be a GDB issue.
12221 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
12222 are described, there is a parameter for specifying the clock frequency
12223 for LPC2000 internal flash devices (e.g. @option{flash bank $_FLASHNAME lpc2000
12224 0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
12225 specified in kilohertz. However, I do have a quartz crystal of a
12226 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
12227 i.e. 14,745.600 kHz). Is it possible to specify real numbers for the
12230 No. The clock frequency specified here must be given as an integral number.
12231 However, this clock frequency is used by the In-Application-Programming (IAP)
12232 routines of the LPC2000 family only, which seems to be very tolerant concerning
12233 the given clock frequency, so a slight difference between the specified clock
12234 frequency and the actual clock frequency will not cause any trouble.
12236 @item @b{Command Order} Do I have to keep a specific order for the commands in the configuration file?
12238 Well, yes and no. Commands can be given in arbitrary order, yet the
12239 devices listed for the JTAG scan chain must be given in the right
12240 order (jtag newdevice), with the device closest to the TDO-Pin being
12241 listed first. In general, whenever objects of the same type exist
12242 which require an index number, then these objects must be given in the
12243 right order (jtag newtap, targets and flash banks - a target
12244 references a jtag newtap and a flash bank references a target).
12246 You can use the ``scan_chain'' command to verify and display the tap order.
12248 Also, some commands can't execute until after @command{init} has been
12249 processed. Such commands include @command{nand probe} and everything
12250 else that needs to write to controller registers, perhaps for setting
12251 up DRAM and loading it with code.
12253 @anchor{faqtaporder}
12254 @item @b{JTAG TAP Order} Do I have to declare the TAPS in some
12257 Yes; whenever you have more than one, you must declare them in
12258 the same order used by the hardware.
12260 Many newer devices have multiple JTAG TAPs. For example:
12261 STMicroelectronics STM32 chips have two TAPs, a ``boundary scan TAP'' and
12262 ``Cortex-M3'' TAP. Example: The STM32 reference manual, Document ID:
12263 RM0008, Section 26.5, Figure 259, page 651/681, the ``TDI'' pin is
12264 connected to the boundary scan TAP, which then connects to the
12265 Cortex-M3 TAP, which then connects to the TDO pin.
12267 Thus, the proper order for the STM32 chip is: (1) The Cortex-M3, then
12268 (2) The boundary scan TAP. If your board includes an additional JTAG
12269 chip in the scan chain (for example a Xilinx CPLD or FPGA) you could
12270 place it before or after the STM32 chip in the chain. For example:
12273 @item OpenOCD_TDI(output) -> STM32 TDI Pin (BS Input)
12274 @item STM32 BS TDO (output) -> STM32 Cortex-M3 TDI (input)
12275 @item STM32 Cortex-M3 TDO (output) -> SM32 TDO Pin
12276 @item STM32 TDO Pin (output) -> Xilinx TDI Pin (input)
12277 @item Xilinx TDO Pin -> OpenOCD TDO (input)
12280 The ``jtag device'' commands would thus be in the order shown below. Note:
12283 @item jtag newtap Xilinx tap -irlen ...
12284 @item jtag newtap stm32 cpu -irlen ...
12285 @item jtag newtap stm32 bs -irlen ...
12286 @item # Create the debug target and say where it is
12287 @item target create stm32.cpu -chain-position stm32.cpu ...
12291 @item @b{SYSCOMP} Sometimes my debugging session terminates with an error. When I look into the
12292 log file, I can see these error messages: Error: arm7_9_common.c:561
12293 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP
12299 @node Tcl Crash Course
12300 @chapter Tcl Crash Course
12303 Not everyone knows Tcl - this is not intended to be a replacement for
12304 learning Tcl, the intent of this chapter is to give you some idea of
12305 how the Tcl scripts work.
12307 This chapter is written with two audiences in mind. (1) OpenOCD users
12308 who need to understand a bit more of how Jim-Tcl works so they can do
12309 something useful, and (2) those that want to add a new command to
12312 @section Tcl Rule #1
12313 There is a famous joke, it goes like this:
12315 @item Rule #1: The wife is always correct
12316 @item Rule #2: If you think otherwise, See Rule #1
12319 The Tcl equal is this:
12322 @item Rule #1: Everything is a string
12323 @item Rule #2: If you think otherwise, See Rule #1
12326 As in the famous joke, the consequences of Rule #1 are profound. Once
12327 you understand Rule #1, you will understand Tcl.
12329 @section Tcl Rule #1b
12330 There is a second pair of rules.
12332 @item Rule #1: Control flow does not exist. Only commands
12333 @* For example: the classic FOR loop or IF statement is not a control
12334 flow item, they are commands, there is no such thing as control flow
12336 @item Rule #2: If you think otherwise, See Rule #1
12337 @* Actually what happens is this: There are commands that by
12338 convention, act like control flow key words in other languages. One of
12339 those commands is the word ``for'', another command is ``if''.
12342 @section Per Rule #1 - All Results are strings
12343 Every Tcl command results in a string. The word ``result'' is used
12344 deliberately. No result is just an empty string. Remember: @i{Rule #1 -
12345 Everything is a string}
12347 @section Tcl Quoting Operators
12348 In life of a Tcl script, there are two important periods of time, the
12349 difference is subtle.
12352 @item Evaluation Time
12355 The two key items here are how ``quoted things'' work in Tcl. Tcl has
12356 three primary quoting constructs, the [square-brackets] the
12357 @{curly-braces@} and ``double-quotes''
12359 By now you should know $VARIABLES always start with a $DOLLAR
12360 sign. BTW: To set a variable, you actually use the command ``set'', as
12361 in ``set VARNAME VALUE'' much like the ancient BASIC language ``let x
12362 = 1'' statement, but without the equal sign.
12365 @item @b{[square-brackets]}
12366 @* @b{[square-brackets]} are command substitutions. It operates much
12367 like Unix Shell `back-ticks`. The result of a [square-bracket]
12368 operation is exactly 1 string. @i{Remember Rule #1 - Everything is a
12369 string}. These two statements are roughly identical:
12373 echo "The Date is: $X"
12376 puts "The Date is: $X"
12378 @item @b{``double-quoted-things''}
12379 @* @b{``double-quoted-things''} are just simply quoted
12380 text. $VARIABLES and [square-brackets] are expanded in place - the
12381 result however is exactly 1 string. @i{Remember Rule #1 - Everything
12385 puts "It is now \"[date]\", $x is in 1 hour"
12387 @item @b{@{Curly-Braces@}}
12388 @*@b{@{Curly-Braces@}} are magic: $VARIABLES and [square-brackets] are
12389 parsed, but are NOT expanded or executed. @{Curly-Braces@} are like
12390 'single-quote' operators in BASH shell scripts, with the added
12391 feature: @{curly-braces@} can be nested, single quotes can not. @{@{@{this is
12392 nested 3 times@}@}@} NOTE: [date] is a bad example;
12393 at this writing, Jim/OpenOCD does not have a date command.
12396 @section Consequences of Rule 1/2/3/4
12398 The consequences of Rule 1 are profound.
12400 @subsection Tokenisation & Execution.
12402 Of course, whitespace, blank lines and #comment lines are handled in
12405 As a script is parsed, each (multi) line in the script file is
12406 tokenised and according to the quoting rules. After tokenisation, that
12407 line is immediately executed.
12409 Multi line statements end with one or more ``still-open''
12410 @{curly-braces@} which - eventually - closes a few lines later.
12412 @subsection Command Execution
12414 Remember earlier: There are no ``control flow''
12415 statements in Tcl. Instead there are COMMANDS that simply act like
12416 control flow operators.
12418 Commands are executed like this:
12421 @item Parse the next line into (argc) and (argv[]).
12422 @item Look up (argv[0]) in a table and call its function.
12423 @item Repeat until End Of File.
12426 It sort of works like this:
12429 ReadAndParse( &argc, &argv );
12431 cmdPtr = LookupCommand( argv[0] );
12433 (*cmdPtr->Execute)( argc, argv );
12437 When the command ``proc'' is parsed (which creates a procedure
12438 function) it gets 3 parameters on the command line. @b{1} the name of
12439 the proc (function), @b{2} the list of parameters, and @b{3} the body
12440 of the function. Note the choice of words: LIST and BODY. The PROC
12441 command stores these items in a table somewhere so it can be found by
12442 ``LookupCommand()''
12444 @subsection The FOR command
12446 The most interesting command to look at is the FOR command. In Tcl,
12447 the FOR command is normally implemented in C. Remember, FOR is a
12448 command just like any other command.
12450 When the ascii text containing the FOR command is parsed, the parser
12451 produces 5 parameter strings, @i{(If in doubt: Refer to Rule #1)} they
12455 @item The ascii text 'for'
12456 @item The start text
12457 @item The test expression
12458 @item The next text
12459 @item The body text
12462 Sort of reminds you of ``main( int argc, char **argv )'' does it not?
12463 Remember @i{Rule #1 - Everything is a string.} The key point is this:
12464 Often many of those parameters are in @{curly-braces@} - thus the
12465 variables inside are not expanded or replaced until later.
12467 Remember that every Tcl command looks like the classic ``main( argc,
12468 argv )'' function in C. In JimTCL - they actually look like this:
12472 MyCommand( Jim_Interp *interp,
12474 Jim_Obj * const *argvs );
12477 Real Tcl is nearly identical. Although the newer versions have
12478 introduced a byte-code parser and interpreter, but at the core, it
12479 still operates in the same basic way.
12481 @subsection FOR command implementation
12483 To understand Tcl it is perhaps most helpful to see the FOR
12484 command. Remember, it is a COMMAND not a control flow structure.
12486 In Tcl there are two underlying C helper functions.
12488 Remember Rule #1 - You are a string.
12490 The @b{first} helper parses and executes commands found in an ascii
12491 string. Commands can be separated by semicolons, or newlines. While
12492 parsing, variables are expanded via the quoting rules.
12494 The @b{second} helper evaluates an ascii string as a numerical
12495 expression and returns a value.
12497 Here is an example of how the @b{FOR} command could be
12498 implemented. The pseudo code below does not show error handling.
12500 void Execute_AsciiString( void *interp, const char *string );
12502 int Evaluate_AsciiExpression( void *interp, const char *string );
12505 MyForCommand( void *interp,
12510 SetResult( interp, "WRONG number of parameters");
12514 // argv[0] = the ascii string just like C
12516 // Execute the start statement.
12517 Execute_AsciiString( interp, argv[1] );
12519 // Top of loop test
12521 i = Evaluate_AsciiExpression(interp, argv[2]);
12525 // Execute the body
12526 Execute_AsciiString( interp, argv[3] );
12528 // Execute the LOOP part
12529 Execute_AsciiString( interp, argv[4] );
12533 SetResult( interp, "" );
12538 Every other command IF, WHILE, FORMAT, PUTS, EXPR, everything works
12539 in the same basic way.
12541 @section OpenOCD Tcl Usage
12543 @subsection source and find commands
12544 @b{Where:} In many configuration files
12545 @* Example: @b{ source [find FILENAME] }
12546 @*Remember the parsing rules
12548 @item The @command{find} command is in square brackets,
12549 and is executed with the parameter FILENAME. It should find and return
12550 the full path to a file with that name; it uses an internal search path.
12551 The RESULT is a string, which is substituted into the command line in
12552 place of the bracketed @command{find} command.
12553 (Don't try to use a FILENAME which includes the "#" character.
12554 That character begins Tcl comments.)
12555 @item The @command{source} command is executed with the resulting filename;
12556 it reads a file and executes as a script.
12558 @subsection format command
12559 @b{Where:} Generally occurs in numerous places.
12560 @* Tcl has no command like @b{printf()}, instead it has @b{format}, which is really more like
12566 puts [format "The answer: %d" [expr @{$x * $y@}]]
12569 @item The SET command creates 2 variables, X and Y.
12570 @item The double [nested] EXPR command performs math
12571 @* The EXPR command produces numerical result as a string.
12572 @* Refer to Rule #1
12573 @item The format command is executed, producing a single string
12574 @* Refer to Rule #1.
12575 @item The PUTS command outputs the text.
12577 @subsection Body or Inlined Text
12578 @b{Where:} Various TARGET scripts.
12581 proc someproc @{@} @{
12582 ... multiple lines of stuff ...
12584 $_TARGETNAME configure -event FOO someproc
12585 #2 Good - no variables
12586 $_TARGETNAME configure -event foo "this ; that;"
12587 #3 Good Curly Braces
12588 $_TARGETNAME configure -event FOO @{
12589 puts "Time: [date]"
12591 #4 DANGER DANGER DANGER
12592 $_TARGETNAME configure -event foo "puts \"Time: [date]\""
12595 @item The $_TARGETNAME is an OpenOCD variable convention.
12596 @*@b{$_TARGETNAME} represents the last target created, the value changes
12597 each time a new target is created. Remember the parsing rules. When
12598 the ascii text is parsed, the @b{$_TARGETNAME} becomes a simple string,
12599 the name of the target which happens to be a TARGET (object)
12601 @item The 2nd parameter to the @option{-event} parameter is a TCBODY
12602 @*There are 4 examples:
12604 @item The TCLBODY is a simple string that happens to be a proc name
12605 @item The TCLBODY is several simple commands separated by semicolons
12606 @item The TCLBODY is a multi-line @{curly-brace@} quoted string
12607 @item The TCLBODY is a string with variables that get expanded.
12610 In the end, when the target event FOO occurs the TCLBODY is
12611 evaluated. Method @b{#1} and @b{#2} are functionally identical. For
12612 Method @b{#3} and @b{#4} it is more interesting. What is the TCLBODY?
12614 Remember the parsing rules. In case #3, @{curly-braces@} mean the
12615 $VARS and [square-brackets] are expanded later, when the EVENT occurs,
12616 and the text is evaluated. In case #4, they are replaced before the
12617 ``Target Object Command'' is executed. This occurs at the same time
12618 $_TARGETNAME is replaced. In case #4 the date will never
12619 change. @{BTW: [date] is a bad example; at this writing,
12620 Jim/OpenOCD does not have a date command@}
12622 @subsection Global Variables
12623 @b{Where:} You might discover this when writing your own procs @* In
12624 simple terms: Inside a PROC, if you need to access a global variable
12625 you must say so. See also ``upvar''. Example:
12627 proc myproc @{ @} @{
12628 set y 0 #Local variable Y
12629 global x #Global variable X
12630 puts [format "X=%d, Y=%d" $x $y]
12633 @section Other Tcl Hacks
12634 @b{Dynamic variable creation}
12636 # Dynamically create a bunch of variables.
12637 for @{ set x 0 @} @{ $x < 32 @} @{ set x [expr @{$x + 1@}]@} @{
12639 set vn [format "BIT%d" $x]
12643 set $vn [expr @{1 << $x@}]
12646 @b{Dynamic proc/command creation}
12648 # One "X" function - 5 uart functions.
12649 foreach who @{A B C D E@}
12650 proc [format "show_uart%c" $who] @{ @} "show_UARTx $who"
12655 @appendix The GNU Free Documentation License.
12658 @node OpenOCD Concept Index
12659 @comment DO NOT use the plain word ``Index'', reason: CYGWIN filename
12660 @comment case issue with ``Index.html'' and ``index.html''
12661 @comment Occurs when creating ``--html --no-split'' output
12662 @comment This fix is based on: http://sourceware.org/ml/binutils/2006-05/msg00215.html
12663 @unnumbered OpenOCD Concept Index
12667 @node Command and Driver Index
12668 @unnumbered Command and Driver Index