Nicolas Pitre listed some more devices.

[fw/openocd] / doc / openocd.texi

\input texinfo  @c -*-texinfo-*-\r
@c %**start of header\r
@setfilename openocd.info\r
@settitle Open On-Chip Debugger (openocd)\r
@c %**end of header\r
\r
@include version.texi\r
\r
@titlepage\r
@title Open On-Chip Debugger (openocd)\r
@subtitle Edition @value{EDITION} for openocd version @value{VERSION}\r
@subtitle @value{UPDATED}\r
@page\r
@vskip 0pt plus 1filll\r
@end titlepage\r
\r
@contents\r
\r
@node Top, About, , (dir)\r
@top OpenOCD\r
\r
This is edition @value{EDITION} of the openocd manual for version\r
@value{VERSION}, @value{UPDATED}\r
\r
@menu\r
* About::             About Openocd.\r
* Developers::        \r
* Building::          Building Openocd\r
* Running::           Running Openocd\r
* Configuration::     Openocd Configuration.\r
* Commands::          Openocd Commands\r
* Sample Scripts::    Sample Target Scripts\r
* GDB and Openocd::   Using GDB and Openocd\r
* FAQ::               Frequently Asked Questions\r
* License::           GNU Free Documentation License\r
* Index::             Main index.\r
@end menu\r
\r
@node About\r
@unnumbered About\r
@cindex about\r
\r
The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming\r
and boundary-scan testing for embedded target devices. The targets are interfaced\r
using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other\r
connection types in the future.\r
\r
Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the\r
Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),\r
ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and\r
Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.\r
\r
Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion\r
command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3\r
and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.\r
\r
@node Developers\r
@chapter Developers\r
@cindex developers\r
\r
Openocd has been created by Dominic Rath as part of a diploma thesis written at the\r
University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).\r
Others interested in improving the state of free and open debug and testing technology\r
are welcome to participate.\r
\r
Other developers have contributed support for additional targets and flashes as well\r
as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors. \r
\r
@node Building\r
@chapter Building\r
@cindex building openocd\r
\r
You can download the current SVN version with SVN client of your choice from the\r
following repositories:\r
\r
 (@uref{svn://svn.berlios.de/openocd/trunk})\r
\r
or\r
\r
 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})\r
\r
Using the SVN command line client, you could use the following command to fetch the\r
latest version (make sure there is no (non-svn) directory called "openocd" in the\r
current directory):\r
\r
@smallexample\r
 svn checkout svn://svn.berlios.de/openocd/trunk\r
@end smallexample\r
\r
Building the OpenOCD requires a recent version of the GNU autotools.\r
On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,\r
you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no\r
other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin\r
paths, resulting in obscure dependency errors (This is an observation I've gathered\r
from the logs of one user - correct me if I'm wrong).\r
\r
You further need the appropriate driver files, if you want to build support for\r
a FTDI FT2232 based interface:\r
@itemize @bullet\r
@item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})\r
@item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})\r
@item When using the Amontec JTAGkey, you have to get the drivers from the Amontec\r
homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID. \r
@end itemize\r
\r
Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.\r
You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.\r
\r
In general, the D2XX driver provides superior performance (several times as fast),\r
but has the draw-back of being binary-only - though that isn't as worse, as it isn't\r
a kernel module, only a user space library.\r
\r
To build OpenOCD (on both Linux and Cygwin), use the following commands:\r
@smallexample\r
 ./bootstrap \r
@end smallexample\r
Bootstrap generates the configure script, and prepares building on your system.\r
@smallexample\r
 ./configure \r
@end smallexample\r
Configure generates the Makefiles used to build OpenOCD\r
@smallexample\r
 make \r
@end smallexample\r
Make builds the OpenOCD, and places the final executable in ./src/\r
\r
The configure script takes several options, specifying which JTAG interfaces\r
should be included:\r
\r
@itemize @bullet\r
@item\r
--enable-parport\r
@item\r
--enable-parport_ppdev\r
@item\r
--enable-amtjtagaccel\r
@item\r
--enable-ft2232_ftd2xx\r
@footnote{Using the latest D2XX drivers from FTDI and following their installation\r
instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to\r
build properly}\r
@item\r
--enable-ft2232_libftdi\r
@item\r
--with-ftd2xx=/path/to/d2xx/\r
@end itemize\r
\r
If you want to access the parallel port using the PPDEV interface you have to specify\r
both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since\r
the @option{--enable-parport_ppdev} option actually is an option to the parport driver\r
(see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).\r
\r
Cygwin users have to specify the location of the FTDI D2XX package. This should be an\r
absolute path containing no spaces.\r
\r
Linux users should copy the various parts of the D2XX package to the appropriate\r
locations, i.e. /usr/include, /usr/lib. \r
\r
@node Running\r
@chapter Running\r
@cindex running openocd\r
@cindex --configfile\r
@cindex --debug_level\r
@cindex --logfile\r
@cindex --search\r
The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).\r
Run with @option{--help} or @option{-h} to view the available command line arguments.\r
\r
It reads its configuration by default from the file openocd.cfg located in the current\r
working directory. This may be overwritten with the @option{-f <configfile>} command line\r
switch.\r
\r
To enable debug output (when reporting problems or working on OpenOCD itself), use\r
the @option{-d} command line switch. This sets the debug_level to "3", outputting\r
the most information, including debug messages. The default setting is "2", outputting\r
only informational messages, warnings and errors. You can also change this setting\r
from within a telnet or gdb session (@option{debug_level <n>}).\r
\r
You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.\r
\r
Search paths for config/script files can be added to openocd by using\r
the @option{-s <search>} switch.\r
\r
@node Configuration\r
@chapter Configuration\r
@cindex configuration\r
The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration\r
by default from the file openocd.cfg in the current directory. A different configuration\r
file can be specified with the  @option{-f <conf.file>} given at the openocd command line.\r
\r
The configuration file is used to specify on which ports the daemon listens for new\r
connections, the JTAG interface used to connect to the target, the layout of the JTAG\r
chain, the targets that should be debugged, and connected flashes.\r
\r
@section Daemon configuration\r
\r
@itemize @bullet\r
@item @b{telnet_port} <@var{number}>\r
@cindex telnet_port\r
Port on which to listen for incoming telnet connections \r
@item @b{gdb_port} <@var{number}>\r
@cindex gdb_port\r
First port on which to listen for incoming GDB connections. The GDB port for the\r
first target will be gdb_port, the second target will listen on gdb_port + 1, and so on. \r
@item @b{gdb_detach} <@var{resume|reset|halt|nothing}>\r
@cindex gdb_detach\r
Configures what openocd will do when gdb detaches from the daeman.\r
Default behaviour is <@var{resume}>\r
@item @b{gdb_memory_map} <@var{enable|disable}>\r
@cindex gdb_memory_map\r
Set to <@var{enable}> so that openocd will send the memory configuration to gdb when\r
requested. gdb will then know when to set hardware breakpoints, and program flash\r
using the gdb load command. @option{gdb_flash_program enable} will also need enabling\r
for flash programming to work.\r
Default behaviour is <@var{disable}>\r
@item @b{gdb_flash_program} <@var{enable|disable}>\r
@cindex gdb_flash_program\r
Set to <@var{enable}> so that openocd will program the flash memory when a\r
vFlash packet is received.\r
Default behaviour is <@var{disable}>\r
@item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}\r
@cindex daemon_startup\r
Tells the OpenOCD whether it should reset the target when the daemon is launched, or\r
if it should just attach to the target. \r
@end itemize\r
\r
@section JTAG interface configuration\r
\r
@itemize @bullet\r
@item @b{interface} <@var{name}>\r
@cindex interface\r
Use the interface driver <@var{name}> to connect to the target. Currently supported\r
interfaces are\r
@itemize @minus\r
@item parport\r
PC parallel port bit-banging (Wigglers, PLD download cable, ...)\r
@end itemize\r
@itemize @minus\r
@item amt_jtagaccel\r
Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP\r
mode parallel port\r
@end itemize\r
@itemize @minus\r
@item ft2232\r
FTDI FT2232 based devices using either the open-source libftdi or the binary only\r
FTD2XX driver. The FTD2XX is superior in performance, but not available on every\r
platform. The libftdi uses libusb, and should be portable to all systems that provide\r
libusb.\r
@end itemize\r
@itemize @minus\r
@item ep93xx\r
Cirrus Logic EP93xx based single-board computer bit-banging (in development)\r
@end itemize\r
@end itemize\r
\r
@itemize @bullet\r
@item @b{jtag_speed} <@var{number}>\r
@cindex jtag_speed\r
Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum\r
speed. The actual effect of this option depends on the JTAG interface used.\r
\r
@itemize @minus\r
@item wiggler: maximum speed / @var{number}\r
@item ft2232: 6MHz / (@var{number}+1)\r
@item amt jtagaccel: 8 / 2**@var{number}\r
@end itemize\r
\r
Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is\r
especially true for synthesized cores (-S).\r
\r
@item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]\r
@cindex reset_config\r
The configuration of the reset signals available on the JTAG interface AND the target.\r
If the JTAG interface provides SRST, but the target doesn't connect that signal properly,\r
then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},\r
@samp{srst_only} or @samp{trst_and_srst}.\r
[@var{combination}] is an optional value specifying broken reset signal implementations.\r
@samp{srst_pulls_trst} states that the testlogic is reset together with the reset of\r
the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says\r
that the system is reset together with the test logic (only hypothetical, I haven't\r
seen hardware with such a bug, and can be worked around).\r
\r
The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the\r
reset lines to be specified. Possible values are @samp{trst_push_pull} (default)\r
and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}\r
(default) and @samp{srst_push_pull} for the system reset. These values only affect\r
JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator. \r
\r
@item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>\r
@cindex jtag_device\r
Describes the devices that form the JTAG daisy chain, with the first device being\r
the one closest to TDO. The parameters are the length of the instruction register\r
(4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask\r
of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).\r
The IDCODE instruction will in future be used to query devices for their JTAG\r
identification code. This line is the same for all ARM7 and ARM9 devices.\r
Other devices, like CPLDs, require different parameters. An example configuration\r
line for a Xilinx XC9500 CPLD would look like this:\r
@smallexample\r
jtag_device 8 0x01 0x0e3 0xfe\r
@end smallexample\r
The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into\r
the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.\r
The IDCODE instruction is 0xfe.\r
\r
@item @b{jtag_nsrst_delay} <@var{ms}>\r
@cindex jtag_nsrst_delay\r
How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before\r
starting new JTAG operations. \r
@item @b{jtag_ntrst_delay} <@var{ms}>\r
@cindex jtag_ntrst_delay\r
How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before\r
starting new JTAG operations. \r
\r
The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,\r
or on-chip features) keep a reset line asserted for some time after the external reset\r
got deasserted.\r
@end itemize\r
\r
@section parport options\r
\r
@itemize @bullet\r
@item @b{parport_port} <@var{number}>\r
@cindex parport_port\r
Either the address of the I/O port (default: 0x378 for LPT1) or the number of\r
the @file{/dev/parport} device\r
\r
When using PPDEV to access the parallel port, use the number of the parallel port:\r
@option{parport_port 0} (the default). If @option{parport_port 0x378} is specified\r
you may encounter a problem.\r
@item @b{parport_cable} <@var{name}>\r
@cindex parport_cable\r
The layout of the parallel port cable used to connect to the target.\r
Currently supported cables are \r
@itemize @minus\r
@item wiggler\r
@cindex wiggler\r
Original Wiggler layout, also supported by several clones, such\r
as the Olimex ARM-JTAG\r
@item old_amt_wiggler\r
@cindex old_amt_wiggler\r
The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new\r
version available from the website uses the original Wiggler layout ('@var{wiggler}')\r
@item chameleon\r
@cindex chameleon\r
Describes the connection of the Amontec Chameleon's CPLD when operated in\r
configuration mode. This is only used to program the Chameleon itself, not\r
a connected target.\r
@item dlc5\r
@cindex dlc5\r
Xilinx Parallel cable III.\r
@item triton\r
@cindex triton\r
The parallel port adapter found on the 'Karo Triton 1 Development Board'.\r
This is also the layout used by the HollyGates design\r
(see @uref{http://www.lartmaker.nl/projects/jtag/}).\r
@item flashlink\r
@cindex flashlink\r
ST Parallel cable. \r
@end itemize\r
@item @b{parport_write_on_exit} <@var{on|off}>\r
@cindex parport_write_on_exit\r
This will configure the parallel driver to write a known value to the parallel\r
interface on exiting openocd\r
@end itemize\r
\r
@section amt_jtagaccel options\r
@itemize @bullet\r
@item @b{parport_port} <@var{number}>\r
@cindex parport_port\r
Either the address of the I/O port (default: 0x378 for LPT1) or the number of the\r
@file{/dev/parport} device \r
@end itemize\r
@section ft2232 options\r
\r
@itemize @bullet\r
@item @b{ft2232_device_desc} <@var{description}>\r
@cindex ft2232_device_desc\r
The USB device description of the FTDI FT2232 device. If not specified, the FTDI\r
default value is used. This setting is only valid if compiled with FTD2XX support.\r
@item @b{ft2232_layout} <@var{name}>\r
@cindex ft2232_layout\r
The layout of the FT2232 GPIO signals used to control output-enables and reset\r
signals. Valid layouts are\r
@itemize @minus\r
@item usbjtag\r
The "USBJTAG-1" layout described in the original OpenOCD diploma thesis\r
@item jtagkey\r
Amontec JTAGkey and JTAGkey-tiny\r
@item signalyzer\r
Signalyzer\r
@item olimex-jtag\r
Olimex ARM-USB-OCD\r
@item m5960\r
American Microsystems M5960\r
@item evb_lm3s811\r
Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or\r
SRST signals on external connector\r
@item comstick\r
Hitex STR9 comstick \r
@item stm32stick\r
Hitex STM32 Performance Stick\r
@item flyswatter\r
Tin Can Tools Flyswatter\r
@item turtelizer2\r
egnite Software turtelizer2\r
@item oocdlink\r
OOCDLink\r
@end itemize\r
\r
@item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>\r
The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI\r
default values are used. This command is not available on Windows. \r
@item @b{ft2232_latency} <@var{ms}>\r
On some systems using ft2232 based JTAG interfaces the FT_Read function call in\r
ft2232_read() fails to return the expected number of bytes. This can be caused by\r
USB communication delays and has proved hard to reproduce and debug. Setting the\r
FT2232 latency timer to a larger value increases delays for short USB packages but it\r
also reduces the risk of timeouts before receiving the expected number of bytes.\r
The OpenOCD default value is 2 and for some systems a value of 10 has proved useful. \r
@end itemize\r
\r
@section ep93xx options\r
@cindex ep93xx options\r
Currently, there are no options available for the ep93xx interface.\r
\r
@page\r
@section Target configuration\r
\r
@itemize @bullet\r
@item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>\r
<@var{variant}>\r
@cindex target\r
Defines a target that should be debugged. Currently supported types are:\r
@itemize @minus\r
@item arm7tdmi\r
@item arm720t\r
@item arm9tdmi\r
@item arm920t\r
@item arm922t\r
@item arm926ejs\r
@item arm966e\r
@item cortex_m3\r
@item feroceon \r
@item xscale \r
@end itemize\r
\r
If you want to use a target board that is not on this list, see Adding a new\r
target board\r
\r
Endianess may be @option{little} or @option{big}.\r
\r
The reset_mode specifies what should happen to the target when a reset occurs:\r
@itemize @minus\r
@item reset_halt\r
@cindex reset_halt\r
Immediately request a target halt after reset. This allows targets to be debugged\r
from the very first instruction. This is only possible with targets and JTAG\r
interfaces that correctly implement the reset signals.\r
@item reset_init\r
@cindex reset_init\r
Similar to @option{reset_halt}, but executes the script file defined to handle the\r
'reset' event for the target. Like @option{reset_halt} this only works with\r
correct reset implementations.\r
@item reset_run\r
@cindex reset_run\r
Simply let the target run after a reset.\r
@item run_and_halt\r
@cindex run_and_halt\r
Let the target run for some time (default: 1s), and then request halt.\r
@item run_and_init\r
@cindex run_and_init\r
A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed\r
to run for some time, then halted, and the @option{reset} event script is executed. \r
@end itemize\r
\r
On JTAG interfaces / targets where system reset and test-logic reset can't be driven\r
completely independent (like the LPC2000 series), or where the JTAG interface is\r
unavailable for some time during startup (like the STR7 series), you can't use\r
@option{reset_halt} or @option{reset_init}.\r
\r
@item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>\r
@cindex target_script\r
Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}\r
\r
TODO: describe exact semantic of events\r
@item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>\r
@cindex run_and_halt_time\r
The amount of time the debugger should wait after releasing reset before it asserts\r
a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}\r
reset modes. \r
@item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>\r
<@var{backup}|@var{nobackup}>\r
@cindex working_area\r
Specifies a working area for the debugger to use. This may be used to speed-up\r
downloads to target memory and flash operations, or to perform otherwise unavailable\r
operations (some coprocessor operations on ARM7/9 systems, for example). The last\r
parameter decides whether the memory should be preserved <@var{backup}>. If possible, use\r
a working_area that doesn't need to be backed up, as that slows down operation. \r
@end itemize\r
\r
@subsection arm7tdmi options\r
@cindex arm7tdmi options\r
target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>\r
The arm7tdmi target definition requires at least one additional argument, specifying\r
the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.\r
The optional [@var{variant}] parameter has been removed in recent versions.\r
The correct feature set is determined at runtime. \r
\r
@subsection arm720t options\r
@cindex arm720t options\r
ARM720t options are similar to ARM7TDMI options.\r
\r
@subsection arm9tdmi options\r
@cindex arm9tdmi options\r
ARM9TDMI options are similar to ARM7TDMI options. Supported variants are\r
@option{arm920t}, @option{arm922t} and @option{arm940t}.\r
This enables the hardware single-stepping support found on these cores.\r
\r
@subsection arm920t options\r
@cindex arm920t options\r
ARM920t options are similar to ARM9TDMI options.\r
\r
@subsection arm966e options\r
@cindex arm966e options\r
ARM966e options are similar to ARM9TDMI options.\r
\r
@subsection xscale options\r
@cindex xscale options\r
Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},\r
@option{pxa250}, @option{pxa255}, @option{pxa26x}.\r
\r
@section Flash configuration\r
@cindex Flash configuration\r
\r
@itemize @bullet\r
@item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>\r
<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]\r
@cindex flash bank\r
Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>\r
and <@var{bus_width}> bytes using the selected flash <driver>.\r
\r
@item @b{flash auto_erase} <@option{on}|@option{off}>\r
@cindex flash auto_erase\r
auto erase flash banks prior to writing. Currently only works when using\r
@option{flash write_image} command. Default is @option{off}.\r
@end itemize\r
\r
@subsection lpc2000 options\r
@cindex lpc2000 options\r
\r
@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>\r
<@var{clock}> [@var{calc_checksum}]\r
LPC flashes don't require the chip and bus width to be specified. Additional\r
parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)\r
or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number\r
of the target this flash belongs to (first is 0), the frequency at which the core\r
is currently running (in kHz - must be an integral number), and the optional keyword\r
@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception\r
vector table. \r
\r
@subsection cfi options\r
@cindex cfi options\r
\r
@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>\r
<@var{target#}>\r
CFI flashes require the number of the target they're connected to as an additional\r
argument. The CFI driver makes use of a working area (specified for the target)\r
to significantly speed up operation. \r
\r
@var{chip_width} and @var{bus_width} are specified in bytes.\r
\r
@subsection at91sam7 options\r
@cindex at91sam7 options\r
\r
@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>\r
AT91SAM7 flashes only require the @var{target#}, all other values are looked up after\r
reading the chip-id and type. \r
\r
@subsection str7 options\r
@cindex str7 options\r
\r
@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>\r
variant can be either STR71x, STR73x or STR75x. \r
\r
@subsection str9 options\r
@cindex str9 options\r
\r
@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>\r
The str9 needs the flash controller to be configured prior to Flash programming, eg.\r
@smallexample\r
str9x flash_config 0 4 2 0 0x80000\r
@end smallexample\r
This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively. \r
\r
@subsection str9 options (str9xpec driver)\r
\r
@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>\r
Before using the flash commands the turbo mode will need enabling using str9xpec\r
@option{enable_turbo} <@var{num>.}\r
\r
Only use this driver for locking/unlocking the device or configuring the option bytes.\r
Use the standard str9 driver for programming.\r
\r
@subsection stellaris (LM3Sxxx) options\r
@cindex stellaris (LM3Sxxx) options\r
\r
@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>\r
stellaris flash plugin only require the @var{target#}. \r
\r
@subsection stm32x options\r
@cindex stm32x options\r
\r
@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>\r
stm32x flash plugin only require the @var{target#}. \r
\r
@node Commands\r
@chapter Commands\r
@cindex commands\r
\r
The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface\r
(default: port 4444) and a GDB server (default: port 3333). The command line interpreter\r
is available from both the telnet interface and a GDB session. To issue commands to the\r
interpreter from within a GDB session, use the @option{monitor} command, e.g. use\r
@option{monitor poll} to issue the @option{poll} command. All output is relayed through the\r
GDB session.\r
\r
@section Daemon\r
\r
@itemize @bullet\r
@item @b{sleep} <@var{msec}>\r
@cindex sleep\r
Wait for n milliseconds before resuming. Useful in connection with script files\r
(@var{script} command and @var{target_script} configuration). \r
\r
@item @b{shutdown}\r
@cindex shutdown\r
Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet). \r
\r
@item @b{debug_level} [@var{n}]\r
@cindex debug_level\r
Display or adjust debug level to n<0-3> \r
\r
@item @b{log_output} <@var{file}>\r
@cindex log_output\r
Redirect logging to <file> (default: stderr) \r
\r
@item @b{script} <@var{file}>\r
@cindex script\r
Execute commands from <file> \r
\r
@end itemize\r
\r
@subsection Target state handling\r
@itemize @bullet\r
@item @b{poll} [@option{on}|@option{off}]\r
@cindex poll\r
Poll the target for its current state. If the target is in debug mode, architecture\r
specific information about the current state are printed. An optional parameter\r
allows continuous polling to be enabled and disabled.\r
\r
@item @b{halt} [@option{ms}]\r
@cindex halt\r
Send a halt request to the target and waits for it to halt for [@option{ms}].\r
Default [@option{ms}] is 5 seconds if no arg given.\r
Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]\r
will stop openocd from waiting.\r
\r
@item @b{wait_halt} [@option{ms}]\r
@cindex wait_halt\r
Wait for the target to enter debug mode. Optional [@option{ms}] is\r
a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no\r
arg given.\r
\r
@item @b{resume} [@var{address}]\r
@cindex resume\r
Resume the target at its current code position, or at an optional address.\r
Openocd will wait 5 seconds for the target to resume.\r
\r
@item @b{step} [@var{address}]\r
@cindex step\r
Single-step the target at its current code position, or at an optional address. \r
\r
@item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}\r
|@option{run_and_init}]\r
@cindex reset\r
Do a hard-reset. The optional parameter specifies what should happen after the reset.\r
This optional parameter overwrites the setting specified in the configuration file,\r
making the new behaviour the default for the @option{reset} command.\r
@itemize @minus\r
@item run\r
@cindex reset run\r
Let the target run.\r
@item halt\r
@cindex reset halt\r
Immediately halt the target (works only with certain configurations).\r
@item init\r
@cindex reset init\r
Immediately halt the target, and execute the reset script (works only with certain\r
configurations)\r
@item run_and_halt\r
@cindex reset run_and_halt\r
Let the target run for a certain amount of time, then request a halt.\r
@item run_and_init\r
@cindex reset run_and_init\r
Let the target run for a certain amount of time, then request a halt. Execute the\r
reset script once the target entered debug mode.\r
@end itemize\r
@end itemize\r
\r
@subsection Memory access commands\r
These commands allow accesses of a specific size to the memory system:\r
@itemize @bullet\r
@item @b{mdw} <@var{addr}> [@var{count}]\r
@cindex mdw\r
display memory words \r
@item @b{mdh} <@var{addr}> [@var{count}]\r
@cindex mdh\r
display memory half-words \r
@item @b{mdb} <@var{addr}> [@var{count}]\r
@cindex mdb\r
display memory bytes \r
@item @b{mww} <@var{addr}> <@var{value}>\r
@cindex mww\r
write memory word \r
@item @b{mwh} <@var{addr}> <@var{value}>\r
@cindex mwh\r
write memory half-word \r
@item @b{mwb} <@var{addr}> <@var{value}>\r
@cindex mwb\r
write memory byte \r
\r
@item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]\r
@cindex load_image\r
Load image <@var{file}> to target memory at <@var{address}> \r
@item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>\r
@cindex dump_image\r
Dump <@var{size}> bytes of target memory starting at <@var{address}> to a\r
(binary) <@var{file}>.\r
@item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]\r
@cindex verify_image\r
Verify <@var{file}> to target memory starting at <@var{address}>.\r
This will first attempt using a crc checksum, if this fails it will try a binary compare.\r
@item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]\r
@cindex load_binary\r
Load binary <@var{file}> to target memory at <@var{address}> \r
@item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]\r
@cindex dump_binary\r
Dump <@var{size}> bytes of target memory starting at <@var{address}> to a\r
(binary) <@var{file}>.\r
@end itemize\r
\r
@subsection Flash commands\r
@cindex Flash commands\r
@itemize @bullet\r
@item @b{flash banks}\r
@cindex flash banks\r
List configured flash banks \r
@item @b{flash info} <@var{num}>\r
@cindex flash info\r
Print info about flash bank <@option{num}> \r
@item @b{flash probe} <@var{num}>\r
@cindex flash probe\r
Identify the flash, or validate the parameters of the configured flash. Operation\r
depends on the flash type. \r
@item @b{flash erase_check} <@var{num}>\r
@cindex flash erase_check\r
Check erase state of sectors in flash bank <@var{num}>. This is the only operation that\r
updates the erase state information displayed by @option{flash info}. That means you have\r
to issue an @option{erase_check} command after erasing or programming the device to get\r
updated information. \r
@item @b{flash protect_check} <@var{num}>\r
@cindex flash protect_check\r
Check protection state of sectors in flash bank <num>. \r
\r
@item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]\r
@cindex flash erase\r
Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including\r
<@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might\r
require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using\r
the CFI driver). This command was replaced by the new command\r
@option{flash erase_sector} using the same syntax. \r
@item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>\r
@cindex flash erase_sector\r
Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including\r
<@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might\r
require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using\r
the CFI driver).\r
@item @b{flash erase_address} <@var{address}> <@var{length}>\r
@cindex flash erase_address\r
Erase sectors starting at <@var{address}> for <@var{length}> number of bytes\r
@item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]\r
@cindex flash write\r
Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>\r
bytes from the beginning of the bank. This command was replaced by the new command\r
@option{flash write_binary} using the same syntax. \r
@item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>\r
@cindex flash write_binary\r
Write the binary <@var{file}> to flash bank <@var{num}>, starting at\r
<@option{offset}> bytes from the beginning of the bank. \r
@item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]\r
@cindex flash write_image\r
Write the image <@var{file}> to the current target's flash bank(s). A relocation\r
[@var{offset}] can be specified and the file [@var{type}] can be specified\r
explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}\r
(ELF file) or @option{s19} (Motorola s19). \r
@item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>\r
@cindex flash protect\r
Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to\r
<@var{last}> of @option{flash bank} <@var{num}>. \r
@item @b{flash auto_erase} <@var{on}|@var{off}>\r
@cindex flash auto_erase\r
Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command\r
only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command. \r
@end itemize\r
\r
@page\r
@section Target Specific Commands\r
@cindex Target Specific Commands\r
\r
@subsection AT91SAM7 specific commands\r
@cindex AT91SAM7 specific commands\r
The flash configuration is deduced from the chip identification register. The flash\r
controller handles erases automatically on a page (128/265 byte) basis so erase is\r
not necessary for flash programming. AT91SAM7 processors with less than 512K flash\r
only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes\r
that can be erased separatly.Only an EraseAll command is supported by the controller\r
for each flash plane and this is called with\r
@itemize @bullet\r
@item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}\r
bulk erase flash planes first_plane to last_plane. \r
@item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>\r
@cindex at91sam7 gpnvm\r
set or clear a gpnvm bit for the processor \r
@end itemize\r
\r
@subsection STR9 specific commands\r
@cindex STR9 specific commands\r
These are flash specific commands when using the str9xpec driver.\r
@itemize @bullet\r
@item @b{str9xpec enable_turbo} <@var{num}>\r
@cindex str9xpec enable_turbo\r
enable turbo mode, simply this will remove the str9 from the chain and talk\r
directly to the embedded flash controller. \r
@item @b{str9xpec disable_turbo} <@var{num}>\r
@cindex str9xpec disable_turbo\r
restore the str9 into jtag chain. \r
@item @b{str9xpec lock} <@var{num}>\r
@cindex str9xpec lock\r
lock str9 device. The str9 will only respond to an unlock command that will\r
erase the device. \r
@item @b{str9xpec unlock} <@var{num}>\r
@cindex str9xpec unlock\r
unlock str9 device. \r
@item @b{str9xpec options_read} <@var{num}>\r
@cindex str9xpec options_read\r
read str9 option bytes. \r
@item @b{str9xpec options_write} <@var{num}>\r
@cindex str9xpec options_write\r
write str9 option bytes. \r
@end itemize\r
\r
@subsection STR9 configuration\r
@cindex STR9 configuration\r
@itemize @bullet\r
@item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>\r
<@var{BBADR}> <@var{NBBADR}>\r
@cindex str9x flash_config\r
Configure str9 flash controller.\r
@smallexample\r
eg. str9x flash_config 0 4 2 0 0x80000\r
This will setup\r
BBSR - Boot Bank Size register\r
NBBSR - Non Boot Bank Size register\r
BBADR - Boot Bank Start Address register\r
NBBADR - Boot Bank Start Address register\r
@end smallexample\r
@end itemize\r
\r
@subsection STR9 option byte configuration\r
@cindex STR9 option byte configuration\r
@itemize @bullet\r
@item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>\r
@cindex str9xpec options_cmap\r
configure str9 boot bank. \r
@item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>\r
@cindex str9xpec options_lvdthd\r
configure str9 lvd threshold. \r
@item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>\r
@cindex str9xpec options_lvdsel\r
configure str9 lvd source. \r
@item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>\r
@cindex str9xpec options_lvdwarn\r
configure str9 lvd reset warning source. \r
@end itemize\r
\r
@subsection STM32x specific commands\r
@cindex STM32x specific commands\r
 \r
These are flash specific commands when using the stm32x driver.\r
@itemize @bullet\r
@item @b{stm32x lock} <@var{num}>\r
@cindex stm32x lock\r
lock stm32 device. \r
@item @b{stm32x unlock} <@var{num}>\r
@cindex stm32x unlock\r
unlock stm32 device. \r
@item @b{stm32x options_read} <@var{num}>\r
@cindex stm32x options_read\r
read stm32 option bytes. \r
@item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>\r
<@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>\r
@cindex stm32x options_write\r
write stm32 option bytes. \r
@item @b{stm32x mass_erase} <@var{num}>\r
@cindex stm32x mass_erase\r
mass erase flash memory. \r
@end itemize\r
\r
@page\r
@section Architecture Specific Commands\r
@cindex Architecture Specific Commands\r
\r
@subsection ARMV4/5 specific commands\r
@cindex ARMV4/5 specific commands\r
\r
These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems\r
or Intel XScale (XScale isn't supported yet).\r
@itemize @bullet\r
@item @b{armv4_5 reg}\r
@cindex armv4_5 reg\r
Display a list of all banked core registers, fetching the current value from every\r
core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current\r
register value. \r
@item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]\r
@cindex armv4_5 core_mode\r
Displays the core_mode, optionally changing it to either ARM or Thumb mode.\r
The target is resumed in the currently set @option{core_mode}. \r
@end itemize\r
\r
@subsection ARM7/9 specific commands\r
@cindex ARM7/9 specific commands\r
\r
These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,\r
ARM920t or ARM926EJ-S.\r
@itemize @bullet\r
@item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>\r
@cindex arm7_9 sw_bkpts\r
Enable/disable use of software breakpoints. On ARMv4 systems, this reserves\r
one of the watchpoint registers to implement software breakpoints. Disabling\r
SW Bkpts frees that register again. \r
@item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>\r
@cindex arm7_9 force_hw_bkpts\r
When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all\r
breakpoints are turned into hardware breakpoints.\r
@item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>\r
@cindex arm7_9 dbgrq\r
Enable use of the DBGRQ bit to force entry into debug mode. This should be\r
safe for all but ARM7TDMI--S cores (like Philips LPC). \r
@item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>\r
@cindex arm7_9 fast_writes [DEPRECATED]\r
See @option{arm7_9 fast_memory_access} instead. \r
@item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>\r
@cindex arm7_9 fast_memory_access\r
Allow the OpenOCD to read and write memory without checking completion of\r
the operation. This provides a huge speed increase, especially with USB JTAG\r
cables (FT2232), but might be unsafe if used with targets running at a very low\r
speed, like the 32kHz startup clock of an AT91RM9200. \r
@item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>\r
@cindex arm7_9 dcc_downloads\r
Enable the use of the debug communications channel (DCC) to write larger (>128 byte)\r
amounts of memory. DCC downloads offer a huge speed increase, but might be potentially\r
unsafe, especially with targets running at a very low speed. This command was introduced\r
with OpenOCD rev. 60. \r
@end itemize\r
\r
@subsection ARM920T specific commands\r
@cindex ARM920T specific commands\r
\r
@itemize @bullet\r
@item @b{arm920t cache_info}\r
@cindex arm920t cache_info\r
Print information about the caches found. This allows you to see if your target\r
is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache). \r
@item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]\r
@cindex arm920t md<bhw>_phys\r
Display memory at physical address addr. \r
@item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>\r
@cindex arm920t mw<bhw>_phys\r
Write memory at physical address addr. \r
@item @b{arm920t read_cache} <@var{filename}>\r
@cindex arm920t read_cache\r
Dump the content of ICache and DCache to a file. \r
@item @b{arm920t read_mmu} <@var{filename}>\r
@cindex arm920t read_mmu\r
Dump the content of the ITLB and DTLB to a file. \r
@item @b{arm920t virt2phys} <@var{VA}>\r
@cindex arm920t virt2phys\r
Translate a virtual address to a physical address. \r
@end itemize\r
\r
@page\r
@section Debug commands\r
@cindex Debug commands\r
The following commands give direct access to the core, and are most likely\r
only useful while debugging the OpenOCD.\r
@itemize @bullet\r
@item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>\r
@cindex arm7_9 write_xpsr\r
Immediately write either the current program status register (CPSR) or the saved\r
program status register (SPSR), without changing the register cache (as displayed\r
by the @option{reg} and @option{armv4_5 reg} commands). \r
@item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>\r
<@var{0=cpsr},@var{1=spsr}>\r
@cindex arm7_9 write_xpsr_im8\r
Write the 8-bit value rotated right by 2*rotate bits, using an immediate write\r
operation (similar to @option{write_xpsr}). \r
@item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>\r
@cindex arm7_9 write_core_reg\r
Write a core register, without changing the register cache (as displayed by the\r
@option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the\r
encoding of the [M4:M0] bits of the PSR. \r
@end itemize\r
\r
@page\r
@section JTAG commands\r
@cindex JTAG commands\r
@itemize @bullet\r
@item @b{scan_chain}\r
@cindex scan_chain\r
Print current scan chain configuration. \r
@item @b{jtag_reset}\r
@cindex jtag_reset\r
Toggle reset lines <@var{trst}> <@var{srst}>. \r
@item @b{endstate} <@var{tap_state}>\r
@cindex endstate\r
Finish JTAG operations in <@var{tap_state}>. \r
@item @b{runtest} <@var{num_cycles}>\r
@cindex runtest\r
Move to Run-Test/Idle, and execute <@var{num_cycles}> \r
@item @b{statemove} [@var{tap_state}]\r
@cindex statemove\r
Move to current endstate or [@var{tap_state}] \r
@item @b{irscan}\r
@cindex irscan\r
Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ... \r
@item @b{drscan}\r
@cindex drscan\r
Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ... \r
@item @b{verify_ircapture}\r
@cindex verify_ircapture\r
Verify value captured during Capture-IR <@option{enable}|@option{disable}> \r
@item @b{var}\r
@cindex var\r
Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ... \r
@item @b{field}\r
@cindex field\r
Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}] \r
@end itemize\r
\r
@node Sample Scripts\r
@chapter Sample Scripts\r
@cindex scripts\r
\r
This page will collect some script examples for different CPUs.\r
\r
The configuration script can be divided in the following section:\r
@itemize @bullet\r
@item daemon configuration\r
@item interface\r
@item jtag scan chain\r
@item target configuration\r
@item flash configuration \r
@end itemize\r
\r
Detailed information about each section can be found at OpenOCD configuration \r
\r
@section OMAP5912 Flash Debug\r
@cindex OMAP5912 Flash Debug\r
The following two scripts were used with a wiggler PP and and a TI OMAP5912\r
dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board\r
- (@uref{http://www.spectrumdigital.com}).\r
@subsection Openocd config\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
\r
#interface\r
interface parport\r
parport_port 0x378\r
parport_cable wiggler\r
jtag_speed 0\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
\r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 38 0x0 0x0 0x0\r
jtag_device 4  0x1 0x0 0xe\r
jtag_device 8  0x0 0x0 0x0\r
\r
#target configuration\r
daemon_startup reset\r
\r
#target <type> <endianness> <reset mode> <chainpos> <variant>\r
target arm926ejs little run_and_init 1 arm926ejs\r
target_script 0 reset omap5912_osk.init\r
run_and_halt_time 0 30\r
\r
# omap5912 lcd frame buffer as working area\r
working_area 0 0x20000000 0x3e800 nobackup\r
\r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank cfi 0x00000000 0x1000000 2 2 0\r
@end smallexample\r
\r
@subsection Openocd init\r
@smallexample\r
#\r
# halt target\r
#\r
poll\r
sleep 1\r
halt\r
wait_halt\r
#\r
# disable wdt\r
#\r
mww 0xfffec808 0x000000f5\r
mww 0xfffec808 0x000000a0\r
\r
mww 0xfffeb048 0x0000aaaa\r
sleep 500\r
mww 0xfffeb048 0x00005555\r
sleep 500\r
#\r
# detect flash\r
#\r
flash probe 0\r
\r
@end smallexample\r
\r
@section STR71x Script\r
@cindex STR71x Script\r
The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 0\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi\r
run_and_halt_time 0 30\r
\r
working_area 0 0x2000C000 0x4000 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x\r
@end smallexample\r
\r
@section STR750 Script\r
@cindex STR750 Script\r
The following script was used with an Amontec JTAGkey and a STR750 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 19\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
#reset_config trst_and_srst srst_pulls_trst\r
reset_config trst_and_srst srst_pulls_trst\r
\r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
\r
#jtag nTRST and nSRST delay\r
jtag_nsrst_delay 500\r
jtag_ntrst_delay 500\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x40000000 0x4000 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x\r
@end smallexample\r
\r
@section STR912 Script\r
@cindex STR912 Script\r
The following script was used with an Amontec JTAGkey and a STR912 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
jtag_speed 1\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 8 0x1 0x1 0xfe\r
jtag_device 4 0x1 0xf 0xe\r
jtag_device 5 0x1 0x1 0x1e\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm966e <endianness> <reset mode> <chainpos> <variant>\r
target arm966e little reset_halt 1 arm966e\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x50000000 16384 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank str9x 0x00000000 0x00080000 0 0 0\r
@end smallexample\r
\r
@section STR912 comstick\r
@cindex STR912 comstick Script\r
The following script was used with a Hitex STR9 Comstick:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "STR9-comStick A"\r
ft2232_layout comstick\r
jtag_speed 1\r
\r
jtag_nsrst_delay 100\r
jtag_ntrst_delay 100\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 8 0x1 0x1 0xfe\r
jtag_device 4 0x1 0xf 0xe\r
jtag_device 5 0x1 0x1 0x1e\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm966e <endianness> <reset mode> <chainpos> <variant>\r
target arm966e little reset_halt 1 arm966e\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x50000000 16384 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank str9x 0x00000000 0x00080000 0 0 0\r
@end smallexample\r
\r
@section STM32x Script\r
@cindex STM32x Script\r
The following script was used with an Amontec JTAGkey and a STM32x cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
jtag_speed 10\r
\r
jtag_nsrst_delay 100\r
jtag_ntrst_delay 100\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
jtag_device 5 0x1 0x1 0x1e\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target cortex_m3 <endianness> <reset mode> <chainpos> <variant>\r
target cortex_m3 little run_and_halt 0\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x20000000 16384 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank stm32x 0x08000000 0x00020000 0 0 0\r
@end smallexample\r
\r
@section STM32x Performance Stick\r
@cindex STM32x Performance Stick Script\r
The following script was used with the Hitex STM32 Performance Stick\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "STM32-PerformanceStick A"\r
ft2232_layout stm32stick\r
jtag_speed 10\r
\r
jtag_nsrst_delay 100\r
jtag_ntrst_delay 100\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
jtag_device 5 0x1 0x1 0x1e\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target cortex_m3 <endianness> <reset mode> <chainpos> <variant>\r
target cortex_m3 little run_and_halt 0\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x20000000 16384 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank stm32x 0x08000000 0x00020000 0 0 0\r
@end smallexample\r
\r
@section LPC2129 Script\r
@cindex LPC2129 Script\r
The following script was used with an wiggler PP and a LPC-2129 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface parport\r
parport_port 0x378\r
parport_cable wiggler\r
jtag_speed 0\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x40000000 0x4000 nobackup\r
 \r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum\r
@end smallexample\r
\r
@section  LPC2148 Script\r
@cindex  LPC2148 Script\r
The following script was used with an Amontec JTAGkey and a LPC2148 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 3\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x40000000 0x8000 nobackup\r
 \r
#flash configuration\r
flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum\r
@end smallexample\r
\r
@section  LPC2294 Script\r
@cindex  LPC2294 Script\r
The following script was used with an Amontec JTAGkey and a LPC2294 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 3\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4\r
run_and_halt_time 0 30\r
 \r
working_area 0 0x40000000 0x4000 nobackup\r
 \r
#flash configuration\r
flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum\r
@end smallexample\r
\r
@section AT91R40008 Script\r
@cindex AT91R40008 Script\r
The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 0\r
jtag_nsrst_delay 200\r
jtag_ntrst_delay 200\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config srst_only srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi\r
run_and_halt_time 0 30\r
@end smallexample\r
\r
@section AT91SAM7s Script\r
@cindex AT91SAM7s Script\r
The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
ft2232_device_desc "Olimex OpenOCD JTAG A"\r
ft2232_layout olimex-jtag\r
ft2232_vid_pid 0x15BA 0x0003\r
jtag_speed 0\r
jtag_nsrst_delay 200\r
jtag_ntrst_delay 200\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config srst_only srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
target arm7tdmi little run_and_halt 0 arm7tdmi\r
run_and_halt_time 0 30\r
 \r
# flash-options AT91\r
working_area 0 0x00200000 0x4000 nobackup\r
flash bank at91sam7 0 0 0 0 0\r
 \r
# Information: \r
# erase command (telnet-interface) for complete flash:\r
# flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)\r
# SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15\r
# set/clear NVM-Bits:\r
# at91sam7 gpnvm <num> <bit> <set|clear>\r
# disable locking from SAM-BA:\r
# flash protect 0 0 1 off\r
@end smallexample\r
\r
@section XSCALE IXP42x Script\r
@cindex XSCALE IXP42x Script\r
The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
\r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 0\r
jtag_nsrst_delay 200\r
jtag_ntrst_delay 200\r
 \r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config srst_only srst_pulls_trst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 7 0x1 0x7f 0x7e\r
 \r
#target configuration\r
daemon_startup reset\r
 \r
#target <type> <startup mode>\r
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
target xscale big run_and_halt 0 IXP42x\r
run_and_halt_time 0 30\r
@end smallexample\r
\r
@section Cirrus Logic EP9301 Script\r
@cindex Cirrus Logic EP9301 Script\r
The following script was used with FT2232 based JTAG interfaces and a\r
Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
 \r
#interface\r
interface ft2232\r
\r
#Olimex ARM-USB-OCD\r
#ft2232_device_desc "Olimex OpenOCD JTAG"\r
#ft2232_layout olimex-jtag\r
#ft2232_vid_pid 0x15ba 0x0003\r
 \r
#Amontec JTAGkey (and JTAGkey-Tiny)\r
#Serial is only necessary if more than one JTAGkey is connected\r
ft2232_device_desc "Amontec JTAGkey A"\r
#ft2232_serial AMTJKV31\r
#ft2232_serial T1P3S2W8\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
 \r
#wiggler/parallel port interface\r
#interface parport\r
#parport_port 0x378\r
#parport_cable wiggler\r
#jtag_speed 0\r
jtag_speed 1\r
reset_config trst_and_srst\r
 \r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
 \r
jtag_nsrst_delay 100\r
jtag_ntrst_delay 100\r
 \r
#target configuration\r
daemon_startup attach\r
 \r
#target <type> <endianess> <reset mode>\r
target arm920t little reset_halt 0\r
working_area 0 0x80014000 0x1000 backup\r
 \r
#flash configuration\r
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]\r
flash bank cfi 0x60000000 0x1000000 2 2 0\r
@end smallexample\r
\r
@section Hilscher netX 100 / 500 Script\r
@cindex Hilscher netX 100 / 500 Script\r
The following script was used with an Amontec JTAGkey and a Hilscher\r
netX 500 cpu:\r
@smallexample\r
#daemon configuration\r
telnet_port 4444\r
gdb_port 3333\r
\r
#interface\r
interface ft2232\r
ft2232_device_desc "Amontec JTAGkey A"\r
ft2232_layout jtagkey\r
ft2232_vid_pid 0x0403 0xcff8\r
jtag_speed 5\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst\r
\r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 4 0x1 0xf 0xe\r
\r
jtag_nsrst_delay 100\r
jtag_ntrst_delay 100\r
\r
#target configuration\r
daemon_startup reset\r
\r
#target <type> <endianness> <startup mode> <chainpos> <variant>\r
target arm926ejs little run_and_halt 0 arm926ejs\r
run_and_halt_time 0 500\r
@end smallexample\r
\r
@section Marvell/Intel PXA270 Script\r
@cindex Marvell/Intel PXA270 Script\r
@smallexample\r
# config for Intel PXA270\r
# not, as of 2007-06-22, openocd only works with the\r
# libftd2xx library from ftdi.  libftdi does not work.\r
\r
telnet_port     3333\r
gdb_port        4444\r
\r
interface ft2232\r
ft2232_layout olimex-jtag\r
ft2232_vid_pid 0x15BA 0x0003\r
ft2232_device_desc "Olimex OpenOCD JTAG"\r
jtag_speed 0\r
# set jtag_nsrst_delay to the delay introduced by your reset circuit\r
# the rest of the needed delays are built into the openocd program\r
jtag_nsrst_delay 260\r
# set the jtag_ntrst_delay to the delay introduced by a reset circuit\r
# the rest of the needed delays are built into the openocd program\r
jtag_ntrst_delay 0\r
\r
#use combined on interfaces or targets that can't set TRST/SRST separately\r
reset_config trst_and_srst separate\r
\r
#jtag scan chain\r
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
jtag_device 7 0x1 0x7f 0x7e\r
\r
#target configuration\r
daemon_startup reset\r
\r
target xscale little reset_halt 0 pxa27x\r
\r
# maps to PXA internal RAM.  If you are using a PXA255\r
# you must initialize SDRAM or leave this option off\r
working_area 0 0x5c000000 0x10000 nobackup\r
\r
run_and_halt_time 0 30\r
\r
#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
# works for P30 flash\r
flash bank cfi 0x00000000 0x1000000 2 4 0\r
@end smallexample\r
\r
@node GDB and Openocd\r
@chapter GDB and Openocd\r
@cindex GDB and Openocd\r
Openocd complies with the remote gdbserver protocol, and as such can be used\r
to debug remote targets.\r
\r
@section Connecting to gdb\r
@cindex Connecting to gdb\r
A connection is typically started as follows:\r
@smallexample\r
target remote localhost:3333\r
@end smallexample\r
This would cause gdb to connect to the gdbserver on the local pc using port 3333.\r
\r
To see a list of available openocd commands type @option{monitor help} on the\r
gdb commandline.\r
\r
Openocd supports the gdb @option{qSupported} packet, this enables information\r
to be sent by the gdb server (openocd) to gdb. Typical information includes\r
packet size and device memory map.\r
\r
Previous versions of openocd required the following gdb options to increase\r
the packet size and speed up gdb communication.\r
@smallexample\r
set remote memory-write-packet-size 1024\r
set remote memory-write-packet-size fixed\r
set remote memory-read-packet-size 1024\r
set remote memory-read-packet-size fixed\r
@end smallexample\r
This is now handled in the @option{qSupported} PacketSize.\r
\r
@section Programming using gdb\r
@cindex Programming using gdb\r
\r
By default the target memory map is not sent to gdb, this can be enabled by\r
the following openocd config option:\r
@smallexample\r
gdb_memory_map enable\r
@end smallexample\r
For this to function correctly a valid flash config must also be configured\r
in openocd. For speed also configure a valid working area.\r
\r
Informing gdb of the memory map of the target will enable gdb to protect any\r
flash area of the target and use hardware breakpoints by default. This means\r
that the openocd option @option{arm7_9 force_hw_bkpts} is not required when\r
using a memory map.\r
\r
To view the configured memory map in gdb, use the gdb command @option{info mem}\r
All other unasigned addresses within gdb are treated as ram.\r
\r
If @option{gdb_flash_program enable} is also used, gdb will be able to\r
program any flash memory using the vFlash interface.\r
\r
gdb will look at the target memory map when a load command is given, if any\r
areas to be programmed lie within the target flash area the vFlash packets\r
will be used.\r
\r
Incase the target needs configuring before gdb programming, a script can be executed.\r
@smallexample\r
target_script 0 gdb_program_config config.script\r
@end smallexample\r
\r
To verify any flash programming the gdb command @option{compare-sections}\r
can be used.\r
\r
@node FAQ\r
@chapter FAQ\r
@cindex faq\r
@enumerate\r
@item OpenOCD complains about a missing cygwin1.dll\r
\r
Make sure you have Cygwin installed, or at least a version of OpenOCD that\r
claims to come with all the necessary dlls. When using Cygwin, try launching\r
the OpenOCD from the Cygwin shell.\r
\r
@item I'm trying to set a breakpoint using GDB (or a frontend like Insight or\r
Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213\r
arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".\r
\r
GDB issues software breakpoints when a normal breakpoint is requested, or to implement\r
source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,\r
software breakpoints consume one of the two available hardware breakpoints,\r
and are therefor disabled by default. If your code is running from RAM, you\r
can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If\r
your code resides in Flash, you can't use software breakpoints, but you can force\r
OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.\r
\r
@item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes\r
and works sometimes fine.\r
\r
Make sure the core frequency specified in the @option{flash lpc2000} line matches the\r
clock at the time you're programming the flash. If you've specified the crystal's\r
frequency, make sure the PLL is disabled, if you've specified the full core speed\r
(e.g. 60MHz), make sure the PLL is enabled.\r
\r
@item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,\r
I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed\r
out while waiting for end of scan, rtck was disabled".\r
\r
Make sure your PC's parallel port operates in EPP mode. You might have to try several\r
settings in your PC Bios (ECP, EPP, and different versions of those).\r
\r
@item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),\r
I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():\r
memory read caused data abort". \r
\r
The errors are non-fatal, and are the result of GDB trying to trace stack frames\r
beyond the last valid frame. It might be possible to prevent this by setting up\r
a proper "initial" stack frame, if you happen to know what exactly has to\r
be done, feel free to add this here.\r
\r
@item I get the following message in the OpenOCD console (or log file):\r
"Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".\r
\r
This warning doesn't indicate any serious problem, as long as you don't want to\r
debug your core right out of reset. Your .cfg file specified @option{jtag_reset\r
trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,\r
your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals\r
independently. With this setup, it's not possible to halt the core right out of\r
reset, everything else should work fine.\r
\r
@item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto\r
Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be\r
unstable. When single-stepping over large blocks of code, GDB and OpenOCD\r
quit with an error message. Is there a stability issue with OpenOCD?\r
\r
No, this is not a stability issue concering OpenOCD. Most users have solved\r
this issue by simply using a self-powered USB Hub, which they connect their\r
Amontec JTAGkey to. Apparently, some computers do not provide a USB power\r
supply stable enough for the Amontec JTAGkey to be operated.\r
\r
@item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the\r
following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:\r
4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".\r
What does that mean and what might be the reason for this?\r
\r
First of all, the reason might be the USB power supply. Try using a self-powered\r
hub instead of a direct connection to your computer. Secondly, the error code 4\r
corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB\r
Chip ran into some sort of error - this points us to a USB problem.\r
\r
@item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following\r
error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".\r
What does that mean and what might be the reason for this?\r
\r
Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)\r
has closed the connection to OpenOCD. This might be a GDB issue.\r
\r
@item In the configuration file in the section where flash device configurations\r
are described, there is a parameter for specifying the clock frequency for\r
LPC2000 internal flash devices (e.g.\r
@option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),\r
which must be sepcified in kilohertz. However, I do have a quartz crystal of a\r
frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).\r
Is it possible to specify real numbers for the clock frequency?\r
\r
No. The clock frequency specified here must be given as an integral number.\r
However, this clock frequency is used by the In-Application-Programming (IAP)\r
routines of the LPC2000 family only, which seems to be very tolerant concerning\r
the given clock frequency, so a slight difference between the specified clock\r
frequency and the actual clock frequency will not cause any trouble.\r
\r
@item Do I have to keep a specific order for the commands in the configuration file?\r
\r
Well, yes and no. Commands can be given in arbitrary order, yet the devices\r
listed for the JTAG scan chain must be given in the right order (jtag_device),\r
with the device closest to the TDO-Pin being listed first. In general,\r
whenever objects of the same type exist which require an index number, then\r
these objects must be given in the right order (jtag_devices, targets and flash\r
banks - a target references a jtag_device and a flash bank references a target).\r
\r
@item Sometimes my debugging session terminates with an error. When I look into the\r
log file, I can see these error messages: Error: arm7_9_common.c:561\r
arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP\r
                                                        \r
@end enumerate\r
\r
@include fdl.texi\r
\r
@node Index\r
@unnumbered Index\r
\r
@printindex cp\r
\r
@bye\r